From 7d315b6a7091f3fa1b76576c27e3bcddf93b0785 Mon Sep 17 00:00:00 2001
From: Gianluca Brilli <gianluca.brilli@unimore.it>
Date: Mon, 17 May 2021 08:53:47 +0200
Subject: [PATCH] solutions for HLS lab2

---
 hls/lab2/README.md                            |     9 +
 hls/lab2/TODO                                 |     0
 hls/lab2/exercise_1.tcl                       |   950 ++
 hls/lab2/exercise_2.tcl                       |   976 ++
 hls/lab2/exercise_3.tcl                       |   971 ++
 hls/lab2/exercise_4.tcl                       |   975 ++
 hls/lab2/exercise_5.tcl                       |   975 ++
 hls/lab2/exercise_6.tcl                       |   975 ++
 hls/lab2/exercise_7.tcl                       |   975 ++
 hls/lab2/exercise_8.tcl                       |   989 ++
 hls/lab2/exercise_9.tcl                       |   989 ++
 .../xilinx_com_hls_exercise_2/component.xml   |  5542 ++++++++
 .../constraints/mmult_ooc.xdc                 |     6 +
 .../doc/ReleaseNotes.txt                      |    10 +
 .../drivers/mmult_v1_0/data/mmult.mdd         |    16 +
 .../drivers/mmult_v1_0/data/mmult.tcl         |    21 +
 .../drivers/mmult_v1_0/src/Makefile           |    32 +
 .../drivers/mmult_v1_0/src/xmmult.c           |   198 +
 .../drivers/mmult_v1_0/src/xmmult.h           |   108 +
 .../drivers/mmult_v1_0/src/xmmult_hw.h        |    50 +
 .../drivers/mmult_v1_0/src/xmmult_linux.c     |   147 +
 .../drivers/mmult_v1_0/src/xmmult_sinit.c     |    43 +
 .../hdl/verilog/mmult.v                       |  1411 +++
 .../hdl/verilog/mmult_in1_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_in2_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_out_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_params_s_axi.v          |   393 +
 .../hdl/vhdl/mmult.vhd                        |  1708 +++
 .../hdl/vhdl/mmult_in1_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_in2_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_out_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_params_s_axi.vhd           |   439 +
 .../xilinx_com_hls_exercise_2/misc/logo.png   |   Bin 0 -> 4077 bytes
 .../xgui/mmult_v1_0.tcl                       |   529 +
 .../xilinx_com_hls_exercise_3/component.xml   |  5560 ++++++++
 .../constraints/mmult_ooc.xdc                 |     6 +
 .../doc/ReleaseNotes.txt                      |    10 +
 .../drivers/mmult_v2_0/data/mmult.mdd         |    16 +
 .../drivers/mmult_v2_0/data/mmult.tcl         |    21 +
 .../drivers/mmult_v2_0/src/Makefile           |    32 +
 .../drivers/mmult_v2_0/src/xmmult.c           |   198 +
 .../drivers/mmult_v2_0/src/xmmult.h           |   108 +
 .../drivers/mmult_v2_0/src/xmmult_hw.h        |    50 +
 .../drivers/mmult_v2_0/src/xmmult_linux.c     |   147 +
 .../drivers/mmult_v2_0/src/xmmult_sinit.c     |    43 +
 .../hdl/verilog/mmult.v                       |  2318 ++++
 .../hdl/verilog/mmult_in1_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_in2_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_out_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_params_s_axi.v          |   393 +
 .../hdl/verilog/mmult_urem_96ns_3bkb.v        |   164 +
 .../hdl/vhdl/mmult.vhd                        |  2579 ++++
 .../hdl/vhdl/mmult_in1_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_in2_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_out_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_params_s_axi.vhd           |   439 +
 .../hdl/vhdl/mmult_urem_96ns_3bkb.vhd         |   219 +
 .../xilinx_com_hls_exercise_3/misc/logo.png   |   Bin 0 -> 4077 bytes
 .../xgui/mmult_v2_0.tcl                       |   529 +
 .../xilinx_com_hls_exercise_4/component.xml   |  5560 ++++++++
 .../constraints/mmult_ooc.xdc                 |     6 +
 .../doc/ReleaseNotes.txt                      |    10 +
 .../drivers/mmult_v3_0/data/mmult.mdd         |    16 +
 .../drivers/mmult_v3_0/data/mmult.tcl         |    21 +
 .../drivers/mmult_v3_0/src/Makefile           |    32 +
 .../drivers/mmult_v3_0/src/xmmult.c           |   198 +
 .../drivers/mmult_v3_0/src/xmmult.h           |   108 +
 .../drivers/mmult_v3_0/src/xmmult_hw.h        |    50 +
 .../drivers/mmult_v3_0/src/xmmult_linux.c     |   147 +
 .../drivers/mmult_v3_0/src/xmmult_sinit.c     |    43 +
 .../hdl/verilog/mmult.v                       |  1958 +++
 .../hdl/verilog/mmult_in1_loc.v               |    68 +
 .../hdl/verilog/mmult_in1_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_in2_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_out_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_params_s_axi.v          |   393 +
 .../hdl/vhdl/mmult.vhd                        |  2337 ++++
 .../hdl/vhdl/mmult_in1_loc.vhd                |   112 +
 .../hdl/vhdl/mmult_in1_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_in2_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_out_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_params_s_axi.vhd           |   439 +
 .../xilinx_com_hls_exercise_4/misc/logo.png   |   Bin 0 -> 4077 bytes
 .../xgui/mmult_v3_0.tcl                       |   529 +
 .../xilinx_com_hls_exercise_5/component.xml   |  5578 ++++++++
 .../constraints/mmult_ooc.xdc                 |     6 +
 .../doc/ReleaseNotes.txt                      |    10 +
 .../drivers/mmult_v4_0/data/mmult.mdd         |    16 +
 .../drivers/mmult_v4_0/data/mmult.tcl         |    21 +
 .../drivers/mmult_v4_0/src/Makefile           |    32 +
 .../drivers/mmult_v4_0/src/xmmult.c           |   198 +
 .../drivers/mmult_v4_0/src/xmmult.h           |   108 +
 .../drivers/mmult_v4_0/src/xmmult_hw.h        |    50 +
 .../drivers/mmult_v4_0/src/xmmult_linux.c     |   147 +
 .../drivers/mmult_v4_0/src/xmmult_sinit.c     |    43 +
 .../hdl/verilog/mmult.v                       |  4497 +++++++
 .../hdl/verilog/mmult_in1_loc.v               |    88 +
 .../hdl/verilog/mmult_in1_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_in2_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_out_loc.v               |    68 +
 .../hdl/verilog/mmult_out_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_params_s_axi.v          |   393 +
 .../hdl/vhdl/mmult.vhd                        |  4778 +++++++
 .../hdl/vhdl/mmult_in1_loc.vhd                |   146 +
 .../hdl/vhdl/mmult_in1_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_in2_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_out_loc.vhd                |   112 +
 .../hdl/vhdl/mmult_out_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_params_s_axi.vhd           |   439 +
 .../xilinx_com_hls_exercise_5/misc/logo.png   |   Bin 0 -> 4077 bytes
 .../xgui/mmult_v4_0.tcl                       |   529 +
 .../xilinx_com_hls_exercise_6/component.xml   |  5578 ++++++++
 .../constraints/mmult_ooc.xdc                 |     6 +
 .../doc/ReleaseNotes.txt                      |    10 +
 .../drivers/mmult_v6_0/data/mmult.mdd         |    16 +
 .../drivers/mmult_v6_0/data/mmult.tcl         |    21 +
 .../drivers/mmult_v6_0/src/Makefile           |    32 +
 .../drivers/mmult_v6_0/src/xmmult.c           |   198 +
 .../drivers/mmult_v6_0/src/xmmult.h           |   108 +
 .../drivers/mmult_v6_0/src/xmmult_hw.h        |    50 +
 .../drivers/mmult_v6_0/src/xmmult_linux.c     |   147 +
 .../drivers/mmult_v6_0/src/xmmult_sinit.c     |    43 +
 .../hdl/verilog/mmult.v                       |  8117 ++++++++++++
 .../hdl/verilog/mmult_in1_loc_0.v             |    68 +
 .../hdl/verilog/mmult_in1_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_in2_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_out_loc.v               |    68 +
 .../hdl/verilog/mmult_out_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_params_s_axi.v          |   393 +
 .../hdl/vhdl/mmult.vhd                        |  9139 ++++++++++++++
 .../hdl/vhdl/mmult_in1_loc_0.vhd              |   112 +
 .../hdl/vhdl/mmult_in1_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_in2_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_out_loc.vhd                |   112 +
 .../hdl/vhdl/mmult_out_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_params_s_axi.vhd           |   439 +
 .../xilinx_com_hls_exercise_6/misc/logo.png   |   Bin 0 -> 4077 bytes
 .../xgui/mmult_v6_0.tcl                       |   529 +
 .../xilinx_com_hls_exercise_7/component.xml   |  5578 ++++++++
 .../constraints/mmult_ooc.xdc                 |     6 +
 .../doc/ReleaseNotes.txt                      |    10 +
 .../drivers/mmult_v7_0/data/mmult.mdd         |    16 +
 .../drivers/mmult_v7_0/data/mmult.tcl         |    21 +
 .../drivers/mmult_v7_0/src/Makefile           |    32 +
 .../drivers/mmult_v7_0/src/xmmult.c           |   198 +
 .../drivers/mmult_v7_0/src/xmmult.h           |   108 +
 .../drivers/mmult_v7_0/src/xmmult_hw.h        |    50 +
 .../drivers/mmult_v7_0/src/xmmult_linux.c     |   147 +
 .../drivers/mmult_v7_0/src/xmmult_sinit.c     |    43 +
 .../hdl/verilog/mmult.v                       |  8287 ++++++++++++
 .../hdl/verilog/mmult_in1_loc_0.v             |    68 +
 .../hdl/verilog/mmult_in1_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_in2_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_out_loc.v               |    83 +
 .../hdl/verilog/mmult_out_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_params_s_axi.v          |   393 +
 .../hdl/vhdl/mmult.vhd                        |  9255 ++++++++++++++
 .../hdl/vhdl/mmult_in1_loc_0.vhd              |   112 +
 .../hdl/vhdl/mmult_in1_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_in2_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_out_loc.vhd                |   129 +
 .../hdl/vhdl/mmult_out_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_params_s_axi.vhd           |   439 +
 .../xilinx_com_hls_exercise_7/misc/logo.png   |   Bin 0 -> 4077 bytes
 .../xgui/mmult_v7_0.tcl                       |   529 +
 .../xilinx_com_hls_exercise_8/component.xml   |  5578 ++++++++
 .../constraints/mmult_ooc.xdc                 |     6 +
 .../doc/ReleaseNotes.txt                      |    10 +
 .../drivers/mmult_v8_0/data/mmult.mdd         |    16 +
 .../drivers/mmult_v8_0/data/mmult.tcl         |    21 +
 .../drivers/mmult_v8_0/src/Makefile           |    32 +
 .../drivers/mmult_v8_0/src/xmmult.c           |   198 +
 .../drivers/mmult_v8_0/src/xmmult.h           |   108 +
 .../drivers/mmult_v8_0/src/xmmult_hw.h        |    50 +
 .../drivers/mmult_v8_0/src/xmmult_linux.c     |   147 +
 .../drivers/mmult_v8_0/src/xmmult_sinit.c     |    43 +
 .../hdl/verilog/mmult.v                       |  8344 ++++++++++++
 .../hdl/verilog/mmult_in1_loc_0.v             |    68 +
 .../hdl/verilog/mmult_in1_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_in2_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_out_loc.v               |    83 +
 .../hdl/verilog/mmult_out_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_params_s_axi.v          |   393 +
 .../hdl/vhdl/mmult.vhd                        |  9452 ++++++++++++++
 .../hdl/vhdl/mmult_in1_loc_0.vhd              |   112 +
 .../hdl/vhdl/mmult_in1_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_in2_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_out_loc.vhd                |   129 +
 .../hdl/vhdl/mmult_out_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_params_s_axi.vhd           |   439 +
 .../xilinx_com_hls_exercise_8/misc/logo.png   |   Bin 0 -> 4077 bytes
 .../xgui/mmult_v8_0.tcl                       |   529 +
 .../xilinx_com_hls_exercise_9/component.xml   |  5614 ++++++++
 .../constraints/mmult_ooc.xdc                 |     6 +
 .../doc/ReleaseNotes.txt                      |    10 +
 .../drivers/mmult_v9_0/data/mmult.mdd         |    16 +
 .../drivers/mmult_v9_0/data/mmult.tcl         |    21 +
 .../drivers/mmult_v9_0/src/Makefile           |    32 +
 .../drivers/mmult_v9_0/src/xmmult.c           |   198 +
 .../drivers/mmult_v9_0/src/xmmult.h           |   108 +
 .../drivers/mmult_v9_0/src/xmmult_hw.h        |    50 +
 .../drivers/mmult_v9_0/src/xmmult_linux.c     |   147 +
 .../drivers/mmult_v9_0/src/xmmult_sinit.c     |    43 +
 .../hdl/verilog/mmult.v                       |  9314 ++++++++++++++
 .../hdl/verilog/mmult_in1_loc_0.v             |    68 +
 .../hdl/verilog/mmult_in1_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_in2_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_mul_32ns_32bkb.v        |    61 +
 .../hdl/verilog/mmult_mul_32s_32scud.v        |    61 +
 .../hdl/verilog/mmult_out_loc.v               |    83 +
 .../hdl/verilog/mmult_out_mem_m_axi.v         |  2692 ++++
 .../hdl/verilog/mmult_params_s_axi.v          |   393 +
 .../hdl/vhdl/mmult.vhd                        | 10532 ++++++++++++++++
 .../hdl/vhdl/mmult_in1_loc_0.vhd              |   112 +
 .../hdl/vhdl/mmult_in1_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_in2_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_mul_32ns_32bkb.vhd         |    88 +
 .../hdl/vhdl/mmult_mul_32s_32scud.vhd         |    88 +
 .../hdl/vhdl/mmult_out_loc.vhd                |   129 +
 .../hdl/vhdl/mmult_out_mem_m_axi.vhd          |  3306 +++++
 .../hdl/vhdl/mmult_params_s_axi.vhd           |   439 +
 .../xilinx_com_hls_exercise_9/misc/logo.png   |   Bin 0 -> 4077 bytes
 .../xgui/mmult_v9_0.tcl                       |   529 +
 hls/lab2/hw/exercise_1.xsa                    |   Bin 0 -> 1249344 bytes
 hls/lab2/hw/exercise_2.xsa                    |   Bin 0 -> 1360510 bytes
 hls/lab2/hw/exercise_3.xsa                    |   Bin 0 -> 1721345 bytes
 hls/lab2/hw/exercise_4.xsa                    |   Bin 0 -> 1356701 bytes
 hls/lab2/hw/exercise_5.xsa                    |   Bin 0 -> 1600326 bytes
 hls/lab2/hw/exercise_6.xsa                    |   Bin 0 -> 1660334 bytes
 hls/lab2/hw/exercise_7.xsa                    |   Bin 0 -> 1672595 bytes
 hls/lab2/hw/exercise_8.xsa                    |   Bin 0 -> 1698646 bytes
 hls/lab2/hw/exercise_9.xsa                    |   Bin 0 -> 1713599 bytes
 hls/lab2/sw/lscript.ld                        |   322 +
 hls/lab2/sw/main.c                            |   102 +
 hls/lab2/sw/platform.c                        |   111 +
 hls/lab2/sw/platform.h                        |    41 +
 hls/lab2/sw/platform_config.h                 |     6 +
 237 files changed, 310679 insertions(+)
 create mode 100644 hls/lab2/README.md
 delete mode 100644 hls/lab2/TODO
 create mode 100644 hls/lab2/exercise_1.tcl
 create mode 100644 hls/lab2/exercise_2.tcl
 create mode 100644 hls/lab2/exercise_3.tcl
 create mode 100644 hls/lab2/exercise_4.tcl
 create mode 100644 hls/lab2/exercise_5.tcl
 create mode 100644 hls/lab2/exercise_6.tcl
 create mode 100644 hls/lab2/exercise_7.tcl
 create mode 100644 hls/lab2/exercise_8.tcl
 create mode 100644 hls/lab2/exercise_9.tcl
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/component.xml
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/constraints/mmult_ooc.xdc
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/doc/ReleaseNotes.txt
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.mdd
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.tcl
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/Makefile
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.c
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.h
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_hw.h
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_linux.c
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_sinit.c
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult.v
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_in1_mem_m_axi.v
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_in2_mem_m_axi.v
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_out_mem_m_axi.v
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_params_s_axi.v
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult.vhd
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_in1_mem_m_axi.vhd
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_in2_mem_m_axi.vhd
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_out_mem_m_axi.vhd
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_params_s_axi.vhd
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/misc/logo.png
 create mode 100644 hls/lab2/exported_ips/xilinx_com_hls_exercise_2/xgui/mmult_v1_0.tcl
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/component.xml
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/constraints/mmult_ooc.xdc
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/doc/ReleaseNotes.txt
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.mdd
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.tcl
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/Makefile
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.c
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.h
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_hw.h
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_linux.c
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 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_9/misc/logo.png
 create mode 100755 hls/lab2/exported_ips/xilinx_com_hls_exercise_9/xgui/mmult_v9_0.tcl
 create mode 100644 hls/lab2/hw/exercise_1.xsa
 create mode 100644 hls/lab2/hw/exercise_2.xsa
 create mode 100644 hls/lab2/hw/exercise_3.xsa
 create mode 100644 hls/lab2/hw/exercise_4.xsa
 create mode 100644 hls/lab2/hw/exercise_5.xsa
 create mode 100644 hls/lab2/hw/exercise_6.xsa
 create mode 100644 hls/lab2/hw/exercise_7.xsa
 create mode 100644 hls/lab2/hw/exercise_8.xsa
 create mode 100644 hls/lab2/hw/exercise_9.xsa
 create mode 100644 hls/lab2/sw/lscript.ld
 create mode 100644 hls/lab2/sw/main.c
 create mode 100644 hls/lab2/sw/platform.c
 create mode 100644 hls/lab2/sw/platform.h
 create mode 100644 hls/lab2/sw/platform_config.h

diff --git a/hls/lab2/README.md b/hls/lab2/README.md
new file mode 100644
index 0000000..262689e
--- /dev/null
+++ b/hls/lab2/README.md
@@ -0,0 +1,9 @@
+exercise 1: design solo PS e AXI Timer;
+exercise 2: mmult baseline
+exercise 3: mmult pipelined
+exercise 4: mmult con BRAM
+exercise 5: mmult Unrolled
+exercise 6: mmult Array Part
+exercise 7: mmult Pipeline outer
+exercise 8: mmult Pipeline outer 200MHz
+exercise 9: mmult Pipeline outer 300MHz
\ No newline at end of file
diff --git a/hls/lab2/TODO b/hls/lab2/TODO
deleted file mode 100644
index e69de29..0000000
diff --git a/hls/lab2/exercise_1.tcl b/hls/lab2/exercise_1.tcl
new file mode 100644
index 0000000..f1ef726
--- /dev/null
+++ b/hls/lab2/exercise_1.tcl
@@ -0,0 +1,950 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {1} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exercise_2.tcl b/hls/lab2/exercise_2.tcl
new file mode 100644
index 0000000..b04eebc
--- /dev/null
+++ b/hls/lab2/exercise_2.tcl
@@ -0,0 +1,976 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_2} [current_project]
+update_ip_catalog
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:1.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exercise_3.tcl b/hls/lab2/exercise_3.tcl
new file mode 100644
index 0000000..83612b9
--- /dev/null
+++ b/hls/lab2/exercise_3.tcl
@@ -0,0 +1,971 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_3} [current_project]
+update_ip_catalog
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:2.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:2.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exercise_4.tcl b/hls/lab2/exercise_4.tcl
new file mode 100644
index 0000000..4293283
--- /dev/null
+++ b/hls/lab2/exercise_4.tcl
@@ -0,0 +1,975 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_4} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:3.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:3.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exercise_5.tcl b/hls/lab2/exercise_5.tcl
new file mode 100644
index 0000000..9e0e9f7
--- /dev/null
+++ b/hls/lab2/exercise_5.tcl
@@ -0,0 +1,975 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_5} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:4.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:4.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exercise_6.tcl b/hls/lab2/exercise_6.tcl
new file mode 100644
index 0000000..799ac57
--- /dev/null
+++ b/hls/lab2/exercise_6.tcl
@@ -0,0 +1,975 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_6} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:6.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:6.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exercise_7.tcl b/hls/lab2/exercise_7.tcl
new file mode 100644
index 0000000..047f938
--- /dev/null
+++ b/hls/lab2/exercise_7.tcl
@@ -0,0 +1,975 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_7} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:7.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:7.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exercise_8.tcl b/hls/lab2/exercise_8.tcl
new file mode 100644
index 0000000..9c9eebd
--- /dev/null
+++ b/hls/lab2/exercise_8.tcl
@@ -0,0 +1,989 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_8} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:ip:clk_wiz:6.0\
+xilinx.com:hls:mmult:8.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: clk_wiz_0, and set properties
+  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+  set_property -dict [ list \
+   CONFIG.CLKOUT1_JITTER {102.086} \
+   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
+   CONFIG.CLK_OUT1_PORT {clk_out_200} \
+   CONFIG.MMCM_CLKOUT0_DIVIDE_F {6.000} \
+   CONFIG.RESET_PORT {resetn} \
+   CONFIG.RESET_TYPE {ACTIVE_LOW} \
+ ] $clk_wiz_0
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:8.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_ps8_0_100M/dcm_locked]
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out_200] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk1 [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins clk_wiz_0/resetn] [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exercise_9.tcl b/hls/lab2/exercise_9.tcl
new file mode 100644
index 0000000..0aab834
--- /dev/null
+++ b/hls/lab2/exercise_9.tcl
@@ -0,0 +1,989 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_9} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:ip:clk_wiz:6.0\
+xilinx.com:hls:mmult:9.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: clk_wiz_0, and set properties
+  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+  set_property -dict [ list \
+   CONFIG.CLKOUT1_JITTER {94.862} \
+   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {300.000} \
+   CONFIG.CLK_OUT1_PORT {clk_out_300} \
+   CONFIG.MMCM_CLKOUT0_DIVIDE_F {4.000} \
+   CONFIG.RESET_PORT {resetn} \
+   CONFIG.RESET_TYPE {ACTIVE_LOW} \
+ ] $clk_wiz_0
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:9.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_ps8_0_100M/dcm_locked]
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out_300] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk1 [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins clk_wiz_0/resetn] [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/component.xml b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/component.xml
new file mode 100644
index 0000000..066e55e
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/component.xml
@@ -0,0 +1,5542 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>hls</spirit:library>
+  <spirit:name>mmult</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_params"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.ADDR_WIDTH">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi_params:m_axi_in1_mem:m_axi_in2_mem:m_axi_out_mem</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interrupt</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in1_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in1_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in2_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in2_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_out_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_out_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in1_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in2_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_out_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_BASE_PARAM">C_S_AXI_PARAMS_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_HIGH_PARAM">C_S_AXI_PARAMS_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>CTRL</spirit:name>
+          <spirit:displayName>CTRL</spirit:displayName>
+          <spirit:description>Control signals</spirit:description>
+          <spirit:addressOffset>0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>AP_START</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_start&apos;.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_DONE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_done&apos;.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_IDLE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_idle&apos;.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_READY</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_ready&apos;.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_1</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">3</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AUTO_RESTART</spirit:name>
+            <spirit:description>Control signal Register for &apos;auto_restart&apos;.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_2</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">24</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GIER</spirit:name>
+          <spirit:displayName>GIER</spirit:displayName>
+          <spirit:description>Global Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>4</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Enable</spirit:name>
+            <spirit:description>Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">31</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_IER</spirit:name>
+          <spirit:displayName>IP_IER</spirit:displayName>
+          <spirit:description>IP Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>8</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 0 (ap_done) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 1 (ap_ready) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_ISR</spirit:name>
+          <spirit:displayName>IP_ISR</spirit:displayName>
+          <spirit:description>IP Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>12</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_ST</spirit:name>
+            <spirit:description>Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 input interrupt, 1 = Channel 0 input interrup</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
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+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_documentation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>doc/ReleaseNotes.txt</spirit:name>
+        <spirit:userFileType>text</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_miscfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>misc/logo.png</spirit:name>
+        <spirit:userFileType>image</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/mmult_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_3f68c42e</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>misc/logo.png</spirit:name>
+        <spirit:userFileType>image</spirit:userFileType>
+        <spirit:userFileType>LOGO</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>An IP generated by Vivado HLS</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" spirit:order="2" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH" spirit:order="3" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="4" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" spirit:order="5" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH" spirit:order="6" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH" spirit:order="7" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH" spirit:order="8" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH" spirit:order="9" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH" spirit:order="10" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE" spirit:order="11" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE" spirit:order="12" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE" spirit:order="13" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" spirit:order="14" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH" spirit:order="15" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="16" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" spirit:order="17" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH" spirit:order="18" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH" spirit:order="19" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH" spirit:order="20" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH" spirit:order="21" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH" spirit:order="22" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE" spirit:order="23" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE" spirit:order="24" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE" spirit:order="25" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" spirit:order="26" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH" spirit:order="27" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="28" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" spirit:order="29" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH" spirit:order="30" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH" spirit:order="31" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH" spirit:order="32" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH" spirit:order="33" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH" spirit:order="34" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE" spirit:order="35" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE" spirit:order="36" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE" spirit:order="37" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mmult_v1_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>clk_period</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.clk_period" spirit:order="38">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>machine</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.machine" spirit:order="39">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>combinational</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.combinational" spirit:order="40">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>latency</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.latency" spirit:order="41">4227201</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>II</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.II" spirit:order="42">x</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/VIVADO_HLS_IP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>Mmult</xilinx:displayName>
+      <xilinx:definitionSource>HLS</xilinx:definitionSource>
+      <xilinx:coreRevision>2105141655</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2021-05-14T14:55:50Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b5dd57e8"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="c6fd4807"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5ce530f0"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d0a00725"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="7681d788"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c9a673dd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="187d9165"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/constraints/mmult_ooc.xdc b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/constraints/mmult_ooc.xdc
new file mode 100644
index 0000000..2ed5eee
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/constraints/mmult_ooc.xdc
@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/doc/ReleaseNotes.txt b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/doc/ReleaseNotes.txt
new file mode 100644
index 0000000..48cc01b
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/doc/ReleaseNotes.txt
@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.mdd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.mdd
new file mode 100644
index 0000000..003057c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.mdd
@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v1_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 1.0;
+
+END driver
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.tcl
new file mode 100644
index 0000000..0de7a9c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.tcl
@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/Makefile b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/Makefile
new file mode 100644
index 0000000..7f76086
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/Makefile
@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.c
new file mode 100644
index 0000000..fb9a1fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.c
@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.h
new file mode 100644
index 0000000..4983669
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.h
@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_hw.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_hw.h
new file mode 100644
index 0000000..3a0a2a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_hw.h
@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_linux.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_linux.c
new file mode 100644
index 0000000..c8dbb33
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_linux.c
@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_sinit.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_sinit.c
new file mode 100644
index 0000000..f099590
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_sinit.c
@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult.v
new file mode 100644
index 0000000..fa39bf4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult.v
@@ -0,0 +1,1411 @@
+// ==============================================================
+// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+// Version: 2020.1
+// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+// 
+// ===========================================================
+
+`timescale 1 ns / 1 ps 
+
+(* CORE_GENERATION_INFO="mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=4227201,HLS_SYN_TPT=none,HLS_SYN_MEM=6,HLS_SYN_DSP=3,HLS_SYN_FF=2413,HLS_SYN_LUT=2800,HLS_VERSION=2020_1}" *)
+
+module mmult (
+        ap_clk,
+        ap_rst_n,
+        m_axi_in1_mem_AWVALID,
+        m_axi_in1_mem_AWREADY,
+        m_axi_in1_mem_AWADDR,
+        m_axi_in1_mem_AWID,
+        m_axi_in1_mem_AWLEN,
+        m_axi_in1_mem_AWSIZE,
+        m_axi_in1_mem_AWBURST,
+        m_axi_in1_mem_AWLOCK,
+        m_axi_in1_mem_AWCACHE,
+        m_axi_in1_mem_AWPROT,
+        m_axi_in1_mem_AWQOS,
+        m_axi_in1_mem_AWREGION,
+        m_axi_in1_mem_AWUSER,
+        m_axi_in1_mem_WVALID,
+        m_axi_in1_mem_WREADY,
+        m_axi_in1_mem_WDATA,
+        m_axi_in1_mem_WSTRB,
+        m_axi_in1_mem_WLAST,
+        m_axi_in1_mem_WID,
+        m_axi_in1_mem_WUSER,
+        m_axi_in1_mem_ARVALID,
+        m_axi_in1_mem_ARREADY,
+        m_axi_in1_mem_ARADDR,
+        m_axi_in1_mem_ARID,
+        m_axi_in1_mem_ARLEN,
+        m_axi_in1_mem_ARSIZE,
+        m_axi_in1_mem_ARBURST,
+        m_axi_in1_mem_ARLOCK,
+        m_axi_in1_mem_ARCACHE,
+        m_axi_in1_mem_ARPROT,
+        m_axi_in1_mem_ARQOS,
+        m_axi_in1_mem_ARREGION,
+        m_axi_in1_mem_ARUSER,
+        m_axi_in1_mem_RVALID,
+        m_axi_in1_mem_RREADY,
+        m_axi_in1_mem_RDATA,
+        m_axi_in1_mem_RLAST,
+        m_axi_in1_mem_RID,
+        m_axi_in1_mem_RUSER,
+        m_axi_in1_mem_RRESP,
+        m_axi_in1_mem_BVALID,
+        m_axi_in1_mem_BREADY,
+        m_axi_in1_mem_BRESP,
+        m_axi_in1_mem_BID,
+        m_axi_in1_mem_BUSER,
+        m_axi_in2_mem_AWVALID,
+        m_axi_in2_mem_AWREADY,
+        m_axi_in2_mem_AWADDR,
+        m_axi_in2_mem_AWID,
+        m_axi_in2_mem_AWLEN,
+        m_axi_in2_mem_AWSIZE,
+        m_axi_in2_mem_AWBURST,
+        m_axi_in2_mem_AWLOCK,
+        m_axi_in2_mem_AWCACHE,
+        m_axi_in2_mem_AWPROT,
+        m_axi_in2_mem_AWQOS,
+        m_axi_in2_mem_AWREGION,
+        m_axi_in2_mem_AWUSER,
+        m_axi_in2_mem_WVALID,
+        m_axi_in2_mem_WREADY,
+        m_axi_in2_mem_WDATA,
+        m_axi_in2_mem_WSTRB,
+        m_axi_in2_mem_WLAST,
+        m_axi_in2_mem_WID,
+        m_axi_in2_mem_WUSER,
+        m_axi_in2_mem_ARVALID,
+        m_axi_in2_mem_ARREADY,
+        m_axi_in2_mem_ARADDR,
+        m_axi_in2_mem_ARID,
+        m_axi_in2_mem_ARLEN,
+        m_axi_in2_mem_ARSIZE,
+        m_axi_in2_mem_ARBURST,
+        m_axi_in2_mem_ARLOCK,
+        m_axi_in2_mem_ARCACHE,
+        m_axi_in2_mem_ARPROT,
+        m_axi_in2_mem_ARQOS,
+        m_axi_in2_mem_ARREGION,
+        m_axi_in2_mem_ARUSER,
+        m_axi_in2_mem_RVALID,
+        m_axi_in2_mem_RREADY,
+        m_axi_in2_mem_RDATA,
+        m_axi_in2_mem_RLAST,
+        m_axi_in2_mem_RID,
+        m_axi_in2_mem_RUSER,
+        m_axi_in2_mem_RRESP,
+        m_axi_in2_mem_BVALID,
+        m_axi_in2_mem_BREADY,
+        m_axi_in2_mem_BRESP,
+        m_axi_in2_mem_BID,
+        m_axi_in2_mem_BUSER,
+        m_axi_out_mem_AWVALID,
+        m_axi_out_mem_AWREADY,
+        m_axi_out_mem_AWADDR,
+        m_axi_out_mem_AWID,
+        m_axi_out_mem_AWLEN,
+        m_axi_out_mem_AWSIZE,
+        m_axi_out_mem_AWBURST,
+        m_axi_out_mem_AWLOCK,
+        m_axi_out_mem_AWCACHE,
+        m_axi_out_mem_AWPROT,
+        m_axi_out_mem_AWQOS,
+        m_axi_out_mem_AWREGION,
+        m_axi_out_mem_AWUSER,
+        m_axi_out_mem_WVALID,
+        m_axi_out_mem_WREADY,
+        m_axi_out_mem_WDATA,
+        m_axi_out_mem_WSTRB,
+        m_axi_out_mem_WLAST,
+        m_axi_out_mem_WID,
+        m_axi_out_mem_WUSER,
+        m_axi_out_mem_ARVALID,
+        m_axi_out_mem_ARREADY,
+        m_axi_out_mem_ARADDR,
+        m_axi_out_mem_ARID,
+        m_axi_out_mem_ARLEN,
+        m_axi_out_mem_ARSIZE,
+        m_axi_out_mem_ARBURST,
+        m_axi_out_mem_ARLOCK,
+        m_axi_out_mem_ARCACHE,
+        m_axi_out_mem_ARPROT,
+        m_axi_out_mem_ARQOS,
+        m_axi_out_mem_ARREGION,
+        m_axi_out_mem_ARUSER,
+        m_axi_out_mem_RVALID,
+        m_axi_out_mem_RREADY,
+        m_axi_out_mem_RDATA,
+        m_axi_out_mem_RLAST,
+        m_axi_out_mem_RID,
+        m_axi_out_mem_RUSER,
+        m_axi_out_mem_RRESP,
+        m_axi_out_mem_BVALID,
+        m_axi_out_mem_BREADY,
+        m_axi_out_mem_BRESP,
+        m_axi_out_mem_BID,
+        m_axi_out_mem_BUSER,
+        s_axi_params_AWVALID,
+        s_axi_params_AWREADY,
+        s_axi_params_AWADDR,
+        s_axi_params_WVALID,
+        s_axi_params_WREADY,
+        s_axi_params_WDATA,
+        s_axi_params_WSTRB,
+        s_axi_params_ARVALID,
+        s_axi_params_ARREADY,
+        s_axi_params_ARADDR,
+        s_axi_params_RVALID,
+        s_axi_params_RREADY,
+        s_axi_params_RDATA,
+        s_axi_params_RRESP,
+        s_axi_params_BVALID,
+        s_axi_params_BREADY,
+        s_axi_params_BRESP,
+        interrupt
+);
+
+parameter    ap_ST_fsm_state1 = 25'd1;
+parameter    ap_ST_fsm_state2 = 25'd2;
+parameter    ap_ST_fsm_state3 = 25'd4;
+parameter    ap_ST_fsm_state4 = 25'd8;
+parameter    ap_ST_fsm_state5 = 25'd16;
+parameter    ap_ST_fsm_state6 = 25'd32;
+parameter    ap_ST_fsm_state7 = 25'd64;
+parameter    ap_ST_fsm_state8 = 25'd128;
+parameter    ap_ST_fsm_state9 = 25'd256;
+parameter    ap_ST_fsm_state10 = 25'd512;
+parameter    ap_ST_fsm_state11 = 25'd1024;
+parameter    ap_ST_fsm_state12 = 25'd2048;
+parameter    ap_ST_fsm_state13 = 25'd4096;
+parameter    ap_ST_fsm_state14 = 25'd8192;
+parameter    ap_ST_fsm_state15 = 25'd16384;
+parameter    ap_ST_fsm_state16 = 25'd32768;
+parameter    ap_ST_fsm_state17 = 25'd65536;
+parameter    ap_ST_fsm_state18 = 25'd131072;
+parameter    ap_ST_fsm_state19 = 25'd262144;
+parameter    ap_ST_fsm_state20 = 25'd524288;
+parameter    ap_ST_fsm_state21 = 25'd1048576;
+parameter    ap_ST_fsm_state22 = 25'd2097152;
+parameter    ap_ST_fsm_state23 = 25'd4194304;
+parameter    ap_ST_fsm_state24 = 25'd8388608;
+parameter    ap_ST_fsm_state25 = 25'd16777216;
+parameter    C_S_AXI_PARAMS_DATA_WIDTH = 32;
+parameter    C_S_AXI_PARAMS_ADDR_WIDTH = 6;
+parameter    C_S_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_OUT_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_CACHE_VALUE = 3;
+
+parameter C_S_AXI_PARAMS_WSTRB_WIDTH = (32 / 8);
+parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN1_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN2_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_OUT_MEM_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+output   m_axi_in1_mem_AWVALID;
+input   m_axi_in1_mem_AWREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_AWADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_AWID;
+output  [7:0] m_axi_in1_mem_AWLEN;
+output  [2:0] m_axi_in1_mem_AWSIZE;
+output  [1:0] m_axi_in1_mem_AWBURST;
+output  [1:0] m_axi_in1_mem_AWLOCK;
+output  [3:0] m_axi_in1_mem_AWCACHE;
+output  [2:0] m_axi_in1_mem_AWPROT;
+output  [3:0] m_axi_in1_mem_AWQOS;
+output  [3:0] m_axi_in1_mem_AWREGION;
+output  [C_M_AXI_IN1_MEM_AWUSER_WIDTH - 1:0] m_axi_in1_mem_AWUSER;
+output   m_axi_in1_mem_WVALID;
+input   m_axi_in1_mem_WREADY;
+output  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_WDATA;
+output  [C_M_AXI_IN1_MEM_WSTRB_WIDTH - 1:0] m_axi_in1_mem_WSTRB;
+output   m_axi_in1_mem_WLAST;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_WID;
+output  [C_M_AXI_IN1_MEM_WUSER_WIDTH - 1:0] m_axi_in1_mem_WUSER;
+output   m_axi_in1_mem_ARVALID;
+input   m_axi_in1_mem_ARREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_ARADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_ARID;
+output  [7:0] m_axi_in1_mem_ARLEN;
+output  [2:0] m_axi_in1_mem_ARSIZE;
+output  [1:0] m_axi_in1_mem_ARBURST;
+output  [1:0] m_axi_in1_mem_ARLOCK;
+output  [3:0] m_axi_in1_mem_ARCACHE;
+output  [2:0] m_axi_in1_mem_ARPROT;
+output  [3:0] m_axi_in1_mem_ARQOS;
+output  [3:0] m_axi_in1_mem_ARREGION;
+output  [C_M_AXI_IN1_MEM_ARUSER_WIDTH - 1:0] m_axi_in1_mem_ARUSER;
+input   m_axi_in1_mem_RVALID;
+output   m_axi_in1_mem_RREADY;
+input  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_RDATA;
+input   m_axi_in1_mem_RLAST;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_RID;
+input  [C_M_AXI_IN1_MEM_RUSER_WIDTH - 1:0] m_axi_in1_mem_RUSER;
+input  [1:0] m_axi_in1_mem_RRESP;
+input   m_axi_in1_mem_BVALID;
+output   m_axi_in1_mem_BREADY;
+input  [1:0] m_axi_in1_mem_BRESP;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_BID;
+input  [C_M_AXI_IN1_MEM_BUSER_WIDTH - 1:0] m_axi_in1_mem_BUSER;
+output   m_axi_in2_mem_AWVALID;
+input   m_axi_in2_mem_AWREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_AWADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_AWID;
+output  [7:0] m_axi_in2_mem_AWLEN;
+output  [2:0] m_axi_in2_mem_AWSIZE;
+output  [1:0] m_axi_in2_mem_AWBURST;
+output  [1:0] m_axi_in2_mem_AWLOCK;
+output  [3:0] m_axi_in2_mem_AWCACHE;
+output  [2:0] m_axi_in2_mem_AWPROT;
+output  [3:0] m_axi_in2_mem_AWQOS;
+output  [3:0] m_axi_in2_mem_AWREGION;
+output  [C_M_AXI_IN2_MEM_AWUSER_WIDTH - 1:0] m_axi_in2_mem_AWUSER;
+output   m_axi_in2_mem_WVALID;
+input   m_axi_in2_mem_WREADY;
+output  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_WDATA;
+output  [C_M_AXI_IN2_MEM_WSTRB_WIDTH - 1:0] m_axi_in2_mem_WSTRB;
+output   m_axi_in2_mem_WLAST;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_WID;
+output  [C_M_AXI_IN2_MEM_WUSER_WIDTH - 1:0] m_axi_in2_mem_WUSER;
+output   m_axi_in2_mem_ARVALID;
+input   m_axi_in2_mem_ARREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_ARADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_ARID;
+output  [7:0] m_axi_in2_mem_ARLEN;
+output  [2:0] m_axi_in2_mem_ARSIZE;
+output  [1:0] m_axi_in2_mem_ARBURST;
+output  [1:0] m_axi_in2_mem_ARLOCK;
+output  [3:0] m_axi_in2_mem_ARCACHE;
+output  [2:0] m_axi_in2_mem_ARPROT;
+output  [3:0] m_axi_in2_mem_ARQOS;
+output  [3:0] m_axi_in2_mem_ARREGION;
+output  [C_M_AXI_IN2_MEM_ARUSER_WIDTH - 1:0] m_axi_in2_mem_ARUSER;
+input   m_axi_in2_mem_RVALID;
+output   m_axi_in2_mem_RREADY;
+input  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_RDATA;
+input   m_axi_in2_mem_RLAST;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_RID;
+input  [C_M_AXI_IN2_MEM_RUSER_WIDTH - 1:0] m_axi_in2_mem_RUSER;
+input  [1:0] m_axi_in2_mem_RRESP;
+input   m_axi_in2_mem_BVALID;
+output   m_axi_in2_mem_BREADY;
+input  [1:0] m_axi_in2_mem_BRESP;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_BID;
+input  [C_M_AXI_IN2_MEM_BUSER_WIDTH - 1:0] m_axi_in2_mem_BUSER;
+output   m_axi_out_mem_AWVALID;
+input   m_axi_out_mem_AWREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_AWADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_AWID;
+output  [7:0] m_axi_out_mem_AWLEN;
+output  [2:0] m_axi_out_mem_AWSIZE;
+output  [1:0] m_axi_out_mem_AWBURST;
+output  [1:0] m_axi_out_mem_AWLOCK;
+output  [3:0] m_axi_out_mem_AWCACHE;
+output  [2:0] m_axi_out_mem_AWPROT;
+output  [3:0] m_axi_out_mem_AWQOS;
+output  [3:0] m_axi_out_mem_AWREGION;
+output  [C_M_AXI_OUT_MEM_AWUSER_WIDTH - 1:0] m_axi_out_mem_AWUSER;
+output   m_axi_out_mem_WVALID;
+input   m_axi_out_mem_WREADY;
+output  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_WDATA;
+output  [C_M_AXI_OUT_MEM_WSTRB_WIDTH - 1:0] m_axi_out_mem_WSTRB;
+output   m_axi_out_mem_WLAST;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_WID;
+output  [C_M_AXI_OUT_MEM_WUSER_WIDTH - 1:0] m_axi_out_mem_WUSER;
+output   m_axi_out_mem_ARVALID;
+input   m_axi_out_mem_ARREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_ARADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_ARID;
+output  [7:0] m_axi_out_mem_ARLEN;
+output  [2:0] m_axi_out_mem_ARSIZE;
+output  [1:0] m_axi_out_mem_ARBURST;
+output  [1:0] m_axi_out_mem_ARLOCK;
+output  [3:0] m_axi_out_mem_ARCACHE;
+output  [2:0] m_axi_out_mem_ARPROT;
+output  [3:0] m_axi_out_mem_ARQOS;
+output  [3:0] m_axi_out_mem_ARREGION;
+output  [C_M_AXI_OUT_MEM_ARUSER_WIDTH - 1:0] m_axi_out_mem_ARUSER;
+input   m_axi_out_mem_RVALID;
+output   m_axi_out_mem_RREADY;
+input  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_RDATA;
+input   m_axi_out_mem_RLAST;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_RID;
+input  [C_M_AXI_OUT_MEM_RUSER_WIDTH - 1:0] m_axi_out_mem_RUSER;
+input  [1:0] m_axi_out_mem_RRESP;
+input   m_axi_out_mem_BVALID;
+output   m_axi_out_mem_BREADY;
+input  [1:0] m_axi_out_mem_BRESP;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_BID;
+input  [C_M_AXI_OUT_MEM_BUSER_WIDTH - 1:0] m_axi_out_mem_BUSER;
+input   s_axi_params_AWVALID;
+output   s_axi_params_AWREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_AWADDR;
+input   s_axi_params_WVALID;
+output   s_axi_params_WREADY;
+input  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_WDATA;
+input  [C_S_AXI_PARAMS_WSTRB_WIDTH - 1:0] s_axi_params_WSTRB;
+input   s_axi_params_ARVALID;
+output   s_axi_params_ARREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_ARADDR;
+output   s_axi_params_RVALID;
+input   s_axi_params_RREADY;
+output  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_RDATA;
+output  [1:0] s_axi_params_RRESP;
+output   s_axi_params_BVALID;
+input   s_axi_params_BREADY;
+output  [1:0] s_axi_params_BRESP;
+output   interrupt;
+
+ reg    ap_rst_n_inv;
+wire    ap_start;
+reg    ap_done;
+reg    ap_idle;
+(* fsm_encoding = "none" *) reg   [24:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    ap_ready;
+wire   [31:0] in1;
+wire   [31:0] in2;
+wire   [31:0] out_r;
+wire   [31:0] dim;
+reg    in1_mem_blk_n_AR;
+wire    ap_CS_fsm_state3;
+wire   [0:0] icmp_ln20_fu_301_p2;
+reg    in1_mem_blk_n_R;
+wire    ap_CS_fsm_state18;
+reg    in2_mem_blk_n_AR;
+wire    ap_CS_fsm_state11;
+reg    in2_mem_blk_n_R;
+reg    out_mem_blk_n_AR;
+reg    out_mem_blk_n_R;
+reg    out_mem_blk_n_AW;
+wire    ap_CS_fsm_state19;
+reg    out_mem_blk_n_W;
+wire    ap_CS_fsm_state20;
+reg    out_mem_blk_n_B;
+wire    ap_CS_fsm_state25;
+wire    in1_mem_AWREADY;
+wire    in1_mem_WREADY;
+reg    in1_mem_ARVALID;
+wire    in1_mem_ARREADY;
+wire    in1_mem_RVALID;
+reg    in1_mem_RREADY;
+wire   [31:0] in1_mem_RDATA;
+wire    in1_mem_RLAST;
+wire   [0:0] in1_mem_RID;
+wire   [0:0] in1_mem_RUSER;
+wire   [1:0] in1_mem_RRESP;
+wire    in1_mem_BVALID;
+wire   [1:0] in1_mem_BRESP;
+wire   [0:0] in1_mem_BID;
+wire   [0:0] in1_mem_BUSER;
+wire    in2_mem_AWREADY;
+wire    in2_mem_WREADY;
+reg    in2_mem_ARVALID;
+wire    in2_mem_ARREADY;
+wire    in2_mem_RVALID;
+reg    in2_mem_RREADY;
+wire   [31:0] in2_mem_RDATA;
+wire    in2_mem_RLAST;
+wire   [0:0] in2_mem_RID;
+wire   [0:0] in2_mem_RUSER;
+wire   [1:0] in2_mem_RRESP;
+wire    in2_mem_BVALID;
+wire   [1:0] in2_mem_BRESP;
+wire   [0:0] in2_mem_BID;
+wire   [0:0] in2_mem_BUSER;
+reg    out_mem_AWVALID;
+wire    out_mem_AWREADY;
+reg    out_mem_WVALID;
+wire    out_mem_WREADY;
+reg    out_mem_ARVALID;
+wire    out_mem_ARREADY;
+wire    out_mem_RVALID;
+reg    out_mem_RREADY;
+wire   [31:0] out_mem_RDATA;
+wire    out_mem_RLAST;
+wire   [0:0] out_mem_RID;
+wire   [0:0] out_mem_RUSER;
+wire   [1:0] out_mem_RRESP;
+wire    out_mem_BVALID;
+reg    out_mem_BREADY;
+wire   [1:0] out_mem_BRESP;
+wire   [0:0] out_mem_BID;
+wire   [0:0] out_mem_BUSER;
+reg   [31:0] dim_read_reg_387;
+wire   [32:0] p_cast11_fu_230_p1;
+reg   [32:0] p_cast11_reg_397;
+wire   [32:0] p_cast10_fu_244_p1;
+reg   [32:0] p_cast10_reg_402;
+wire   [32:0] p_cast_fu_258_p1;
+reg   [32:0] p_cast_reg_407;
+wire   [31:0] add_ln18_fu_262_p2;
+reg   [31:0] add_ln18_reg_412;
+wire    ap_CS_fsm_state2;
+wire   [30:0] i_fu_276_p2;
+reg   [30:0] i_reg_420;
+reg   [31:0] in1_mem_addr_reg_425;
+wire   [0:0] icmp_ln18_fu_271_p2;
+wire   [31:0] j_fu_306_p2;
+reg   [31:0] j_reg_434;
+reg    ap_block_state3_io;
+reg   [31:0] out_mem_addr_reg_439;
+wire   [31:0] k_fu_342_p2;
+reg   [31:0] k_reg_449;
+wire    ap_CS_fsm_state10;
+wire   [31:0] add_ln25_5_fu_348_p2;
+reg   [31:0] add_ln25_5_reg_454;
+wire   [0:0] icmp_ln22_fu_337_p2;
+reg   [31:0] in2_mem_addr_reg_459;
+reg  signed [31:0] in1_mem_addr_read_reg_465;
+reg    ap_block_state18;
+reg  signed [31:0] in2_mem_addr_read_reg_470;
+reg   [31:0] out_mem_addr_read_reg_475;
+wire   [31:0] add_ln25_3_fu_382_p2;
+reg   [31:0] add_ln25_3_reg_480;
+reg   [30:0] i_0_reg_163;
+reg  signed [31:0] phi_mul8_reg_174;
+reg   [31:0] j_0_reg_186;
+reg   [31:0] k_0_reg_198;
+wire    ap_CS_fsm_state9;
+reg   [31:0] phi_mul_reg_209;
+wire  signed [63:0] sext_ln25_1_fu_291_p1;
+wire  signed [63:0] sext_ln25_3_fu_327_p1;
+wire  signed [63:0] sext_ln25_5_fu_368_p1;
+reg    ap_block_state11_io;
+wire   [29:0] tmp_3_fu_220_p4;
+wire   [29:0] tmp_4_fu_234_p4;
+wire   [29:0] tmp_5_fu_248_p4;
+wire   [31:0] zext_ln18_fu_267_p1;
+wire  signed [32:0] sext_ln25_fu_282_p1;
+wire   [32:0] add_ln25_1_fu_286_p2;
+wire   [31:0] add_ln25_fu_312_p2;
+wire  signed [32:0] sext_ln25_2_fu_318_p1;
+wire   [32:0] add_ln25_4_fu_322_p2;
+wire   [31:0] add_ln25_2_fu_353_p2;
+wire  signed [32:0] sext_ln25_4_fu_359_p1;
+wire   [32:0] add_ln25_6_fu_363_p2;
+wire   [31:0] mul_ln25_fu_378_p2;
+reg   [24:0] ap_NS_fsm;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 25'd1;
+end
+
+mmult_params_s_axi #(
+    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PARAMS_ADDR_WIDTH ),
+    .C_S_AXI_DATA_WIDTH( C_S_AXI_PARAMS_DATA_WIDTH ))
+mmult_params_s_axi_U(
+    .AWVALID(s_axi_params_AWVALID),
+    .AWREADY(s_axi_params_AWREADY),
+    .AWADDR(s_axi_params_AWADDR),
+    .WVALID(s_axi_params_WVALID),
+    .WREADY(s_axi_params_WREADY),
+    .WDATA(s_axi_params_WDATA),
+    .WSTRB(s_axi_params_WSTRB),
+    .ARVALID(s_axi_params_ARVALID),
+    .ARREADY(s_axi_params_ARREADY),
+    .ARADDR(s_axi_params_ARADDR),
+    .RVALID(s_axi_params_RVALID),
+    .RREADY(s_axi_params_RREADY),
+    .RDATA(s_axi_params_RDATA),
+    .RRESP(s_axi_params_RRESP),
+    .BVALID(s_axi_params_BVALID),
+    .BREADY(s_axi_params_BREADY),
+    .BRESP(s_axi_params_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .in1(in1),
+    .in2(in2),
+    .out_r(out_r),
+    .dim(dim)
+);
+
+mmult_in1_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN1_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN1_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN1_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN1_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN1_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN1_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN1_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN1_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN1_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN1_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN1_MEM_CACHE_VALUE ))
+mmult_in1_mem_m_axi_U(
+    .AWVALID(m_axi_in1_mem_AWVALID),
+    .AWREADY(m_axi_in1_mem_AWREADY),
+    .AWADDR(m_axi_in1_mem_AWADDR),
+    .AWID(m_axi_in1_mem_AWID),
+    .AWLEN(m_axi_in1_mem_AWLEN),
+    .AWSIZE(m_axi_in1_mem_AWSIZE),
+    .AWBURST(m_axi_in1_mem_AWBURST),
+    .AWLOCK(m_axi_in1_mem_AWLOCK),
+    .AWCACHE(m_axi_in1_mem_AWCACHE),
+    .AWPROT(m_axi_in1_mem_AWPROT),
+    .AWQOS(m_axi_in1_mem_AWQOS),
+    .AWREGION(m_axi_in1_mem_AWREGION),
+    .AWUSER(m_axi_in1_mem_AWUSER),
+    .WVALID(m_axi_in1_mem_WVALID),
+    .WREADY(m_axi_in1_mem_WREADY),
+    .WDATA(m_axi_in1_mem_WDATA),
+    .WSTRB(m_axi_in1_mem_WSTRB),
+    .WLAST(m_axi_in1_mem_WLAST),
+    .WID(m_axi_in1_mem_WID),
+    .WUSER(m_axi_in1_mem_WUSER),
+    .ARVALID(m_axi_in1_mem_ARVALID),
+    .ARREADY(m_axi_in1_mem_ARREADY),
+    .ARADDR(m_axi_in1_mem_ARADDR),
+    .ARID(m_axi_in1_mem_ARID),
+    .ARLEN(m_axi_in1_mem_ARLEN),
+    .ARSIZE(m_axi_in1_mem_ARSIZE),
+    .ARBURST(m_axi_in1_mem_ARBURST),
+    .ARLOCK(m_axi_in1_mem_ARLOCK),
+    .ARCACHE(m_axi_in1_mem_ARCACHE),
+    .ARPROT(m_axi_in1_mem_ARPROT),
+    .ARQOS(m_axi_in1_mem_ARQOS),
+    .ARREGION(m_axi_in1_mem_ARREGION),
+    .ARUSER(m_axi_in1_mem_ARUSER),
+    .RVALID(m_axi_in1_mem_RVALID),
+    .RREADY(m_axi_in1_mem_RREADY),
+    .RDATA(m_axi_in1_mem_RDATA),
+    .RLAST(m_axi_in1_mem_RLAST),
+    .RID(m_axi_in1_mem_RID),
+    .RUSER(m_axi_in1_mem_RUSER),
+    .RRESP(m_axi_in1_mem_RRESP),
+    .BVALID(m_axi_in1_mem_BVALID),
+    .BREADY(m_axi_in1_mem_BREADY),
+    .BRESP(m_axi_in1_mem_BRESP),
+    .BID(m_axi_in1_mem_BID),
+    .BUSER(m_axi_in1_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in1_mem_ARVALID),
+    .I_ARREADY(in1_mem_ARREADY),
+    .I_ARADDR(in1_mem_addr_reg_425),
+    .I_ARID(1'd0),
+    .I_ARLEN(dim_read_reg_387),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in1_mem_RVALID),
+    .I_RREADY(in1_mem_RREADY),
+    .I_RDATA(in1_mem_RDATA),
+    .I_RID(in1_mem_RID),
+    .I_RUSER(in1_mem_RUSER),
+    .I_RRESP(in1_mem_RRESP),
+    .I_RLAST(in1_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in1_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in1_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in1_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in1_mem_BRESP),
+    .I_BID(in1_mem_BID),
+    .I_BUSER(in1_mem_BUSER)
+);
+
+mmult_in2_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN2_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN2_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN2_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN2_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN2_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN2_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN2_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN2_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN2_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN2_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN2_MEM_CACHE_VALUE ))
+mmult_in2_mem_m_axi_U(
+    .AWVALID(m_axi_in2_mem_AWVALID),
+    .AWREADY(m_axi_in2_mem_AWREADY),
+    .AWADDR(m_axi_in2_mem_AWADDR),
+    .AWID(m_axi_in2_mem_AWID),
+    .AWLEN(m_axi_in2_mem_AWLEN),
+    .AWSIZE(m_axi_in2_mem_AWSIZE),
+    .AWBURST(m_axi_in2_mem_AWBURST),
+    .AWLOCK(m_axi_in2_mem_AWLOCK),
+    .AWCACHE(m_axi_in2_mem_AWCACHE),
+    .AWPROT(m_axi_in2_mem_AWPROT),
+    .AWQOS(m_axi_in2_mem_AWQOS),
+    .AWREGION(m_axi_in2_mem_AWREGION),
+    .AWUSER(m_axi_in2_mem_AWUSER),
+    .WVALID(m_axi_in2_mem_WVALID),
+    .WREADY(m_axi_in2_mem_WREADY),
+    .WDATA(m_axi_in2_mem_WDATA),
+    .WSTRB(m_axi_in2_mem_WSTRB),
+    .WLAST(m_axi_in2_mem_WLAST),
+    .WID(m_axi_in2_mem_WID),
+    .WUSER(m_axi_in2_mem_WUSER),
+    .ARVALID(m_axi_in2_mem_ARVALID),
+    .ARREADY(m_axi_in2_mem_ARREADY),
+    .ARADDR(m_axi_in2_mem_ARADDR),
+    .ARID(m_axi_in2_mem_ARID),
+    .ARLEN(m_axi_in2_mem_ARLEN),
+    .ARSIZE(m_axi_in2_mem_ARSIZE),
+    .ARBURST(m_axi_in2_mem_ARBURST),
+    .ARLOCK(m_axi_in2_mem_ARLOCK),
+    .ARCACHE(m_axi_in2_mem_ARCACHE),
+    .ARPROT(m_axi_in2_mem_ARPROT),
+    .ARQOS(m_axi_in2_mem_ARQOS),
+    .ARREGION(m_axi_in2_mem_ARREGION),
+    .ARUSER(m_axi_in2_mem_ARUSER),
+    .RVALID(m_axi_in2_mem_RVALID),
+    .RREADY(m_axi_in2_mem_RREADY),
+    .RDATA(m_axi_in2_mem_RDATA),
+    .RLAST(m_axi_in2_mem_RLAST),
+    .RID(m_axi_in2_mem_RID),
+    .RUSER(m_axi_in2_mem_RUSER),
+    .RRESP(m_axi_in2_mem_RRESP),
+    .BVALID(m_axi_in2_mem_BVALID),
+    .BREADY(m_axi_in2_mem_BREADY),
+    .BRESP(m_axi_in2_mem_BRESP),
+    .BID(m_axi_in2_mem_BID),
+    .BUSER(m_axi_in2_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in2_mem_ARVALID),
+    .I_ARREADY(in2_mem_ARREADY),
+    .I_ARADDR(in2_mem_addr_reg_459),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd1),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in2_mem_RVALID),
+    .I_RREADY(in2_mem_RREADY),
+    .I_RDATA(in2_mem_RDATA),
+    .I_RID(in2_mem_RID),
+    .I_RUSER(in2_mem_RUSER),
+    .I_RRESP(in2_mem_RRESP),
+    .I_RLAST(in2_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in2_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in2_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in2_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in2_mem_BRESP),
+    .I_BID(in2_mem_BID),
+    .I_BUSER(in2_mem_BUSER)
+);
+
+mmult_out_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_OUT_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_OUT_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_OUT_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_OUT_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_OUT_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_OUT_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_OUT_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_OUT_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_OUT_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_OUT_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_OUT_MEM_CACHE_VALUE ))
+mmult_out_mem_m_axi_U(
+    .AWVALID(m_axi_out_mem_AWVALID),
+    .AWREADY(m_axi_out_mem_AWREADY),
+    .AWADDR(m_axi_out_mem_AWADDR),
+    .AWID(m_axi_out_mem_AWID),
+    .AWLEN(m_axi_out_mem_AWLEN),
+    .AWSIZE(m_axi_out_mem_AWSIZE),
+    .AWBURST(m_axi_out_mem_AWBURST),
+    .AWLOCK(m_axi_out_mem_AWLOCK),
+    .AWCACHE(m_axi_out_mem_AWCACHE),
+    .AWPROT(m_axi_out_mem_AWPROT),
+    .AWQOS(m_axi_out_mem_AWQOS),
+    .AWREGION(m_axi_out_mem_AWREGION),
+    .AWUSER(m_axi_out_mem_AWUSER),
+    .WVALID(m_axi_out_mem_WVALID),
+    .WREADY(m_axi_out_mem_WREADY),
+    .WDATA(m_axi_out_mem_WDATA),
+    .WSTRB(m_axi_out_mem_WSTRB),
+    .WLAST(m_axi_out_mem_WLAST),
+    .WID(m_axi_out_mem_WID),
+    .WUSER(m_axi_out_mem_WUSER),
+    .ARVALID(m_axi_out_mem_ARVALID),
+    .ARREADY(m_axi_out_mem_ARREADY),
+    .ARADDR(m_axi_out_mem_ARADDR),
+    .ARID(m_axi_out_mem_ARID),
+    .ARLEN(m_axi_out_mem_ARLEN),
+    .ARSIZE(m_axi_out_mem_ARSIZE),
+    .ARBURST(m_axi_out_mem_ARBURST),
+    .ARLOCK(m_axi_out_mem_ARLOCK),
+    .ARCACHE(m_axi_out_mem_ARCACHE),
+    .ARPROT(m_axi_out_mem_ARPROT),
+    .ARQOS(m_axi_out_mem_ARQOS),
+    .ARREGION(m_axi_out_mem_ARREGION),
+    .ARUSER(m_axi_out_mem_ARUSER),
+    .RVALID(m_axi_out_mem_RVALID),
+    .RREADY(m_axi_out_mem_RREADY),
+    .RDATA(m_axi_out_mem_RDATA),
+    .RLAST(m_axi_out_mem_RLAST),
+    .RID(m_axi_out_mem_RID),
+    .RUSER(m_axi_out_mem_RUSER),
+    .RRESP(m_axi_out_mem_RRESP),
+    .BVALID(m_axi_out_mem_BVALID),
+    .BREADY(m_axi_out_mem_BREADY),
+    .BRESP(m_axi_out_mem_BRESP),
+    .BID(m_axi_out_mem_BID),
+    .BUSER(m_axi_out_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(out_mem_ARVALID),
+    .I_ARREADY(out_mem_ARREADY),
+    .I_ARADDR(out_mem_addr_reg_439),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd1),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(out_mem_RVALID),
+    .I_RREADY(out_mem_RREADY),
+    .I_RDATA(out_mem_RDATA),
+    .I_RID(out_mem_RID),
+    .I_RUSER(out_mem_RUSER),
+    .I_RRESP(out_mem_RRESP),
+    .I_RLAST(out_mem_RLAST),
+    .I_AWVALID(out_mem_AWVALID),
+    .I_AWREADY(out_mem_AWREADY),
+    .I_AWADDR(out_mem_addr_reg_439),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd1),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(out_mem_WVALID),
+    .I_WREADY(out_mem_WREADY),
+    .I_WDATA(add_ln25_3_reg_480),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd15),
+    .I_BVALID(out_mem_BVALID),
+    .I_BREADY(out_mem_BREADY),
+    .I_BRESP(out_mem_BRESP),
+    .I_BID(out_mem_BID),
+    .I_BUSER(out_mem_BUSER)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state3_io) & (icmp_ln20_fu_301_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
+        i_0_reg_163 <= i_reg_420;
+    end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        i_0_reg_163 <= 31'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln22_fu_337_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state10))) begin
+        j_0_reg_186 <= j_reg_434;
+    end else if (((icmp_ln18_fu_271_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        j_0_reg_186 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+        k_0_reg_198 <= k_reg_449;
+    end else if ((1'b1 == ap_CS_fsm_state9)) begin
+        k_0_reg_198 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state3_io) & (icmp_ln20_fu_301_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
+        phi_mul8_reg_174 <= add_ln18_reg_412;
+    end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        phi_mul8_reg_174 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+        phi_mul_reg_209 <= add_ln25_5_reg_454;
+    end else if ((1'b1 == ap_CS_fsm_state9)) begin
+        phi_mul_reg_209 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        add_ln18_reg_412 <= add_ln18_fu_262_p2;
+        i_reg_420 <= i_fu_276_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state19))) begin
+        add_ln25_3_reg_480 <= add_ln25_3_fu_382_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln22_fu_337_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state10))) begin
+        add_ln25_5_reg_454 <= add_ln25_5_fu_348_p2;
+        in2_mem_addr_reg_459 <= sext_ln25_5_fu_368_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        dim_read_reg_387 <= dim;
+        p_cast10_reg_402[29 : 0] <= p_cast10_fu_244_p1[29 : 0];
+        p_cast11_reg_397[29 : 0] <= p_cast11_fu_230_p1[29 : 0];
+        p_cast_reg_407[29 : 0] <= p_cast_fu_258_p1[29 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((~((out_mem_RVALID == 1'b0) | (in2_mem_RVALID == 1'b0) | (in1_mem_RVALID == 1'b0)) & (1'b1 == ap_CS_fsm_state18))) begin
+        in1_mem_addr_read_reg_465 <= in1_mem_RDATA;
+        in2_mem_addr_read_reg_470 <= in2_mem_RDATA;
+        out_mem_addr_read_reg_475 <= out_mem_RDATA;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln18_fu_271_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        in1_mem_addr_reg_425 <= sext_ln25_1_fu_291_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state3_io) & (1'b1 == ap_CS_fsm_state3))) begin
+        j_reg_434 <= j_fu_306_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state10)) begin
+        k_reg_449 <= k_fu_342_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state3_io) & (icmp_ln20_fu_301_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin
+        out_mem_addr_reg_439 <= sext_ln25_3_fu_327_p1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln18_fu_271_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln18_fu_271_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state3_io) & (icmp_ln20_fu_301_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin
+        in1_mem_ARVALID = 1'b1;
+    end else begin
+        in1_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((~((out_mem_RVALID == 1'b0) | (in2_mem_RVALID == 1'b0) | (in1_mem_RVALID == 1'b0)) & (1'b1 == ap_CS_fsm_state18))) begin
+        in1_mem_RREADY = 1'b1;
+    end else begin
+        in1_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln20_fu_301_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin
+        in1_mem_blk_n_AR = m_axi_in1_mem_ARREADY;
+    end else begin
+        in1_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        in1_mem_blk_n_R = m_axi_in1_mem_RVALID;
+    end else begin
+        in1_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state11_io) & (1'b1 == ap_CS_fsm_state11))) begin
+        in2_mem_ARVALID = 1'b1;
+    end else begin
+        in2_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((~((out_mem_RVALID == 1'b0) | (in2_mem_RVALID == 1'b0) | (in1_mem_RVALID == 1'b0)) & (1'b1 == ap_CS_fsm_state18))) begin
+        in2_mem_RREADY = 1'b1;
+    end else begin
+        in2_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state11)) begin
+        in2_mem_blk_n_AR = m_axi_in2_mem_ARREADY;
+    end else begin
+        in2_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        in2_mem_blk_n_R = m_axi_in2_mem_RVALID;
+    end else begin
+        in2_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state11_io) & (1'b1 == ap_CS_fsm_state11))) begin
+        out_mem_ARVALID = 1'b1;
+    end else begin
+        out_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state19))) begin
+        out_mem_AWVALID = 1'b1;
+    end else begin
+        out_mem_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+        out_mem_BREADY = 1'b1;
+    end else begin
+        out_mem_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((~((out_mem_RVALID == 1'b0) | (in2_mem_RVALID == 1'b0) | (in1_mem_RVALID == 1'b0)) & (1'b1 == ap_CS_fsm_state18))) begin
+        out_mem_RREADY = 1'b1;
+    end else begin
+        out_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_WREADY == 1'b1) & (1'b1 == ap_CS_fsm_state20))) begin
+        out_mem_WVALID = 1'b1;
+    end else begin
+        out_mem_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state11)) begin
+        out_mem_blk_n_AR = m_axi_out_mem_ARREADY;
+    end else begin
+        out_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state19)) begin
+        out_mem_blk_n_AW = m_axi_out_mem_AWREADY;
+    end else begin
+        out_mem_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        out_mem_blk_n_B = m_axi_out_mem_BVALID;
+    end else begin
+        out_mem_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        out_mem_blk_n_R = m_axi_out_mem_RVALID;
+    end else begin
+        out_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state20)) begin
+        out_mem_blk_n_W = m_axi_out_mem_WREADY;
+    end else begin
+        out_mem_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((icmp_ln18_fu_271_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b0 == ap_block_state3_io) & (icmp_ln20_fu_301_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else if (((1'b0 == ap_block_state3_io) & (icmp_ln20_fu_301_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state4;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            ap_NS_fsm = ap_ST_fsm_state9;
+        end
+        ap_ST_fsm_state9 : begin
+            ap_NS_fsm = ap_ST_fsm_state10;
+        end
+        ap_ST_fsm_state10 : begin
+            if (((icmp_ln22_fu_337_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state10))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state11;
+            end
+        end
+        ap_ST_fsm_state11 : begin
+            if (((1'b0 == ap_block_state11_io) & (1'b1 == ap_CS_fsm_state11))) begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state11;
+            end
+        end
+        ap_ST_fsm_state12 : begin
+            ap_NS_fsm = ap_ST_fsm_state13;
+        end
+        ap_ST_fsm_state13 : begin
+            ap_NS_fsm = ap_ST_fsm_state14;
+        end
+        ap_ST_fsm_state14 : begin
+            ap_NS_fsm = ap_ST_fsm_state15;
+        end
+        ap_ST_fsm_state15 : begin
+            ap_NS_fsm = ap_ST_fsm_state16;
+        end
+        ap_ST_fsm_state16 : begin
+            ap_NS_fsm = ap_ST_fsm_state17;
+        end
+        ap_ST_fsm_state17 : begin
+            ap_NS_fsm = ap_ST_fsm_state18;
+        end
+        ap_ST_fsm_state18 : begin
+            if ((~((out_mem_RVALID == 1'b0) | (in2_mem_RVALID == 1'b0) | (in1_mem_RVALID == 1'b0)) & (1'b1 == ap_CS_fsm_state18))) begin
+                ap_NS_fsm = ap_ST_fsm_state19;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state18;
+            end
+        end
+        ap_ST_fsm_state19 : begin
+            if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state19))) begin
+                ap_NS_fsm = ap_ST_fsm_state20;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state19;
+            end
+        end
+        ap_ST_fsm_state20 : begin
+            if (((out_mem_WREADY == 1'b1) & (1'b1 == ap_CS_fsm_state20))) begin
+                ap_NS_fsm = ap_ST_fsm_state21;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state20;
+            end
+        end
+        ap_ST_fsm_state21 : begin
+            ap_NS_fsm = ap_ST_fsm_state22;
+        end
+        ap_ST_fsm_state22 : begin
+            ap_NS_fsm = ap_ST_fsm_state23;
+        end
+        ap_ST_fsm_state23 : begin
+            ap_NS_fsm = ap_ST_fsm_state24;
+        end
+        ap_ST_fsm_state24 : begin
+            ap_NS_fsm = ap_ST_fsm_state25;
+        end
+        ap_ST_fsm_state25 : begin
+            if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+                ap_NS_fsm = ap_ST_fsm_state10;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state25;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln18_fu_262_p2 = ($signed(phi_mul8_reg_174) + $signed(dim_read_reg_387));
+
+assign add_ln25_1_fu_286_p2 = ($signed(sext_ln25_fu_282_p1) + $signed(p_cast_reg_407));
+
+assign add_ln25_2_fu_353_p2 = (j_0_reg_186 + phi_mul_reg_209);
+
+assign add_ln25_3_fu_382_p2 = (mul_ln25_fu_378_p2 + out_mem_addr_read_reg_475);
+
+assign add_ln25_4_fu_322_p2 = ($signed(sext_ln25_2_fu_318_p1) + $signed(p_cast11_reg_397));
+
+assign add_ln25_5_fu_348_p2 = (dim_read_reg_387 + phi_mul_reg_209);
+
+assign add_ln25_6_fu_363_p2 = ($signed(sext_ln25_4_fu_359_p1) + $signed(p_cast10_reg_402));
+
+assign add_ln25_fu_312_p2 = ($signed(phi_mul8_reg_174) + $signed(j_0_reg_186));
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9];
+
+assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10];
+
+assign ap_CS_fsm_state18 = ap_CS_fsm[32'd17];
+
+assign ap_CS_fsm_state19 = ap_CS_fsm[32'd18];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state20 = ap_CS_fsm[32'd19];
+
+assign ap_CS_fsm_state25 = ap_CS_fsm[32'd24];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8];
+
+always @ (*) begin
+    ap_block_state11_io = ((out_mem_ARREADY == 1'b0) | (in2_mem_ARREADY == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state18 = ((out_mem_RVALID == 1'b0) | (in2_mem_RVALID == 1'b0) | (in1_mem_RVALID == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state3_io = ((in1_mem_ARREADY == 1'b0) & (icmp_ln20_fu_301_p2 == 1'd0));
+end
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign i_fu_276_p2 = (i_0_reg_163 + 31'd1);
+
+assign icmp_ln18_fu_271_p2 = (($signed(zext_ln18_fu_267_p1) < $signed(dim_read_reg_387)) ? 1'b1 : 1'b0);
+
+assign icmp_ln20_fu_301_p2 = ((j_0_reg_186 == dim_read_reg_387) ? 1'b1 : 1'b0);
+
+assign icmp_ln22_fu_337_p2 = ((k_0_reg_198 == dim_read_reg_387) ? 1'b1 : 1'b0);
+
+assign j_fu_306_p2 = (j_0_reg_186 + 32'd1);
+
+assign k_fu_342_p2 = (k_0_reg_198 + 32'd1);
+
+assign mul_ln25_fu_378_p2 = ($signed(in1_mem_addr_read_reg_465) * $signed(in2_mem_addr_read_reg_470));
+
+assign p_cast10_fu_244_p1 = tmp_4_fu_234_p4;
+
+assign p_cast11_fu_230_p1 = tmp_3_fu_220_p4;
+
+assign p_cast_fu_258_p1 = tmp_5_fu_248_p4;
+
+assign sext_ln25_1_fu_291_p1 = $signed(add_ln25_1_fu_286_p2);
+
+assign sext_ln25_2_fu_318_p1 = $signed(add_ln25_fu_312_p2);
+
+assign sext_ln25_3_fu_327_p1 = $signed(add_ln25_4_fu_322_p2);
+
+assign sext_ln25_4_fu_359_p1 = $signed(add_ln25_2_fu_353_p2);
+
+assign sext_ln25_5_fu_368_p1 = $signed(add_ln25_6_fu_363_p2);
+
+assign sext_ln25_fu_282_p1 = phi_mul8_reg_174;
+
+assign tmp_3_fu_220_p4 = {{out_r[31:2]}};
+
+assign tmp_4_fu_234_p4 = {{in2[31:2]}};
+
+assign tmp_5_fu_248_p4 = {{in1[31:2]}};
+
+assign zext_ln18_fu_267_p1 = i_0_reg_163;
+
+always @ (posedge ap_clk) begin
+    p_cast11_reg_397[32:30] <= 3'b000;
+    p_cast10_reg_402[32:30] <= 3'b000;
+    p_cast_reg_407[32:30] <= 3'b000;
+end
+
+endmodule //mmult
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_in1_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_in1_mem_m_axi.v
new file mode 100644
index 0000000..81f7248
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_in1_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in1_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in1_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in1_mem_m_axi_write
+mmult_in1_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in1_mem_m_axi_read
+mmult_in1_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in1_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in1_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in1_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in1_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in1_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_in2_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_in2_mem_m_axi.v
new file mode 100644
index 0000000..a2eab07
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_in2_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in2_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in2_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in2_mem_m_axi_write
+mmult_in2_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in2_mem_m_axi_read
+mmult_in2_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in2_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in2_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in2_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in2_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in2_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_out_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_out_mem_m_axi.v
new file mode 100644
index 0000000..cc472db
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_out_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_out_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_out_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_out_mem_m_axi_write
+mmult_out_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_out_mem_m_axi_read
+mmult_out_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_out_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_out_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_out_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_out_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_out_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_params_s_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_params_s_axi.v
new file mode 100644
index 0000000..d470352
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_params_s_axi.v
@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult.vhd
new file mode 100644
index 0000000..6378dc3
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult.vhd
@@ -0,0 +1,1708 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+-- Version: 2020.1
+-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult is
+generic (
+    C_M_AXI_IN1_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_S_AXI_PARAMS_ADDR_WIDTH : INTEGER := 6;
+    C_S_AXI_PARAMS_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_IN2_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_OUT_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_CACHE_VALUE : INTEGER := 3 );
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    m_axi_in1_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in1_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_WREADY : IN STD_LOGIC;
+    m_axi_in1_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in1_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in1_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in1_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RVALID : IN STD_LOGIC;
+    m_axi_in1_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_RLAST : IN STD_LOGIC;
+    m_axi_in1_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BVALID : IN STD_LOGIC;
+    m_axi_in1_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in2_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_WREADY : IN STD_LOGIC;
+    m_axi_in2_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in2_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in2_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in2_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RVALID : IN STD_LOGIC;
+    m_axi_in2_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_RLAST : IN STD_LOGIC;
+    m_axi_in2_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BVALID : IN STD_LOGIC;
+    m_axi_in2_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_out_mem_AWREADY : IN STD_LOGIC;
+    m_axi_out_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_WVALID : OUT STD_LOGIC;
+    m_axi_out_mem_WREADY : IN STD_LOGIC;
+    m_axi_out_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_out_mem_WLAST : OUT STD_LOGIC;
+    m_axi_out_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_out_mem_ARREADY : IN STD_LOGIC;
+    m_axi_out_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RVALID : IN STD_LOGIC;
+    m_axi_out_mem_RREADY : OUT STD_LOGIC;
+    m_axi_out_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_RLAST : IN STD_LOGIC;
+    m_axi_out_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BVALID : IN STD_LOGIC;
+    m_axi_out_mem_BREADY : OUT STD_LOGIC;
+    m_axi_out_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_BUSER_WIDTH-1 downto 0);
+    s_axi_params_AWVALID : IN STD_LOGIC;
+    s_axi_params_AWREADY : OUT STD_LOGIC;
+    s_axi_params_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_WVALID : IN STD_LOGIC;
+    s_axi_params_WREADY : OUT STD_LOGIC;
+    s_axi_params_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH/8-1 downto 0);
+    s_axi_params_ARVALID : IN STD_LOGIC;
+    s_axi_params_ARREADY : OUT STD_LOGIC;
+    s_axi_params_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_RVALID : OUT STD_LOGIC;
+    s_axi_params_RREADY : IN STD_LOGIC;
+    s_axi_params_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    s_axi_params_BVALID : OUT STD_LOGIC;
+    s_axi_params_BREADY : IN STD_LOGIC;
+    s_axi_params_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    interrupt : OUT STD_LOGIC );
+end;
+
+
+architecture behav of mmult is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=4227201,HLS_SYN_TPT=none,HLS_SYN_MEM=6,HLS_SYN_DSP=3,HLS_SYN_FF=2413,HLS_SYN_LUT=2800,HLS_VERSION=2020_1}";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000100";
+    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000001000";
+    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000010000";
+    constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000100000";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000001000000";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000010000000";
+    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000100000000";
+    constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000001000000000";
+    constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000010000000000";
+    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000100000000000";
+    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000001000000000000";
+    constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000010000000000000";
+    constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000100000000000000";
+    constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (24 downto 0) := "0000000001000000000000000";
+    constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (24 downto 0) := "0000000010000000000000000";
+    constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (24 downto 0) := "0000000100000000000000000";
+    constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (24 downto 0) := "0000001000000000000000000";
+    constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (24 downto 0) := "0000010000000000000000000";
+    constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (24 downto 0) := "0000100000000000000000000";
+    constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (24 downto 0) := "0001000000000000000000000";
+    constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (24 downto 0) := "0010000000000000000000000";
+    constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (24 downto 0) := "0100000000000000000000000";
+    constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (24 downto 0) := "1000000000000000000000000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
+    constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
+    constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
+    constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
+    constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
+    constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
+    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
+    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
+    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
+    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal ap_start : STD_LOGIC;
+    signal ap_done : STD_LOGIC;
+    signal ap_idle : STD_LOGIC;
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal ap_ready : STD_LOGIC;
+    signal in1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_r : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state3 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
+    signal icmp_ln20_fu_301_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_state18 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
+    signal in2_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state11 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
+    signal in2_mem_blk_n_R : STD_LOGIC;
+    signal out_mem_blk_n_AR : STD_LOGIC;
+    signal out_mem_blk_n_R : STD_LOGIC;
+    signal out_mem_blk_n_AW : STD_LOGIC;
+    signal ap_CS_fsm_state19 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state19 : signal is "none";
+    signal out_mem_blk_n_W : STD_LOGIC;
+    signal ap_CS_fsm_state20 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state20 : signal is "none";
+    signal out_mem_blk_n_B : STD_LOGIC;
+    signal ap_CS_fsm_state25 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
+    signal in1_mem_AWREADY : STD_LOGIC;
+    signal in1_mem_WREADY : STD_LOGIC;
+    signal in1_mem_ARVALID : STD_LOGIC;
+    signal in1_mem_ARREADY : STD_LOGIC;
+    signal in1_mem_RVALID : STD_LOGIC;
+    signal in1_mem_RREADY : STD_LOGIC;
+    signal in1_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RLAST : STD_LOGIC;
+    signal in1_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BVALID : STD_LOGIC;
+    signal in1_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_AWREADY : STD_LOGIC;
+    signal in2_mem_WREADY : STD_LOGIC;
+    signal in2_mem_ARVALID : STD_LOGIC;
+    signal in2_mem_ARREADY : STD_LOGIC;
+    signal in2_mem_RVALID : STD_LOGIC;
+    signal in2_mem_RREADY : STD_LOGIC;
+    signal in2_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_RLAST : STD_LOGIC;
+    signal in2_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BVALID : STD_LOGIC;
+    signal in2_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_AWVALID : STD_LOGIC;
+    signal out_mem_AWREADY : STD_LOGIC;
+    signal out_mem_WVALID : STD_LOGIC;
+    signal out_mem_WREADY : STD_LOGIC;
+    signal out_mem_ARVALID : STD_LOGIC;
+    signal out_mem_ARREADY : STD_LOGIC;
+    signal out_mem_RVALID : STD_LOGIC;
+    signal out_mem_RREADY : STD_LOGIC;
+    signal out_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_RLAST : STD_LOGIC;
+    signal out_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BVALID : STD_LOGIC;
+    signal out_mem_BREADY : STD_LOGIC;
+    signal out_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal dim_read_reg_387 : STD_LOGIC_VECTOR (31 downto 0);
+    signal p_cast11_fu_230_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast11_reg_397 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast10_fu_244_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast10_reg_402 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast_fu_258_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast_reg_407 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln18_fu_262_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln18_reg_412 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal i_fu_276_p2 : STD_LOGIC_VECTOR (30 downto 0);
+    signal i_reg_420 : STD_LOGIC_VECTOR (30 downto 0);
+    signal in1_mem_addr_reg_425 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln18_fu_271_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_fu_306_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal j_reg_434 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state3_io : BOOLEAN;
+    signal out_mem_addr_reg_439 : STD_LOGIC_VECTOR (31 downto 0);
+    signal k_fu_342_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal k_reg_449 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state10 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
+    signal add_ln25_5_fu_348_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln25_5_reg_454 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln22_fu_337_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_addr_reg_459 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_addr_read_reg_465 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state18 : BOOLEAN;
+    signal in2_mem_addr_read_reg_470 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_read_reg_475 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln25_3_fu_382_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln25_3_reg_480 : STD_LOGIC_VECTOR (31 downto 0);
+    signal i_0_reg_163 : STD_LOGIC_VECTOR (30 downto 0);
+    signal phi_mul8_reg_174 : STD_LOGIC_VECTOR (31 downto 0);
+    signal j_0_reg_186 : STD_LOGIC_VECTOR (31 downto 0);
+    signal k_0_reg_198 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state9 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
+    signal phi_mul_reg_209 : STD_LOGIC_VECTOR (31 downto 0);
+    signal sext_ln25_1_fu_291_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln25_3_fu_327_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln25_5_fu_368_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_state11_io : BOOLEAN;
+    signal tmp_3_fu_220_p4 : STD_LOGIC_VECTOR (29 downto 0);
+    signal tmp_4_fu_234_p4 : STD_LOGIC_VECTOR (29 downto 0);
+    signal tmp_5_fu_248_p4 : STD_LOGIC_VECTOR (29 downto 0);
+    signal zext_ln18_fu_267_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal sext_ln25_fu_282_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln25_1_fu_286_p2 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln25_fu_312_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal sext_ln25_2_fu_318_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln25_4_fu_322_p2 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln25_2_fu_353_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal sext_ln25_4_fu_359_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln25_6_fu_363_p2 : STD_LOGIC_VECTOR (32 downto 0);
+    signal mul_ln25_fu_378_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (24 downto 0);
+
+    component mmult_params_s_axi IS
+    generic (
+        C_S_AXI_ADDR_WIDTH : INTEGER;
+        C_S_AXI_DATA_WIDTH : INTEGER );
+    port (
+        AWVALID : IN STD_LOGIC;
+        AWREADY : OUT STD_LOGIC;
+        AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        WVALID : IN STD_LOGIC;
+        WREADY : OUT STD_LOGIC;
+        WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
+        ARVALID : IN STD_LOGIC;
+        ARREADY : OUT STD_LOGIC;
+        ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        RVALID : OUT STD_LOGIC;
+        RREADY : IN STD_LOGIC;
+        RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : OUT STD_LOGIC;
+        BREADY : IN STD_LOGIC;
+        BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        ap_start : OUT STD_LOGIC;
+        interrupt : OUT STD_LOGIC;
+        ap_ready : IN STD_LOGIC;
+        ap_done : IN STD_LOGIC;
+        ap_idle : IN STD_LOGIC;
+        in1 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        in2 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        out_r : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dim : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_in2_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_out_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+
+begin
+    mmult_params_s_axi_U : component mmult_params_s_axi
+    generic map (
+        C_S_AXI_ADDR_WIDTH => C_S_AXI_PARAMS_ADDR_WIDTH,
+        C_S_AXI_DATA_WIDTH => C_S_AXI_PARAMS_DATA_WIDTH)
+    port map (
+        AWVALID => s_axi_params_AWVALID,
+        AWREADY => s_axi_params_AWREADY,
+        AWADDR => s_axi_params_AWADDR,
+        WVALID => s_axi_params_WVALID,
+        WREADY => s_axi_params_WREADY,
+        WDATA => s_axi_params_WDATA,
+        WSTRB => s_axi_params_WSTRB,
+        ARVALID => s_axi_params_ARVALID,
+        ARREADY => s_axi_params_ARREADY,
+        ARADDR => s_axi_params_ARADDR,
+        RVALID => s_axi_params_RVALID,
+        RREADY => s_axi_params_RREADY,
+        RDATA => s_axi_params_RDATA,
+        RRESP => s_axi_params_RRESP,
+        BVALID => s_axi_params_BVALID,
+        BREADY => s_axi_params_BREADY,
+        BRESP => s_axi_params_BRESP,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        ap_start => ap_start,
+        interrupt => interrupt,
+        ap_ready => ap_ready,
+        ap_done => ap_done,
+        ap_idle => ap_idle,
+        in1 => in1,
+        in2 => in2,
+        out_r => out_r,
+        dim => dim);
+
+    mmult_in1_mem_m_axi_U : component mmult_in1_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN1_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN1_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN1_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN1_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN1_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN1_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN1_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN1_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN1_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN1_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN1_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in1_mem_AWVALID,
+        AWREADY => m_axi_in1_mem_AWREADY,
+        AWADDR => m_axi_in1_mem_AWADDR,
+        AWID => m_axi_in1_mem_AWID,
+        AWLEN => m_axi_in1_mem_AWLEN,
+        AWSIZE => m_axi_in1_mem_AWSIZE,
+        AWBURST => m_axi_in1_mem_AWBURST,
+        AWLOCK => m_axi_in1_mem_AWLOCK,
+        AWCACHE => m_axi_in1_mem_AWCACHE,
+        AWPROT => m_axi_in1_mem_AWPROT,
+        AWQOS => m_axi_in1_mem_AWQOS,
+        AWREGION => m_axi_in1_mem_AWREGION,
+        AWUSER => m_axi_in1_mem_AWUSER,
+        WVALID => m_axi_in1_mem_WVALID,
+        WREADY => m_axi_in1_mem_WREADY,
+        WDATA => m_axi_in1_mem_WDATA,
+        WSTRB => m_axi_in1_mem_WSTRB,
+        WLAST => m_axi_in1_mem_WLAST,
+        WID => m_axi_in1_mem_WID,
+        WUSER => m_axi_in1_mem_WUSER,
+        ARVALID => m_axi_in1_mem_ARVALID,
+        ARREADY => m_axi_in1_mem_ARREADY,
+        ARADDR => m_axi_in1_mem_ARADDR,
+        ARID => m_axi_in1_mem_ARID,
+        ARLEN => m_axi_in1_mem_ARLEN,
+        ARSIZE => m_axi_in1_mem_ARSIZE,
+        ARBURST => m_axi_in1_mem_ARBURST,
+        ARLOCK => m_axi_in1_mem_ARLOCK,
+        ARCACHE => m_axi_in1_mem_ARCACHE,
+        ARPROT => m_axi_in1_mem_ARPROT,
+        ARQOS => m_axi_in1_mem_ARQOS,
+        ARREGION => m_axi_in1_mem_ARREGION,
+        ARUSER => m_axi_in1_mem_ARUSER,
+        RVALID => m_axi_in1_mem_RVALID,
+        RREADY => m_axi_in1_mem_RREADY,
+        RDATA => m_axi_in1_mem_RDATA,
+        RLAST => m_axi_in1_mem_RLAST,
+        RID => m_axi_in1_mem_RID,
+        RUSER => m_axi_in1_mem_RUSER,
+        RRESP => m_axi_in1_mem_RRESP,
+        BVALID => m_axi_in1_mem_BVALID,
+        BREADY => m_axi_in1_mem_BREADY,
+        BRESP => m_axi_in1_mem_BRESP,
+        BID => m_axi_in1_mem_BID,
+        BUSER => m_axi_in1_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in1_mem_ARVALID,
+        I_ARREADY => in1_mem_ARREADY,
+        I_ARADDR => in1_mem_addr_reg_425,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => dim_read_reg_387,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in1_mem_RVALID,
+        I_RREADY => in1_mem_RREADY,
+        I_RDATA => in1_mem_RDATA,
+        I_RID => in1_mem_RID,
+        I_RUSER => in1_mem_RUSER,
+        I_RRESP => in1_mem_RRESP,
+        I_RLAST => in1_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in1_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in1_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in1_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in1_mem_BRESP,
+        I_BID => in1_mem_BID,
+        I_BUSER => in1_mem_BUSER);
+
+    mmult_in2_mem_m_axi_U : component mmult_in2_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN2_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN2_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN2_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN2_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN2_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN2_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN2_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN2_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN2_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN2_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN2_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in2_mem_AWVALID,
+        AWREADY => m_axi_in2_mem_AWREADY,
+        AWADDR => m_axi_in2_mem_AWADDR,
+        AWID => m_axi_in2_mem_AWID,
+        AWLEN => m_axi_in2_mem_AWLEN,
+        AWSIZE => m_axi_in2_mem_AWSIZE,
+        AWBURST => m_axi_in2_mem_AWBURST,
+        AWLOCK => m_axi_in2_mem_AWLOCK,
+        AWCACHE => m_axi_in2_mem_AWCACHE,
+        AWPROT => m_axi_in2_mem_AWPROT,
+        AWQOS => m_axi_in2_mem_AWQOS,
+        AWREGION => m_axi_in2_mem_AWREGION,
+        AWUSER => m_axi_in2_mem_AWUSER,
+        WVALID => m_axi_in2_mem_WVALID,
+        WREADY => m_axi_in2_mem_WREADY,
+        WDATA => m_axi_in2_mem_WDATA,
+        WSTRB => m_axi_in2_mem_WSTRB,
+        WLAST => m_axi_in2_mem_WLAST,
+        WID => m_axi_in2_mem_WID,
+        WUSER => m_axi_in2_mem_WUSER,
+        ARVALID => m_axi_in2_mem_ARVALID,
+        ARREADY => m_axi_in2_mem_ARREADY,
+        ARADDR => m_axi_in2_mem_ARADDR,
+        ARID => m_axi_in2_mem_ARID,
+        ARLEN => m_axi_in2_mem_ARLEN,
+        ARSIZE => m_axi_in2_mem_ARSIZE,
+        ARBURST => m_axi_in2_mem_ARBURST,
+        ARLOCK => m_axi_in2_mem_ARLOCK,
+        ARCACHE => m_axi_in2_mem_ARCACHE,
+        ARPROT => m_axi_in2_mem_ARPROT,
+        ARQOS => m_axi_in2_mem_ARQOS,
+        ARREGION => m_axi_in2_mem_ARREGION,
+        ARUSER => m_axi_in2_mem_ARUSER,
+        RVALID => m_axi_in2_mem_RVALID,
+        RREADY => m_axi_in2_mem_RREADY,
+        RDATA => m_axi_in2_mem_RDATA,
+        RLAST => m_axi_in2_mem_RLAST,
+        RID => m_axi_in2_mem_RID,
+        RUSER => m_axi_in2_mem_RUSER,
+        RRESP => m_axi_in2_mem_RRESP,
+        BVALID => m_axi_in2_mem_BVALID,
+        BREADY => m_axi_in2_mem_BREADY,
+        BRESP => m_axi_in2_mem_BRESP,
+        BID => m_axi_in2_mem_BID,
+        BUSER => m_axi_in2_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in2_mem_ARVALID,
+        I_ARREADY => in2_mem_ARREADY,
+        I_ARADDR => in2_mem_addr_reg_459,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in2_mem_RVALID,
+        I_RREADY => in2_mem_RREADY,
+        I_RDATA => in2_mem_RDATA,
+        I_RID => in2_mem_RID,
+        I_RUSER => in2_mem_RUSER,
+        I_RRESP => in2_mem_RRESP,
+        I_RLAST => in2_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in2_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in2_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in2_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in2_mem_BRESP,
+        I_BID => in2_mem_BID,
+        I_BUSER => in2_mem_BUSER);
+
+    mmult_out_mem_m_axi_U : component mmult_out_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_OUT_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_OUT_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_OUT_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_OUT_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_OUT_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_OUT_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_OUT_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_OUT_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_OUT_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_OUT_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_OUT_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_out_mem_AWVALID,
+        AWREADY => m_axi_out_mem_AWREADY,
+        AWADDR => m_axi_out_mem_AWADDR,
+        AWID => m_axi_out_mem_AWID,
+        AWLEN => m_axi_out_mem_AWLEN,
+        AWSIZE => m_axi_out_mem_AWSIZE,
+        AWBURST => m_axi_out_mem_AWBURST,
+        AWLOCK => m_axi_out_mem_AWLOCK,
+        AWCACHE => m_axi_out_mem_AWCACHE,
+        AWPROT => m_axi_out_mem_AWPROT,
+        AWQOS => m_axi_out_mem_AWQOS,
+        AWREGION => m_axi_out_mem_AWREGION,
+        AWUSER => m_axi_out_mem_AWUSER,
+        WVALID => m_axi_out_mem_WVALID,
+        WREADY => m_axi_out_mem_WREADY,
+        WDATA => m_axi_out_mem_WDATA,
+        WSTRB => m_axi_out_mem_WSTRB,
+        WLAST => m_axi_out_mem_WLAST,
+        WID => m_axi_out_mem_WID,
+        WUSER => m_axi_out_mem_WUSER,
+        ARVALID => m_axi_out_mem_ARVALID,
+        ARREADY => m_axi_out_mem_ARREADY,
+        ARADDR => m_axi_out_mem_ARADDR,
+        ARID => m_axi_out_mem_ARID,
+        ARLEN => m_axi_out_mem_ARLEN,
+        ARSIZE => m_axi_out_mem_ARSIZE,
+        ARBURST => m_axi_out_mem_ARBURST,
+        ARLOCK => m_axi_out_mem_ARLOCK,
+        ARCACHE => m_axi_out_mem_ARCACHE,
+        ARPROT => m_axi_out_mem_ARPROT,
+        ARQOS => m_axi_out_mem_ARQOS,
+        ARREGION => m_axi_out_mem_ARREGION,
+        ARUSER => m_axi_out_mem_ARUSER,
+        RVALID => m_axi_out_mem_RVALID,
+        RREADY => m_axi_out_mem_RREADY,
+        RDATA => m_axi_out_mem_RDATA,
+        RLAST => m_axi_out_mem_RLAST,
+        RID => m_axi_out_mem_RID,
+        RUSER => m_axi_out_mem_RUSER,
+        RRESP => m_axi_out_mem_RRESP,
+        BVALID => m_axi_out_mem_BVALID,
+        BREADY => m_axi_out_mem_BREADY,
+        BRESP => m_axi_out_mem_BRESP,
+        BID => m_axi_out_mem_BID,
+        BUSER => m_axi_out_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => out_mem_ARVALID,
+        I_ARREADY => out_mem_ARREADY,
+        I_ARADDR => out_mem_addr_reg_439,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => out_mem_RVALID,
+        I_RREADY => out_mem_RREADY,
+        I_RDATA => out_mem_RDATA,
+        I_RID => out_mem_RID,
+        I_RUSER => out_mem_RUSER,
+        I_RRESP => out_mem_RRESP,
+        I_RLAST => out_mem_RLAST,
+        I_AWVALID => out_mem_AWVALID,
+        I_AWREADY => out_mem_AWREADY,
+        I_AWADDR => out_mem_addr_reg_439,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_1,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => out_mem_WVALID,
+        I_WREADY => out_mem_WREADY,
+        I_WDATA => add_ln25_3_reg_480,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_F,
+        I_BVALID => out_mem_BVALID,
+        I_BREADY => out_mem_BREADY,
+        I_BRESP => out_mem_BRESP,
+        I_BID => out_mem_BID,
+        I_BUSER => out_mem_BUSER);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    i_0_reg_163_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state3_io) and (icmp_ln20_fu_301_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then 
+                i_0_reg_163 <= i_reg_420;
+            elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                i_0_reg_163 <= ap_const_lv31_0;
+            end if; 
+        end if;
+    end process;
+
+    j_0_reg_186_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln22_fu_337_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state10))) then 
+                j_0_reg_186 <= j_reg_434;
+            elsif (((icmp_ln18_fu_271_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                j_0_reg_186 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    k_0_reg_198_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then 
+                k_0_reg_198 <= k_reg_449;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
+                k_0_reg_198 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_mul8_reg_174_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state3_io) and (icmp_ln20_fu_301_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then 
+                phi_mul8_reg_174 <= add_ln18_reg_412;
+            elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                phi_mul8_reg_174 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_mul_reg_209_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then 
+                phi_mul_reg_209 <= add_ln25_5_reg_454;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
+                phi_mul_reg_209 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
+                add_ln18_reg_412 <= add_ln18_fu_262_p2;
+                i_reg_420 <= i_fu_276_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state19))) then
+                add_ln25_3_reg_480 <= add_ln25_3_fu_382_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln22_fu_337_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state10))) then
+                add_ln25_5_reg_454 <= add_ln25_5_fu_348_p2;
+                in2_mem_addr_reg_459 <= sext_ln25_5_fu_368_p1(32 - 1 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                dim_read_reg_387 <= dim;
+                    p_cast10_reg_402(29 downto 0) <= p_cast10_fu_244_p1(29 downto 0);
+                    p_cast11_reg_397(29 downto 0) <= p_cast11_fu_230_p1(29 downto 0);
+                    p_cast_reg_407(29 downto 0) <= p_cast_fu_258_p1(29 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((out_mem_RVALID = ap_const_logic_0) or (in2_mem_RVALID = ap_const_logic_0) or (in1_mem_RVALID = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state18))) then
+                in1_mem_addr_read_reg_465 <= in1_mem_RDATA;
+                in2_mem_addr_read_reg_470 <= in2_mem_RDATA;
+                out_mem_addr_read_reg_475 <= out_mem_RDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln18_fu_271_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                in1_mem_addr_reg_425 <= sext_ln25_1_fu_291_p1(32 - 1 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state3_io) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
+                j_reg_434 <= j_fu_306_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
+                k_reg_449 <= k_fu_342_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state3_io) and (icmp_ln20_fu_301_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
+                out_mem_addr_reg_439 <= sext_ln25_3_fu_327_p1(32 - 1 downto 0);
+            end if;
+        end if;
+    end process;
+    p_cast11_reg_397(32 downto 30) <= "000";
+    p_cast10_reg_402(32 downto 30) <= "000";
+    p_cast_reg_407(32 downto 30) <= "000";
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state3, icmp_ln20_fu_301_p2, ap_CS_fsm_state18, ap_CS_fsm_state11, ap_CS_fsm_state19, ap_CS_fsm_state20, ap_CS_fsm_state25, in1_mem_RVALID, in2_mem_RVALID, out_mem_AWREADY, out_mem_WREADY, out_mem_RVALID, out_mem_BVALID, ap_CS_fsm_state2, icmp_ln18_fu_271_p2, ap_block_state3_io, ap_CS_fsm_state10, icmp_ln22_fu_337_p2, ap_block_state11_io)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((icmp_ln18_fu_271_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                end if;
+            when ap_ST_fsm_state3 => 
+                if (((ap_const_boolean_0 = ap_block_state3_io) and (icmp_ln20_fu_301_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                elsif (((ap_const_boolean_0 = ap_block_state3_io) and (icmp_ln20_fu_301_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
+                    ap_NS_fsm <= ap_ST_fsm_state4;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                end if;
+            when ap_ST_fsm_state4 => 
+                ap_NS_fsm <= ap_ST_fsm_state5;
+            when ap_ST_fsm_state5 => 
+                ap_NS_fsm <= ap_ST_fsm_state6;
+            when ap_ST_fsm_state6 => 
+                ap_NS_fsm <= ap_ST_fsm_state7;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state8;
+            when ap_ST_fsm_state8 => 
+                ap_NS_fsm <= ap_ST_fsm_state9;
+            when ap_ST_fsm_state9 => 
+                ap_NS_fsm <= ap_ST_fsm_state10;
+            when ap_ST_fsm_state10 => 
+                if (((icmp_ln22_fu_337_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state10))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state11;
+                end if;
+            when ap_ST_fsm_state11 => 
+                if (((ap_const_boolean_0 = ap_block_state11_io) and (ap_const_logic_1 = ap_CS_fsm_state11))) then
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state11;
+                end if;
+            when ap_ST_fsm_state12 => 
+                ap_NS_fsm <= ap_ST_fsm_state13;
+            when ap_ST_fsm_state13 => 
+                ap_NS_fsm <= ap_ST_fsm_state14;
+            when ap_ST_fsm_state14 => 
+                ap_NS_fsm <= ap_ST_fsm_state15;
+            when ap_ST_fsm_state15 => 
+                ap_NS_fsm <= ap_ST_fsm_state16;
+            when ap_ST_fsm_state16 => 
+                ap_NS_fsm <= ap_ST_fsm_state17;
+            when ap_ST_fsm_state17 => 
+                ap_NS_fsm <= ap_ST_fsm_state18;
+            when ap_ST_fsm_state18 => 
+                if ((not(((out_mem_RVALID = ap_const_logic_0) or (in2_mem_RVALID = ap_const_logic_0) or (in1_mem_RVALID = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state18))) then
+                    ap_NS_fsm <= ap_ST_fsm_state19;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state18;
+                end if;
+            when ap_ST_fsm_state19 => 
+                if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state19))) then
+                    ap_NS_fsm <= ap_ST_fsm_state20;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state19;
+                end if;
+            when ap_ST_fsm_state20 => 
+                if (((out_mem_WREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state20))) then
+                    ap_NS_fsm <= ap_ST_fsm_state21;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state20;
+                end if;
+            when ap_ST_fsm_state21 => 
+                ap_NS_fsm <= ap_ST_fsm_state22;
+            when ap_ST_fsm_state22 => 
+                ap_NS_fsm <= ap_ST_fsm_state23;
+            when ap_ST_fsm_state23 => 
+                ap_NS_fsm <= ap_ST_fsm_state24;
+            when ap_ST_fsm_state24 => 
+                ap_NS_fsm <= ap_ST_fsm_state25;
+            when ap_ST_fsm_state25 => 
+                if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then
+                    ap_NS_fsm <= ap_ST_fsm_state10;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state25;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
+        end case;
+    end process;
+    add_ln18_fu_262_p2 <= std_logic_vector(signed(phi_mul8_reg_174) + signed(dim_read_reg_387));
+    add_ln25_1_fu_286_p2 <= std_logic_vector(signed(sext_ln25_fu_282_p1) + signed(p_cast_reg_407));
+    add_ln25_2_fu_353_p2 <= std_logic_vector(unsigned(j_0_reg_186) + unsigned(phi_mul_reg_209));
+    add_ln25_3_fu_382_p2 <= std_logic_vector(unsigned(mul_ln25_fu_378_p2) + unsigned(out_mem_addr_read_reg_475));
+    add_ln25_4_fu_322_p2 <= std_logic_vector(signed(sext_ln25_2_fu_318_p1) + signed(p_cast11_reg_397));
+    add_ln25_5_fu_348_p2 <= std_logic_vector(unsigned(dim_read_reg_387) + unsigned(phi_mul_reg_209));
+    add_ln25_6_fu_363_p2 <= std_logic_vector(signed(sext_ln25_4_fu_359_p1) + signed(p_cast10_reg_402));
+    add_ln25_fu_312_p2 <= std_logic_vector(signed(phi_mul8_reg_174) + signed(j_0_reg_186));
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state10 <= ap_CS_fsm(9);
+    ap_CS_fsm_state11 <= ap_CS_fsm(10);
+    ap_CS_fsm_state18 <= ap_CS_fsm(17);
+    ap_CS_fsm_state19 <= ap_CS_fsm(18);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state20 <= ap_CS_fsm(19);
+    ap_CS_fsm_state25 <= ap_CS_fsm(24);
+    ap_CS_fsm_state3 <= ap_CS_fsm(2);
+    ap_CS_fsm_state9 <= ap_CS_fsm(8);
+
+    ap_block_state11_io_assign_proc : process(in2_mem_ARREADY, out_mem_ARREADY)
+    begin
+                ap_block_state11_io <= ((out_mem_ARREADY = ap_const_logic_0) or (in2_mem_ARREADY = ap_const_logic_0));
+    end process;
+
+
+    ap_block_state18_assign_proc : process(in1_mem_RVALID, in2_mem_RVALID, out_mem_RVALID)
+    begin
+                ap_block_state18 <= ((out_mem_RVALID = ap_const_logic_0) or (in2_mem_RVALID = ap_const_logic_0) or (in1_mem_RVALID = ap_const_logic_0));
+    end process;
+
+
+    ap_block_state3_io_assign_proc : process(icmp_ln20_fu_301_p2, in1_mem_ARREADY)
+    begin
+                ap_block_state3_io <= ((in1_mem_ARREADY = ap_const_logic_0) and (icmp_ln20_fu_301_p2 = ap_const_lv1_0));
+    end process;
+
+
+    ap_done_assign_proc : process(ap_CS_fsm_state2, icmp_ln18_fu_271_p2)
+    begin
+        if (((icmp_ln18_fu_271_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state2, icmp_ln18_fu_271_p2)
+    begin
+        if (((icmp_ln18_fu_271_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    i_fu_276_p2 <= std_logic_vector(unsigned(i_0_reg_163) + unsigned(ap_const_lv31_1));
+    icmp_ln18_fu_271_p2 <= "1" when (signed(zext_ln18_fu_267_p1) < signed(dim_read_reg_387)) else "0";
+    icmp_ln20_fu_301_p2 <= "1" when (j_0_reg_186 = dim_read_reg_387) else "0";
+    icmp_ln22_fu_337_p2 <= "1" when (k_0_reg_198 = dim_read_reg_387) else "0";
+
+    in1_mem_ARVALID_assign_proc : process(ap_CS_fsm_state3, icmp_ln20_fu_301_p2, ap_block_state3_io)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state3_io) and (icmp_ln20_fu_301_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then 
+            in1_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in1_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_RREADY_assign_proc : process(ap_CS_fsm_state18, in1_mem_RVALID, in2_mem_RVALID, out_mem_RVALID)
+    begin
+        if ((not(((out_mem_RVALID = ap_const_logic_0) or (in2_mem_RVALID = ap_const_logic_0) or (in1_mem_RVALID = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state18))) then 
+            in1_mem_RREADY <= ap_const_logic_1;
+        else 
+            in1_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_AR_assign_proc : process(m_axi_in1_mem_ARREADY, ap_CS_fsm_state3, icmp_ln20_fu_301_p2)
+    begin
+        if (((icmp_ln20_fu_301_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then 
+            in1_mem_blk_n_AR <= m_axi_in1_mem_ARREADY;
+        else 
+            in1_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_R_assign_proc : process(m_axi_in1_mem_RVALID, ap_CS_fsm_state18)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+            in1_mem_blk_n_R <= m_axi_in1_mem_RVALID;
+        else 
+            in1_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_ARVALID_assign_proc : process(ap_CS_fsm_state11, ap_block_state11_io)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state11_io) and (ap_const_logic_1 = ap_CS_fsm_state11))) then 
+            in2_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in2_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_RREADY_assign_proc : process(ap_CS_fsm_state18, in1_mem_RVALID, in2_mem_RVALID, out_mem_RVALID)
+    begin
+        if ((not(((out_mem_RVALID = ap_const_logic_0) or (in2_mem_RVALID = ap_const_logic_0) or (in1_mem_RVALID = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state18))) then 
+            in2_mem_RREADY <= ap_const_logic_1;
+        else 
+            in2_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_AR_assign_proc : process(m_axi_in2_mem_ARREADY, ap_CS_fsm_state11)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
+            in2_mem_blk_n_AR <= m_axi_in2_mem_ARREADY;
+        else 
+            in2_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_R_assign_proc : process(m_axi_in2_mem_RVALID, ap_CS_fsm_state18)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+            in2_mem_blk_n_R <= m_axi_in2_mem_RVALID;
+        else 
+            in2_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    j_fu_306_p2 <= std_logic_vector(unsigned(j_0_reg_186) + unsigned(ap_const_lv32_1));
+    k_fu_342_p2 <= std_logic_vector(unsigned(k_0_reg_198) + unsigned(ap_const_lv32_1));
+    mul_ln25_fu_378_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in1_mem_addr_read_reg_465) * signed(in2_mem_addr_read_reg_470))), 32));
+
+    out_mem_ARVALID_assign_proc : process(ap_CS_fsm_state11, ap_block_state11_io)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state11_io) and (ap_const_logic_1 = ap_CS_fsm_state11))) then 
+            out_mem_ARVALID <= ap_const_logic_1;
+        else 
+            out_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_AWVALID_assign_proc : process(ap_CS_fsm_state19, out_mem_AWREADY)
+    begin
+        if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state19))) then 
+            out_mem_AWVALID <= ap_const_logic_1;
+        else 
+            out_mem_AWVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_BREADY_assign_proc : process(ap_CS_fsm_state25, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then 
+            out_mem_BREADY <= ap_const_logic_1;
+        else 
+            out_mem_BREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_RREADY_assign_proc : process(ap_CS_fsm_state18, in1_mem_RVALID, in2_mem_RVALID, out_mem_RVALID)
+    begin
+        if ((not(((out_mem_RVALID = ap_const_logic_0) or (in2_mem_RVALID = ap_const_logic_0) or (in1_mem_RVALID = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state18))) then 
+            out_mem_RREADY <= ap_const_logic_1;
+        else 
+            out_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_WVALID_assign_proc : process(ap_CS_fsm_state20, out_mem_WREADY)
+    begin
+        if (((out_mem_WREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state20))) then 
+            out_mem_WVALID <= ap_const_logic_1;
+        else 
+            out_mem_WVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AR_assign_proc : process(m_axi_out_mem_ARREADY, ap_CS_fsm_state11)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
+            out_mem_blk_n_AR <= m_axi_out_mem_ARREADY;
+        else 
+            out_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AW_assign_proc : process(m_axi_out_mem_AWREADY, ap_CS_fsm_state19)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state19)) then 
+            out_mem_blk_n_AW <= m_axi_out_mem_AWREADY;
+        else 
+            out_mem_blk_n_AW <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_B_assign_proc : process(m_axi_out_mem_BVALID, ap_CS_fsm_state25)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            out_mem_blk_n_B <= m_axi_out_mem_BVALID;
+        else 
+            out_mem_blk_n_B <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_R_assign_proc : process(m_axi_out_mem_RVALID, ap_CS_fsm_state18)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+            out_mem_blk_n_R <= m_axi_out_mem_RVALID;
+        else 
+            out_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_W_assign_proc : process(m_axi_out_mem_WREADY, ap_CS_fsm_state20)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state20)) then 
+            out_mem_blk_n_W <= m_axi_out_mem_WREADY;
+        else 
+            out_mem_blk_n_W <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    p_cast10_fu_244_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_fu_234_p4),33));
+    p_cast11_fu_230_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_3_fu_220_p4),33));
+    p_cast_fu_258_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_fu_248_p4),33));
+        sext_ln25_1_fu_291_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln25_1_fu_286_p2),64));
+
+        sext_ln25_2_fu_318_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln25_fu_312_p2),33));
+
+        sext_ln25_3_fu_327_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln25_4_fu_322_p2),64));
+
+        sext_ln25_4_fu_359_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln25_2_fu_353_p2),33));
+
+        sext_ln25_5_fu_368_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln25_6_fu_363_p2),64));
+
+        sext_ln25_fu_282_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(phi_mul8_reg_174),33));
+
+    tmp_3_fu_220_p4 <= out_r(31 downto 2);
+    tmp_4_fu_234_p4 <= in2(31 downto 2);
+    tmp_5_fu_248_p4 <= in1(31 downto 2);
+    zext_ln18_fu_267_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_0_reg_163),32));
+end behav;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_in1_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_in1_mem_m_axi.vhd
new file mode 100644
index 0000000..5d4f5b4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_in1_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi;
+
+architecture behave of mmult_in1_mem_m_axi is
+    component mmult_in1_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_write;
+
+    component mmult_in1_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_read;
+
+    component mmult_in1_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in1_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in1_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in1_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in1_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in1_mem_m_axi_fifo;
+
+architecture behave of mmult_in1_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in1_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in1_mem_m_axi_decoder;
+
+architecture behav of mmult_in1_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in1_mem_m_axi_throttl;
+
+architecture behav of mmult_in1_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in1_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in1_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_read;
+
+architecture behave of mmult_in1_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_write;
+
+architecture behave of mmult_in1_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in1_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in1_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_in2_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_in2_mem_m_axi.vhd
new file mode 100644
index 0000000..84687e2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_in2_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi;
+
+architecture behave of mmult_in2_mem_m_axi is
+    component mmult_in2_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_write;
+
+    component mmult_in2_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_read;
+
+    component mmult_in2_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in2_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in2_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in2_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in2_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in2_mem_m_axi_fifo;
+
+architecture behave of mmult_in2_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in2_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in2_mem_m_axi_decoder;
+
+architecture behav of mmult_in2_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in2_mem_m_axi_throttl;
+
+architecture behav of mmult_in2_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in2_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in2_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_read;
+
+architecture behave of mmult_in2_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_write;
+
+architecture behave of mmult_in2_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in2_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in2_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_out_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_out_mem_m_axi.vhd
new file mode 100644
index 0000000..f2bd717
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_out_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi;
+
+architecture behave of mmult_out_mem_m_axi is
+    component mmult_out_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_write;
+
+    component mmult_out_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_read;
+
+    component mmult_out_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_out_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_out_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_out_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi_reg_slice;
+
+architecture behave of mmult_out_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_out_mem_m_axi_fifo;
+
+architecture behave of mmult_out_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_out_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_out_mem_m_axi_decoder;
+
+architecture behav of mmult_out_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_out_mem_m_axi_throttl;
+
+architecture behav of mmult_out_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_out_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_out_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_read;
+
+architecture behave of mmult_out_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_write;
+
+architecture behave of mmult_out_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_out_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_out_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_params_s_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_params_s_axi.vhd
new file mode 100644
index 0000000..1f9adde
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_params_s_axi.vhd
@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/misc/logo.png b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/misc/logo.png
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diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/xgui/mmult_v1_0.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/xgui/mmult_v1_0.tcl
new file mode 100644
index 0000000..0276fbf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_2/xgui/mmult_v1_0.tcl
@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/component.xml b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/component.xml
new file mode 100755
index 0000000..4dbbf4e
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/component.xml
@@ -0,0 +1,5560 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>hls</spirit:library>
+  <spirit:name>mmult</spirit:name>
+  <spirit:version>2.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_params"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.ADDR_WIDTH">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi_params:m_axi_in1_mem:m_axi_in2_mem:m_axi_out_mem</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interrupt</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in1_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in1_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in2_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in2_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_out_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_out_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in1_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in2_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_out_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_BASE_PARAM">C_S_AXI_PARAMS_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_HIGH_PARAM">C_S_AXI_PARAMS_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>CTRL</spirit:name>
+          <spirit:displayName>CTRL</spirit:displayName>
+          <spirit:description>Control signals</spirit:description>
+          <spirit:addressOffset>0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>AP_START</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_start&apos;.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_DONE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_done&apos;.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_IDLE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_idle&apos;.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_READY</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_ready&apos;.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_1</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">3</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AUTO_RESTART</spirit:name>
+            <spirit:description>Control signal Register for &apos;auto_restart&apos;.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_2</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">24</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GIER</spirit:name>
+          <spirit:displayName>GIER</spirit:displayName>
+          <spirit:description>Global Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>4</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Enable</spirit:name>
+            <spirit:description>Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">31</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_IER</spirit:name>
+          <spirit:displayName>IP_IER</spirit:displayName>
+          <spirit:description>IP Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>8</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 0 (ap_done) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 1 (ap_ready) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_ISR</spirit:name>
+          <spirit:displayName>IP_ISR</spirit:displayName>
+          <spirit:description>IP Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>12</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_ST</spirit:name>
+            <spirit:description>Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 input interrupt, 1 = Channel 0 input interrup</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_ST</spirit:name>
+            <spirit:description>Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 input interrupt, 1 = Channel 1 input interrup</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:name>in1</spirit:name>
+          <spirit:displayName>in1</spirit:displayName>
+          <spirit:description>Data signal of in1</spirit:description>
+          <spirit:addressOffset>16</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+          <spirit:field>
+            <spirit:name>in1</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of in1</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:displayName>in2</spirit:displayName>
+          <spirit:description>Data signal of in2</spirit:description>
+          <spirit:addressOffset>24</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+            <spirit:name>in2</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of in2</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:description>Data signal of out_r</spirit:description>
+          <spirit:addressOffset>32</spirit:addressOffset>
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+          <spirit:access>write-only</spirit:access>
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+            <spirit:value spirit:format="long">0</spirit:value>
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+            <spirit:description>Bit 31 to 0 Data signal of out_r</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
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+            <spirit:description>Bit 31 to 0 Data signal of dim</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE" spirit:order="12" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE" spirit:order="13" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" spirit:order="14" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH" spirit:order="15" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="16" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" spirit:order="17" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH" spirit:order="18" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH" spirit:order="19" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH" spirit:order="20" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH" spirit:order="21" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH" spirit:order="22" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE" spirit:order="23" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE" spirit:order="24" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE" spirit:order="25" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" spirit:order="26" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH" spirit:order="27" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="28" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" spirit:order="29" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH" spirit:order="30" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH" spirit:order="31" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH" spirit:order="32" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH" spirit:order="33" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH" spirit:order="34" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE" spirit:order="35" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE" spirit:order="36" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE" spirit:order="37" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mmult_v2_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>clk_period</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.clk_period" spirit:order="38">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>machine</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.machine" spirit:order="39">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>combinational</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.combinational" spirit:order="40">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>latency</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.latency" spirit:order="41">3932262</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>II</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.II" spirit:order="42">x</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/VIVADO_HLS_IP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>mmult pipeline</xilinx:displayName>
+      <xilinx:definitionSource>HLS</xilinx:definitionSource>
+      <xilinx:coreRevision>2105141659</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2021-05-14T15:00:08Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b5dd57e8"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="c6fd4807"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5ce530f0"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="828bcf25"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="7681d788"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c9a673dd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="cd57ab3c"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/constraints/mmult_ooc.xdc b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/constraints/mmult_ooc.xdc
new file mode 100755
index 0000000..2ed5eee
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/constraints/mmult_ooc.xdc
@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/doc/ReleaseNotes.txt b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/doc/ReleaseNotes.txt
new file mode 100755
index 0000000..48cc01b
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/doc/ReleaseNotes.txt
@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.mdd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.mdd
new file mode 100755
index 0000000..0c2ccb9
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.mdd
@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v2_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 2.0;
+
+END driver
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.tcl
new file mode 100755
index 0000000..0de7a9c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.tcl
@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/Makefile b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/Makefile
new file mode 100755
index 0000000..7f76086
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/Makefile
@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.c
new file mode 100755
index 0000000..fb9a1fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.c
@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.h
new file mode 100755
index 0000000..4983669
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.h
@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_hw.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_hw.h
new file mode 100755
index 0000000..3a0a2a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_hw.h
@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_linux.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_linux.c
new file mode 100755
index 0000000..c8dbb33
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_linux.c
@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_sinit.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_sinit.c
new file mode 100755
index 0000000..f099590
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_sinit.c
@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult.v
new file mode 100755
index 0000000..fdd02a0
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult.v
@@ -0,0 +1,2318 @@
+// ==============================================================
+// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+// Version: 2020.1
+// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+// 
+// ===========================================================
+
+`timescale 1 ns / 1 ps 
+
+(* CORE_GENERATION_INFO="mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=3932262,HLS_SYN_TPT=none,HLS_SYN_MEM=6,HLS_SYN_DSP=28,HLS_SYN_FF=11990,HLS_SYN_LUT=10233,HLS_VERSION=2020_1}" *)
+
+module mmult (
+        ap_clk,
+        ap_rst_n,
+        m_axi_in1_mem_AWVALID,
+        m_axi_in1_mem_AWREADY,
+        m_axi_in1_mem_AWADDR,
+        m_axi_in1_mem_AWID,
+        m_axi_in1_mem_AWLEN,
+        m_axi_in1_mem_AWSIZE,
+        m_axi_in1_mem_AWBURST,
+        m_axi_in1_mem_AWLOCK,
+        m_axi_in1_mem_AWCACHE,
+        m_axi_in1_mem_AWPROT,
+        m_axi_in1_mem_AWQOS,
+        m_axi_in1_mem_AWREGION,
+        m_axi_in1_mem_AWUSER,
+        m_axi_in1_mem_WVALID,
+        m_axi_in1_mem_WREADY,
+        m_axi_in1_mem_WDATA,
+        m_axi_in1_mem_WSTRB,
+        m_axi_in1_mem_WLAST,
+        m_axi_in1_mem_WID,
+        m_axi_in1_mem_WUSER,
+        m_axi_in1_mem_ARVALID,
+        m_axi_in1_mem_ARREADY,
+        m_axi_in1_mem_ARADDR,
+        m_axi_in1_mem_ARID,
+        m_axi_in1_mem_ARLEN,
+        m_axi_in1_mem_ARSIZE,
+        m_axi_in1_mem_ARBURST,
+        m_axi_in1_mem_ARLOCK,
+        m_axi_in1_mem_ARCACHE,
+        m_axi_in1_mem_ARPROT,
+        m_axi_in1_mem_ARQOS,
+        m_axi_in1_mem_ARREGION,
+        m_axi_in1_mem_ARUSER,
+        m_axi_in1_mem_RVALID,
+        m_axi_in1_mem_RREADY,
+        m_axi_in1_mem_RDATA,
+        m_axi_in1_mem_RLAST,
+        m_axi_in1_mem_RID,
+        m_axi_in1_mem_RUSER,
+        m_axi_in1_mem_RRESP,
+        m_axi_in1_mem_BVALID,
+        m_axi_in1_mem_BREADY,
+        m_axi_in1_mem_BRESP,
+        m_axi_in1_mem_BID,
+        m_axi_in1_mem_BUSER,
+        m_axi_in2_mem_AWVALID,
+        m_axi_in2_mem_AWREADY,
+        m_axi_in2_mem_AWADDR,
+        m_axi_in2_mem_AWID,
+        m_axi_in2_mem_AWLEN,
+        m_axi_in2_mem_AWSIZE,
+        m_axi_in2_mem_AWBURST,
+        m_axi_in2_mem_AWLOCK,
+        m_axi_in2_mem_AWCACHE,
+        m_axi_in2_mem_AWPROT,
+        m_axi_in2_mem_AWQOS,
+        m_axi_in2_mem_AWREGION,
+        m_axi_in2_mem_AWUSER,
+        m_axi_in2_mem_WVALID,
+        m_axi_in2_mem_WREADY,
+        m_axi_in2_mem_WDATA,
+        m_axi_in2_mem_WSTRB,
+        m_axi_in2_mem_WLAST,
+        m_axi_in2_mem_WID,
+        m_axi_in2_mem_WUSER,
+        m_axi_in2_mem_ARVALID,
+        m_axi_in2_mem_ARREADY,
+        m_axi_in2_mem_ARADDR,
+        m_axi_in2_mem_ARID,
+        m_axi_in2_mem_ARLEN,
+        m_axi_in2_mem_ARSIZE,
+        m_axi_in2_mem_ARBURST,
+        m_axi_in2_mem_ARLOCK,
+        m_axi_in2_mem_ARCACHE,
+        m_axi_in2_mem_ARPROT,
+        m_axi_in2_mem_ARQOS,
+        m_axi_in2_mem_ARREGION,
+        m_axi_in2_mem_ARUSER,
+        m_axi_in2_mem_RVALID,
+        m_axi_in2_mem_RREADY,
+        m_axi_in2_mem_RDATA,
+        m_axi_in2_mem_RLAST,
+        m_axi_in2_mem_RID,
+        m_axi_in2_mem_RUSER,
+        m_axi_in2_mem_RRESP,
+        m_axi_in2_mem_BVALID,
+        m_axi_in2_mem_BREADY,
+        m_axi_in2_mem_BRESP,
+        m_axi_in2_mem_BID,
+        m_axi_in2_mem_BUSER,
+        m_axi_out_mem_AWVALID,
+        m_axi_out_mem_AWREADY,
+        m_axi_out_mem_AWADDR,
+        m_axi_out_mem_AWID,
+        m_axi_out_mem_AWLEN,
+        m_axi_out_mem_AWSIZE,
+        m_axi_out_mem_AWBURST,
+        m_axi_out_mem_AWLOCK,
+        m_axi_out_mem_AWCACHE,
+        m_axi_out_mem_AWPROT,
+        m_axi_out_mem_AWQOS,
+        m_axi_out_mem_AWREGION,
+        m_axi_out_mem_AWUSER,
+        m_axi_out_mem_WVALID,
+        m_axi_out_mem_WREADY,
+        m_axi_out_mem_WDATA,
+        m_axi_out_mem_WSTRB,
+        m_axi_out_mem_WLAST,
+        m_axi_out_mem_WID,
+        m_axi_out_mem_WUSER,
+        m_axi_out_mem_ARVALID,
+        m_axi_out_mem_ARREADY,
+        m_axi_out_mem_ARADDR,
+        m_axi_out_mem_ARID,
+        m_axi_out_mem_ARLEN,
+        m_axi_out_mem_ARSIZE,
+        m_axi_out_mem_ARBURST,
+        m_axi_out_mem_ARLOCK,
+        m_axi_out_mem_ARCACHE,
+        m_axi_out_mem_ARPROT,
+        m_axi_out_mem_ARQOS,
+        m_axi_out_mem_ARREGION,
+        m_axi_out_mem_ARUSER,
+        m_axi_out_mem_RVALID,
+        m_axi_out_mem_RREADY,
+        m_axi_out_mem_RDATA,
+        m_axi_out_mem_RLAST,
+        m_axi_out_mem_RID,
+        m_axi_out_mem_RUSER,
+        m_axi_out_mem_RRESP,
+        m_axi_out_mem_BVALID,
+        m_axi_out_mem_BREADY,
+        m_axi_out_mem_BRESP,
+        m_axi_out_mem_BID,
+        m_axi_out_mem_BUSER,
+        s_axi_params_AWVALID,
+        s_axi_params_AWREADY,
+        s_axi_params_AWADDR,
+        s_axi_params_WVALID,
+        s_axi_params_WREADY,
+        s_axi_params_WDATA,
+        s_axi_params_WSTRB,
+        s_axi_params_ARVALID,
+        s_axi_params_ARREADY,
+        s_axi_params_ARADDR,
+        s_axi_params_RVALID,
+        s_axi_params_RREADY,
+        s_axi_params_RDATA,
+        s_axi_params_RRESP,
+        s_axi_params_BVALID,
+        s_axi_params_BREADY,
+        s_axi_params_BRESP,
+        interrupt
+);
+
+parameter    ap_ST_fsm_state1 = 18'd1;
+parameter    ap_ST_fsm_state2 = 18'd2;
+parameter    ap_ST_fsm_pp0_stage0 = 18'd4;
+parameter    ap_ST_fsm_pp0_stage1 = 18'd8;
+parameter    ap_ST_fsm_pp0_stage2 = 18'd16;
+parameter    ap_ST_fsm_pp0_stage3 = 18'd32;
+parameter    ap_ST_fsm_pp0_stage4 = 18'd64;
+parameter    ap_ST_fsm_pp0_stage5 = 18'd128;
+parameter    ap_ST_fsm_pp0_stage6 = 18'd256;
+parameter    ap_ST_fsm_pp0_stage7 = 18'd512;
+parameter    ap_ST_fsm_pp0_stage8 = 18'd1024;
+parameter    ap_ST_fsm_pp0_stage9 = 18'd2048;
+parameter    ap_ST_fsm_pp0_stage10 = 18'd4096;
+parameter    ap_ST_fsm_pp0_stage11 = 18'd8192;
+parameter    ap_ST_fsm_pp0_stage12 = 18'd16384;
+parameter    ap_ST_fsm_pp0_stage13 = 18'd32768;
+parameter    ap_ST_fsm_pp0_stage14 = 18'd65536;
+parameter    ap_ST_fsm_state118 = 18'd131072;
+parameter    C_S_AXI_PARAMS_DATA_WIDTH = 32;
+parameter    C_S_AXI_PARAMS_ADDR_WIDTH = 6;
+parameter    C_S_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_OUT_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_CACHE_VALUE = 3;
+
+parameter C_S_AXI_PARAMS_WSTRB_WIDTH = (32 / 8);
+parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN1_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN2_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_OUT_MEM_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+output   m_axi_in1_mem_AWVALID;
+input   m_axi_in1_mem_AWREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_AWADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_AWID;
+output  [7:0] m_axi_in1_mem_AWLEN;
+output  [2:0] m_axi_in1_mem_AWSIZE;
+output  [1:0] m_axi_in1_mem_AWBURST;
+output  [1:0] m_axi_in1_mem_AWLOCK;
+output  [3:0] m_axi_in1_mem_AWCACHE;
+output  [2:0] m_axi_in1_mem_AWPROT;
+output  [3:0] m_axi_in1_mem_AWQOS;
+output  [3:0] m_axi_in1_mem_AWREGION;
+output  [C_M_AXI_IN1_MEM_AWUSER_WIDTH - 1:0] m_axi_in1_mem_AWUSER;
+output   m_axi_in1_mem_WVALID;
+input   m_axi_in1_mem_WREADY;
+output  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_WDATA;
+output  [C_M_AXI_IN1_MEM_WSTRB_WIDTH - 1:0] m_axi_in1_mem_WSTRB;
+output   m_axi_in1_mem_WLAST;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_WID;
+output  [C_M_AXI_IN1_MEM_WUSER_WIDTH - 1:0] m_axi_in1_mem_WUSER;
+output   m_axi_in1_mem_ARVALID;
+input   m_axi_in1_mem_ARREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_ARADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_ARID;
+output  [7:0] m_axi_in1_mem_ARLEN;
+output  [2:0] m_axi_in1_mem_ARSIZE;
+output  [1:0] m_axi_in1_mem_ARBURST;
+output  [1:0] m_axi_in1_mem_ARLOCK;
+output  [3:0] m_axi_in1_mem_ARCACHE;
+output  [2:0] m_axi_in1_mem_ARPROT;
+output  [3:0] m_axi_in1_mem_ARQOS;
+output  [3:0] m_axi_in1_mem_ARREGION;
+output  [C_M_AXI_IN1_MEM_ARUSER_WIDTH - 1:0] m_axi_in1_mem_ARUSER;
+input   m_axi_in1_mem_RVALID;
+output   m_axi_in1_mem_RREADY;
+input  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_RDATA;
+input   m_axi_in1_mem_RLAST;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_RID;
+input  [C_M_AXI_IN1_MEM_RUSER_WIDTH - 1:0] m_axi_in1_mem_RUSER;
+input  [1:0] m_axi_in1_mem_RRESP;
+input   m_axi_in1_mem_BVALID;
+output   m_axi_in1_mem_BREADY;
+input  [1:0] m_axi_in1_mem_BRESP;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_BID;
+input  [C_M_AXI_IN1_MEM_BUSER_WIDTH - 1:0] m_axi_in1_mem_BUSER;
+output   m_axi_in2_mem_AWVALID;
+input   m_axi_in2_mem_AWREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_AWADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_AWID;
+output  [7:0] m_axi_in2_mem_AWLEN;
+output  [2:0] m_axi_in2_mem_AWSIZE;
+output  [1:0] m_axi_in2_mem_AWBURST;
+output  [1:0] m_axi_in2_mem_AWLOCK;
+output  [3:0] m_axi_in2_mem_AWCACHE;
+output  [2:0] m_axi_in2_mem_AWPROT;
+output  [3:0] m_axi_in2_mem_AWQOS;
+output  [3:0] m_axi_in2_mem_AWREGION;
+output  [C_M_AXI_IN2_MEM_AWUSER_WIDTH - 1:0] m_axi_in2_mem_AWUSER;
+output   m_axi_in2_mem_WVALID;
+input   m_axi_in2_mem_WREADY;
+output  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_WDATA;
+output  [C_M_AXI_IN2_MEM_WSTRB_WIDTH - 1:0] m_axi_in2_mem_WSTRB;
+output   m_axi_in2_mem_WLAST;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_WID;
+output  [C_M_AXI_IN2_MEM_WUSER_WIDTH - 1:0] m_axi_in2_mem_WUSER;
+output   m_axi_in2_mem_ARVALID;
+input   m_axi_in2_mem_ARREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_ARADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_ARID;
+output  [7:0] m_axi_in2_mem_ARLEN;
+output  [2:0] m_axi_in2_mem_ARSIZE;
+output  [1:0] m_axi_in2_mem_ARBURST;
+output  [1:0] m_axi_in2_mem_ARLOCK;
+output  [3:0] m_axi_in2_mem_ARCACHE;
+output  [2:0] m_axi_in2_mem_ARPROT;
+output  [3:0] m_axi_in2_mem_ARQOS;
+output  [3:0] m_axi_in2_mem_ARREGION;
+output  [C_M_AXI_IN2_MEM_ARUSER_WIDTH - 1:0] m_axi_in2_mem_ARUSER;
+input   m_axi_in2_mem_RVALID;
+output   m_axi_in2_mem_RREADY;
+input  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_RDATA;
+input   m_axi_in2_mem_RLAST;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_RID;
+input  [C_M_AXI_IN2_MEM_RUSER_WIDTH - 1:0] m_axi_in2_mem_RUSER;
+input  [1:0] m_axi_in2_mem_RRESP;
+input   m_axi_in2_mem_BVALID;
+output   m_axi_in2_mem_BREADY;
+input  [1:0] m_axi_in2_mem_BRESP;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_BID;
+input  [C_M_AXI_IN2_MEM_BUSER_WIDTH - 1:0] m_axi_in2_mem_BUSER;
+output   m_axi_out_mem_AWVALID;
+input   m_axi_out_mem_AWREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_AWADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_AWID;
+output  [7:0] m_axi_out_mem_AWLEN;
+output  [2:0] m_axi_out_mem_AWSIZE;
+output  [1:0] m_axi_out_mem_AWBURST;
+output  [1:0] m_axi_out_mem_AWLOCK;
+output  [3:0] m_axi_out_mem_AWCACHE;
+output  [2:0] m_axi_out_mem_AWPROT;
+output  [3:0] m_axi_out_mem_AWQOS;
+output  [3:0] m_axi_out_mem_AWREGION;
+output  [C_M_AXI_OUT_MEM_AWUSER_WIDTH - 1:0] m_axi_out_mem_AWUSER;
+output   m_axi_out_mem_WVALID;
+input   m_axi_out_mem_WREADY;
+output  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_WDATA;
+output  [C_M_AXI_OUT_MEM_WSTRB_WIDTH - 1:0] m_axi_out_mem_WSTRB;
+output   m_axi_out_mem_WLAST;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_WID;
+output  [C_M_AXI_OUT_MEM_WUSER_WIDTH - 1:0] m_axi_out_mem_WUSER;
+output   m_axi_out_mem_ARVALID;
+input   m_axi_out_mem_ARREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_ARADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_ARID;
+output  [7:0] m_axi_out_mem_ARLEN;
+output  [2:0] m_axi_out_mem_ARSIZE;
+output  [1:0] m_axi_out_mem_ARBURST;
+output  [1:0] m_axi_out_mem_ARLOCK;
+output  [3:0] m_axi_out_mem_ARCACHE;
+output  [2:0] m_axi_out_mem_ARPROT;
+output  [3:0] m_axi_out_mem_ARQOS;
+output  [3:0] m_axi_out_mem_ARREGION;
+output  [C_M_AXI_OUT_MEM_ARUSER_WIDTH - 1:0] m_axi_out_mem_ARUSER;
+input   m_axi_out_mem_RVALID;
+output   m_axi_out_mem_RREADY;
+input  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_RDATA;
+input   m_axi_out_mem_RLAST;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_RID;
+input  [C_M_AXI_OUT_MEM_RUSER_WIDTH - 1:0] m_axi_out_mem_RUSER;
+input  [1:0] m_axi_out_mem_RRESP;
+input   m_axi_out_mem_BVALID;
+output   m_axi_out_mem_BREADY;
+input  [1:0] m_axi_out_mem_BRESP;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_BID;
+input  [C_M_AXI_OUT_MEM_BUSER_WIDTH - 1:0] m_axi_out_mem_BUSER;
+input   s_axi_params_AWVALID;
+output   s_axi_params_AWREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_AWADDR;
+input   s_axi_params_WVALID;
+output   s_axi_params_WREADY;
+input  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_WDATA;
+input  [C_S_AXI_PARAMS_WSTRB_WIDTH - 1:0] s_axi_params_WSTRB;
+input   s_axi_params_ARVALID;
+output   s_axi_params_ARREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_ARADDR;
+output   s_axi_params_RVALID;
+input   s_axi_params_RREADY;
+output  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_RDATA;
+output  [1:0] s_axi_params_RRESP;
+output   s_axi_params_BVALID;
+input   s_axi_params_BREADY;
+output  [1:0] s_axi_params_BRESP;
+output   interrupt;
+
+ reg    ap_rst_n_inv;
+wire    ap_start;
+reg    ap_done;
+reg    ap_idle;
+(* fsm_encoding = "none" *) reg   [17:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    ap_ready;
+wire   [31:0] in1;
+wire   [31:0] in2;
+wire   [31:0] out_r;
+wire   [31:0] dim;
+reg    in1_mem_blk_n_AR;
+wire    ap_CS_fsm_pp0_stage10;
+reg    ap_enable_reg_pp0_iter6;
+wire    ap_block_pp0_stage10;
+reg   [0:0] icmp_ln8_reg_676;
+reg    in1_mem_blk_n_R;
+wire    ap_CS_fsm_pp0_stage2;
+reg    ap_enable_reg_pp0_iter7;
+wire    ap_block_pp0_stage2;
+reg   [0:0] icmp_ln19_reg_600;
+reg   [0:0] icmp_ln19_reg_600_pp0_iter7_reg;
+reg    in2_mem_blk_n_AR;
+wire    ap_CS_fsm_pp0_stage3;
+reg    ap_enable_reg_pp0_iter0;
+wire    ap_block_pp0_stage3;
+reg    in2_mem_blk_n_R;
+reg    out_mem_blk_n_AR;
+reg   [0:0] icmp_ln19_reg_600_pp0_iter6_reg;
+reg    out_mem_blk_n_R;
+reg    out_mem_blk_n_AW;
+reg    out_mem_blk_n_W;
+wire    ap_CS_fsm_pp0_stage4;
+wire    ap_block_pp0_stage4;
+reg    out_mem_blk_n_B;
+wire    ap_CS_fsm_pp0_stage9;
+wire    ap_block_pp0_stage9;
+wire    in1_mem_AWREADY;
+wire    in1_mem_WREADY;
+reg    in1_mem_ARVALID;
+wire    in1_mem_ARREADY;
+wire    in1_mem_RVALID;
+reg    in1_mem_RREADY;
+wire   [31:0] in1_mem_RDATA;
+wire    in1_mem_RLAST;
+wire   [0:0] in1_mem_RID;
+wire   [0:0] in1_mem_RUSER;
+wire   [1:0] in1_mem_RRESP;
+wire    in1_mem_BVALID;
+wire   [1:0] in1_mem_BRESP;
+wire   [0:0] in1_mem_BID;
+wire   [0:0] in1_mem_BUSER;
+wire    in2_mem_AWREADY;
+wire    in2_mem_WREADY;
+reg    in2_mem_ARVALID;
+wire    in2_mem_ARREADY;
+wire    in2_mem_RVALID;
+reg    in2_mem_RREADY;
+wire   [31:0] in2_mem_RDATA;
+wire    in2_mem_RLAST;
+wire   [0:0] in2_mem_RID;
+wire   [0:0] in2_mem_RUSER;
+wire   [1:0] in2_mem_RRESP;
+wire    in2_mem_BVALID;
+wire   [1:0] in2_mem_BRESP;
+wire   [0:0] in2_mem_BID;
+wire   [0:0] in2_mem_BUSER;
+reg    out_mem_AWVALID;
+wire    out_mem_AWREADY;
+reg    out_mem_WVALID;
+wire    out_mem_WREADY;
+reg    out_mem_ARVALID;
+wire    out_mem_ARREADY;
+wire    out_mem_RVALID;
+reg    out_mem_RREADY;
+wire   [31:0] out_mem_RDATA;
+wire    out_mem_RLAST;
+wire   [0:0] out_mem_RID;
+wire   [0:0] out_mem_RUSER;
+wire   [1:0] out_mem_RRESP;
+wire    out_mem_BVALID;
+reg    out_mem_BREADY;
+wire   [1:0] out_mem_BRESP;
+wire   [0:0] out_mem_BID;
+wire   [0:0] out_mem_BUSER;
+reg   [95:0] indvar_flatten18_reg_171;
+wire    ap_CS_fsm_pp0_stage0;
+wire    ap_block_state3_pp0_stage0_iter0;
+wire    ap_block_state18_pp0_stage0_iter1;
+wire    ap_block_state33_pp0_stage0_iter2;
+wire    ap_block_state48_pp0_stage0_iter3;
+wire    ap_block_state63_pp0_stage0_iter4;
+wire    ap_block_state78_pp0_stage0_iter5;
+wire    ap_block_state93_pp0_stage0_iter6;
+wire    ap_block_state108_pp0_stage0_iter7;
+wire    ap_block_pp0_stage0_11001;
+reg   [30:0] i_0_reg_183;
+reg   [63:0] indvar_flatten_reg_195;
+reg   [31:0] j_0_reg_207;
+reg   [31:0] k_0_reg_219;
+reg   [31:0] dim_read_reg_528;
+reg   [29:0] tmp_reg_539;
+reg   [29:0] tmp_1_reg_544;
+reg   [29:0] tmp_3_reg_549;
+wire   [63:0] bound_fu_265_p2;
+reg   [63:0] bound_reg_554;
+wire   [32:0] p_cast20_fu_271_p1;
+reg   [32:0] p_cast20_reg_560;
+wire    ap_CS_fsm_state2;
+wire   [32:0] p_cast19_fu_274_p1;
+reg   [32:0] p_cast19_reg_565;
+wire   [32:0] p_cast_fu_277_p1;
+reg   [32:0] p_cast_reg_570;
+wire   [95:0] cast5_fu_280_p1;
+reg   [95:0] cast5_reg_575;
+wire   [95:0] bound7_fu_286_p2;
+reg   [95:0] bound7_reg_580;
+wire   [0:0] icmp_ln21_fu_292_p2;
+reg   [0:0] icmp_ln21_reg_585;
+wire   [31:0] mul_ln26_fu_301_p2;
+reg   [31:0] mul_ln26_reg_590;
+wire   [31:0] add_ln26_fu_306_p2;
+reg   [31:0] add_ln26_reg_595;
+wire   [0:0] icmp_ln19_fu_312_p2;
+reg   [0:0] icmp_ln19_reg_600_pp0_iter1_reg;
+reg   [0:0] icmp_ln19_reg_600_pp0_iter2_reg;
+reg   [0:0] icmp_ln19_reg_600_pp0_iter3_reg;
+reg   [0:0] icmp_ln19_reg_600_pp0_iter4_reg;
+reg   [0:0] icmp_ln19_reg_600_pp0_iter5_reg;
+wire   [95:0] add_ln19_fu_317_p2;
+reg   [95:0] add_ln19_reg_604;
+wire   [30:0] add_ln19_1_fu_328_p2;
+reg   [30:0] add_ln19_1_reg_609;
+wire    ap_CS_fsm_pp0_stage1;
+wire    ap_block_state4_pp0_stage1_iter0;
+wire    ap_block_state19_pp0_stage1_iter1;
+wire    ap_block_state34_pp0_stage1_iter2;
+wire    ap_block_state49_pp0_stage1_iter3;
+wire    ap_block_state64_pp0_stage1_iter4;
+wire    ap_block_state79_pp0_stage1_iter5;
+wire    ap_block_state94_pp0_stage1_iter6;
+wire    ap_block_state109_pp0_stage1_iter7;
+wire    ap_block_pp0_stage1_11001;
+wire   [0:0] icmp_ln21_1_fu_338_p2;
+reg   [0:0] icmp_ln21_1_reg_614;
+wire  signed [31:0] select_ln26_fu_398_p3;
+reg  signed [31:0] select_ln26_reg_620;
+wire   [31:0] select_ln21_fu_424_p3;
+reg   [31:0] select_ln21_reg_626;
+reg   [31:0] in1_mem_addr_reg_632;
+reg   [31:0] in1_mem_addr_reg_632_pp0_iter1_reg;
+reg   [31:0] in1_mem_addr_reg_632_pp0_iter2_reg;
+reg   [31:0] in1_mem_addr_reg_632_pp0_iter3_reg;
+reg   [31:0] in1_mem_addr_reg_632_pp0_iter4_reg;
+reg   [31:0] in1_mem_addr_reg_632_pp0_iter5_reg;
+reg   [31:0] in1_mem_addr_reg_632_pp0_iter6_reg;
+reg   [31:0] out_mem_addr_reg_638;
+reg   [31:0] out_mem_addr_reg_638_pp0_iter1_reg;
+reg   [31:0] out_mem_addr_reg_638_pp0_iter2_reg;
+reg   [31:0] out_mem_addr_reg_638_pp0_iter3_reg;
+reg   [31:0] out_mem_addr_reg_638_pp0_iter4_reg;
+reg   [31:0] out_mem_addr_reg_638_pp0_iter5_reg;
+reg   [31:0] out_mem_addr_reg_638_pp0_iter6_reg;
+reg   [31:0] out_mem_addr_reg_638_pp0_iter7_reg;
+wire   [63:0] add_ln21_1_fu_462_p2;
+reg   [63:0] add_ln21_1_reg_645;
+reg   [31:0] in2_mem_addr_reg_650;
+wire    ap_block_state5_pp0_stage2_iter0;
+wire    ap_block_state20_pp0_stage2_iter1;
+wire    ap_block_state35_pp0_stage2_iter2;
+wire    ap_block_state50_pp0_stage2_iter3;
+wire    ap_block_state65_pp0_stage2_iter4;
+wire    ap_block_state80_pp0_stage2_iter5;
+wire    ap_block_state95_pp0_stage2_iter6;
+reg    ap_block_state110_pp0_stage2_iter7;
+reg    ap_block_pp0_stage2_11001;
+reg  signed [31:0] in2_mem_addr_read_reg_656;
+reg    ap_block_state13_pp0_stage10_iter0;
+wire    ap_block_state28_pp0_stage10_iter1;
+wire    ap_block_state43_pp0_stage10_iter2;
+wire    ap_block_state58_pp0_stage10_iter3;
+wire    ap_block_state73_pp0_stage10_iter4;
+wire    ap_block_state88_pp0_stage10_iter5;
+wire    ap_block_state103_pp0_stage10_iter6;
+reg    ap_block_state103_io;
+reg    ap_block_pp0_stage10_11001;
+reg  signed [31:0] in2_mem_addr_read_reg_656_pp0_iter1_reg;
+reg  signed [31:0] in2_mem_addr_read_reg_656_pp0_iter2_reg;
+reg  signed [31:0] in2_mem_addr_read_reg_656_pp0_iter3_reg;
+reg  signed [31:0] in2_mem_addr_read_reg_656_pp0_iter4_reg;
+reg  signed [31:0] in2_mem_addr_read_reg_656_pp0_iter5_reg;
+reg  signed [31:0] in2_mem_addr_read_reg_656_pp0_iter6_reg;
+wire   [30:0] select_ln19_4_fu_496_p3;
+reg   [30:0] select_ln19_4_reg_661;
+wire    ap_CS_fsm_pp0_stage14;
+wire    ap_block_state17_pp0_stage14_iter0;
+wire    ap_block_state32_pp0_stage14_iter1;
+wire    ap_block_state47_pp0_stage14_iter2;
+wire    ap_block_state62_pp0_stage14_iter3;
+wire    ap_block_state77_pp0_stage14_iter4;
+wire    ap_block_state92_pp0_stage14_iter5;
+wire    ap_block_state107_pp0_stage14_iter6;
+wire    ap_block_pp0_stage14_11001;
+wire   [31:0] k_fu_502_p2;
+reg   [31:0] k_reg_666;
+reg    ap_enable_reg_pp0_iter1;
+wire   [63:0] select_ln21_1_fu_507_p3;
+reg   [63:0] select_ln21_1_reg_671;
+wire   [0:0] icmp_ln8_fu_513_p2;
+wire    ap_block_state12_pp0_stage9_iter0;
+wire    ap_block_state27_pp0_stage9_iter1;
+wire    ap_block_state42_pp0_stage9_iter2;
+wire    ap_block_state57_pp0_stage9_iter3;
+wire    ap_block_state72_pp0_stage9_iter4;
+wire    ap_block_state87_pp0_stage9_iter5;
+wire    ap_block_state102_pp0_stage9_iter6;
+reg    ap_block_state117_pp0_stage9_iter7;
+reg    ap_block_pp0_stage9_11001;
+reg  signed [31:0] in1_mem_addr_read_reg_680;
+reg   [31:0] out_mem_addr_read_reg_685;
+wire   [31:0] add_ln26_3_fu_523_p2;
+reg   [31:0] add_ln26_3_reg_690;
+wire    ap_block_state6_pp0_stage3_iter0;
+reg    ap_block_state6_io;
+wire    ap_block_state21_pp0_stage3_iter1;
+wire    ap_block_state36_pp0_stage3_iter2;
+wire    ap_block_state51_pp0_stage3_iter3;
+wire    ap_block_state66_pp0_stage3_iter4;
+wire    ap_block_state81_pp0_stage3_iter5;
+wire    ap_block_state96_pp0_stage3_iter6;
+wire    ap_block_state111_pp0_stage3_iter7;
+reg    ap_block_state111_io;
+reg    ap_block_pp0_stage3_11001;
+wire    ap_block_pp0_stage0_subdone;
+reg    ap_condition_pp0_exit_iter0_state3;
+wire    ap_block_pp0_stage14_subdone;
+reg    ap_block_pp0_stage9_subdone;
+reg    ap_enable_reg_pp0_iter2;
+reg    ap_enable_reg_pp0_iter3;
+reg    ap_enable_reg_pp0_iter4;
+reg    ap_enable_reg_pp0_iter5;
+reg   [95:0] ap_phi_mux_indvar_flatten18_phi_fu_175_p4;
+wire    ap_block_pp0_stage0;
+reg   [30:0] ap_phi_mux_i_0_phi_fu_187_p4;
+reg   [63:0] ap_phi_mux_indvar_flatten_phi_fu_199_p4;
+wire    ap_block_pp0_stage1;
+reg   [31:0] ap_phi_mux_j_0_phi_fu_211_p4;
+reg   [31:0] ap_phi_mux_k_0_phi_fu_223_p4;
+wire  signed [63:0] sext_ln26_1_fu_437_p1;
+wire  signed [63:0] sext_ln26_4_fu_452_p1;
+wire  signed [63:0] sext_ln26_3_fu_486_p1;
+wire    ap_block_state7_pp0_stage4_iter0;
+wire    ap_block_state22_pp0_stage4_iter1;
+wire    ap_block_state37_pp0_stage4_iter2;
+wire    ap_block_state52_pp0_stage4_iter3;
+wire    ap_block_state67_pp0_stage4_iter4;
+wire    ap_block_state82_pp0_stage4_iter5;
+wire    ap_block_state97_pp0_stage4_iter6;
+wire    ap_block_state112_pp0_stage4_iter7;
+reg    ap_block_state112_io;
+reg    ap_block_pp0_stage4_11001;
+wire    ap_block_pp0_stage4_01001;
+wire  signed [31:0] cast_fu_261_p0;
+wire   [31:0] bound_fu_265_p0;
+wire   [63:0] cast_fu_261_p1;
+wire   [31:0] bound_fu_265_p1;
+wire   [63:0] bound7_fu_286_p0;
+wire   [31:0] bound7_fu_286_p1;
+wire   [30:0] mul_ln26_fu_301_p1;
+wire   [31:0] grp_fu_323_p1;
+wire   [30:0] mul_ln26_3_fu_351_p1;
+wire   [31:0] mul_ln26_3_fu_351_p2;
+wire  signed [31:0] select_ln19_1_fu_356_p3;
+wire   [0:0] icmp_ln23_fu_374_p2;
+wire   [31:0] select_ln19_fu_343_p3;
+wire   [0:0] select_ln19_3_fu_379_p3;
+wire   [0:0] or_ln26_fu_392_p2;
+wire   [31:0] j_fu_386_p2;
+wire   [31:0] add_ln26_1_fu_406_p2;
+wire   [31:0] select_ln19_2_fu_367_p3;
+wire   [31:0] select_ln26_1_fu_412_p3;
+wire  signed [32:0] sext_ln19_fu_363_p1;
+wire   [32:0] add_ln26_4_fu_432_p2;
+wire  signed [32:0] sext_ln26_fu_420_p1;
+wire   [32:0] add_ln26_6_fu_447_p2;
+wire   [31:0] mul_ln26_1_fu_468_p2;
+wire   [31:0] add_ln26_2_fu_472_p2;
+wire  signed [32:0] sext_ln26_2_fu_477_p1;
+wire   [32:0] add_ln26_5_fu_481_p2;
+wire    ap_block_pp0_stage14;
+wire   [95:0] grp_fu_323_p2;
+wire   [31:0] mul_ln26_2_fu_519_p2;
+reg    grp_fu_323_ce;
+wire    ap_block_state8_pp0_stage5_iter0;
+wire    ap_block_state23_pp0_stage5_iter1;
+wire    ap_block_state38_pp0_stage5_iter2;
+wire    ap_block_state53_pp0_stage5_iter3;
+wire    ap_block_state68_pp0_stage5_iter4;
+wire    ap_block_state83_pp0_stage5_iter5;
+wire    ap_block_state98_pp0_stage5_iter6;
+wire    ap_block_state113_pp0_stage5_iter7;
+wire    ap_block_pp0_stage5_11001;
+wire    ap_CS_fsm_pp0_stage5;
+wire    ap_block_state9_pp0_stage6_iter0;
+wire    ap_block_state24_pp0_stage6_iter1;
+wire    ap_block_state39_pp0_stage6_iter2;
+wire    ap_block_state54_pp0_stage6_iter3;
+wire    ap_block_state69_pp0_stage6_iter4;
+wire    ap_block_state84_pp0_stage6_iter5;
+wire    ap_block_state99_pp0_stage6_iter6;
+wire    ap_block_state114_pp0_stage6_iter7;
+wire    ap_block_pp0_stage6_11001;
+wire    ap_CS_fsm_pp0_stage6;
+wire    ap_block_state10_pp0_stage7_iter0;
+wire    ap_block_state25_pp0_stage7_iter1;
+wire    ap_block_state40_pp0_stage7_iter2;
+wire    ap_block_state55_pp0_stage7_iter3;
+wire    ap_block_state70_pp0_stage7_iter4;
+wire    ap_block_state85_pp0_stage7_iter5;
+wire    ap_block_state100_pp0_stage7_iter6;
+wire    ap_block_state115_pp0_stage7_iter7;
+wire    ap_block_pp0_stage7_11001;
+wire    ap_CS_fsm_pp0_stage7;
+wire    ap_block_state11_pp0_stage8_iter0;
+wire    ap_block_state26_pp0_stage8_iter1;
+wire    ap_block_state41_pp0_stage8_iter2;
+wire    ap_block_state56_pp0_stage8_iter3;
+wire    ap_block_state71_pp0_stage8_iter4;
+wire    ap_block_state86_pp0_stage8_iter5;
+wire    ap_block_state101_pp0_stage8_iter6;
+wire    ap_block_state116_pp0_stage8_iter7;
+wire    ap_block_pp0_stage8_11001;
+wire    ap_CS_fsm_pp0_stage8;
+wire    ap_block_state14_pp0_stage11_iter0;
+wire    ap_block_state29_pp0_stage11_iter1;
+wire    ap_block_state44_pp0_stage11_iter2;
+wire    ap_block_state59_pp0_stage11_iter3;
+wire    ap_block_state74_pp0_stage11_iter4;
+wire    ap_block_state89_pp0_stage11_iter5;
+wire    ap_block_state104_pp0_stage11_iter6;
+wire    ap_block_pp0_stage11_11001;
+wire    ap_CS_fsm_pp0_stage11;
+wire    ap_block_state15_pp0_stage12_iter0;
+wire    ap_block_state30_pp0_stage12_iter1;
+wire    ap_block_state45_pp0_stage12_iter2;
+wire    ap_block_state60_pp0_stage12_iter3;
+wire    ap_block_state75_pp0_stage12_iter4;
+wire    ap_block_state90_pp0_stage12_iter5;
+wire    ap_block_state105_pp0_stage12_iter6;
+wire    ap_block_pp0_stage12_11001;
+wire    ap_CS_fsm_pp0_stage12;
+wire    ap_block_state16_pp0_stage13_iter0;
+wire    ap_block_state31_pp0_stage13_iter1;
+wire    ap_block_state46_pp0_stage13_iter2;
+wire    ap_block_state61_pp0_stage13_iter3;
+wire    ap_block_state76_pp0_stage13_iter4;
+wire    ap_block_state91_pp0_stage13_iter5;
+wire    ap_block_state106_pp0_stage13_iter6;
+wire    ap_block_pp0_stage13_11001;
+wire    ap_CS_fsm_pp0_stage13;
+wire    ap_CS_fsm_state118;
+reg   [17:0] ap_NS_fsm;
+wire    ap_block_pp0_stage1_subdone;
+reg    ap_block_pp0_stage2_subdone;
+reg    ap_block_pp0_stage3_subdone;
+reg    ap_block_pp0_stage4_subdone;
+wire    ap_block_pp0_stage5_subdone;
+wire    ap_block_pp0_stage6_subdone;
+wire    ap_block_pp0_stage7_subdone;
+wire    ap_block_pp0_stage8_subdone;
+reg    ap_block_pp0_stage10_subdone;
+wire    ap_block_pp0_stage11_subdone;
+wire    ap_block_pp0_stage12_subdone;
+wire    ap_block_pp0_stage13_subdone;
+reg    ap_idle_pp0;
+wire    ap_enable_pp0;
+wire   [95:0] bound7_fu_286_p00;
+wire   [95:0] bound7_fu_286_p10;
+wire   [31:0] mul_ln26_3_fu_351_p10;
+wire   [31:0] mul_ln26_fu_301_p10;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 18'd1;
+#0 ap_enable_reg_pp0_iter6 = 1'b0;
+#0 ap_enable_reg_pp0_iter7 = 1'b0;
+#0 ap_enable_reg_pp0_iter0 = 1'b0;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp0_iter3 = 1'b0;
+#0 ap_enable_reg_pp0_iter4 = 1'b0;
+#0 ap_enable_reg_pp0_iter5 = 1'b0;
+end
+
+mmult_params_s_axi #(
+    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PARAMS_ADDR_WIDTH ),
+    .C_S_AXI_DATA_WIDTH( C_S_AXI_PARAMS_DATA_WIDTH ))
+mmult_params_s_axi_U(
+    .AWVALID(s_axi_params_AWVALID),
+    .AWREADY(s_axi_params_AWREADY),
+    .AWADDR(s_axi_params_AWADDR),
+    .WVALID(s_axi_params_WVALID),
+    .WREADY(s_axi_params_WREADY),
+    .WDATA(s_axi_params_WDATA),
+    .WSTRB(s_axi_params_WSTRB),
+    .ARVALID(s_axi_params_ARVALID),
+    .ARREADY(s_axi_params_ARREADY),
+    .ARADDR(s_axi_params_ARADDR),
+    .RVALID(s_axi_params_RVALID),
+    .RREADY(s_axi_params_RREADY),
+    .RDATA(s_axi_params_RDATA),
+    .RRESP(s_axi_params_RRESP),
+    .BVALID(s_axi_params_BVALID),
+    .BREADY(s_axi_params_BREADY),
+    .BRESP(s_axi_params_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .in1(in1),
+    .in2(in2),
+    .out_r(out_r),
+    .dim(dim)
+);
+
+mmult_in1_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN1_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN1_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN1_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN1_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN1_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN1_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN1_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN1_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN1_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN1_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN1_MEM_CACHE_VALUE ))
+mmult_in1_mem_m_axi_U(
+    .AWVALID(m_axi_in1_mem_AWVALID),
+    .AWREADY(m_axi_in1_mem_AWREADY),
+    .AWADDR(m_axi_in1_mem_AWADDR),
+    .AWID(m_axi_in1_mem_AWID),
+    .AWLEN(m_axi_in1_mem_AWLEN),
+    .AWSIZE(m_axi_in1_mem_AWSIZE),
+    .AWBURST(m_axi_in1_mem_AWBURST),
+    .AWLOCK(m_axi_in1_mem_AWLOCK),
+    .AWCACHE(m_axi_in1_mem_AWCACHE),
+    .AWPROT(m_axi_in1_mem_AWPROT),
+    .AWQOS(m_axi_in1_mem_AWQOS),
+    .AWREGION(m_axi_in1_mem_AWREGION),
+    .AWUSER(m_axi_in1_mem_AWUSER),
+    .WVALID(m_axi_in1_mem_WVALID),
+    .WREADY(m_axi_in1_mem_WREADY),
+    .WDATA(m_axi_in1_mem_WDATA),
+    .WSTRB(m_axi_in1_mem_WSTRB),
+    .WLAST(m_axi_in1_mem_WLAST),
+    .WID(m_axi_in1_mem_WID),
+    .WUSER(m_axi_in1_mem_WUSER),
+    .ARVALID(m_axi_in1_mem_ARVALID),
+    .ARREADY(m_axi_in1_mem_ARREADY),
+    .ARADDR(m_axi_in1_mem_ARADDR),
+    .ARID(m_axi_in1_mem_ARID),
+    .ARLEN(m_axi_in1_mem_ARLEN),
+    .ARSIZE(m_axi_in1_mem_ARSIZE),
+    .ARBURST(m_axi_in1_mem_ARBURST),
+    .ARLOCK(m_axi_in1_mem_ARLOCK),
+    .ARCACHE(m_axi_in1_mem_ARCACHE),
+    .ARPROT(m_axi_in1_mem_ARPROT),
+    .ARQOS(m_axi_in1_mem_ARQOS),
+    .ARREGION(m_axi_in1_mem_ARREGION),
+    .ARUSER(m_axi_in1_mem_ARUSER),
+    .RVALID(m_axi_in1_mem_RVALID),
+    .RREADY(m_axi_in1_mem_RREADY),
+    .RDATA(m_axi_in1_mem_RDATA),
+    .RLAST(m_axi_in1_mem_RLAST),
+    .RID(m_axi_in1_mem_RID),
+    .RUSER(m_axi_in1_mem_RUSER),
+    .RRESP(m_axi_in1_mem_RRESP),
+    .BVALID(m_axi_in1_mem_BVALID),
+    .BREADY(m_axi_in1_mem_BREADY),
+    .BRESP(m_axi_in1_mem_BRESP),
+    .BID(m_axi_in1_mem_BID),
+    .BUSER(m_axi_in1_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in1_mem_ARVALID),
+    .I_ARREADY(in1_mem_ARREADY),
+    .I_ARADDR(in1_mem_addr_reg_632_pp0_iter6_reg),
+    .I_ARID(1'd0),
+    .I_ARLEN(dim_read_reg_528),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in1_mem_RVALID),
+    .I_RREADY(in1_mem_RREADY),
+    .I_RDATA(in1_mem_RDATA),
+    .I_RID(in1_mem_RID),
+    .I_RUSER(in1_mem_RUSER),
+    .I_RRESP(in1_mem_RRESP),
+    .I_RLAST(in1_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in1_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in1_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in1_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in1_mem_BRESP),
+    .I_BID(in1_mem_BID),
+    .I_BUSER(in1_mem_BUSER)
+);
+
+mmult_in2_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN2_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN2_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN2_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN2_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN2_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN2_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN2_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN2_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN2_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN2_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN2_MEM_CACHE_VALUE ))
+mmult_in2_mem_m_axi_U(
+    .AWVALID(m_axi_in2_mem_AWVALID),
+    .AWREADY(m_axi_in2_mem_AWREADY),
+    .AWADDR(m_axi_in2_mem_AWADDR),
+    .AWID(m_axi_in2_mem_AWID),
+    .AWLEN(m_axi_in2_mem_AWLEN),
+    .AWSIZE(m_axi_in2_mem_AWSIZE),
+    .AWBURST(m_axi_in2_mem_AWBURST),
+    .AWLOCK(m_axi_in2_mem_AWLOCK),
+    .AWCACHE(m_axi_in2_mem_AWCACHE),
+    .AWPROT(m_axi_in2_mem_AWPROT),
+    .AWQOS(m_axi_in2_mem_AWQOS),
+    .AWREGION(m_axi_in2_mem_AWREGION),
+    .AWUSER(m_axi_in2_mem_AWUSER),
+    .WVALID(m_axi_in2_mem_WVALID),
+    .WREADY(m_axi_in2_mem_WREADY),
+    .WDATA(m_axi_in2_mem_WDATA),
+    .WSTRB(m_axi_in2_mem_WSTRB),
+    .WLAST(m_axi_in2_mem_WLAST),
+    .WID(m_axi_in2_mem_WID),
+    .WUSER(m_axi_in2_mem_WUSER),
+    .ARVALID(m_axi_in2_mem_ARVALID),
+    .ARREADY(m_axi_in2_mem_ARREADY),
+    .ARADDR(m_axi_in2_mem_ARADDR),
+    .ARID(m_axi_in2_mem_ARID),
+    .ARLEN(m_axi_in2_mem_ARLEN),
+    .ARSIZE(m_axi_in2_mem_ARSIZE),
+    .ARBURST(m_axi_in2_mem_ARBURST),
+    .ARLOCK(m_axi_in2_mem_ARLOCK),
+    .ARCACHE(m_axi_in2_mem_ARCACHE),
+    .ARPROT(m_axi_in2_mem_ARPROT),
+    .ARQOS(m_axi_in2_mem_ARQOS),
+    .ARREGION(m_axi_in2_mem_ARREGION),
+    .ARUSER(m_axi_in2_mem_ARUSER),
+    .RVALID(m_axi_in2_mem_RVALID),
+    .RREADY(m_axi_in2_mem_RREADY),
+    .RDATA(m_axi_in2_mem_RDATA),
+    .RLAST(m_axi_in2_mem_RLAST),
+    .RID(m_axi_in2_mem_RID),
+    .RUSER(m_axi_in2_mem_RUSER),
+    .RRESP(m_axi_in2_mem_RRESP),
+    .BVALID(m_axi_in2_mem_BVALID),
+    .BREADY(m_axi_in2_mem_BREADY),
+    .BRESP(m_axi_in2_mem_BRESP),
+    .BID(m_axi_in2_mem_BID),
+    .BUSER(m_axi_in2_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in2_mem_ARVALID),
+    .I_ARREADY(in2_mem_ARREADY),
+    .I_ARADDR(in2_mem_addr_reg_650),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd1),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in2_mem_RVALID),
+    .I_RREADY(in2_mem_RREADY),
+    .I_RDATA(in2_mem_RDATA),
+    .I_RID(in2_mem_RID),
+    .I_RUSER(in2_mem_RUSER),
+    .I_RRESP(in2_mem_RRESP),
+    .I_RLAST(in2_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in2_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in2_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in2_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in2_mem_BRESP),
+    .I_BID(in2_mem_BID),
+    .I_BUSER(in2_mem_BUSER)
+);
+
+mmult_out_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_OUT_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_OUT_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_OUT_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_OUT_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_OUT_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_OUT_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_OUT_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_OUT_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_OUT_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_OUT_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_OUT_MEM_CACHE_VALUE ))
+mmult_out_mem_m_axi_U(
+    .AWVALID(m_axi_out_mem_AWVALID),
+    .AWREADY(m_axi_out_mem_AWREADY),
+    .AWADDR(m_axi_out_mem_AWADDR),
+    .AWID(m_axi_out_mem_AWID),
+    .AWLEN(m_axi_out_mem_AWLEN),
+    .AWSIZE(m_axi_out_mem_AWSIZE),
+    .AWBURST(m_axi_out_mem_AWBURST),
+    .AWLOCK(m_axi_out_mem_AWLOCK),
+    .AWCACHE(m_axi_out_mem_AWCACHE),
+    .AWPROT(m_axi_out_mem_AWPROT),
+    .AWQOS(m_axi_out_mem_AWQOS),
+    .AWREGION(m_axi_out_mem_AWREGION),
+    .AWUSER(m_axi_out_mem_AWUSER),
+    .WVALID(m_axi_out_mem_WVALID),
+    .WREADY(m_axi_out_mem_WREADY),
+    .WDATA(m_axi_out_mem_WDATA),
+    .WSTRB(m_axi_out_mem_WSTRB),
+    .WLAST(m_axi_out_mem_WLAST),
+    .WID(m_axi_out_mem_WID),
+    .WUSER(m_axi_out_mem_WUSER),
+    .ARVALID(m_axi_out_mem_ARVALID),
+    .ARREADY(m_axi_out_mem_ARREADY),
+    .ARADDR(m_axi_out_mem_ARADDR),
+    .ARID(m_axi_out_mem_ARID),
+    .ARLEN(m_axi_out_mem_ARLEN),
+    .ARSIZE(m_axi_out_mem_ARSIZE),
+    .ARBURST(m_axi_out_mem_ARBURST),
+    .ARLOCK(m_axi_out_mem_ARLOCK),
+    .ARCACHE(m_axi_out_mem_ARCACHE),
+    .ARPROT(m_axi_out_mem_ARPROT),
+    .ARQOS(m_axi_out_mem_ARQOS),
+    .ARREGION(m_axi_out_mem_ARREGION),
+    .ARUSER(m_axi_out_mem_ARUSER),
+    .RVALID(m_axi_out_mem_RVALID),
+    .RREADY(m_axi_out_mem_RREADY),
+    .RDATA(m_axi_out_mem_RDATA),
+    .RLAST(m_axi_out_mem_RLAST),
+    .RID(m_axi_out_mem_RID),
+    .RUSER(m_axi_out_mem_RUSER),
+    .RRESP(m_axi_out_mem_RRESP),
+    .BVALID(m_axi_out_mem_BVALID),
+    .BREADY(m_axi_out_mem_BREADY),
+    .BRESP(m_axi_out_mem_BRESP),
+    .BID(m_axi_out_mem_BID),
+    .BUSER(m_axi_out_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(out_mem_ARVALID),
+    .I_ARREADY(out_mem_ARREADY),
+    .I_ARADDR(out_mem_addr_reg_638_pp0_iter6_reg),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd1),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(out_mem_RVALID),
+    .I_RREADY(out_mem_RREADY),
+    .I_RDATA(out_mem_RDATA),
+    .I_RID(out_mem_RID),
+    .I_RUSER(out_mem_RUSER),
+    .I_RRESP(out_mem_RRESP),
+    .I_RLAST(out_mem_RLAST),
+    .I_AWVALID(out_mem_AWVALID),
+    .I_AWREADY(out_mem_AWREADY),
+    .I_AWADDR(out_mem_addr_reg_638_pp0_iter7_reg),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd1),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(out_mem_WVALID),
+    .I_WREADY(out_mem_WREADY),
+    .I_WDATA(add_ln26_3_reg_690),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd15),
+    .I_BVALID(out_mem_BVALID),
+    .I_BREADY(out_mem_BREADY),
+    .I_BRESP(out_mem_BRESP),
+    .I_BID(out_mem_BID),
+    .I_BUSER(out_mem_BUSER)
+);
+
+mmult_urem_96ns_3bkb #(
+    .ID( 1 ),
+    .NUM_STAGE( 100 ),
+    .din0_WIDTH( 96 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 96 ))
+mmult_urem_96ns_3bkb_U1(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(ap_phi_mux_indvar_flatten18_phi_fu_175_p4),
+    .din1(grp_fu_323_p1),
+    .ce(grp_fu_323_ce),
+    .dout(grp_fu_323_p2)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter0 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state3) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_enable_reg_pp0_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state2)) begin
+            ap_enable_reg_pp0_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage14_subdone) & (1'b1 == ap_CS_fsm_pp0_stage14))) begin
+            ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage14_subdone) & (1'b1 == ap_CS_fsm_pp0_stage14))) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter3 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage14_subdone) & (1'b1 == ap_CS_fsm_pp0_stage14))) begin
+            ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter4 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage14_subdone) & (1'b1 == ap_CS_fsm_pp0_stage14))) begin
+            ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter5 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage14_subdone) & (1'b1 == ap_CS_fsm_pp0_stage14))) begin
+            ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter6 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage14_subdone) & (1'b1 == ap_CS_fsm_pp0_stage14))) begin
+            ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter7 <= 1'b0;
+    end else begin
+        if ((((1'b0 == ap_block_pp0_stage14_subdone) & (1'b1 == ap_CS_fsm_pp0_stage14)) | ((1'b0 == ap_block_pp0_stage9_subdone) & (1'b1 == ap_CS_fsm_pp0_stage9)))) begin
+            ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
+        end else if ((1'b1 == ap_CS_fsm_state2)) begin
+            ap_enable_reg_pp0_iter7 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        i_0_reg_183 <= select_ln19_4_reg_661;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        i_0_reg_183 <= 31'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        indvar_flatten18_reg_171 <= add_ln19_reg_604;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        indvar_flatten18_reg_171 <= 96'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln19_reg_600_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
+        indvar_flatten_reg_195 <= select_ln21_1_reg_671;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        indvar_flatten_reg_195 <= 64'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        j_0_reg_207 <= select_ln21_reg_626;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        j_0_reg_207 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln19_reg_600_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
+        k_0_reg_219 <= k_reg_666;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        k_0_reg_219 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln19_reg_600 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
+        add_ln19_1_reg_609 <= add_ln19_1_fu_328_p2;
+        add_ln21_1_reg_645 <= add_ln21_1_fu_462_p2;
+        icmp_ln21_1_reg_614 <= icmp_ln21_1_fu_338_p2;
+        in1_mem_addr_reg_632 <= sext_ln26_1_fu_437_p1;
+        out_mem_addr_reg_638 <= sext_ln26_4_fu_452_p1;
+        select_ln26_reg_620 <= select_ln26_fu_398_p3;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin
+        add_ln19_reg_604 <= add_ln19_fu_317_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
+        add_ln26_3_reg_690 <= add_ln26_3_fu_523_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        add_ln26_reg_595 <= add_ln26_fu_306_p2;
+        icmp_ln19_reg_600 <= icmp_ln19_fu_312_p2;
+        icmp_ln19_reg_600_pp0_iter1_reg <= icmp_ln19_reg_600;
+        icmp_ln19_reg_600_pp0_iter2_reg <= icmp_ln19_reg_600_pp0_iter1_reg;
+        icmp_ln19_reg_600_pp0_iter3_reg <= icmp_ln19_reg_600_pp0_iter2_reg;
+        icmp_ln19_reg_600_pp0_iter4_reg <= icmp_ln19_reg_600_pp0_iter3_reg;
+        icmp_ln19_reg_600_pp0_iter5_reg <= icmp_ln19_reg_600_pp0_iter4_reg;
+        icmp_ln19_reg_600_pp0_iter6_reg <= icmp_ln19_reg_600_pp0_iter5_reg;
+        icmp_ln19_reg_600_pp0_iter7_reg <= icmp_ln19_reg_600_pp0_iter6_reg;
+        mul_ln26_reg_590 <= mul_ln26_fu_301_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        bound7_reg_580 <= bound7_fu_286_p2;
+        cast5_reg_575[31 : 0] <= cast5_fu_280_p1[31 : 0];
+        icmp_ln21_reg_585 <= icmp_ln21_fu_292_p2;
+        p_cast19_reg_565[29 : 0] <= p_cast19_fu_274_p1[29 : 0];
+        p_cast20_reg_560[29 : 0] <= p_cast20_fu_271_p1[29 : 0];
+        p_cast_reg_570[29 : 0] <= p_cast_fu_277_p1[29 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        bound_reg_554 <= bound_fu_265_p2;
+        dim_read_reg_528 <= dim;
+        tmp_1_reg_544 <= {{in2[31:2]}};
+        tmp_3_reg_549 <= {{in1[31:2]}};
+        tmp_reg_539 <= {{out_r[31:2]}};
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage9_11001) & (icmp_ln19_reg_600_pp0_iter6_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9))) begin
+        icmp_ln8_reg_676 <= icmp_ln8_fu_513_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
+        in1_mem_addr_read_reg_680 <= in1_mem_RDATA;
+        out_mem_addr_read_reg_685 <= out_mem_RDATA;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
+        in1_mem_addr_reg_632_pp0_iter1_reg <= in1_mem_addr_reg_632;
+        in1_mem_addr_reg_632_pp0_iter2_reg <= in1_mem_addr_reg_632_pp0_iter1_reg;
+        in1_mem_addr_reg_632_pp0_iter3_reg <= in1_mem_addr_reg_632_pp0_iter2_reg;
+        in1_mem_addr_reg_632_pp0_iter4_reg <= in1_mem_addr_reg_632_pp0_iter3_reg;
+        in1_mem_addr_reg_632_pp0_iter5_reg <= in1_mem_addr_reg_632_pp0_iter4_reg;
+        in1_mem_addr_reg_632_pp0_iter6_reg <= in1_mem_addr_reg_632_pp0_iter5_reg;
+        out_mem_addr_reg_638_pp0_iter1_reg <= out_mem_addr_reg_638;
+        out_mem_addr_reg_638_pp0_iter2_reg <= out_mem_addr_reg_638_pp0_iter1_reg;
+        out_mem_addr_reg_638_pp0_iter3_reg <= out_mem_addr_reg_638_pp0_iter2_reg;
+        out_mem_addr_reg_638_pp0_iter4_reg <= out_mem_addr_reg_638_pp0_iter3_reg;
+        out_mem_addr_reg_638_pp0_iter5_reg <= out_mem_addr_reg_638_pp0_iter4_reg;
+        out_mem_addr_reg_638_pp0_iter6_reg <= out_mem_addr_reg_638_pp0_iter5_reg;
+        out_mem_addr_reg_638_pp0_iter7_reg <= out_mem_addr_reg_638_pp0_iter6_reg;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage10_11001) & (icmp_ln19_reg_600 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage10))) begin
+        in2_mem_addr_read_reg_656 <= in2_mem_RDATA;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage10_11001) & (1'b1 == ap_CS_fsm_pp0_stage10))) begin
+        in2_mem_addr_read_reg_656_pp0_iter1_reg <= in2_mem_addr_read_reg_656;
+        in2_mem_addr_read_reg_656_pp0_iter2_reg <= in2_mem_addr_read_reg_656_pp0_iter1_reg;
+        in2_mem_addr_read_reg_656_pp0_iter3_reg <= in2_mem_addr_read_reg_656_pp0_iter2_reg;
+        in2_mem_addr_read_reg_656_pp0_iter4_reg <= in2_mem_addr_read_reg_656_pp0_iter3_reg;
+        in2_mem_addr_read_reg_656_pp0_iter5_reg <= in2_mem_addr_read_reg_656_pp0_iter4_reg;
+        in2_mem_addr_read_reg_656_pp0_iter6_reg <= in2_mem_addr_read_reg_656_pp0_iter5_reg;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln19_reg_600 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
+        in2_mem_addr_reg_650 <= sext_ln26_3_fu_486_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        k_reg_666 <= k_fu_502_p2;
+        select_ln21_1_reg_671 <= select_ln21_1_fu_507_p3;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage14_11001) & (icmp_ln19_reg_600 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage14) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin
+        select_ln19_4_reg_661 <= select_ln19_4_fu_496_p3;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage1_11001) & (icmp_ln19_reg_600 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin
+        select_ln21_reg_626 <= select_ln21_fu_424_p3;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln19_fu_312_p2 == 1'd1)) begin
+        ap_condition_pp0_exit_iter0_state3 = 1'b1;
+    end else begin
+        ap_condition_pp0_exit_iter0_state3 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state118)) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter5 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter7 == 1'b0) & (ap_enable_reg_pp0_iter6 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_phi_mux_i_0_phi_fu_187_p4 = select_ln19_4_reg_661;
+    end else begin
+        ap_phi_mux_i_0_phi_fu_187_p4 = i_0_reg_183;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_phi_mux_indvar_flatten18_phi_fu_175_p4 = add_ln19_reg_604;
+    end else begin
+        ap_phi_mux_indvar_flatten18_phi_fu_175_p4 = indvar_flatten18_reg_171;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage1) & (icmp_ln19_reg_600_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
+        ap_phi_mux_indvar_flatten_phi_fu_199_p4 = select_ln21_1_reg_671;
+    end else begin
+        ap_phi_mux_indvar_flatten_phi_fu_199_p4 = indvar_flatten_reg_195;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_phi_mux_j_0_phi_fu_211_p4 = select_ln21_reg_626;
+    end else begin
+        ap_phi_mux_j_0_phi_fu_211_p4 = j_0_reg_207;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage1) & (icmp_ln19_reg_600_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
+        ap_phi_mux_k_0_phi_fu_223_p4 = k_reg_666;
+    end else begin
+        ap_phi_mux_k_0_phi_fu_223_p4 = k_0_reg_219;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state118)) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage14_11001) & (1'b1 == ap_CS_fsm_pp0_stage14)) | ((1'b0 == ap_block_pp0_stage1_11001) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0)) | ((1'b0 == ap_block_pp0_stage9_11001) & (1'b1 == ap_CS_fsm_pp0_stage9)) | ((1'b0 == ap_block_pp0_stage4_11001) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((1'b0 == ap_block_pp0_stage3_11001) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((1'b0 == ap_block_pp0_stage2_11001) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((1'b0 == ap_block_pp0_stage10_11001) & (1'b1 == ap_CS_fsm_pp0_stage10)) | ((1'b1 == ap_CS_fsm_pp0_stage13) & (1'b0 == ap_block_pp0_stage13_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage12) & (1'b0 == ap_block_pp0_stage12_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage11) & (1'b0 == ap_block_pp0_stage11_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b0 == ap_block_pp0_stage8_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage7) & (1'b0 == ap_block_pp0_stage7_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (1'b0 == ap_block_pp0_stage6_11001)) | ((1'b1 == ap_CS_fsm_pp0_stage5) & (1'b0 == ap_block_pp0_stage5_11001)))) begin
+        grp_fu_323_ce = 1'b1;
+    end else begin
+        grp_fu_323_ce = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage10_11001) & (icmp_ln8_reg_676 == 1'd1) & (ap_enable_reg_pp0_iter6 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage10))) begin
+        in1_mem_ARVALID = 1'b1;
+    end else begin
+        in1_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (ap_enable_reg_pp0_iter7 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
+        in1_mem_RREADY = 1'b1;
+    end else begin
+        in1_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln8_reg_676 == 1'd1) & (1'b0 == ap_block_pp0_stage10) & (ap_enable_reg_pp0_iter6 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage10))) begin
+        in1_mem_blk_n_AR = m_axi_in1_mem_ARREADY;
+    end else begin
+        in1_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter7 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
+        in1_mem_blk_n_R = m_axi_in1_mem_RVALID;
+    end else begin
+        in1_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
+        in2_mem_ARVALID = 1'b1;
+    end else begin
+        in2_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage10_11001) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage10))) begin
+        in2_mem_RREADY = 1'b1;
+    end else begin
+        in2_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage3) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
+        in2_mem_blk_n_AR = m_axi_in2_mem_ARREADY;
+    end else begin
+        in2_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln19_reg_600 == 1'd0) & (1'b0 == ap_block_pp0_stage10) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage10))) begin
+        in2_mem_blk_n_R = m_axi_in2_mem_RVALID;
+    end else begin
+        in2_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage10_11001) & (icmp_ln19_reg_600_pp0_iter6_reg == 1'd0) & (ap_enable_reg_pp0_iter6 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage10))) begin
+        out_mem_ARVALID = 1'b1;
+    end else begin
+        out_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage3_11001) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin
+        out_mem_AWVALID = 1'b1;
+    end else begin
+        out_mem_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage9_11001) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin
+        out_mem_BREADY = 1'b1;
+    end else begin
+        out_mem_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage2_11001) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (ap_enable_reg_pp0_iter7 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
+        out_mem_RREADY = 1'b1;
+    end else begin
+        out_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage4_11001) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin
+        out_mem_WVALID = 1'b1;
+    end else begin
+        out_mem_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln19_reg_600_pp0_iter6_reg == 1'd0) & (1'b0 == ap_block_pp0_stage10) & (ap_enable_reg_pp0_iter6 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage10))) begin
+        out_mem_blk_n_AR = m_axi_out_mem_ARREADY;
+    end else begin
+        out_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage3) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin
+        out_mem_blk_n_AW = m_axi_out_mem_AWREADY;
+    end else begin
+        out_mem_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage9) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin
+        out_mem_blk_n_B = m_axi_out_mem_BVALID;
+    end else begin
+        out_mem_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b0 == ap_block_pp0_stage2) & (ap_enable_reg_pp0_iter7 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
+        out_mem_blk_n_R = m_axi_out_mem_RVALID;
+    end else begin
+        out_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage4) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin
+        out_mem_blk_n_W = m_axi_out_mem_WREADY;
+    end else begin
+        out_mem_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        ap_ST_fsm_pp0_stage0 : begin
+            if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln19_fu_312_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1)) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage1;
+            end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (icmp_ln19_fu_312_p2 == 1'd1) & (ap_enable_reg_pp0_iter0 == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state118;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end
+        end
+        ap_ST_fsm_pp0_stage1 : begin
+            if ((1'b0 == ap_block_pp0_stage1_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage1;
+            end
+        end
+        ap_ST_fsm_pp0_stage2 : begin
+            if ((1'b0 == ap_block_pp0_stage2_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage2;
+            end
+        end
+        ap_ST_fsm_pp0_stage3 : begin
+            if ((1'b0 == ap_block_pp0_stage3_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage4;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage3;
+            end
+        end
+        ap_ST_fsm_pp0_stage4 : begin
+            if ((1'b0 == ap_block_pp0_stage4_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage5;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage4;
+            end
+        end
+        ap_ST_fsm_pp0_stage5 : begin
+            if ((1'b0 == ap_block_pp0_stage5_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage6;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage5;
+            end
+        end
+        ap_ST_fsm_pp0_stage6 : begin
+            if ((1'b0 == ap_block_pp0_stage6_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage7;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage6;
+            end
+        end
+        ap_ST_fsm_pp0_stage7 : begin
+            if ((1'b0 == ap_block_pp0_stage7_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage8;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage7;
+            end
+        end
+        ap_ST_fsm_pp0_stage8 : begin
+            if ((1'b0 == ap_block_pp0_stage8_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage9;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage8;
+            end
+        end
+        ap_ST_fsm_pp0_stage9 : begin
+            if ((~((1'b0 == ap_block_pp0_stage9_subdone) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_enable_reg_pp0_iter7 == 1'b1)) & (1'b0 == ap_block_pp0_stage9_subdone))) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage10;
+            end else if (((1'b0 == ap_block_pp0_stage9_subdone) & (ap_enable_reg_pp0_iter6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage9) & (ap_enable_reg_pp0_iter7 == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state118;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage9;
+            end
+        end
+        ap_ST_fsm_pp0_stage10 : begin
+            if ((1'b0 == ap_block_pp0_stage10_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage11;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage10;
+            end
+        end
+        ap_ST_fsm_pp0_stage11 : begin
+            if ((1'b0 == ap_block_pp0_stage11_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage12;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage11;
+            end
+        end
+        ap_ST_fsm_pp0_stage12 : begin
+            if ((1'b0 == ap_block_pp0_stage12_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage13;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage12;
+            end
+        end
+        ap_ST_fsm_pp0_stage13 : begin
+            if ((1'b0 == ap_block_pp0_stage13_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage14;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage13;
+            end
+        end
+        ap_ST_fsm_pp0_stage14 : begin
+            if ((1'b0 == ap_block_pp0_stage14_subdone)) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage14;
+            end
+        end
+        ap_ST_fsm_state118 : begin
+            ap_NS_fsm = ap_ST_fsm_state1;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln19_1_fu_328_p2 = (i_0_reg_183 + 31'd1);
+
+assign add_ln19_fu_317_p2 = (ap_phi_mux_indvar_flatten18_phi_fu_175_p4 + 96'd1);
+
+assign add_ln21_1_fu_462_p2 = (ap_phi_mux_indvar_flatten_phi_fu_199_p4 + 64'd1);
+
+assign add_ln26_1_fu_406_p2 = ($signed(j_fu_386_p2) + $signed(select_ln19_1_fu_356_p3));
+
+assign add_ln26_2_fu_472_p2 = (mul_ln26_1_fu_468_p2 + select_ln21_reg_626);
+
+assign add_ln26_3_fu_523_p2 = (out_mem_addr_read_reg_685 + mul_ln26_2_fu_519_p2);
+
+assign add_ln26_4_fu_432_p2 = ($signed(sext_ln19_fu_363_p1) + $signed(p_cast_reg_570));
+
+assign add_ln26_5_fu_481_p2 = ($signed(sext_ln26_2_fu_477_p1) + $signed(p_cast19_reg_565));
+
+assign add_ln26_6_fu_447_p2 = ($signed(sext_ln26_fu_420_p1) + $signed(p_cast20_reg_560));
+
+assign add_ln26_fu_306_p2 = (mul_ln26_fu_301_p2 + ap_phi_mux_j_0_phi_fu_211_p4);
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd2];
+
+assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd3];
+
+assign ap_CS_fsm_pp0_stage10 = ap_CS_fsm[32'd12];
+
+assign ap_CS_fsm_pp0_stage11 = ap_CS_fsm[32'd13];
+
+assign ap_CS_fsm_pp0_stage12 = ap_CS_fsm[32'd14];
+
+assign ap_CS_fsm_pp0_stage13 = ap_CS_fsm[32'd15];
+
+assign ap_CS_fsm_pp0_stage14 = ap_CS_fsm[32'd16];
+
+assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd4];
+
+assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd5];
+
+assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd6];
+
+assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd7];
+
+assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd8];
+
+assign ap_CS_fsm_pp0_stage7 = ap_CS_fsm[32'd9];
+
+assign ap_CS_fsm_pp0_stage8 = ap_CS_fsm[32'd10];
+
+assign ap_CS_fsm_pp0_stage9 = ap_CS_fsm[32'd11];
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state118 = ap_CS_fsm[32'd17];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage10 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage10_11001 = (((in2_mem_RVALID == 1'b0) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b1 == ap_block_state103_io) & (ap_enable_reg_pp0_iter6 == 1'b1)));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage10_subdone = (((in2_mem_RVALID == 1'b0) & (icmp_ln19_reg_600 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b1 == ap_block_state103_io) & (ap_enable_reg_pp0_iter6 == 1'b1)));
+end
+
+assign ap_block_pp0_stage11_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage11_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage12_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage12_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage13_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage13_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage14 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage14_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage14_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage2_11001 = ((ap_enable_reg_pp0_iter7 == 1'b1) & (((out_mem_RVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0)) | ((in1_mem_RVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0))));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage2_subdone = ((ap_enable_reg_pp0_iter7 == 1'b1) & (((out_mem_RVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0)) | ((in1_mem_RVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0))));
+end
+
+assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage3_11001 = (((1'b1 == ap_block_state6_io) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b1 == ap_block_state111_io) & (ap_enable_reg_pp0_iter7 == 1'b1)));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage3_subdone = (((1'b1 == ap_block_state6_io) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b1 == ap_block_state111_io) & (ap_enable_reg_pp0_iter7 == 1'b1)));
+end
+
+assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage4_01001 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage4_11001 = ((1'b1 == ap_block_state112_io) & (ap_enable_reg_pp0_iter7 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage4_subdone = ((1'b1 == ap_block_state112_io) & (ap_enable_reg_pp0_iter7 == 1'b1));
+end
+
+assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage7_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage7_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage8_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage8_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage9 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage9_11001 = ((out_mem_BVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (ap_enable_reg_pp0_iter7 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage9_subdone = ((out_mem_BVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0) & (ap_enable_reg_pp0_iter7 == 1'b1));
+end
+
+assign ap_block_state100_pp0_stage7_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state101_pp0_stage8_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state102_pp0_stage9_iter6 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state103_io = (((out_mem_ARREADY == 1'b0) & (icmp_ln19_reg_600_pp0_iter6_reg == 1'd0)) | ((in1_mem_ARREADY == 1'b0) & (icmp_ln8_reg_676 == 1'd1)));
+end
+
+assign ap_block_state103_pp0_stage10_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state104_pp0_stage11_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state105_pp0_stage12_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state106_pp0_stage13_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state107_pp0_stage14_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state108_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
+
+assign ap_block_state109_pp0_stage1_iter7 = ~(1'b1 == 1'b1);
+
+assign ap_block_state10_pp0_stage7_iter0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state110_pp0_stage2_iter7 = (((out_mem_RVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0)) | ((in1_mem_RVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0)));
+end
+
+always @ (*) begin
+    ap_block_state111_io = ((out_mem_AWREADY == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0));
+end
+
+assign ap_block_state111_pp0_stage3_iter7 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state112_io = ((out_mem_WREADY == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0));
+end
+
+assign ap_block_state112_pp0_stage4_iter7 = ~(1'b1 == 1'b1);
+
+assign ap_block_state113_pp0_stage5_iter7 = ~(1'b1 == 1'b1);
+
+assign ap_block_state114_pp0_stage6_iter7 = ~(1'b1 == 1'b1);
+
+assign ap_block_state115_pp0_stage7_iter7 = ~(1'b1 == 1'b1);
+
+assign ap_block_state116_pp0_stage8_iter7 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state117_pp0_stage9_iter7 = ((out_mem_BVALID == 1'b0) & (icmp_ln19_reg_600_pp0_iter7_reg == 1'd0));
+end
+
+assign ap_block_state11_pp0_stage8_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state12_pp0_stage9_iter0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state13_pp0_stage10_iter0 = ((in2_mem_RVALID == 1'b0) & (icmp_ln19_reg_600 == 1'd0));
+end
+
+assign ap_block_state14_pp0_stage11_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state15_pp0_stage12_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state16_pp0_stage13_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state17_pp0_stage14_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state18_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state19_pp0_stage1_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state20_pp0_stage2_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state21_pp0_stage3_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state22_pp0_stage4_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state23_pp0_stage5_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state24_pp0_stage6_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state25_pp0_stage7_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state26_pp0_stage8_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state27_pp0_stage9_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state28_pp0_stage10_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state29_pp0_stage11_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state30_pp0_stage12_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state31_pp0_stage13_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state32_pp0_stage14_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state33_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state34_pp0_stage1_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state35_pp0_stage2_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state36_pp0_stage3_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state37_pp0_stage4_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state38_pp0_stage5_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state39_pp0_stage6_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state3_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state40_pp0_stage7_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state41_pp0_stage8_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state42_pp0_stage9_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state43_pp0_stage10_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state44_pp0_stage11_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state45_pp0_stage12_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state46_pp0_stage13_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state47_pp0_stage14_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state48_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state49_pp0_stage1_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state4_pp0_stage1_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state50_pp0_stage2_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state51_pp0_stage3_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state52_pp0_stage4_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state53_pp0_stage5_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state54_pp0_stage6_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state55_pp0_stage7_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state56_pp0_stage8_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state57_pp0_stage9_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state58_pp0_stage10_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state59_pp0_stage11_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state5_pp0_stage2_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state60_pp0_stage12_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state61_pp0_stage13_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state62_pp0_stage14_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state63_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state64_pp0_stage1_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state65_pp0_stage2_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state66_pp0_stage3_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state67_pp0_stage4_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state68_pp0_stage5_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state69_pp0_stage6_iter4 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state6_io = ((in2_mem_ARREADY == 1'b0) & (icmp_ln19_reg_600 == 1'd0));
+end
+
+assign ap_block_state6_pp0_stage3_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state70_pp0_stage7_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state71_pp0_stage8_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state72_pp0_stage9_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state73_pp0_stage10_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state74_pp0_stage11_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state75_pp0_stage12_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state76_pp0_stage13_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state77_pp0_stage14_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state78_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state79_pp0_stage1_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state7_pp0_stage4_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state80_pp0_stage2_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state81_pp0_stage3_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state82_pp0_stage4_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state83_pp0_stage5_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state84_pp0_stage6_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state85_pp0_stage7_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state86_pp0_stage8_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state87_pp0_stage9_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state88_pp0_stage10_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state89_pp0_stage11_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state8_pp0_stage5_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state90_pp0_stage12_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state91_pp0_stage13_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state92_pp0_stage14_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state93_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state94_pp0_stage1_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state95_pp0_stage2_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state96_pp0_stage3_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state97_pp0_stage4_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state98_pp0_stage5_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state99_pp0_stage6_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state9_pp0_stage6_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign bound7_fu_286_p0 = bound7_fu_286_p00;
+
+assign bound7_fu_286_p00 = bound_reg_554;
+
+assign bound7_fu_286_p1 = bound7_fu_286_p10;
+
+assign bound7_fu_286_p10 = dim_read_reg_528;
+
+assign bound7_fu_286_p2 = (bound7_fu_286_p0 * bound7_fu_286_p1);
+
+assign bound_fu_265_p0 = cast_fu_261_p1;
+
+assign bound_fu_265_p1 = cast_fu_261_p1;
+
+assign bound_fu_265_p2 = (bound_fu_265_p0 * bound_fu_265_p1);
+
+assign cast5_fu_280_p1 = dim_read_reg_528;
+
+assign cast_fu_261_p0 = dim;
+
+assign cast_fu_261_p1 = $unsigned(cast_fu_261_p0);
+
+assign grp_fu_323_p1 = cast5_reg_575;
+
+assign icmp_ln19_fu_312_p2 = ((ap_phi_mux_indvar_flatten18_phi_fu_175_p4 == bound7_reg_580) ? 1'b1 : 1'b0);
+
+assign icmp_ln21_1_fu_338_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_199_p4 == bound_reg_554) ? 1'b1 : 1'b0);
+
+assign icmp_ln21_fu_292_p2 = ((dim_read_reg_528 == 32'd0) ? 1'b1 : 1'b0);
+
+assign icmp_ln23_fu_374_p2 = ((ap_phi_mux_k_0_phi_fu_223_p4 == dim_read_reg_528) ? 1'b1 : 1'b0);
+
+assign icmp_ln8_fu_513_p2 = ((grp_fu_323_p2 == 96'd0) ? 1'b1 : 1'b0);
+
+assign j_fu_386_p2 = (select_ln19_fu_343_p3 + 32'd1);
+
+assign k_fu_502_p2 = ($signed(select_ln26_reg_620) + $signed(32'd1));
+
+assign mul_ln26_1_fu_468_p2 = ($signed({{1'b0}, {dim_read_reg_528}}) * $signed(select_ln26_reg_620));
+
+assign mul_ln26_2_fu_519_p2 = ($signed(in2_mem_addr_read_reg_656_pp0_iter6_reg) * $signed(in1_mem_addr_read_reg_680));
+
+assign mul_ln26_3_fu_351_p1 = mul_ln26_3_fu_351_p10;
+
+assign mul_ln26_3_fu_351_p10 = add_ln19_1_fu_328_p2;
+
+assign mul_ln26_3_fu_351_p2 = (dim_read_reg_528 * mul_ln26_3_fu_351_p1);
+
+assign mul_ln26_fu_301_p1 = mul_ln26_fu_301_p10;
+
+assign mul_ln26_fu_301_p10 = ap_phi_mux_i_0_phi_fu_187_p4;
+
+assign mul_ln26_fu_301_p2 = (dim_read_reg_528 * mul_ln26_fu_301_p1);
+
+assign or_ln26_fu_392_p2 = (select_ln19_3_fu_379_p3 | icmp_ln21_1_fu_338_p2);
+
+assign p_cast19_fu_274_p1 = tmp_1_reg_544;
+
+assign p_cast20_fu_271_p1 = tmp_reg_539;
+
+assign p_cast_fu_277_p1 = tmp_3_reg_549;
+
+assign select_ln19_1_fu_356_p3 = ((icmp_ln21_1_fu_338_p2[0:0] === 1'b1) ? mul_ln26_3_fu_351_p2 : mul_ln26_reg_590);
+
+assign select_ln19_2_fu_367_p3 = ((icmp_ln21_1_fu_338_p2[0:0] === 1'b1) ? mul_ln26_3_fu_351_p2 : add_ln26_reg_595);
+
+assign select_ln19_3_fu_379_p3 = ((icmp_ln21_1_fu_338_p2[0:0] === 1'b1) ? icmp_ln21_reg_585 : icmp_ln23_fu_374_p2);
+
+assign select_ln19_4_fu_496_p3 = ((icmp_ln21_1_reg_614[0:0] === 1'b1) ? add_ln19_1_reg_609 : i_0_reg_183);
+
+assign select_ln19_fu_343_p3 = ((icmp_ln21_1_fu_338_p2[0:0] === 1'b1) ? 32'd0 : j_0_reg_207);
+
+assign select_ln21_1_fu_507_p3 = ((icmp_ln21_1_reg_614[0:0] === 1'b1) ? 64'd1 : add_ln21_1_reg_645);
+
+assign select_ln21_fu_424_p3 = ((select_ln19_3_fu_379_p3[0:0] === 1'b1) ? j_fu_386_p2 : select_ln19_fu_343_p3);
+
+assign select_ln26_1_fu_412_p3 = ((select_ln19_3_fu_379_p3[0:0] === 1'b1) ? add_ln26_1_fu_406_p2 : select_ln19_2_fu_367_p3);
+
+assign select_ln26_fu_398_p3 = ((or_ln26_fu_392_p2[0:0] === 1'b1) ? 32'd0 : ap_phi_mux_k_0_phi_fu_223_p4);
+
+assign sext_ln19_fu_363_p1 = select_ln19_1_fu_356_p3;
+
+assign sext_ln26_1_fu_437_p1 = $signed(add_ln26_4_fu_432_p2);
+
+assign sext_ln26_2_fu_477_p1 = $signed(add_ln26_2_fu_472_p2);
+
+assign sext_ln26_3_fu_486_p1 = $signed(add_ln26_5_fu_481_p2);
+
+assign sext_ln26_4_fu_452_p1 = $signed(add_ln26_6_fu_447_p2);
+
+assign sext_ln26_fu_420_p1 = $signed(select_ln26_1_fu_412_p3);
+
+always @ (posedge ap_clk) begin
+    p_cast20_reg_560[32:30] <= 3'b000;
+    p_cast19_reg_565[32:30] <= 3'b000;
+    p_cast_reg_570[32:30] <= 3'b000;
+    cast5_reg_575[95:32] <= 64'b0000000000000000000000000000000000000000000000000000000000000000;
+end
+
+endmodule //mmult
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_in1_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_in1_mem_m_axi.v
new file mode 100755
index 0000000..81f7248
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_in1_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in1_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in1_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in1_mem_m_axi_write
+mmult_in1_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in1_mem_m_axi_read
+mmult_in1_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in1_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in1_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in1_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in1_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in1_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_in2_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_in2_mem_m_axi.v
new file mode 100755
index 0000000..a2eab07
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_in2_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in2_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in2_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in2_mem_m_axi_write
+mmult_in2_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in2_mem_m_axi_read
+mmult_in2_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in2_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in2_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in2_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in2_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in2_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_out_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_out_mem_m_axi.v
new file mode 100755
index 0000000..cc472db
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_out_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_out_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_out_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_out_mem_m_axi_write
+mmult_out_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_out_mem_m_axi_read
+mmult_out_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_out_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_out_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_out_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_out_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_out_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_params_s_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_params_s_axi.v
new file mode 100755
index 0000000..d470352
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_params_s_axi.v
@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_urem_96ns_3bkb.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_urem_96ns_3bkb.v
new file mode 100755
index 0000000..3991faf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_urem_96ns_3bkb.v
@@ -0,0 +1,164 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+
+module mmult_urem_96ns_3bkb_div_u
+#(parameter
+    in0_WIDTH = 32,
+    in1_WIDTH = 32,
+    out_WIDTH = 32
+)
+(
+    input                       clk,
+    input                       reset,
+    input                       ce,
+    input       [in0_WIDTH-1:0] dividend,
+    input       [in1_WIDTH-1:0] divisor,
+    output wire [out_WIDTH-1:0] quot,
+    output wire [out_WIDTH-1:0] remd
+);
+
+localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH;
+
+//------------------------Local signal-------------------
+reg  [in0_WIDTH-1:0] dividend_tmp[0:in0_WIDTH];
+reg  [in1_WIDTH-1:0] divisor_tmp[0:in0_WIDTH];
+reg  [in0_WIDTH-1:0] remd_tmp[0:in0_WIDTH];
+wire [in0_WIDTH-1:0] comb_tmp[0:in0_WIDTH-1];
+wire [cal_WIDTH:0]   cal_tmp[0:in0_WIDTH-1];
+//------------------------Body---------------------------
+assign  quot    = dividend_tmp[in0_WIDTH];
+assign  remd    = remd_tmp[in0_WIDTH];
+
+// dividend_tmp[0], divisor_tmp[0], remd_tmp[0]
+always @(posedge clk)
+begin
+    if (ce) begin
+        dividend_tmp[0] <= dividend;
+        divisor_tmp[0]  <= divisor;
+        remd_tmp[0]     <= 1'b0;
+    end
+end
+
+genvar i;
+generate 
+    for (i = 0; i < in0_WIDTH; i = i + 1)
+    begin : loop
+        if (in0_WIDTH == 1) assign  comb_tmp[i]     = dividend_tmp[i][0];
+        else                assign  comb_tmp[i]     = {remd_tmp[i][in0_WIDTH-2:0], dividend_tmp[i][in0_WIDTH-1]};
+        assign  cal_tmp[i]      = {1'b0, comb_tmp[i]} - {1'b0, divisor_tmp[i]};
+
+        always @(posedge clk)
+        begin
+            if (ce) begin
+                if (in0_WIDTH == 1) dividend_tmp[i+1] <= ~cal_tmp[i][cal_WIDTH];
+                else                dividend_tmp[i+1] <= {dividend_tmp[i][in0_WIDTH-2:0], ~cal_tmp[i][cal_WIDTH]};
+                divisor_tmp[i+1]  <= divisor_tmp[i];
+                remd_tmp[i+1]     <= cal_tmp[i][cal_WIDTH]? comb_tmp[i] : cal_tmp[i][in0_WIDTH-1:0];
+            end
+        end
+    end
+endgenerate
+
+endmodule
+
+module mmult_urem_96ns_3bkb_div
+#(parameter
+        in0_WIDTH   = 32,
+        in1_WIDTH   = 32,
+        out_WIDTH   = 32
+)
+(
+        input                           clk,
+        input                           reset,
+        input                           ce,
+        input           [in0_WIDTH-1:0] dividend,
+        input           [in1_WIDTH-1:0] divisor,
+        output  reg     [out_WIDTH-1:0] quot,
+        output  reg     [out_WIDTH-1:0] remd
+);
+//------------------------Local signal-------------------
+reg     [in0_WIDTH-1:0] dividend0;
+reg     [in1_WIDTH-1:0] divisor0;
+wire    [in0_WIDTH-1:0] dividend_u;
+wire    [in1_WIDTH-1:0] divisor_u;
+wire    [out_WIDTH-1:0] quot_u;
+wire    [out_WIDTH-1:0] remd_u;
+//------------------------Instantiation------------------
+mmult_urem_96ns_3bkb_div_u #(
+    .in0_WIDTH      ( in0_WIDTH ),
+    .in1_WIDTH      ( in1_WIDTH ),
+    .out_WIDTH      ( out_WIDTH )
+) mmult_urem_96ns_3bkb_div_u_0 (
+    .clk      ( clk ),
+    .reset    ( reset ),
+    .ce       ( ce ),
+    .dividend ( dividend_u ),
+    .divisor  ( divisor_u ),
+    .quot     ( quot_u ),
+    .remd     ( remd_u )
+);
+//------------------------Body---------------------------
+assign dividend_u = dividend0;
+assign divisor_u = divisor0;
+
+always @(posedge clk)
+begin
+    if (ce) begin
+        dividend0 <= dividend;
+        divisor0  <= divisor;
+    end
+end
+
+always @(posedge clk)
+begin
+    if (ce) begin
+        quot <= quot_u;
+        remd <= remd_u;
+    end
+end
+
+endmodule
+
+
+`timescale 1 ns / 1 ps
+module mmult_urem_96ns_3bkb(
+    clk,
+    reset,
+    ce,
+    din0,
+    din1,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+input clk;
+input reset;
+input ce;
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+output[dout_WIDTH - 1:0] dout;
+
+wire[dout_WIDTH - 1:0] sig_quot;
+
+
+mmult_urem_96ns_3bkb_div #(
+.in0_WIDTH( din0_WIDTH ),
+.in1_WIDTH( din1_WIDTH ),
+.out_WIDTH( dout_WIDTH ))
+mmult_urem_96ns_3bkb_div_U(
+    .dividend( din0 ),
+    .divisor( din1 ),
+    .remd( dout ),
+    .quot( sig_quot ),
+    .clk( clk ),
+    .ce( ce ),
+    .reset( reset ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult.vhd
new file mode 100755
index 0000000..81676f0
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult.vhd
@@ -0,0 +1,2579 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+-- Version: 2020.1
+-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult is
+generic (
+    C_M_AXI_IN1_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_S_AXI_PARAMS_ADDR_WIDTH : INTEGER := 6;
+    C_S_AXI_PARAMS_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_IN2_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_OUT_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_CACHE_VALUE : INTEGER := 3 );
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    m_axi_in1_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in1_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_WREADY : IN STD_LOGIC;
+    m_axi_in1_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in1_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in1_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in1_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RVALID : IN STD_LOGIC;
+    m_axi_in1_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_RLAST : IN STD_LOGIC;
+    m_axi_in1_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BVALID : IN STD_LOGIC;
+    m_axi_in1_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in2_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_WREADY : IN STD_LOGIC;
+    m_axi_in2_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in2_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in2_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in2_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RVALID : IN STD_LOGIC;
+    m_axi_in2_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_RLAST : IN STD_LOGIC;
+    m_axi_in2_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BVALID : IN STD_LOGIC;
+    m_axi_in2_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_out_mem_AWREADY : IN STD_LOGIC;
+    m_axi_out_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_WVALID : OUT STD_LOGIC;
+    m_axi_out_mem_WREADY : IN STD_LOGIC;
+    m_axi_out_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_out_mem_WLAST : OUT STD_LOGIC;
+    m_axi_out_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_out_mem_ARREADY : IN STD_LOGIC;
+    m_axi_out_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RVALID : IN STD_LOGIC;
+    m_axi_out_mem_RREADY : OUT STD_LOGIC;
+    m_axi_out_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_RLAST : IN STD_LOGIC;
+    m_axi_out_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BVALID : IN STD_LOGIC;
+    m_axi_out_mem_BREADY : OUT STD_LOGIC;
+    m_axi_out_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_BUSER_WIDTH-1 downto 0);
+    s_axi_params_AWVALID : IN STD_LOGIC;
+    s_axi_params_AWREADY : OUT STD_LOGIC;
+    s_axi_params_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_WVALID : IN STD_LOGIC;
+    s_axi_params_WREADY : OUT STD_LOGIC;
+    s_axi_params_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH/8-1 downto 0);
+    s_axi_params_ARVALID : IN STD_LOGIC;
+    s_axi_params_ARREADY : OUT STD_LOGIC;
+    s_axi_params_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_RVALID : OUT STD_LOGIC;
+    s_axi_params_RREADY : IN STD_LOGIC;
+    s_axi_params_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    s_axi_params_BVALID : OUT STD_LOGIC;
+    s_axi_params_BREADY : IN STD_LOGIC;
+    s_axi_params_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    interrupt : OUT STD_LOGIC );
+end;
+
+
+architecture behav of mmult is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=3932262,HLS_SYN_TPT=none,HLS_SYN_MEM=6,HLS_SYN_DSP=28,HLS_SYN_FF=11990,HLS_SYN_LUT=10233,HLS_VERSION=2020_1}";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000010";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000100";
+    constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000001000";
+    constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000010000";
+    constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000100000";
+    constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (17 downto 0) := "000000000001000000";
+    constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (17 downto 0) := "000000000010000000";
+    constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (17 downto 0) := "000000000100000000";
+    constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (17 downto 0) := "000000001000000000";
+    constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (17 downto 0) := "000000010000000000";
+    constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (17 downto 0) := "000000100000000000";
+    constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (17 downto 0) := "000001000000000000";
+    constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (17 downto 0) := "000010000000000000";
+    constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (17 downto 0) := "000100000000000000";
+    constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (17 downto 0) := "001000000000000000";
+    constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (17 downto 0) := "010000000000000000";
+    constant ap_ST_fsm_state118 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
+    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
+    constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
+    constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv96_0 : STD_LOGIC_VECTOR (95 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
+    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv96_1 : STD_LOGIC_VECTOR (95 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
+    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
+    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
+    constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
+    constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
+    constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
+    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
+    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal ap_start : STD_LOGIC;
+    signal ap_done : STD_LOGIC;
+    signal ap_idle : STD_LOGIC;
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal ap_ready : STD_LOGIC;
+    signal in1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_r : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
+    signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage10 : BOOLEAN;
+    signal icmp_ln8_reg_676 : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
+    signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage2 : BOOLEAN;
+    signal icmp_ln19_reg_600 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln19_reg_600_pp0_iter7_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage3 : BOOLEAN;
+    signal in2_mem_blk_n_R : STD_LOGIC;
+    signal out_mem_blk_n_AR : STD_LOGIC;
+    signal icmp_ln19_reg_600_pp0_iter6_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_R : STD_LOGIC;
+    signal out_mem_blk_n_AW : STD_LOGIC;
+    signal out_mem_blk_n_W : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
+    signal ap_block_pp0_stage4 : BOOLEAN;
+    signal out_mem_blk_n_B : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
+    signal ap_block_pp0_stage9 : BOOLEAN;
+    signal in1_mem_AWREADY : STD_LOGIC;
+    signal in1_mem_WREADY : STD_LOGIC;
+    signal in1_mem_ARVALID : STD_LOGIC;
+    signal in1_mem_ARREADY : STD_LOGIC;
+    signal in1_mem_RVALID : STD_LOGIC;
+    signal in1_mem_RREADY : STD_LOGIC;
+    signal in1_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RLAST : STD_LOGIC;
+    signal in1_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BVALID : STD_LOGIC;
+    signal in1_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_AWREADY : STD_LOGIC;
+    signal in2_mem_WREADY : STD_LOGIC;
+    signal in2_mem_ARVALID : STD_LOGIC;
+    signal in2_mem_ARREADY : STD_LOGIC;
+    signal in2_mem_RVALID : STD_LOGIC;
+    signal in2_mem_RREADY : STD_LOGIC;
+    signal in2_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_RLAST : STD_LOGIC;
+    signal in2_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BVALID : STD_LOGIC;
+    signal in2_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_AWVALID : STD_LOGIC;
+    signal out_mem_AWREADY : STD_LOGIC;
+    signal out_mem_WVALID : STD_LOGIC;
+    signal out_mem_WREADY : STD_LOGIC;
+    signal out_mem_ARVALID : STD_LOGIC;
+    signal out_mem_ARREADY : STD_LOGIC;
+    signal out_mem_RVALID : STD_LOGIC;
+    signal out_mem_RREADY : STD_LOGIC;
+    signal out_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_RLAST : STD_LOGIC;
+    signal out_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BVALID : STD_LOGIC;
+    signal out_mem_BREADY : STD_LOGIC;
+    signal out_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten18_reg_171 : STD_LOGIC_VECTOR (95 downto 0);
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state18_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state33_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_state48_pp0_stage0_iter3 : BOOLEAN;
+    signal ap_block_state63_pp0_stage0_iter4 : BOOLEAN;
+    signal ap_block_state78_pp0_stage0_iter5 : BOOLEAN;
+    signal ap_block_state93_pp0_stage0_iter6 : BOOLEAN;
+    signal ap_block_state108_pp0_stage0_iter7 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal i_0_reg_183 : STD_LOGIC_VECTOR (30 downto 0);
+    signal indvar_flatten_reg_195 : STD_LOGIC_VECTOR (63 downto 0);
+    signal j_0_reg_207 : STD_LOGIC_VECTOR (31 downto 0);
+    signal k_0_reg_219 : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim_read_reg_528 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_reg_539 : STD_LOGIC_VECTOR (29 downto 0);
+    signal tmp_1_reg_544 : STD_LOGIC_VECTOR (29 downto 0);
+    signal tmp_3_reg_549 : STD_LOGIC_VECTOR (29 downto 0);
+    signal bound_fu_265_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_reg_554 : STD_LOGIC_VECTOR (63 downto 0);
+    signal p_cast20_fu_271_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast20_reg_560 : STD_LOGIC_VECTOR (32 downto 0);
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal p_cast19_fu_274_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast19_reg_565 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast_fu_277_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal p_cast_reg_570 : STD_LOGIC_VECTOR (32 downto 0);
+    signal cast5_fu_280_p1 : STD_LOGIC_VECTOR (95 downto 0);
+    signal cast5_reg_575 : STD_LOGIC_VECTOR (95 downto 0);
+    signal bound7_fu_286_p2 : STD_LOGIC_VECTOR (95 downto 0);
+    signal bound7_reg_580 : STD_LOGIC_VECTOR (95 downto 0);
+    signal icmp_ln21_fu_292_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln21_reg_585 : STD_LOGIC_VECTOR (0 downto 0);
+    signal mul_ln26_fu_301_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln26_reg_590 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln26_fu_306_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln26_reg_595 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln19_fu_312_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln19_reg_600_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln19_reg_600_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln19_reg_600_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln19_reg_600_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln19_reg_600_pp0_iter5_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln19_fu_317_p2 : STD_LOGIC_VECTOR (95 downto 0);
+    signal add_ln19_reg_604 : STD_LOGIC_VECTOR (95 downto 0);
+    signal add_ln19_1_fu_328_p2 : STD_LOGIC_VECTOR (30 downto 0);
+    signal add_ln19_1_reg_609 : STD_LOGIC_VECTOR (30 downto 0);
+    signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
+    signal ap_block_state4_pp0_stage1_iter0 : BOOLEAN;
+    signal ap_block_state19_pp0_stage1_iter1 : BOOLEAN;
+    signal ap_block_state34_pp0_stage1_iter2 : BOOLEAN;
+    signal ap_block_state49_pp0_stage1_iter3 : BOOLEAN;
+    signal ap_block_state64_pp0_stage1_iter4 : BOOLEAN;
+    signal ap_block_state79_pp0_stage1_iter5 : BOOLEAN;
+    signal ap_block_state94_pp0_stage1_iter6 : BOOLEAN;
+    signal ap_block_state109_pp0_stage1_iter7 : BOOLEAN;
+    signal ap_block_pp0_stage1_11001 : BOOLEAN;
+    signal icmp_ln21_1_fu_338_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln21_1_reg_614 : STD_LOGIC_VECTOR (0 downto 0);
+    signal select_ln26_fu_398_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln26_reg_620 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln21_fu_424_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln21_reg_626 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_addr_reg_632 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_addr_reg_632_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_addr_reg_632_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_addr_reg_632_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_addr_reg_632_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_addr_reg_632_pp0_iter5_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_addr_reg_632_pp0_iter6_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_reg_638 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_reg_638_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_reg_638_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_reg_638_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_reg_638_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_reg_638_pp0_iter5_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_reg_638_pp0_iter6_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_reg_638_pp0_iter7_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln21_1_fu_462_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal add_ln21_1_reg_645 : STD_LOGIC_VECTOR (63 downto 0);
+    signal in2_mem_addr_reg_650 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state5_pp0_stage2_iter0 : BOOLEAN;
+    signal ap_block_state20_pp0_stage2_iter1 : BOOLEAN;
+    signal ap_block_state35_pp0_stage2_iter2 : BOOLEAN;
+    signal ap_block_state50_pp0_stage2_iter3 : BOOLEAN;
+    signal ap_block_state65_pp0_stage2_iter4 : BOOLEAN;
+    signal ap_block_state80_pp0_stage2_iter5 : BOOLEAN;
+    signal ap_block_state95_pp0_stage2_iter6 : BOOLEAN;
+    signal ap_block_state110_pp0_stage2_iter7 : BOOLEAN;
+    signal ap_block_pp0_stage2_11001 : BOOLEAN;
+    signal in2_mem_addr_read_reg_656 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state13_pp0_stage10_iter0 : BOOLEAN;
+    signal ap_block_state28_pp0_stage10_iter1 : BOOLEAN;
+    signal ap_block_state43_pp0_stage10_iter2 : BOOLEAN;
+    signal ap_block_state58_pp0_stage10_iter3 : BOOLEAN;
+    signal ap_block_state73_pp0_stage10_iter4 : BOOLEAN;
+    signal ap_block_state88_pp0_stage10_iter5 : BOOLEAN;
+    signal ap_block_state103_pp0_stage10_iter6 : BOOLEAN;
+    signal ap_block_state103_io : BOOLEAN;
+    signal ap_block_pp0_stage10_11001 : BOOLEAN;
+    signal in2_mem_addr_read_reg_656_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_addr_read_reg_656_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_addr_read_reg_656_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_addr_read_reg_656_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_addr_read_reg_656_pp0_iter5_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_addr_read_reg_656_pp0_iter6_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln19_4_fu_496_p3 : STD_LOGIC_VECTOR (30 downto 0);
+    signal select_ln19_4_reg_661 : STD_LOGIC_VECTOR (30 downto 0);
+    signal ap_CS_fsm_pp0_stage14 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none";
+    signal ap_block_state17_pp0_stage14_iter0 : BOOLEAN;
+    signal ap_block_state32_pp0_stage14_iter1 : BOOLEAN;
+    signal ap_block_state47_pp0_stage14_iter2 : BOOLEAN;
+    signal ap_block_state62_pp0_stage14_iter3 : BOOLEAN;
+    signal ap_block_state77_pp0_stage14_iter4 : BOOLEAN;
+    signal ap_block_state92_pp0_stage14_iter5 : BOOLEAN;
+    signal ap_block_state107_pp0_stage14_iter6 : BOOLEAN;
+    signal ap_block_pp0_stage14_11001 : BOOLEAN;
+    signal k_fu_502_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal k_reg_666 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal select_ln21_1_fu_507_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal select_ln21_1_reg_671 : STD_LOGIC_VECTOR (63 downto 0);
+    signal icmp_ln8_fu_513_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state12_pp0_stage9_iter0 : BOOLEAN;
+    signal ap_block_state27_pp0_stage9_iter1 : BOOLEAN;
+    signal ap_block_state42_pp0_stage9_iter2 : BOOLEAN;
+    signal ap_block_state57_pp0_stage9_iter3 : BOOLEAN;
+    signal ap_block_state72_pp0_stage9_iter4 : BOOLEAN;
+    signal ap_block_state87_pp0_stage9_iter5 : BOOLEAN;
+    signal ap_block_state102_pp0_stage9_iter6 : BOOLEAN;
+    signal ap_block_state117_pp0_stage9_iter7 : BOOLEAN;
+    signal ap_block_pp0_stage9_11001 : BOOLEAN;
+    signal in1_mem_addr_read_reg_680 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_addr_read_reg_685 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln26_3_fu_523_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln26_3_reg_690 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state6_pp0_stage3_iter0 : BOOLEAN;
+    signal ap_block_state6_io : BOOLEAN;
+    signal ap_block_state21_pp0_stage3_iter1 : BOOLEAN;
+    signal ap_block_state36_pp0_stage3_iter2 : BOOLEAN;
+    signal ap_block_state51_pp0_stage3_iter3 : BOOLEAN;
+    signal ap_block_state66_pp0_stage3_iter4 : BOOLEAN;
+    signal ap_block_state81_pp0_stage3_iter5 : BOOLEAN;
+    signal ap_block_state96_pp0_stage3_iter6 : BOOLEAN;
+    signal ap_block_state111_pp0_stage3_iter7 : BOOLEAN;
+    signal ap_block_state111_io : BOOLEAN;
+    signal ap_block_pp0_stage3_11001 : BOOLEAN;
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
+    signal ap_block_pp0_stage14_subdone : BOOLEAN;
+    signal ap_block_pp0_stage9_subdone : BOOLEAN;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
+    signal ap_phi_mux_indvar_flatten18_phi_fu_175_p4 : STD_LOGIC_VECTOR (95 downto 0);
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal ap_phi_mux_i_0_phi_fu_187_p4 : STD_LOGIC_VECTOR (30 downto 0);
+    signal ap_phi_mux_indvar_flatten_phi_fu_199_p4 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp0_stage1 : BOOLEAN;
+    signal ap_phi_mux_j_0_phi_fu_211_p4 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_phi_mux_k_0_phi_fu_223_p4 : STD_LOGIC_VECTOR (31 downto 0);
+    signal sext_ln26_1_fu_437_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln26_4_fu_452_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln26_3_fu_486_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_state7_pp0_stage4_iter0 : BOOLEAN;
+    signal ap_block_state22_pp0_stage4_iter1 : BOOLEAN;
+    signal ap_block_state37_pp0_stage4_iter2 : BOOLEAN;
+    signal ap_block_state52_pp0_stage4_iter3 : BOOLEAN;
+    signal ap_block_state67_pp0_stage4_iter4 : BOOLEAN;
+    signal ap_block_state82_pp0_stage4_iter5 : BOOLEAN;
+    signal ap_block_state97_pp0_stage4_iter6 : BOOLEAN;
+    signal ap_block_state112_pp0_stage4_iter7 : BOOLEAN;
+    signal ap_block_state112_io : BOOLEAN;
+    signal ap_block_pp0_stage4_11001 : BOOLEAN;
+    signal ap_block_pp0_stage4_01001 : BOOLEAN;
+    signal cast_fu_261_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_265_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal cast_fu_261_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_fu_265_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound7_fu_286_p0 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound7_fu_286_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln26_fu_301_p1 : STD_LOGIC_VECTOR (30 downto 0);
+    signal grp_fu_323_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln26_3_fu_351_p1 : STD_LOGIC_VECTOR (30 downto 0);
+    signal mul_ln26_3_fu_351_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln19_1_fu_356_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln23_fu_374_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal select_ln19_fu_343_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln19_3_fu_379_p3 : STD_LOGIC_VECTOR (0 downto 0);
+    signal or_ln26_fu_392_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_fu_386_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln26_1_fu_406_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln19_2_fu_367_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln26_1_fu_412_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal sext_ln19_fu_363_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln26_4_fu_432_p2 : STD_LOGIC_VECTOR (32 downto 0);
+    signal sext_ln26_fu_420_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln26_6_fu_447_p2 : STD_LOGIC_VECTOR (32 downto 0);
+    signal mul_ln26_1_fu_468_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln26_2_fu_472_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal sext_ln26_2_fu_477_p1 : STD_LOGIC_VECTOR (32 downto 0);
+    signal add_ln26_5_fu_481_p2 : STD_LOGIC_VECTOR (32 downto 0);
+    signal ap_block_pp0_stage14 : BOOLEAN;
+    signal grp_fu_323_p2 : STD_LOGIC_VECTOR (95 downto 0);
+    signal mul_ln26_2_fu_519_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_323_ce : STD_LOGIC;
+    signal ap_block_state8_pp0_stage5_iter0 : BOOLEAN;
+    signal ap_block_state23_pp0_stage5_iter1 : BOOLEAN;
+    signal ap_block_state38_pp0_stage5_iter2 : BOOLEAN;
+    signal ap_block_state53_pp0_stage5_iter3 : BOOLEAN;
+    signal ap_block_state68_pp0_stage5_iter4 : BOOLEAN;
+    signal ap_block_state83_pp0_stage5_iter5 : BOOLEAN;
+    signal ap_block_state98_pp0_stage5_iter6 : BOOLEAN;
+    signal ap_block_state113_pp0_stage5_iter7 : BOOLEAN;
+    signal ap_block_pp0_stage5_11001 : BOOLEAN;
+    signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
+    signal ap_block_state9_pp0_stage6_iter0 : BOOLEAN;
+    signal ap_block_state24_pp0_stage6_iter1 : BOOLEAN;
+    signal ap_block_state39_pp0_stage6_iter2 : BOOLEAN;
+    signal ap_block_state54_pp0_stage6_iter3 : BOOLEAN;
+    signal ap_block_state69_pp0_stage6_iter4 : BOOLEAN;
+    signal ap_block_state84_pp0_stage6_iter5 : BOOLEAN;
+    signal ap_block_state99_pp0_stage6_iter6 : BOOLEAN;
+    signal ap_block_state114_pp0_stage6_iter7 : BOOLEAN;
+    signal ap_block_pp0_stage6_11001 : BOOLEAN;
+    signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
+    signal ap_block_state10_pp0_stage7_iter0 : BOOLEAN;
+    signal ap_block_state25_pp0_stage7_iter1 : BOOLEAN;
+    signal ap_block_state40_pp0_stage7_iter2 : BOOLEAN;
+    signal ap_block_state55_pp0_stage7_iter3 : BOOLEAN;
+    signal ap_block_state70_pp0_stage7_iter4 : BOOLEAN;
+    signal ap_block_state85_pp0_stage7_iter5 : BOOLEAN;
+    signal ap_block_state100_pp0_stage7_iter6 : BOOLEAN;
+    signal ap_block_state115_pp0_stage7_iter7 : BOOLEAN;
+    signal ap_block_pp0_stage7_11001 : BOOLEAN;
+    signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
+    signal ap_block_state11_pp0_stage8_iter0 : BOOLEAN;
+    signal ap_block_state26_pp0_stage8_iter1 : BOOLEAN;
+    signal ap_block_state41_pp0_stage8_iter2 : BOOLEAN;
+    signal ap_block_state56_pp0_stage8_iter3 : BOOLEAN;
+    signal ap_block_state71_pp0_stage8_iter4 : BOOLEAN;
+    signal ap_block_state86_pp0_stage8_iter5 : BOOLEAN;
+    signal ap_block_state101_pp0_stage8_iter6 : BOOLEAN;
+    signal ap_block_state116_pp0_stage8_iter7 : BOOLEAN;
+    signal ap_block_pp0_stage8_11001 : BOOLEAN;
+    signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
+    signal ap_block_state14_pp0_stage11_iter0 : BOOLEAN;
+    signal ap_block_state29_pp0_stage11_iter1 : BOOLEAN;
+    signal ap_block_state44_pp0_stage11_iter2 : BOOLEAN;
+    signal ap_block_state59_pp0_stage11_iter3 : BOOLEAN;
+    signal ap_block_state74_pp0_stage11_iter4 : BOOLEAN;
+    signal ap_block_state89_pp0_stage11_iter5 : BOOLEAN;
+    signal ap_block_state104_pp0_stage11_iter6 : BOOLEAN;
+    signal ap_block_pp0_stage11_11001 : BOOLEAN;
+    signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
+    signal ap_block_state15_pp0_stage12_iter0 : BOOLEAN;
+    signal ap_block_state30_pp0_stage12_iter1 : BOOLEAN;
+    signal ap_block_state45_pp0_stage12_iter2 : BOOLEAN;
+    signal ap_block_state60_pp0_stage12_iter3 : BOOLEAN;
+    signal ap_block_state75_pp0_stage12_iter4 : BOOLEAN;
+    signal ap_block_state90_pp0_stage12_iter5 : BOOLEAN;
+    signal ap_block_state105_pp0_stage12_iter6 : BOOLEAN;
+    signal ap_block_pp0_stage12_11001 : BOOLEAN;
+    signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
+    signal ap_block_state16_pp0_stage13_iter0 : BOOLEAN;
+    signal ap_block_state31_pp0_stage13_iter1 : BOOLEAN;
+    signal ap_block_state46_pp0_stage13_iter2 : BOOLEAN;
+    signal ap_block_state61_pp0_stage13_iter3 : BOOLEAN;
+    signal ap_block_state76_pp0_stage13_iter4 : BOOLEAN;
+    signal ap_block_state91_pp0_stage13_iter5 : BOOLEAN;
+    signal ap_block_state106_pp0_stage13_iter6 : BOOLEAN;
+    signal ap_block_pp0_stage13_11001 : BOOLEAN;
+    signal ap_CS_fsm_pp0_stage13 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none";
+    signal ap_CS_fsm_state118 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state118 : signal is "none";
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (17 downto 0);
+    signal ap_block_pp0_stage1_subdone : BOOLEAN;
+    signal ap_block_pp0_stage2_subdone : BOOLEAN;
+    signal ap_block_pp0_stage3_subdone : BOOLEAN;
+    signal ap_block_pp0_stage4_subdone : BOOLEAN;
+    signal ap_block_pp0_stage5_subdone : BOOLEAN;
+    signal ap_block_pp0_stage6_subdone : BOOLEAN;
+    signal ap_block_pp0_stage7_subdone : BOOLEAN;
+    signal ap_block_pp0_stage8_subdone : BOOLEAN;
+    signal ap_block_pp0_stage10_subdone : BOOLEAN;
+    signal ap_block_pp0_stage11_subdone : BOOLEAN;
+    signal ap_block_pp0_stage12_subdone : BOOLEAN;
+    signal ap_block_pp0_stage13_subdone : BOOLEAN;
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal bound7_fu_286_p00 : STD_LOGIC_VECTOR (95 downto 0);
+    signal bound7_fu_286_p10 : STD_LOGIC_VECTOR (95 downto 0);
+    signal mul_ln26_3_fu_351_p10 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln26_fu_301_p10 : STD_LOGIC_VECTOR (31 downto 0);
+
+    component mmult_urem_96ns_3bkb IS
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        din0 : IN STD_LOGIC_VECTOR (95 downto 0);
+        din1 : IN STD_LOGIC_VECTOR (31 downto 0);
+        ce : IN STD_LOGIC;
+        dout : OUT STD_LOGIC_VECTOR (95 downto 0) );
+    end component;
+
+
+    component mmult_params_s_axi IS
+    generic (
+        C_S_AXI_ADDR_WIDTH : INTEGER;
+        C_S_AXI_DATA_WIDTH : INTEGER );
+    port (
+        AWVALID : IN STD_LOGIC;
+        AWREADY : OUT STD_LOGIC;
+        AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        WVALID : IN STD_LOGIC;
+        WREADY : OUT STD_LOGIC;
+        WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
+        ARVALID : IN STD_LOGIC;
+        ARREADY : OUT STD_LOGIC;
+        ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        RVALID : OUT STD_LOGIC;
+        RREADY : IN STD_LOGIC;
+        RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : OUT STD_LOGIC;
+        BREADY : IN STD_LOGIC;
+        BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        ap_start : OUT STD_LOGIC;
+        interrupt : OUT STD_LOGIC;
+        ap_ready : IN STD_LOGIC;
+        ap_done : IN STD_LOGIC;
+        ap_idle : IN STD_LOGIC;
+        in1 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        in2 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        out_r : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dim : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_in2_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_out_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+
+begin
+    mmult_params_s_axi_U : component mmult_params_s_axi
+    generic map (
+        C_S_AXI_ADDR_WIDTH => C_S_AXI_PARAMS_ADDR_WIDTH,
+        C_S_AXI_DATA_WIDTH => C_S_AXI_PARAMS_DATA_WIDTH)
+    port map (
+        AWVALID => s_axi_params_AWVALID,
+        AWREADY => s_axi_params_AWREADY,
+        AWADDR => s_axi_params_AWADDR,
+        WVALID => s_axi_params_WVALID,
+        WREADY => s_axi_params_WREADY,
+        WDATA => s_axi_params_WDATA,
+        WSTRB => s_axi_params_WSTRB,
+        ARVALID => s_axi_params_ARVALID,
+        ARREADY => s_axi_params_ARREADY,
+        ARADDR => s_axi_params_ARADDR,
+        RVALID => s_axi_params_RVALID,
+        RREADY => s_axi_params_RREADY,
+        RDATA => s_axi_params_RDATA,
+        RRESP => s_axi_params_RRESP,
+        BVALID => s_axi_params_BVALID,
+        BREADY => s_axi_params_BREADY,
+        BRESP => s_axi_params_BRESP,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        ap_start => ap_start,
+        interrupt => interrupt,
+        ap_ready => ap_ready,
+        ap_done => ap_done,
+        ap_idle => ap_idle,
+        in1 => in1,
+        in2 => in2,
+        out_r => out_r,
+        dim => dim);
+
+    mmult_in1_mem_m_axi_U : component mmult_in1_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN1_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN1_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN1_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN1_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN1_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN1_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN1_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN1_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN1_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN1_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN1_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in1_mem_AWVALID,
+        AWREADY => m_axi_in1_mem_AWREADY,
+        AWADDR => m_axi_in1_mem_AWADDR,
+        AWID => m_axi_in1_mem_AWID,
+        AWLEN => m_axi_in1_mem_AWLEN,
+        AWSIZE => m_axi_in1_mem_AWSIZE,
+        AWBURST => m_axi_in1_mem_AWBURST,
+        AWLOCK => m_axi_in1_mem_AWLOCK,
+        AWCACHE => m_axi_in1_mem_AWCACHE,
+        AWPROT => m_axi_in1_mem_AWPROT,
+        AWQOS => m_axi_in1_mem_AWQOS,
+        AWREGION => m_axi_in1_mem_AWREGION,
+        AWUSER => m_axi_in1_mem_AWUSER,
+        WVALID => m_axi_in1_mem_WVALID,
+        WREADY => m_axi_in1_mem_WREADY,
+        WDATA => m_axi_in1_mem_WDATA,
+        WSTRB => m_axi_in1_mem_WSTRB,
+        WLAST => m_axi_in1_mem_WLAST,
+        WID => m_axi_in1_mem_WID,
+        WUSER => m_axi_in1_mem_WUSER,
+        ARVALID => m_axi_in1_mem_ARVALID,
+        ARREADY => m_axi_in1_mem_ARREADY,
+        ARADDR => m_axi_in1_mem_ARADDR,
+        ARID => m_axi_in1_mem_ARID,
+        ARLEN => m_axi_in1_mem_ARLEN,
+        ARSIZE => m_axi_in1_mem_ARSIZE,
+        ARBURST => m_axi_in1_mem_ARBURST,
+        ARLOCK => m_axi_in1_mem_ARLOCK,
+        ARCACHE => m_axi_in1_mem_ARCACHE,
+        ARPROT => m_axi_in1_mem_ARPROT,
+        ARQOS => m_axi_in1_mem_ARQOS,
+        ARREGION => m_axi_in1_mem_ARREGION,
+        ARUSER => m_axi_in1_mem_ARUSER,
+        RVALID => m_axi_in1_mem_RVALID,
+        RREADY => m_axi_in1_mem_RREADY,
+        RDATA => m_axi_in1_mem_RDATA,
+        RLAST => m_axi_in1_mem_RLAST,
+        RID => m_axi_in1_mem_RID,
+        RUSER => m_axi_in1_mem_RUSER,
+        RRESP => m_axi_in1_mem_RRESP,
+        BVALID => m_axi_in1_mem_BVALID,
+        BREADY => m_axi_in1_mem_BREADY,
+        BRESP => m_axi_in1_mem_BRESP,
+        BID => m_axi_in1_mem_BID,
+        BUSER => m_axi_in1_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in1_mem_ARVALID,
+        I_ARREADY => in1_mem_ARREADY,
+        I_ARADDR => in1_mem_addr_reg_632_pp0_iter6_reg,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => dim_read_reg_528,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in1_mem_RVALID,
+        I_RREADY => in1_mem_RREADY,
+        I_RDATA => in1_mem_RDATA,
+        I_RID => in1_mem_RID,
+        I_RUSER => in1_mem_RUSER,
+        I_RRESP => in1_mem_RRESP,
+        I_RLAST => in1_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in1_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in1_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in1_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in1_mem_BRESP,
+        I_BID => in1_mem_BID,
+        I_BUSER => in1_mem_BUSER);
+
+    mmult_in2_mem_m_axi_U : component mmult_in2_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN2_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN2_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN2_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN2_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN2_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN2_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN2_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN2_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN2_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN2_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN2_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in2_mem_AWVALID,
+        AWREADY => m_axi_in2_mem_AWREADY,
+        AWADDR => m_axi_in2_mem_AWADDR,
+        AWID => m_axi_in2_mem_AWID,
+        AWLEN => m_axi_in2_mem_AWLEN,
+        AWSIZE => m_axi_in2_mem_AWSIZE,
+        AWBURST => m_axi_in2_mem_AWBURST,
+        AWLOCK => m_axi_in2_mem_AWLOCK,
+        AWCACHE => m_axi_in2_mem_AWCACHE,
+        AWPROT => m_axi_in2_mem_AWPROT,
+        AWQOS => m_axi_in2_mem_AWQOS,
+        AWREGION => m_axi_in2_mem_AWREGION,
+        AWUSER => m_axi_in2_mem_AWUSER,
+        WVALID => m_axi_in2_mem_WVALID,
+        WREADY => m_axi_in2_mem_WREADY,
+        WDATA => m_axi_in2_mem_WDATA,
+        WSTRB => m_axi_in2_mem_WSTRB,
+        WLAST => m_axi_in2_mem_WLAST,
+        WID => m_axi_in2_mem_WID,
+        WUSER => m_axi_in2_mem_WUSER,
+        ARVALID => m_axi_in2_mem_ARVALID,
+        ARREADY => m_axi_in2_mem_ARREADY,
+        ARADDR => m_axi_in2_mem_ARADDR,
+        ARID => m_axi_in2_mem_ARID,
+        ARLEN => m_axi_in2_mem_ARLEN,
+        ARSIZE => m_axi_in2_mem_ARSIZE,
+        ARBURST => m_axi_in2_mem_ARBURST,
+        ARLOCK => m_axi_in2_mem_ARLOCK,
+        ARCACHE => m_axi_in2_mem_ARCACHE,
+        ARPROT => m_axi_in2_mem_ARPROT,
+        ARQOS => m_axi_in2_mem_ARQOS,
+        ARREGION => m_axi_in2_mem_ARREGION,
+        ARUSER => m_axi_in2_mem_ARUSER,
+        RVALID => m_axi_in2_mem_RVALID,
+        RREADY => m_axi_in2_mem_RREADY,
+        RDATA => m_axi_in2_mem_RDATA,
+        RLAST => m_axi_in2_mem_RLAST,
+        RID => m_axi_in2_mem_RID,
+        RUSER => m_axi_in2_mem_RUSER,
+        RRESP => m_axi_in2_mem_RRESP,
+        BVALID => m_axi_in2_mem_BVALID,
+        BREADY => m_axi_in2_mem_BREADY,
+        BRESP => m_axi_in2_mem_BRESP,
+        BID => m_axi_in2_mem_BID,
+        BUSER => m_axi_in2_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in2_mem_ARVALID,
+        I_ARREADY => in2_mem_ARREADY,
+        I_ARADDR => in2_mem_addr_reg_650,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in2_mem_RVALID,
+        I_RREADY => in2_mem_RREADY,
+        I_RDATA => in2_mem_RDATA,
+        I_RID => in2_mem_RID,
+        I_RUSER => in2_mem_RUSER,
+        I_RRESP => in2_mem_RRESP,
+        I_RLAST => in2_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in2_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in2_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in2_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in2_mem_BRESP,
+        I_BID => in2_mem_BID,
+        I_BUSER => in2_mem_BUSER);
+
+    mmult_out_mem_m_axi_U : component mmult_out_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_OUT_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_OUT_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_OUT_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_OUT_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_OUT_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_OUT_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_OUT_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_OUT_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_OUT_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_OUT_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_OUT_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_out_mem_AWVALID,
+        AWREADY => m_axi_out_mem_AWREADY,
+        AWADDR => m_axi_out_mem_AWADDR,
+        AWID => m_axi_out_mem_AWID,
+        AWLEN => m_axi_out_mem_AWLEN,
+        AWSIZE => m_axi_out_mem_AWSIZE,
+        AWBURST => m_axi_out_mem_AWBURST,
+        AWLOCK => m_axi_out_mem_AWLOCK,
+        AWCACHE => m_axi_out_mem_AWCACHE,
+        AWPROT => m_axi_out_mem_AWPROT,
+        AWQOS => m_axi_out_mem_AWQOS,
+        AWREGION => m_axi_out_mem_AWREGION,
+        AWUSER => m_axi_out_mem_AWUSER,
+        WVALID => m_axi_out_mem_WVALID,
+        WREADY => m_axi_out_mem_WREADY,
+        WDATA => m_axi_out_mem_WDATA,
+        WSTRB => m_axi_out_mem_WSTRB,
+        WLAST => m_axi_out_mem_WLAST,
+        WID => m_axi_out_mem_WID,
+        WUSER => m_axi_out_mem_WUSER,
+        ARVALID => m_axi_out_mem_ARVALID,
+        ARREADY => m_axi_out_mem_ARREADY,
+        ARADDR => m_axi_out_mem_ARADDR,
+        ARID => m_axi_out_mem_ARID,
+        ARLEN => m_axi_out_mem_ARLEN,
+        ARSIZE => m_axi_out_mem_ARSIZE,
+        ARBURST => m_axi_out_mem_ARBURST,
+        ARLOCK => m_axi_out_mem_ARLOCK,
+        ARCACHE => m_axi_out_mem_ARCACHE,
+        ARPROT => m_axi_out_mem_ARPROT,
+        ARQOS => m_axi_out_mem_ARQOS,
+        ARREGION => m_axi_out_mem_ARREGION,
+        ARUSER => m_axi_out_mem_ARUSER,
+        RVALID => m_axi_out_mem_RVALID,
+        RREADY => m_axi_out_mem_RREADY,
+        RDATA => m_axi_out_mem_RDATA,
+        RLAST => m_axi_out_mem_RLAST,
+        RID => m_axi_out_mem_RID,
+        RUSER => m_axi_out_mem_RUSER,
+        RRESP => m_axi_out_mem_RRESP,
+        BVALID => m_axi_out_mem_BVALID,
+        BREADY => m_axi_out_mem_BREADY,
+        BRESP => m_axi_out_mem_BRESP,
+        BID => m_axi_out_mem_BID,
+        BUSER => m_axi_out_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => out_mem_ARVALID,
+        I_ARREADY => out_mem_ARREADY,
+        I_ARADDR => out_mem_addr_reg_638_pp0_iter6_reg,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => out_mem_RVALID,
+        I_RREADY => out_mem_RREADY,
+        I_RDATA => out_mem_RDATA,
+        I_RID => out_mem_RID,
+        I_RUSER => out_mem_RUSER,
+        I_RRESP => out_mem_RRESP,
+        I_RLAST => out_mem_RLAST,
+        I_AWVALID => out_mem_AWVALID,
+        I_AWREADY => out_mem_AWREADY,
+        I_AWADDR => out_mem_addr_reg_638_pp0_iter7_reg,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_1,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => out_mem_WVALID,
+        I_WREADY => out_mem_WREADY,
+        I_WDATA => add_ln26_3_reg_690,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_F,
+        I_BVALID => out_mem_BVALID,
+        I_BREADY => out_mem_BREADY,
+        I_BRESP => out_mem_BRESP,
+        I_BID => out_mem_BID,
+        I_BUSER => out_mem_BUSER);
+
+    mmult_urem_96ns_3bkb_U1 : component mmult_urem_96ns_3bkb
+    generic map (
+        ID => 1,
+        NUM_STAGE => 100,
+        din0_WIDTH => 96,
+        din1_WIDTH => 32,
+        dout_WIDTH => 96)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => ap_phi_mux_indvar_flatten18_phi_fu_175_p4,
+        din1 => grp_fu_323_p1,
+        ce => grp_fu_323_ce,
+        dout => grp_fu_323_p2);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage14_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14))) then 
+                    ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage14_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14))) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage14_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14))) then 
+                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage14_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14))) then 
+                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage14_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14))) then 
+                    ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage14_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14))) then 
+                    ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
+            else
+                if ((((ap_const_boolean_0 = ap_block_pp0_stage14_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14)) or ((ap_const_boolean_0 = ap_block_pp0_stage9_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9)))) then 
+                    ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0_reg_183_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                i_0_reg_183 <= select_ln19_4_reg_661;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                i_0_reg_183 <= ap_const_lv31_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten18_reg_171_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                indvar_flatten18_reg_171 <= add_ln19_reg_604;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                indvar_flatten18_reg_171 <= ap_const_lv96_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_195_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage1_11001) and (icmp_ln19_reg_600_pp0_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then 
+                indvar_flatten_reg_195 <= select_ln21_1_reg_671;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                indvar_flatten_reg_195 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    j_0_reg_207_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                j_0_reg_207 <= select_ln21_reg_626;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                j_0_reg_207 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    k_0_reg_219_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage1_11001) and (icmp_ln19_reg_600_pp0_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then 
+                k_0_reg_219 <= k_reg_666;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                k_0_reg_219 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage1_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
+                add_ln19_1_reg_609 <= add_ln19_1_fu_328_p2;
+                add_ln21_1_reg_645 <= add_ln21_1_fu_462_p2;
+                icmp_ln21_1_reg_614 <= icmp_ln21_1_fu_338_p2;
+                in1_mem_addr_reg_632 <= sext_ln26_1_fu_437_p1(32 - 1 downto 0);
+                out_mem_addr_reg_638 <= sext_ln26_4_fu_452_p1(32 - 1 downto 0);
+                select_ln26_reg_620 <= select_ln26_fu_398_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) then
+                add_ln19_reg_604 <= add_ln19_fu_317_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage3_11001) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
+                add_ln26_3_reg_690 <= add_ln26_3_fu_523_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                add_ln26_reg_595 <= add_ln26_fu_306_p2;
+                icmp_ln19_reg_600 <= icmp_ln19_fu_312_p2;
+                icmp_ln19_reg_600_pp0_iter1_reg <= icmp_ln19_reg_600;
+                icmp_ln19_reg_600_pp0_iter2_reg <= icmp_ln19_reg_600_pp0_iter1_reg;
+                icmp_ln19_reg_600_pp0_iter3_reg <= icmp_ln19_reg_600_pp0_iter2_reg;
+                icmp_ln19_reg_600_pp0_iter4_reg <= icmp_ln19_reg_600_pp0_iter3_reg;
+                icmp_ln19_reg_600_pp0_iter5_reg <= icmp_ln19_reg_600_pp0_iter4_reg;
+                icmp_ln19_reg_600_pp0_iter6_reg <= icmp_ln19_reg_600_pp0_iter5_reg;
+                icmp_ln19_reg_600_pp0_iter7_reg <= icmp_ln19_reg_600_pp0_iter6_reg;
+                mul_ln26_reg_590 <= mul_ln26_fu_301_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
+                bound7_reg_580 <= bound7_fu_286_p2;
+                    cast5_reg_575(31 downto 0) <= cast5_fu_280_p1(31 downto 0);
+                icmp_ln21_reg_585 <= icmp_ln21_fu_292_p2;
+                    p_cast19_reg_565(29 downto 0) <= p_cast19_fu_274_p1(29 downto 0);
+                    p_cast20_reg_560(29 downto 0) <= p_cast20_fu_271_p1(29 downto 0);
+                    p_cast_reg_570(29 downto 0) <= p_cast_fu_277_p1(29 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                bound_reg_554 <= bound_fu_265_p2;
+                dim_read_reg_528 <= dim;
+                tmp_1_reg_544 <= in2(31 downto 2);
+                tmp_3_reg_549 <= in1(31 downto 2);
+                tmp_reg_539 <= out_r(31 downto 2);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage9_11001) and (icmp_ln19_reg_600_pp0_iter6_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9))) then
+                icmp_ln8_reg_676 <= icmp_ln8_fu_513_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage2_11001) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
+                in1_mem_addr_read_reg_680 <= in1_mem_RDATA;
+                out_mem_addr_read_reg_685 <= out_mem_RDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage1_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
+                in1_mem_addr_reg_632_pp0_iter1_reg <= in1_mem_addr_reg_632;
+                in1_mem_addr_reg_632_pp0_iter2_reg <= in1_mem_addr_reg_632_pp0_iter1_reg;
+                in1_mem_addr_reg_632_pp0_iter3_reg <= in1_mem_addr_reg_632_pp0_iter2_reg;
+                in1_mem_addr_reg_632_pp0_iter4_reg <= in1_mem_addr_reg_632_pp0_iter3_reg;
+                in1_mem_addr_reg_632_pp0_iter5_reg <= in1_mem_addr_reg_632_pp0_iter4_reg;
+                in1_mem_addr_reg_632_pp0_iter6_reg <= in1_mem_addr_reg_632_pp0_iter5_reg;
+                out_mem_addr_reg_638_pp0_iter1_reg <= out_mem_addr_reg_638;
+                out_mem_addr_reg_638_pp0_iter2_reg <= out_mem_addr_reg_638_pp0_iter1_reg;
+                out_mem_addr_reg_638_pp0_iter3_reg <= out_mem_addr_reg_638_pp0_iter2_reg;
+                out_mem_addr_reg_638_pp0_iter4_reg <= out_mem_addr_reg_638_pp0_iter3_reg;
+                out_mem_addr_reg_638_pp0_iter5_reg <= out_mem_addr_reg_638_pp0_iter4_reg;
+                out_mem_addr_reg_638_pp0_iter6_reg <= out_mem_addr_reg_638_pp0_iter5_reg;
+                out_mem_addr_reg_638_pp0_iter7_reg <= out_mem_addr_reg_638_pp0_iter6_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage10_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10))) then
+                in2_mem_addr_read_reg_656 <= in2_mem_RDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage10_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10))) then
+                in2_mem_addr_read_reg_656_pp0_iter1_reg <= in2_mem_addr_read_reg_656;
+                in2_mem_addr_read_reg_656_pp0_iter2_reg <= in2_mem_addr_read_reg_656_pp0_iter1_reg;
+                in2_mem_addr_read_reg_656_pp0_iter3_reg <= in2_mem_addr_read_reg_656_pp0_iter2_reg;
+                in2_mem_addr_read_reg_656_pp0_iter4_reg <= in2_mem_addr_read_reg_656_pp0_iter3_reg;
+                in2_mem_addr_read_reg_656_pp0_iter5_reg <= in2_mem_addr_read_reg_656_pp0_iter4_reg;
+                in2_mem_addr_read_reg_656_pp0_iter6_reg <= in2_mem_addr_read_reg_656_pp0_iter5_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage2_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
+                in2_mem_addr_reg_650 <= sext_ln26_3_fu_486_p1(32 - 1 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                k_reg_666 <= k_fu_502_p2;
+                select_ln21_1_reg_671 <= select_ln21_1_fu_507_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage14_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) then
+                select_ln19_4_reg_661 <= select_ln19_4_fu_496_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage1_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) then
+                select_ln21_reg_626 <= select_ln21_fu_424_p3;
+            end if;
+        end if;
+    end process;
+    p_cast20_reg_560(32 downto 30) <= "000";
+    p_cast19_reg_565(32 downto 30) <= "000";
+    p_cast_reg_570(32 downto 30) <= "000";
+    cast5_reg_575(95 downto 32) <= "0000000000000000000000000000000000000000000000000000000000000000";
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage9, icmp_ln19_fu_312_p2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_subdone, ap_block_pp0_stage14_subdone, ap_block_pp0_stage9_subdone, ap_block_pp0_stage1_subdone, ap_block_pp0_stage2_subdone, ap_block_pp0_stage3_subdone, ap_block_pp0_stage4_subdone, ap_block_pp0_stage5_subdone, ap_block_pp0_stage6_subdone, ap_block_pp0_stage7_subdone, ap_block_pp0_stage8_subdone, ap_block_pp0_stage10_subdone, ap_block_pp0_stage11_subdone, ap_block_pp0_stage12_subdone, ap_block_pp0_stage13_subdone)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (icmp_ln19_fu_312_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
+                elsif (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (icmp_ln19_fu_312_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state118;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_pp0_stage1 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage1_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
+                end if;
+            when ap_ST_fsm_pp0_stage2 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage2_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
+                end if;
+            when ap_ST_fsm_pp0_stage3 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage3_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
+                end if;
+            when ap_ST_fsm_pp0_stage4 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage4_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
+                end if;
+            when ap_ST_fsm_pp0_stage5 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage5_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
+                end if;
+            when ap_ST_fsm_pp0_stage6 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage6_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
+                end if;
+            when ap_ST_fsm_pp0_stage7 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage7_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
+                end if;
+            when ap_ST_fsm_pp0_stage8 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage8_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
+                end if;
+            when ap_ST_fsm_pp0_stage9 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage9_subdone) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) and (ap_const_boolean_0 = ap_block_pp0_stage9_subdone))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
+                elsif (((ap_const_boolean_0 = ap_block_pp0_stage9_subdone) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state118;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
+                end if;
+            when ap_ST_fsm_pp0_stage10 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage10_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
+                end if;
+            when ap_ST_fsm_pp0_stage11 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage11_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
+                end if;
+            when ap_ST_fsm_pp0_stage12 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage12_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
+                end if;
+            when ap_ST_fsm_pp0_stage13 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage13_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
+                end if;
+            when ap_ST_fsm_pp0_stage14 => 
+                if ((ap_const_boolean_0 = ap_block_pp0_stage14_subdone)) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
+                end if;
+            when ap_ST_fsm_state118 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXX";
+        end case;
+    end process;
+    add_ln19_1_fu_328_p2 <= std_logic_vector(unsigned(i_0_reg_183) + unsigned(ap_const_lv31_1));
+    add_ln19_fu_317_p2 <= std_logic_vector(unsigned(ap_phi_mux_indvar_flatten18_phi_fu_175_p4) + unsigned(ap_const_lv96_1));
+    add_ln21_1_fu_462_p2 <= std_logic_vector(unsigned(ap_phi_mux_indvar_flatten_phi_fu_199_p4) + unsigned(ap_const_lv64_1));
+    add_ln26_1_fu_406_p2 <= std_logic_vector(unsigned(j_fu_386_p2) + unsigned(select_ln19_1_fu_356_p3));
+    add_ln26_2_fu_472_p2 <= std_logic_vector(unsigned(mul_ln26_1_fu_468_p2) + unsigned(select_ln21_reg_626));
+    add_ln26_3_fu_523_p2 <= std_logic_vector(unsigned(out_mem_addr_read_reg_685) + unsigned(mul_ln26_2_fu_519_p2));
+    add_ln26_4_fu_432_p2 <= std_logic_vector(signed(sext_ln19_fu_363_p1) + signed(p_cast_reg_570));
+    add_ln26_5_fu_481_p2 <= std_logic_vector(signed(sext_ln26_2_fu_477_p1) + signed(p_cast19_reg_565));
+    add_ln26_6_fu_447_p2 <= std_logic_vector(signed(sext_ln26_fu_420_p1) + signed(p_cast20_reg_560));
+    add_ln26_fu_306_p2 <= std_logic_vector(unsigned(mul_ln26_fu_301_p2) + unsigned(ap_phi_mux_j_0_phi_fu_211_p4));
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
+    ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(3);
+    ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(12);
+    ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(13);
+    ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(14);
+    ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(15);
+    ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(16);
+    ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(4);
+    ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(5);
+    ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(6);
+    ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(7);
+    ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(8);
+    ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(9);
+    ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(10);
+    ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(11);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state118 <= ap_CS_fsm(17);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage0_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage10_11001_assign_proc : process(ap_enable_reg_pp0_iter6, icmp_ln19_reg_600, ap_enable_reg_pp0_iter0, in2_mem_RVALID, ap_block_state103_io)
+    begin
+                ap_block_pp0_stage10_11001 <= (((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state103_io) and (ap_enable_reg_pp0_iter6 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_pp0_stage10_subdone_assign_proc : process(ap_enable_reg_pp0_iter6, icmp_ln19_reg_600, ap_enable_reg_pp0_iter0, in2_mem_RVALID, ap_block_state103_io)
+    begin
+                ap_block_pp0_stage10_subdone <= (((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state103_io) and (ap_enable_reg_pp0_iter6 = ap_const_logic_1)));
+    end process;
+
+        ap_block_pp0_stage11_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage11_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage12_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage12_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage13_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage13_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage14_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage14_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage1_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage1_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage2_11001_assign_proc : process(ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, in1_mem_RVALID, out_mem_RVALID)
+    begin
+                ap_block_pp0_stage2_11001 <= ((ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (((out_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0)) or ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0))));
+    end process;
+
+
+    ap_block_pp0_stage2_subdone_assign_proc : process(ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, in1_mem_RVALID, out_mem_RVALID)
+    begin
+                ap_block_pp0_stage2_subdone <= ((ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (((out_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0)) or ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0))));
+    end process;
+
+        ap_block_pp0_stage3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage3_11001_assign_proc : process(ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter0, ap_block_state6_io, ap_block_state111_io)
+    begin
+                ap_block_pp0_stage3_11001 <= (((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state111_io) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_pp0_stage3_subdone_assign_proc : process(ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter0, ap_block_state6_io, ap_block_state111_io)
+    begin
+                ap_block_pp0_stage3_subdone <= (((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state111_io) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1)));
+    end process;
+
+        ap_block_pp0_stage4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage4_01001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage4_11001_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_state112_io)
+    begin
+                ap_block_pp0_stage4_11001 <= ((ap_const_boolean_1 = ap_block_state112_io) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage4_subdone_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_state112_io)
+    begin
+                ap_block_pp0_stage4_subdone <= ((ap_const_boolean_1 = ap_block_state112_io) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp0_stage5_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage5_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage6_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage6_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage7_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage7_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage8_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage8_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp0_stage9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage9_11001_assign_proc : process(ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, out_mem_BVALID)
+    begin
+                ap_block_pp0_stage9_11001 <= ((out_mem_BVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage9_subdone_assign_proc : process(ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, out_mem_BVALID)
+    begin
+                ap_block_pp0_stage9_subdone <= ((out_mem_BVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1));
+    end process;
+
+        ap_block_state100_pp0_stage7_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state101_pp0_stage8_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state102_pp0_stage9_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state103_io_assign_proc : process(icmp_ln8_reg_676, icmp_ln19_reg_600_pp0_iter6_reg, in1_mem_ARREADY, out_mem_ARREADY)
+    begin
+                ap_block_state103_io <= (((out_mem_ARREADY = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter6_reg = ap_const_lv1_0)) or ((in1_mem_ARREADY = ap_const_logic_0) and (icmp_ln8_reg_676 = ap_const_lv1_1)));
+    end process;
+
+        ap_block_state103_pp0_stage10_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state104_pp0_stage11_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state105_pp0_stage12_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state106_pp0_stage13_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state107_pp0_stage14_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state108_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state109_pp0_stage1_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state10_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state110_pp0_stage2_iter7_assign_proc : process(icmp_ln19_reg_600_pp0_iter7_reg, in1_mem_RVALID, out_mem_RVALID)
+    begin
+                ap_block_state110_pp0_stage2_iter7 <= (((out_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0)) or ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0)));
+    end process;
+
+
+    ap_block_state111_io_assign_proc : process(icmp_ln19_reg_600_pp0_iter7_reg, out_mem_AWREADY)
+    begin
+                ap_block_state111_io <= ((out_mem_AWREADY = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state111_pp0_stage3_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state112_io_assign_proc : process(icmp_ln19_reg_600_pp0_iter7_reg, out_mem_WREADY)
+    begin
+                ap_block_state112_io <= ((out_mem_WREADY = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state112_pp0_stage4_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state113_pp0_stage5_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state114_pp0_stage6_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state115_pp0_stage7_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state116_pp0_stage8_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state117_pp0_stage9_iter7_assign_proc : process(icmp_ln19_reg_600_pp0_iter7_reg, out_mem_BVALID)
+    begin
+                ap_block_state117_pp0_stage9_iter7 <= ((out_mem_BVALID = ap_const_logic_0) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state11_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state12_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state13_pp0_stage10_iter0_assign_proc : process(icmp_ln19_reg_600, in2_mem_RVALID)
+    begin
+                ap_block_state13_pp0_stage10_iter0 <= ((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln19_reg_600 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state14_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state15_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state16_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state17_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state18_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state19_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state20_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state21_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state22_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state23_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state24_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state25_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state26_pp0_stage8_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state27_pp0_stage9_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state28_pp0_stage10_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state29_pp0_stage11_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state30_pp0_stage12_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state31_pp0_stage13_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state32_pp0_stage14_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state33_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state34_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state35_pp0_stage2_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state36_pp0_stage3_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state37_pp0_stage4_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state38_pp0_stage5_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state39_pp0_stage6_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state40_pp0_stage7_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state41_pp0_stage8_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state42_pp0_stage9_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state43_pp0_stage10_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state44_pp0_stage11_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state45_pp0_stage12_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state46_pp0_stage13_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state47_pp0_stage14_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state48_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state49_pp0_stage1_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state4_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state50_pp0_stage2_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state51_pp0_stage3_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state52_pp0_stage4_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state53_pp0_stage5_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state54_pp0_stage6_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state55_pp0_stage7_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state56_pp0_stage8_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state57_pp0_stage9_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state58_pp0_stage10_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state59_pp0_stage11_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state5_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state60_pp0_stage12_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state61_pp0_stage13_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state62_pp0_stage14_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state63_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state64_pp0_stage1_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state65_pp0_stage2_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state66_pp0_stage3_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state67_pp0_stage4_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state68_pp0_stage5_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state69_pp0_stage6_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state6_io_assign_proc : process(icmp_ln19_reg_600, in2_mem_ARREADY)
+    begin
+                ap_block_state6_io <= ((in2_mem_ARREADY = ap_const_logic_0) and (icmp_ln19_reg_600 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state6_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state70_pp0_stage7_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state71_pp0_stage8_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state72_pp0_stage9_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state73_pp0_stage10_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state74_pp0_stage11_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state75_pp0_stage12_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state76_pp0_stage13_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state77_pp0_stage14_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state78_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state79_pp0_stage1_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state7_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state80_pp0_stage2_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state81_pp0_stage3_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state82_pp0_stage4_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state83_pp0_stage5_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state84_pp0_stage6_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state85_pp0_stage7_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state86_pp0_stage8_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state87_pp0_stage9_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state88_pp0_stage10_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state89_pp0_stage11_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state8_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state90_pp0_stage12_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state91_pp0_stage13_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state92_pp0_stage14_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state93_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state94_pp0_stage1_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state95_pp0_stage2_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state96_pp0_stage3_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state97_pp0_stage4_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state98_pp0_stage5_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state99_pp0_stage6_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state9_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state3_assign_proc : process(icmp_ln19_fu_312_p2)
+    begin
+        if ((icmp_ln19_fu_312_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_CS_fsm_state118)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state118)) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5)
+    begin
+        if (((ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_i_0_phi_fu_187_p4_assign_proc : process(icmp_ln19_reg_600, ap_CS_fsm_pp0_stage0, i_0_reg_183, select_ln19_4_reg_661, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            ap_phi_mux_i_0_phi_fu_187_p4 <= select_ln19_4_reg_661;
+        else 
+            ap_phi_mux_i_0_phi_fu_187_p4 <= i_0_reg_183;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_indvar_flatten18_phi_fu_175_p4_assign_proc : process(icmp_ln19_reg_600, indvar_flatten18_reg_171, ap_CS_fsm_pp0_stage0, add_ln19_reg_604, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            ap_phi_mux_indvar_flatten18_phi_fu_175_p4 <= add_ln19_reg_604;
+        else 
+            ap_phi_mux_indvar_flatten18_phi_fu_175_p4 <= indvar_flatten18_reg_171;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_indvar_flatten_phi_fu_199_p4_assign_proc : process(indvar_flatten_reg_195, icmp_ln19_reg_600_pp0_iter1_reg, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter1, select_ln21_1_reg_671, ap_block_pp0_stage1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage1) and (icmp_ln19_reg_600_pp0_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then 
+            ap_phi_mux_indvar_flatten_phi_fu_199_p4 <= select_ln21_1_reg_671;
+        else 
+            ap_phi_mux_indvar_flatten_phi_fu_199_p4 <= indvar_flatten_reg_195;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_j_0_phi_fu_211_p4_assign_proc : process(icmp_ln19_reg_600, ap_CS_fsm_pp0_stage0, j_0_reg_207, select_ln21_reg_626, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            ap_phi_mux_j_0_phi_fu_211_p4 <= select_ln21_reg_626;
+        else 
+            ap_phi_mux_j_0_phi_fu_211_p4 <= j_0_reg_207;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_k_0_phi_fu_223_p4_assign_proc : process(k_0_reg_219, icmp_ln19_reg_600_pp0_iter1_reg, ap_CS_fsm_pp0_stage1, k_reg_666, ap_enable_reg_pp0_iter1, ap_block_pp0_stage1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage1) and (icmp_ln19_reg_600_pp0_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then 
+            ap_phi_mux_k_0_phi_fu_223_p4 <= k_reg_666;
+        else 
+            ap_phi_mux_k_0_phi_fu_223_p4 <= k_0_reg_219;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state118)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state118)) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    bound7_fu_286_p0 <= bound7_fu_286_p00(64 - 1 downto 0);
+    bound7_fu_286_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_reg_554),96));
+    bound7_fu_286_p1 <= bound7_fu_286_p10(32 - 1 downto 0);
+    bound7_fu_286_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(dim_read_reg_528),96));
+    bound7_fu_286_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound7_fu_286_p0) * unsigned(bound7_fu_286_p1), 96));
+    bound_fu_265_p0 <= cast_fu_261_p1(32 - 1 downto 0);
+    bound_fu_265_p1 <= cast_fu_261_p1(32 - 1 downto 0);
+    bound_fu_265_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_265_p0) * unsigned(bound_fu_265_p1), 64));
+    cast5_fu_280_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(dim_read_reg_528),96));
+    cast_fu_261_p0 <= dim;
+    cast_fu_261_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(cast_fu_261_p0),64));
+
+    grp_fu_323_ce_assign_proc : process(ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_block_pp0_stage2_11001, ap_block_pp0_stage10_11001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_11001, ap_block_pp0_stage9_11001, ap_block_pp0_stage3_11001, ap_block_pp0_stage4_11001, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage7_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage8_11001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage11_11001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage12_11001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage13_11001, ap_CS_fsm_pp0_stage13)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage14_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14)) or ((ap_const_boolean_0 = ap_block_pp0_stage1_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage9_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9)) or ((ap_const_boolean_0 = ap_block_pp0_stage4_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_const_boolean_0 = ap_block_pp0_stage3_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_const_boolean_0 = ap_block_pp0_stage2_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_const_boolean_0 = ap_block_pp0_stage10_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_const_boolean_0 = ap_block_pp0_stage13_11001)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_boolean_0 = ap_block_pp0_stage12_11001)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_boolean_0 = ap_block_pp0_stage11_11001)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_boolean_0 = ap_block_pp0_stage8_11001)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_boolean_0 = ap_block_pp0_stage7_11001)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_boolean_0 = ap_block_pp0_stage6_11001)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_boolean_0 = ap_block_pp0_stage5_11001)))) then 
+            grp_fu_323_ce <= ap_const_logic_1;
+        else 
+            grp_fu_323_ce <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    grp_fu_323_p1 <= cast5_reg_575(32 - 1 downto 0);
+    icmp_ln19_fu_312_p2 <= "1" when (ap_phi_mux_indvar_flatten18_phi_fu_175_p4 = bound7_reg_580) else "0";
+    icmp_ln21_1_fu_338_p2 <= "1" when (ap_phi_mux_indvar_flatten_phi_fu_199_p4 = bound_reg_554) else "0";
+    icmp_ln21_fu_292_p2 <= "1" when (dim_read_reg_528 = ap_const_lv32_0) else "0";
+    icmp_ln23_fu_374_p2 <= "1" when (ap_phi_mux_k_0_phi_fu_223_p4 = dim_read_reg_528) else "0";
+    icmp_ln8_fu_513_p2 <= "1" when (grp_fu_323_p2 = ap_const_lv96_0) else "0";
+
+    in1_mem_ARVALID_assign_proc : process(ap_CS_fsm_pp0_stage10, ap_enable_reg_pp0_iter6, icmp_ln8_reg_676, ap_block_pp0_stage10_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage10_11001) and (icmp_ln8_reg_676 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter6 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10))) then 
+            in1_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in1_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, ap_block_pp0_stage2_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage2_11001) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then 
+            in1_mem_RREADY <= ap_const_logic_1;
+        else 
+            in1_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_AR_assign_proc : process(m_axi_in1_mem_ARREADY, ap_CS_fsm_pp0_stage10, ap_enable_reg_pp0_iter6, ap_block_pp0_stage10, icmp_ln8_reg_676)
+    begin
+        if (((icmp_ln8_reg_676 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage10) and (ap_enable_reg_pp0_iter6 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10))) then 
+            in1_mem_blk_n_AR <= m_axi_in1_mem_ARREADY;
+        else 
+            in1_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_R_assign_proc : process(m_axi_in1_mem_RVALID, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter7, ap_block_pp0_stage2, icmp_ln19_reg_600_pp0_iter7_reg)
+    begin
+        if (((icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage2) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then 
+            in1_mem_blk_n_R <= m_axi_in1_mem_RVALID;
+        else 
+            in1_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_ARVALID_assign_proc : process(icmp_ln19_reg_600, ap_CS_fsm_pp0_stage3, ap_enable_reg_pp0_iter0, ap_block_pp0_stage3_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage3_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then 
+            in2_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in2_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage10, icmp_ln19_reg_600, ap_enable_reg_pp0_iter0, ap_block_pp0_stage10_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage10_11001) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10))) then 
+            in2_mem_RREADY <= ap_const_logic_1;
+        else 
+            in2_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_AR_assign_proc : process(m_axi_in2_mem_ARREADY, icmp_ln19_reg_600, ap_CS_fsm_pp0_stage3, ap_enable_reg_pp0_iter0, ap_block_pp0_stage3)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage3) and (icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then 
+            in2_mem_blk_n_AR <= m_axi_in2_mem_ARREADY;
+        else 
+            in2_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_R_assign_proc : process(m_axi_in2_mem_RVALID, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10, icmp_ln19_reg_600, ap_enable_reg_pp0_iter0)
+    begin
+        if (((icmp_ln19_reg_600 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage10) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10))) then 
+            in2_mem_blk_n_R <= m_axi_in2_mem_RVALID;
+        else 
+            in2_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    j_fu_386_p2 <= std_logic_vector(unsigned(select_ln19_fu_343_p3) + unsigned(ap_const_lv32_1));
+    k_fu_502_p2 <= std_logic_vector(signed(select_ln26_reg_620) + signed(ap_const_lv32_1));
+    mul_ln26_1_fu_468_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed('0' &dim_read_reg_528) * signed(select_ln26_reg_620))), 32));
+    mul_ln26_2_fu_519_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_mem_addr_read_reg_656_pp0_iter6_reg) * signed(in1_mem_addr_read_reg_680))), 32));
+    mul_ln26_3_fu_351_p1 <= mul_ln26_3_fu_351_p10(31 - 1 downto 0);
+    mul_ln26_3_fu_351_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln19_1_fu_328_p2),32));
+    mul_ln26_3_fu_351_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(dim_read_reg_528) * unsigned(mul_ln26_3_fu_351_p1), 32));
+    mul_ln26_fu_301_p1 <= mul_ln26_fu_301_p10(31 - 1 downto 0);
+    mul_ln26_fu_301_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_phi_mux_i_0_phi_fu_187_p4),32));
+    mul_ln26_fu_301_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(dim_read_reg_528) * unsigned(mul_ln26_fu_301_p1), 32));
+    or_ln26_fu_392_p2 <= (select_ln19_3_fu_379_p3 or icmp_ln21_1_fu_338_p2);
+
+    out_mem_ARVALID_assign_proc : process(ap_CS_fsm_pp0_stage10, ap_enable_reg_pp0_iter6, icmp_ln19_reg_600_pp0_iter6_reg, ap_block_pp0_stage10_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage10_11001) and (icmp_ln19_reg_600_pp0_iter6_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter6 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10))) then 
+            out_mem_ARVALID <= ap_const_logic_1;
+        else 
+            out_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_AWVALID_assign_proc : process(ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage3_11001) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) then 
+            out_mem_AWVALID <= ap_const_logic_1;
+        else 
+            out_mem_AWVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_BREADY_assign_proc : process(ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage9_11001) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) then 
+            out_mem_BREADY <= ap_const_logic_1;
+        else 
+            out_mem_BREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, ap_block_pp0_stage2_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage2_11001) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then 
+            out_mem_RREADY <= ap_const_logic_1;
+        else 
+            out_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_WVALID_assign_proc : process(ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage4_11001) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) then 
+            out_mem_WVALID <= ap_const_logic_1;
+        else 
+            out_mem_WVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AR_assign_proc : process(m_axi_out_mem_ARREADY, ap_CS_fsm_pp0_stage10, ap_enable_reg_pp0_iter6, ap_block_pp0_stage10, icmp_ln19_reg_600_pp0_iter6_reg)
+    begin
+        if (((icmp_ln19_reg_600_pp0_iter6_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage10) and (ap_enable_reg_pp0_iter6 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10))) then 
+            out_mem_blk_n_AR <= m_axi_out_mem_ARREADY;
+        else 
+            out_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AW_assign_proc : process(m_axi_out_mem_AWREADY, ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage3) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) then 
+            out_mem_blk_n_AW <= m_axi_out_mem_AWREADY;
+        else 
+            out_mem_blk_n_AW <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_B_assign_proc : process(m_axi_out_mem_BVALID, ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage9) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) then 
+            out_mem_blk_n_B <= m_axi_out_mem_BVALID;
+        else 
+            out_mem_blk_n_B <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_R_assign_proc : process(m_axi_out_mem_RVALID, ap_CS_fsm_pp0_stage2, ap_enable_reg_pp0_iter7, ap_block_pp0_stage2, icmp_ln19_reg_600_pp0_iter7_reg)
+    begin
+        if (((icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage2) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then 
+            out_mem_blk_n_R <= m_axi_out_mem_RVALID;
+        else 
+            out_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_W_assign_proc : process(m_axi_out_mem_WREADY, ap_enable_reg_pp0_iter7, icmp_ln19_reg_600_pp0_iter7_reg, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage4) and (icmp_ln19_reg_600_pp0_iter7_reg = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) then 
+            out_mem_blk_n_W <= m_axi_out_mem_WREADY;
+        else 
+            out_mem_blk_n_W <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    p_cast19_fu_274_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_reg_544),33));
+    p_cast20_fu_271_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_reg_539),33));
+    p_cast_fu_277_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_3_reg_549),33));
+    select_ln19_1_fu_356_p3 <= 
+        mul_ln26_3_fu_351_p2 when (icmp_ln21_1_fu_338_p2(0) = '1') else 
+        mul_ln26_reg_590;
+    select_ln19_2_fu_367_p3 <= 
+        mul_ln26_3_fu_351_p2 when (icmp_ln21_1_fu_338_p2(0) = '1') else 
+        add_ln26_reg_595;
+    select_ln19_3_fu_379_p3 <= 
+        icmp_ln21_reg_585 when (icmp_ln21_1_fu_338_p2(0) = '1') else 
+        icmp_ln23_fu_374_p2;
+    select_ln19_4_fu_496_p3 <= 
+        add_ln19_1_reg_609 when (icmp_ln21_1_reg_614(0) = '1') else 
+        i_0_reg_183;
+    select_ln19_fu_343_p3 <= 
+        ap_const_lv32_0 when (icmp_ln21_1_fu_338_p2(0) = '1') else 
+        j_0_reg_207;
+    select_ln21_1_fu_507_p3 <= 
+        ap_const_lv64_1 when (icmp_ln21_1_reg_614(0) = '1') else 
+        add_ln21_1_reg_645;
+    select_ln21_fu_424_p3 <= 
+        j_fu_386_p2 when (select_ln19_3_fu_379_p3(0) = '1') else 
+        select_ln19_fu_343_p3;
+    select_ln26_1_fu_412_p3 <= 
+        add_ln26_1_fu_406_p2 when (select_ln19_3_fu_379_p3(0) = '1') else 
+        select_ln19_2_fu_367_p3;
+    select_ln26_fu_398_p3 <= 
+        ap_const_lv32_0 when (or_ln26_fu_392_p2(0) = '1') else 
+        ap_phi_mux_k_0_phi_fu_223_p4;
+        sext_ln19_fu_363_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(select_ln19_1_fu_356_p3),33));
+
+        sext_ln26_1_fu_437_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln26_4_fu_432_p2),64));
+
+        sext_ln26_2_fu_477_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln26_2_fu_472_p2),33));
+
+        sext_ln26_3_fu_486_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln26_5_fu_481_p2),64));
+
+        sext_ln26_4_fu_452_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln26_6_fu_447_p2),64));
+
+        sext_ln26_fu_420_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(select_ln26_1_fu_412_p3),33));
+
+end behav;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_in1_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_in1_mem_m_axi.vhd
new file mode 100755
index 0000000..5d4f5b4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_in1_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi;
+
+architecture behave of mmult_in1_mem_m_axi is
+    component mmult_in1_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_write;
+
+    component mmult_in1_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_read;
+
+    component mmult_in1_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in1_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in1_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in1_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in1_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in1_mem_m_axi_fifo;
+
+architecture behave of mmult_in1_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in1_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in1_mem_m_axi_decoder;
+
+architecture behav of mmult_in1_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in1_mem_m_axi_throttl;
+
+architecture behav of mmult_in1_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in1_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in1_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_read;
+
+architecture behave of mmult_in1_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_write;
+
+architecture behave of mmult_in1_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in1_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in1_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_in2_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_in2_mem_m_axi.vhd
new file mode 100755
index 0000000..84687e2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_in2_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi;
+
+architecture behave of mmult_in2_mem_m_axi is
+    component mmult_in2_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_write;
+
+    component mmult_in2_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_read;
+
+    component mmult_in2_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in2_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in2_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in2_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in2_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in2_mem_m_axi_fifo;
+
+architecture behave of mmult_in2_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in2_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in2_mem_m_axi_decoder;
+
+architecture behav of mmult_in2_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in2_mem_m_axi_throttl;
+
+architecture behav of mmult_in2_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in2_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in2_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_read;
+
+architecture behave of mmult_in2_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_write;
+
+architecture behave of mmult_in2_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in2_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in2_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_out_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_out_mem_m_axi.vhd
new file mode 100755
index 0000000..f2bd717
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_out_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi;
+
+architecture behave of mmult_out_mem_m_axi is
+    component mmult_out_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_write;
+
+    component mmult_out_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_read;
+
+    component mmult_out_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_out_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_out_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_out_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi_reg_slice;
+
+architecture behave of mmult_out_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_out_mem_m_axi_fifo;
+
+architecture behave of mmult_out_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_out_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_out_mem_m_axi_decoder;
+
+architecture behav of mmult_out_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_out_mem_m_axi_throttl;
+
+architecture behav of mmult_out_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_out_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_out_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_read;
+
+architecture behave of mmult_out_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_write;
+
+architecture behave of mmult_out_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_out_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_out_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_params_s_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_params_s_axi.vhd
new file mode 100755
index 0000000..1f9adde
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_params_s_axi.vhd
@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_urem_96ns_3bkb.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_urem_96ns_3bkb.vhd
new file mode 100755
index 0000000..f0a00fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_urem_96ns_3bkb.vhd
@@ -0,0 +1,219 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mmult_urem_96ns_3bkb_div_u is
+    generic (
+        in0_WIDTH   : INTEGER :=32;
+        in1_WIDTH   : INTEGER :=32;
+        out_WIDTH   : INTEGER :=32);
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        ce          : in  STD_LOGIC;
+        dividend    : in  STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+        divisor     : in  STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+        quot        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+        remd        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
+
+    function max (left, right : INTEGER) return INTEGER is
+    begin
+        if left > right then return left;
+        else return right;
+        end if;
+    end max;
+
+end entity;
+
+architecture rtl of mmult_urem_96ns_3bkb_div_u is
+    constant cal_WIDTH      : INTEGER := max(in0_WIDTH, in1_WIDTH);
+    type  in0_vector  is array(INTEGER range <>) of UNSIGNED(in0_WIDTH-1 downto 0);
+    type  in1_vector  is array(INTEGER range <>) of UNSIGNED(in1_WIDTH-1 downto 0);
+    type  cal_vector  is array(INTEGER range <>) of UNSIGNED(cal_WIDTH downto 0);
+
+    signal dividend_tmp     : in0_vector(0 to in0_WIDTH);
+    signal divisor_tmp      : in1_vector(0 to in0_WIDTH);
+    signal remd_tmp         : in0_vector(0 to in0_WIDTH);
+    signal comb_tmp         : in0_vector(0 to in0_WIDTH-1);
+    signal cal_tmp          : cal_vector(0 to in0_WIDTH-1);
+begin
+    quot   <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp(in0_WIDTH), out_WIDTH));
+    remd   <= STD_LOGIC_VECTOR(RESIZE(remd_tmp(in0_WIDTH), out_WIDTH));
+
+    tran_tmp_proc : process (clk)
+    begin
+        if (clk'event and clk='1') then
+            if (ce = '1') then
+                dividend_tmp(0) <= UNSIGNED(dividend);
+                divisor_tmp(0)  <= UNSIGNED(divisor);
+                remd_tmp(0) <= (others => '0');
+            end if;
+        end if;
+    end process tran_tmp_proc;
+
+    run_proc: for i in 0 to in0_WIDTH-1 generate
+    begin
+        comb_tmp(i) <= remd_tmp(i)(in0_WIDTH-2 downto 0) & dividend_tmp(i)(in0_WIDTH-1);
+        cal_tmp(i)  <= ('0' & comb_tmp(i)) - ('0' & divisor_tmp(i));
+
+        process (clk)
+        begin
+            if (clk'event and clk='1') then
+                if (ce = '1') then
+                    dividend_tmp(i+1) <= dividend_tmp(i)(in0_WIDTH-2 downto 0) & (not cal_tmp(i)(cal_WIDTH));
+                    divisor_tmp(i+1)  <= divisor_tmp(i);
+                    if cal_tmp(i)(cal_WIDTH) = '1' then
+                        remd_tmp(i+1) <= comb_tmp(i);
+                    else
+                        remd_tmp(i+1) <= cal_tmp(i)(in0_WIDTH-1 downto 0);
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate run_proc;
+
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mmult_urem_96ns_3bkb_div is
+    generic (
+        in0_WIDTH   : INTEGER :=32;
+        in1_WIDTH   : INTEGER :=32;
+        out_WIDTH   : INTEGER :=32);
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        ce          : in  STD_LOGIC;
+        dividend    : in  STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+        divisor     : in  STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+        quot        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+        remd        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
+end entity;
+
+architecture rtl of mmult_urem_96ns_3bkb_div is
+    component mmult_urem_96ns_3bkb_div_u is
+        generic (
+            in0_WIDTH   : INTEGER :=32;
+            in1_WIDTH   : INTEGER :=32;
+            out_WIDTH   : INTEGER :=32);
+        port (
+            reset       : in  STD_LOGIC;
+            clk         : in  STD_LOGIC;
+            ce          : in  STD_LOGIC;
+            dividend    : in  STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+            divisor     : in  STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+            quot        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+            remd        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
+    end component;
+
+    signal dividend0  : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+    signal divisor0   : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+    signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+    signal divisor_u  : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+    signal quot_u     : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+    signal remd_u     : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+begin
+    mmult_urem_96ns_3bkb_div_u_0 : mmult_urem_96ns_3bkb_div_u
+        generic map(
+            in0_WIDTH   => in0_WIDTH,
+            in1_WIDTH   => in1_WIDTH,
+            out_WIDTH   => out_WIDTH)
+        port map(
+            clk         => clk,
+            reset       => reset,
+            ce          => ce,
+            dividend    => dividend_u,
+            divisor     => divisor_u,
+            quot        => quot_u,
+            remd        => remd_u);
+
+    dividend_u  <= dividend0;
+    divisor_u   <= divisor0;
+
+process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            dividend0 <= dividend;
+            divisor0 <= divisor;
+        end if;
+    end if;
+end process;
+
+process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            quot <= quot_u;
+            remd <= remd_u;
+        end if;
+    end if;
+end process;
+
+end architecture;
+
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_urem_96ns_3bkb is
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        ce : IN STD_LOGIC;
+        din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
+        din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
+        dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_urem_96ns_3bkb is
+    component mmult_urem_96ns_3bkb_div is
+        generic (
+            in0_WIDTH : INTEGER;
+            in1_WIDTH : INTEGER;
+            out_WIDTH : INTEGER);
+        port (
+            dividend : IN STD_LOGIC_VECTOR;
+            divisor : IN STD_LOGIC_VECTOR;
+            remd : OUT STD_LOGIC_VECTOR;
+            quot : OUT STD_LOGIC_VECTOR;
+            clk : IN STD_LOGIC;
+            ce : IN STD_LOGIC;
+            reset : IN STD_LOGIC);
+    end component;
+
+    signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
+    signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
+
+
+begin
+    mmult_urem_96ns_3bkb_div_U :  component mmult_urem_96ns_3bkb_div
+    generic map (
+        in0_WIDTH => din0_WIDTH,
+        in1_WIDTH => din1_WIDTH,
+        out_WIDTH => dout_WIDTH)
+    port map (
+        dividend => din0,
+        divisor => din1,
+        remd => dout,
+        quot => sig_quot,
+        clk => clk,
+        ce => ce,
+        reset => reset);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/misc/logo.png b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/misc/logo.png
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diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/xgui/mmult_v2_0.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/xgui/mmult_v2_0.tcl
new file mode 100755
index 0000000..0276fbf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_3/xgui/mmult_v2_0.tcl
@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/component.xml b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/component.xml
new file mode 100755
index 0000000..a898174
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/component.xml
@@ -0,0 +1,5560 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>hls</spirit:library>
+  <spirit:name>mmult</spirit:name>
+  <spirit:version>3.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_params"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.ADDR_WIDTH">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi_params:m_axi_in1_mem:m_axi_in2_mem:m_axi_out_mem</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interrupt</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in1_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in1_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in2_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in2_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_out_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_out_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in1_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in2_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_out_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_BASE_PARAM">C_S_AXI_PARAMS_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_HIGH_PARAM">C_S_AXI_PARAMS_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>CTRL</spirit:name>
+          <spirit:displayName>CTRL</spirit:displayName>
+          <spirit:description>Control signals</spirit:description>
+          <spirit:addressOffset>0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>AP_START</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_start&apos;.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_DONE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_done&apos;.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_IDLE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_idle&apos;.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_READY</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_ready&apos;.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_1</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">3</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AUTO_RESTART</spirit:name>
+            <spirit:description>Control signal Register for &apos;auto_restart&apos;.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_2</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">24</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GIER</spirit:name>
+          <spirit:displayName>GIER</spirit:displayName>
+          <spirit:description>Global Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>4</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Enable</spirit:name>
+            <spirit:description>Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">31</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_IER</spirit:name>
+          <spirit:displayName>IP_IER</spirit:displayName>
+          <spirit:description>IP Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>8</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 0 (ap_done) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 1 (ap_ready) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_ISR</spirit:name>
+          <spirit:displayName>IP_ISR</spirit:displayName>
+          <spirit:description>IP Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>12</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_ST</spirit:name>
+            <spirit:description>Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 input interrupt, 1 = Channel 0 input interrup</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_ST</spirit:name>
+            <spirit:description>Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 input interrupt, 1 = Channel 1 input interrup</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:name>in1</spirit:name>
+          <spirit:displayName>in1</spirit:displayName>
+          <spirit:description>Data signal of in1</spirit:description>
+          <spirit:addressOffset>16</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+          <spirit:field>
+            <spirit:name>in1</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of in1</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:displayName>in2</spirit:displayName>
+          <spirit:description>Data signal of in2</spirit:description>
+          <spirit:addressOffset>24</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+            <spirit:name>in2</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of in2</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:description>Data signal of out_r</spirit:description>
+          <spirit:addressOffset>32</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
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+            <spirit:value spirit:format="long">0</spirit:value>
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+            <spirit:name>out_r</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of out_r</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+            <spirit:description>Bit 31 to 0 Data signal of dim</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE" spirit:order="12" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE" spirit:order="13" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" spirit:order="14" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH" spirit:order="15" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="16" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" spirit:order="17" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH" spirit:order="18" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH" spirit:order="19" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH" spirit:order="20" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH" spirit:order="21" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH" spirit:order="22" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE" spirit:order="23" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE" spirit:order="24" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE" spirit:order="25" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" spirit:order="26" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH" spirit:order="27" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="28" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" spirit:order="29" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH" spirit:order="30" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH" spirit:order="31" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH" spirit:order="32" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH" spirit:order="33" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH" spirit:order="34" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE" spirit:order="35" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE" spirit:order="36" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE" spirit:order="37" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mmult_v3_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>clk_period</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.clk_period" spirit:order="38">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>machine</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.machine" spirit:order="39">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>combinational</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.combinational" spirit:order="40">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>latency</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.latency" spirit:order="41">536604</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>II</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.II" spirit:order="42">x</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/VIVADO_HLS_IP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>Mmult</xilinx:displayName>
+      <xilinx:definitionSource>HLS</xilinx:definitionSource>
+      <xilinx:coreRevision>2105141703</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2021-05-14T15:03:24Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b5dd57e8"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="c6fd4807"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5ce530f0"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="31ba212c"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="7681d788"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c9a673dd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="ea1a73e9"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/constraints/mmult_ooc.xdc b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/constraints/mmult_ooc.xdc
new file mode 100755
index 0000000..2ed5eee
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/constraints/mmult_ooc.xdc
@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/doc/ReleaseNotes.txt b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/doc/ReleaseNotes.txt
new file mode 100755
index 0000000..48cc01b
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/doc/ReleaseNotes.txt
@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/data/mmult.mdd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/data/mmult.mdd
new file mode 100755
index 0000000..742dc85
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/data/mmult.mdd
@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v3_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 3.0;
+
+END driver
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/data/mmult.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/data/mmult.tcl
new file mode 100755
index 0000000..0de7a9c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/data/mmult.tcl
@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/Makefile b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/Makefile
new file mode 100755
index 0000000..7f76086
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/Makefile
@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult.c
new file mode 100755
index 0000000..fb9a1fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult.c
@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult.h
new file mode 100755
index 0000000..4983669
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult.h
@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_hw.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_hw.h
new file mode 100755
index 0000000..3a0a2a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_hw.h
@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_linux.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_linux.c
new file mode 100755
index 0000000..c8dbb33
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_linux.c
@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_sinit.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_sinit.c
new file mode 100755
index 0000000..f099590
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_sinit.c
@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult.v
new file mode 100755
index 0000000..8784b8f
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult.v
@@ -0,0 +1,1958 @@
+// ==============================================================
+// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+// Version: 2020.1
+// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+// 
+// ===========================================================
+
+`timescale 1 ns / 1 ps 
+
+(* CORE_GENERATION_INFO="mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=536604,HLS_SYN_TPT=none,HLS_SYN_MEM=30,HLS_SYN_DSP=8,HLS_SYN_FF=2601,HLS_SYN_LUT=3166,HLS_VERSION=2020_1}" *)
+
+module mmult (
+        ap_clk,
+        ap_rst_n,
+        m_axi_in1_mem_AWVALID,
+        m_axi_in1_mem_AWREADY,
+        m_axi_in1_mem_AWADDR,
+        m_axi_in1_mem_AWID,
+        m_axi_in1_mem_AWLEN,
+        m_axi_in1_mem_AWSIZE,
+        m_axi_in1_mem_AWBURST,
+        m_axi_in1_mem_AWLOCK,
+        m_axi_in1_mem_AWCACHE,
+        m_axi_in1_mem_AWPROT,
+        m_axi_in1_mem_AWQOS,
+        m_axi_in1_mem_AWREGION,
+        m_axi_in1_mem_AWUSER,
+        m_axi_in1_mem_WVALID,
+        m_axi_in1_mem_WREADY,
+        m_axi_in1_mem_WDATA,
+        m_axi_in1_mem_WSTRB,
+        m_axi_in1_mem_WLAST,
+        m_axi_in1_mem_WID,
+        m_axi_in1_mem_WUSER,
+        m_axi_in1_mem_ARVALID,
+        m_axi_in1_mem_ARREADY,
+        m_axi_in1_mem_ARADDR,
+        m_axi_in1_mem_ARID,
+        m_axi_in1_mem_ARLEN,
+        m_axi_in1_mem_ARSIZE,
+        m_axi_in1_mem_ARBURST,
+        m_axi_in1_mem_ARLOCK,
+        m_axi_in1_mem_ARCACHE,
+        m_axi_in1_mem_ARPROT,
+        m_axi_in1_mem_ARQOS,
+        m_axi_in1_mem_ARREGION,
+        m_axi_in1_mem_ARUSER,
+        m_axi_in1_mem_RVALID,
+        m_axi_in1_mem_RREADY,
+        m_axi_in1_mem_RDATA,
+        m_axi_in1_mem_RLAST,
+        m_axi_in1_mem_RID,
+        m_axi_in1_mem_RUSER,
+        m_axi_in1_mem_RRESP,
+        m_axi_in1_mem_BVALID,
+        m_axi_in1_mem_BREADY,
+        m_axi_in1_mem_BRESP,
+        m_axi_in1_mem_BID,
+        m_axi_in1_mem_BUSER,
+        m_axi_in2_mem_AWVALID,
+        m_axi_in2_mem_AWREADY,
+        m_axi_in2_mem_AWADDR,
+        m_axi_in2_mem_AWID,
+        m_axi_in2_mem_AWLEN,
+        m_axi_in2_mem_AWSIZE,
+        m_axi_in2_mem_AWBURST,
+        m_axi_in2_mem_AWLOCK,
+        m_axi_in2_mem_AWCACHE,
+        m_axi_in2_mem_AWPROT,
+        m_axi_in2_mem_AWQOS,
+        m_axi_in2_mem_AWREGION,
+        m_axi_in2_mem_AWUSER,
+        m_axi_in2_mem_WVALID,
+        m_axi_in2_mem_WREADY,
+        m_axi_in2_mem_WDATA,
+        m_axi_in2_mem_WSTRB,
+        m_axi_in2_mem_WLAST,
+        m_axi_in2_mem_WID,
+        m_axi_in2_mem_WUSER,
+        m_axi_in2_mem_ARVALID,
+        m_axi_in2_mem_ARREADY,
+        m_axi_in2_mem_ARADDR,
+        m_axi_in2_mem_ARID,
+        m_axi_in2_mem_ARLEN,
+        m_axi_in2_mem_ARSIZE,
+        m_axi_in2_mem_ARBURST,
+        m_axi_in2_mem_ARLOCK,
+        m_axi_in2_mem_ARCACHE,
+        m_axi_in2_mem_ARPROT,
+        m_axi_in2_mem_ARQOS,
+        m_axi_in2_mem_ARREGION,
+        m_axi_in2_mem_ARUSER,
+        m_axi_in2_mem_RVALID,
+        m_axi_in2_mem_RREADY,
+        m_axi_in2_mem_RDATA,
+        m_axi_in2_mem_RLAST,
+        m_axi_in2_mem_RID,
+        m_axi_in2_mem_RUSER,
+        m_axi_in2_mem_RRESP,
+        m_axi_in2_mem_BVALID,
+        m_axi_in2_mem_BREADY,
+        m_axi_in2_mem_BRESP,
+        m_axi_in2_mem_BID,
+        m_axi_in2_mem_BUSER,
+        m_axi_out_mem_AWVALID,
+        m_axi_out_mem_AWREADY,
+        m_axi_out_mem_AWADDR,
+        m_axi_out_mem_AWID,
+        m_axi_out_mem_AWLEN,
+        m_axi_out_mem_AWSIZE,
+        m_axi_out_mem_AWBURST,
+        m_axi_out_mem_AWLOCK,
+        m_axi_out_mem_AWCACHE,
+        m_axi_out_mem_AWPROT,
+        m_axi_out_mem_AWQOS,
+        m_axi_out_mem_AWREGION,
+        m_axi_out_mem_AWUSER,
+        m_axi_out_mem_WVALID,
+        m_axi_out_mem_WREADY,
+        m_axi_out_mem_WDATA,
+        m_axi_out_mem_WSTRB,
+        m_axi_out_mem_WLAST,
+        m_axi_out_mem_WID,
+        m_axi_out_mem_WUSER,
+        m_axi_out_mem_ARVALID,
+        m_axi_out_mem_ARREADY,
+        m_axi_out_mem_ARADDR,
+        m_axi_out_mem_ARID,
+        m_axi_out_mem_ARLEN,
+        m_axi_out_mem_ARSIZE,
+        m_axi_out_mem_ARBURST,
+        m_axi_out_mem_ARLOCK,
+        m_axi_out_mem_ARCACHE,
+        m_axi_out_mem_ARPROT,
+        m_axi_out_mem_ARQOS,
+        m_axi_out_mem_ARREGION,
+        m_axi_out_mem_ARUSER,
+        m_axi_out_mem_RVALID,
+        m_axi_out_mem_RREADY,
+        m_axi_out_mem_RDATA,
+        m_axi_out_mem_RLAST,
+        m_axi_out_mem_RID,
+        m_axi_out_mem_RUSER,
+        m_axi_out_mem_RRESP,
+        m_axi_out_mem_BVALID,
+        m_axi_out_mem_BREADY,
+        m_axi_out_mem_BRESP,
+        m_axi_out_mem_BID,
+        m_axi_out_mem_BUSER,
+        s_axi_params_AWVALID,
+        s_axi_params_AWREADY,
+        s_axi_params_AWADDR,
+        s_axi_params_WVALID,
+        s_axi_params_WREADY,
+        s_axi_params_WDATA,
+        s_axi_params_WSTRB,
+        s_axi_params_ARVALID,
+        s_axi_params_ARREADY,
+        s_axi_params_ARADDR,
+        s_axi_params_RVALID,
+        s_axi_params_RREADY,
+        s_axi_params_RDATA,
+        s_axi_params_RRESP,
+        s_axi_params_BVALID,
+        s_axi_params_BREADY,
+        s_axi_params_BRESP,
+        interrupt
+);
+
+parameter    ap_ST_fsm_state1 = 27'd1;
+parameter    ap_ST_fsm_state2 = 27'd2;
+parameter    ap_ST_fsm_state3 = 27'd4;
+parameter    ap_ST_fsm_state4 = 27'd8;
+parameter    ap_ST_fsm_state5 = 27'd16;
+parameter    ap_ST_fsm_state6 = 27'd32;
+parameter    ap_ST_fsm_state7 = 27'd64;
+parameter    ap_ST_fsm_state8 = 27'd128;
+parameter    ap_ST_fsm_pp0_stage0 = 27'd256;
+parameter    ap_ST_fsm_state12 = 27'd512;
+parameter    ap_ST_fsm_state13 = 27'd1024;
+parameter    ap_ST_fsm_state14 = 27'd2048;
+parameter    ap_ST_fsm_state15 = 27'd4096;
+parameter    ap_ST_fsm_state16 = 27'd8192;
+parameter    ap_ST_fsm_state17 = 27'd16384;
+parameter    ap_ST_fsm_state18 = 27'd32768;
+parameter    ap_ST_fsm_pp1_stage0 = 27'd65536;
+parameter    ap_ST_fsm_state22 = 27'd131072;
+parameter    ap_ST_fsm_state23 = 27'd262144;
+parameter    ap_ST_fsm_state24 = 27'd524288;
+parameter    ap_ST_fsm_state25 = 27'd1048576;
+parameter    ap_ST_fsm_pp3_stage0 = 27'd2097152;
+parameter    ap_ST_fsm_state29 = 27'd4194304;
+parameter    ap_ST_fsm_state30 = 27'd8388608;
+parameter    ap_ST_fsm_state31 = 27'd16777216;
+parameter    ap_ST_fsm_state32 = 27'd33554432;
+parameter    ap_ST_fsm_state33 = 27'd67108864;
+parameter    C_S_AXI_PARAMS_DATA_WIDTH = 32;
+parameter    C_S_AXI_PARAMS_ADDR_WIDTH = 6;
+parameter    C_S_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_OUT_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_CACHE_VALUE = 3;
+
+parameter C_S_AXI_PARAMS_WSTRB_WIDTH = (32 / 8);
+parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN1_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN2_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_OUT_MEM_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+output   m_axi_in1_mem_AWVALID;
+input   m_axi_in1_mem_AWREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_AWADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_AWID;
+output  [7:0] m_axi_in1_mem_AWLEN;
+output  [2:0] m_axi_in1_mem_AWSIZE;
+output  [1:0] m_axi_in1_mem_AWBURST;
+output  [1:0] m_axi_in1_mem_AWLOCK;
+output  [3:0] m_axi_in1_mem_AWCACHE;
+output  [2:0] m_axi_in1_mem_AWPROT;
+output  [3:0] m_axi_in1_mem_AWQOS;
+output  [3:0] m_axi_in1_mem_AWREGION;
+output  [C_M_AXI_IN1_MEM_AWUSER_WIDTH - 1:0] m_axi_in1_mem_AWUSER;
+output   m_axi_in1_mem_WVALID;
+input   m_axi_in1_mem_WREADY;
+output  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_WDATA;
+output  [C_M_AXI_IN1_MEM_WSTRB_WIDTH - 1:0] m_axi_in1_mem_WSTRB;
+output   m_axi_in1_mem_WLAST;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_WID;
+output  [C_M_AXI_IN1_MEM_WUSER_WIDTH - 1:0] m_axi_in1_mem_WUSER;
+output   m_axi_in1_mem_ARVALID;
+input   m_axi_in1_mem_ARREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_ARADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_ARID;
+output  [7:0] m_axi_in1_mem_ARLEN;
+output  [2:0] m_axi_in1_mem_ARSIZE;
+output  [1:0] m_axi_in1_mem_ARBURST;
+output  [1:0] m_axi_in1_mem_ARLOCK;
+output  [3:0] m_axi_in1_mem_ARCACHE;
+output  [2:0] m_axi_in1_mem_ARPROT;
+output  [3:0] m_axi_in1_mem_ARQOS;
+output  [3:0] m_axi_in1_mem_ARREGION;
+output  [C_M_AXI_IN1_MEM_ARUSER_WIDTH - 1:0] m_axi_in1_mem_ARUSER;
+input   m_axi_in1_mem_RVALID;
+output   m_axi_in1_mem_RREADY;
+input  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_RDATA;
+input   m_axi_in1_mem_RLAST;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_RID;
+input  [C_M_AXI_IN1_MEM_RUSER_WIDTH - 1:0] m_axi_in1_mem_RUSER;
+input  [1:0] m_axi_in1_mem_RRESP;
+input   m_axi_in1_mem_BVALID;
+output   m_axi_in1_mem_BREADY;
+input  [1:0] m_axi_in1_mem_BRESP;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_BID;
+input  [C_M_AXI_IN1_MEM_BUSER_WIDTH - 1:0] m_axi_in1_mem_BUSER;
+output   m_axi_in2_mem_AWVALID;
+input   m_axi_in2_mem_AWREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_AWADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_AWID;
+output  [7:0] m_axi_in2_mem_AWLEN;
+output  [2:0] m_axi_in2_mem_AWSIZE;
+output  [1:0] m_axi_in2_mem_AWBURST;
+output  [1:0] m_axi_in2_mem_AWLOCK;
+output  [3:0] m_axi_in2_mem_AWCACHE;
+output  [2:0] m_axi_in2_mem_AWPROT;
+output  [3:0] m_axi_in2_mem_AWQOS;
+output  [3:0] m_axi_in2_mem_AWREGION;
+output  [C_M_AXI_IN2_MEM_AWUSER_WIDTH - 1:0] m_axi_in2_mem_AWUSER;
+output   m_axi_in2_mem_WVALID;
+input   m_axi_in2_mem_WREADY;
+output  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_WDATA;
+output  [C_M_AXI_IN2_MEM_WSTRB_WIDTH - 1:0] m_axi_in2_mem_WSTRB;
+output   m_axi_in2_mem_WLAST;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_WID;
+output  [C_M_AXI_IN2_MEM_WUSER_WIDTH - 1:0] m_axi_in2_mem_WUSER;
+output   m_axi_in2_mem_ARVALID;
+input   m_axi_in2_mem_ARREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_ARADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_ARID;
+output  [7:0] m_axi_in2_mem_ARLEN;
+output  [2:0] m_axi_in2_mem_ARSIZE;
+output  [1:0] m_axi_in2_mem_ARBURST;
+output  [1:0] m_axi_in2_mem_ARLOCK;
+output  [3:0] m_axi_in2_mem_ARCACHE;
+output  [2:0] m_axi_in2_mem_ARPROT;
+output  [3:0] m_axi_in2_mem_ARQOS;
+output  [3:0] m_axi_in2_mem_ARREGION;
+output  [C_M_AXI_IN2_MEM_ARUSER_WIDTH - 1:0] m_axi_in2_mem_ARUSER;
+input   m_axi_in2_mem_RVALID;
+output   m_axi_in2_mem_RREADY;
+input  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_RDATA;
+input   m_axi_in2_mem_RLAST;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_RID;
+input  [C_M_AXI_IN2_MEM_RUSER_WIDTH - 1:0] m_axi_in2_mem_RUSER;
+input  [1:0] m_axi_in2_mem_RRESP;
+input   m_axi_in2_mem_BVALID;
+output   m_axi_in2_mem_BREADY;
+input  [1:0] m_axi_in2_mem_BRESP;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_BID;
+input  [C_M_AXI_IN2_MEM_BUSER_WIDTH - 1:0] m_axi_in2_mem_BUSER;
+output   m_axi_out_mem_AWVALID;
+input   m_axi_out_mem_AWREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_AWADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_AWID;
+output  [7:0] m_axi_out_mem_AWLEN;
+output  [2:0] m_axi_out_mem_AWSIZE;
+output  [1:0] m_axi_out_mem_AWBURST;
+output  [1:0] m_axi_out_mem_AWLOCK;
+output  [3:0] m_axi_out_mem_AWCACHE;
+output  [2:0] m_axi_out_mem_AWPROT;
+output  [3:0] m_axi_out_mem_AWQOS;
+output  [3:0] m_axi_out_mem_AWREGION;
+output  [C_M_AXI_OUT_MEM_AWUSER_WIDTH - 1:0] m_axi_out_mem_AWUSER;
+output   m_axi_out_mem_WVALID;
+input   m_axi_out_mem_WREADY;
+output  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_WDATA;
+output  [C_M_AXI_OUT_MEM_WSTRB_WIDTH - 1:0] m_axi_out_mem_WSTRB;
+output   m_axi_out_mem_WLAST;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_WID;
+output  [C_M_AXI_OUT_MEM_WUSER_WIDTH - 1:0] m_axi_out_mem_WUSER;
+output   m_axi_out_mem_ARVALID;
+input   m_axi_out_mem_ARREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_ARADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_ARID;
+output  [7:0] m_axi_out_mem_ARLEN;
+output  [2:0] m_axi_out_mem_ARSIZE;
+output  [1:0] m_axi_out_mem_ARBURST;
+output  [1:0] m_axi_out_mem_ARLOCK;
+output  [3:0] m_axi_out_mem_ARCACHE;
+output  [2:0] m_axi_out_mem_ARPROT;
+output  [3:0] m_axi_out_mem_ARQOS;
+output  [3:0] m_axi_out_mem_ARREGION;
+output  [C_M_AXI_OUT_MEM_ARUSER_WIDTH - 1:0] m_axi_out_mem_ARUSER;
+input   m_axi_out_mem_RVALID;
+output   m_axi_out_mem_RREADY;
+input  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_RDATA;
+input   m_axi_out_mem_RLAST;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_RID;
+input  [C_M_AXI_OUT_MEM_RUSER_WIDTH - 1:0] m_axi_out_mem_RUSER;
+input  [1:0] m_axi_out_mem_RRESP;
+input   m_axi_out_mem_BVALID;
+output   m_axi_out_mem_BREADY;
+input  [1:0] m_axi_out_mem_BRESP;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_BID;
+input  [C_M_AXI_OUT_MEM_BUSER_WIDTH - 1:0] m_axi_out_mem_BUSER;
+input   s_axi_params_AWVALID;
+output   s_axi_params_AWREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_AWADDR;
+input   s_axi_params_WVALID;
+output   s_axi_params_WREADY;
+input  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_WDATA;
+input  [C_S_AXI_PARAMS_WSTRB_WIDTH - 1:0] s_axi_params_WSTRB;
+input   s_axi_params_ARVALID;
+output   s_axi_params_ARREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_ARADDR;
+output   s_axi_params_RVALID;
+input   s_axi_params_RREADY;
+output  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_RDATA;
+output  [1:0] s_axi_params_RRESP;
+output   s_axi_params_BVALID;
+input   s_axi_params_BREADY;
+output  [1:0] s_axi_params_BRESP;
+output   interrupt;
+
+ reg    ap_rst_n_inv;
+wire    ap_start;
+reg    ap_done;
+reg    ap_idle;
+(* fsm_encoding = "none" *) reg   [26:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    ap_ready;
+wire   [31:0] in1;
+wire   [31:0] in2;
+wire   [31:0] out_r;
+wire   [31:0] dim;
+reg    in1_mem_blk_n_AR;
+wire    ap_CS_fsm_state2;
+reg    in1_mem_blk_n_R;
+wire    ap_CS_fsm_pp0_stage0;
+reg    ap_enable_reg_pp0_iter1;
+wire    ap_block_pp0_stage0;
+reg   [0:0] icmp_ln27_reg_748;
+reg    in2_mem_blk_n_AR;
+wire    ap_CS_fsm_state12;
+reg    in2_mem_blk_n_R;
+wire    ap_CS_fsm_pp1_stage0;
+reg    ap_enable_reg_pp1_iter1;
+wire    ap_block_pp1_stage0;
+reg   [0:0] icmp_ln28_reg_762;
+reg    out_mem_blk_n_AW;
+wire    ap_CS_fsm_state25;
+reg    out_mem_blk_n_W;
+reg    ap_enable_reg_pp3_iter2;
+wire    ap_block_pp3_stage0;
+reg   [0:0] icmp_ln42_reg_834;
+reg   [0:0] icmp_ln42_reg_834_pp3_iter1_reg;
+reg    out_mem_blk_n_B;
+wire    ap_CS_fsm_state33;
+wire    in1_mem_AWREADY;
+wire    in1_mem_WREADY;
+reg    in1_mem_ARVALID;
+wire    in1_mem_ARREADY;
+wire   [31:0] in1_mem_ARADDR;
+wire    in1_mem_RVALID;
+reg    in1_mem_RREADY;
+wire   [31:0] in1_mem_RDATA;
+wire    in1_mem_RLAST;
+wire   [0:0] in1_mem_RID;
+wire   [0:0] in1_mem_RUSER;
+wire   [1:0] in1_mem_RRESP;
+wire    in1_mem_BVALID;
+wire   [1:0] in1_mem_BRESP;
+wire   [0:0] in1_mem_BID;
+wire   [0:0] in1_mem_BUSER;
+wire    in2_mem_AWREADY;
+wire    in2_mem_WREADY;
+reg    in2_mem_ARVALID;
+wire    in2_mem_ARREADY;
+wire    in2_mem_RVALID;
+reg    in2_mem_RREADY;
+wire   [31:0] in2_mem_RDATA;
+wire    in2_mem_RLAST;
+wire   [0:0] in2_mem_RID;
+wire   [0:0] in2_mem_RUSER;
+wire   [1:0] in2_mem_RRESP;
+wire    in2_mem_BVALID;
+wire   [1:0] in2_mem_BRESP;
+wire   [0:0] in2_mem_BID;
+wire   [0:0] in2_mem_BUSER;
+reg    out_mem_AWVALID;
+wire    out_mem_AWREADY;
+reg    out_mem_WVALID;
+wire    out_mem_WREADY;
+wire    out_mem_ARREADY;
+wire    out_mem_RVALID;
+wire   [31:0] out_mem_RDATA;
+wire    out_mem_RLAST;
+wire   [0:0] out_mem_RID;
+wire   [0:0] out_mem_RUSER;
+wire   [1:0] out_mem_RRESP;
+wire    out_mem_BVALID;
+reg    out_mem_BREADY;
+wire   [1:0] out_mem_BRESP;
+wire   [0:0] out_mem_BID;
+wire   [0:0] out_mem_BUSER;
+reg   [12:0] phi_ln27_reg_285;
+reg   [12:0] phi_ln27_reg_285_pp0_iter1_reg;
+wire    ap_block_state9_pp0_stage0_iter0;
+reg    ap_block_state10_pp0_stage0_iter1;
+wire    ap_block_state11_pp0_stage0_iter2;
+reg    ap_block_pp0_stage0_11001;
+reg   [12:0] phi_ln28_reg_297;
+reg   [12:0] phi_ln28_reg_297_pp1_iter1_reg;
+wire    ap_block_state19_pp1_stage0_iter0;
+reg    ap_block_state20_pp1_stage0_iter1;
+wire    ap_block_state21_pp1_stage0_iter2;
+reg    ap_block_pp1_stage0_11001;
+reg   [12:0] phi_ln42_reg_364;
+reg   [31:0] dim_read_reg_709;
+reg   [29:0] out5_reg_715;
+reg   [29:0] in_reg_720;
+reg   [29:0] in3_reg_725;
+reg   [31:0] out_mem_addr_reg_736;
+wire    ap_CS_fsm_state8;
+reg   [31:0] in2_mem_addr_reg_742;
+wire   [0:0] icmp_ln27_fu_433_p2;
+reg   [0:0] icmp_ln27_reg_748_pp0_iter1_reg;
+wire   [12:0] add_ln27_fu_439_p2;
+reg   [12:0] add_ln27_reg_752;
+reg    ap_enable_reg_pp0_iter0;
+reg   [31:0] in1_mem_addr_read_reg_757;
+wire   [0:0] icmp_ln28_fu_450_p2;
+reg   [0:0] icmp_ln28_reg_762_pp1_iter1_reg;
+wire   [12:0] add_ln28_fu_456_p2;
+reg   [12:0] add_ln28_reg_766;
+reg    ap_enable_reg_pp1_iter0;
+reg   [31:0] in2_mem_addr_read_reg_771;
+wire   [38:0] zext_ln31_fu_474_p1;
+reg   [38:0] zext_ln31_reg_776;
+wire    ap_CS_fsm_state22;
+wire   [69:0] mul_ln31_fu_485_p2;
+reg   [69:0] mul_ln31_reg_781;
+wire   [69:0] add_ln31_fu_496_p2;
+reg   [69:0] add_ln31_reg_789;
+wire    ap_CS_fsm_state23;
+wire   [30:0] select_ln31_1_fu_521_p3;
+reg   [30:0] select_ln31_1_reg_794;
+wire   [0:0] icmp_ln31_fu_491_p2;
+wire   [6:0] select_ln38_fu_571_p3;
+reg   [6:0] select_ln38_reg_799;
+reg   [11:0] out_loc_addr_reg_804;
+wire   [31:0] select_ln33_fu_614_p3;
+reg   [31:0] select_ln33_reg_809;
+wire   [38:0] select_ln33_1_fu_666_p3;
+reg   [38:0] select_ln33_1_reg_824;
+wire   [6:0] k_fu_687_p2;
+wire    ap_CS_fsm_state24;
+wire   [0:0] icmp_ln42_fu_692_p2;
+wire    ap_CS_fsm_pp3_stage0;
+wire    ap_block_state26_pp3_stage0_iter0;
+wire    ap_block_state27_pp3_stage0_iter1;
+wire    ap_block_state28_pp3_stage0_iter2;
+reg    ap_block_state28_io;
+reg    ap_block_pp3_stage0_11001;
+wire   [12:0] add_ln42_fu_698_p2;
+reg    ap_enable_reg_pp3_iter0;
+wire   [31:0] out_loc_q0;
+reg   [31:0] out_loc_load_reg_848;
+reg    ap_enable_reg_pp3_iter1;
+reg    ap_block_pp0_stage0_subdone;
+reg    ap_condition_pp0_exit_iter0_state9;
+reg    ap_enable_reg_pp0_iter2;
+wire    ap_CS_fsm_state18;
+reg    ap_block_pp1_stage0_subdone;
+reg    ap_condition_pp1_exit_iter0_state19;
+reg    ap_enable_reg_pp1_iter2;
+reg    ap_block_pp3_stage0_subdone;
+reg    ap_condition_pp3_exit_iter0_state26;
+reg   [11:0] in1_loc_address0;
+reg    in1_loc_ce0;
+reg    in1_loc_we0;
+wire   [31:0] in1_loc_q0;
+reg   [11:0] in2_loc_address0;
+reg    in2_loc_ce0;
+reg    in2_loc_we0;
+wire   [31:0] in2_loc_q0;
+reg   [11:0] out_loc_address0;
+reg    out_loc_ce0;
+reg    out_loc_we0;
+wire   [31:0] out_loc_d0;
+reg   [12:0] ap_phi_mux_phi_ln27_phi_fu_289_p4;
+reg   [12:0] ap_phi_mux_phi_ln28_phi_fu_301_p4;
+reg   [69:0] indvar_flatten15_reg_309;
+reg   [30:0] i_0_reg_320;
+reg   [38:0] indvar_flatten_reg_331;
+reg   [31:0] j_0_reg_342;
+reg   [6:0] k_0_reg_353;
+wire   [63:0] zext_ln27_fu_445_p1;
+wire   [63:0] zext_ln28_fu_462_p1;
+wire  signed [63:0] sext_ln38_fu_609_p1;
+wire   [63:0] zext_ln38_1_fu_632_p1;
+wire  signed [63:0] sext_ln38_1_fu_655_p1;
+wire   [63:0] zext_ln42_fu_704_p1;
+wire   [63:0] empty_6_fu_405_p1;
+wire   [63:0] empty_fu_415_p1;
+wire   [63:0] empty_5_fu_424_p1;
+wire    ap_block_pp3_stage0_01001;
+wire   [37:0] tmp_fu_467_p3;
+wire   [31:0] mul_ln31_fu_485_p0;
+wire   [37:0] mul_ln31_fu_485_p1;
+wire   [0:0] icmp_ln33_fu_508_p2;
+wire   [30:0] i_fu_502_p2;
+wire   [7:0] trunc_ln38_fu_529_p1;
+wire   [0:0] icmp_ln35_fu_547_p2;
+wire   [0:0] xor_ln31_fu_541_p2;
+wire   [31:0] select_ln31_fu_513_p3;
+wire   [0:0] and_ln31_fu_553_p2;
+wire   [0:0] or_ln38_fu_565_p2;
+wire   [31:0] j_fu_559_p2;
+wire   [13:0] trunc_ln38_2_fu_583_p1;
+wire   [13:0] trunc_ln38_1_fu_579_p1;
+wire   [13:0] select_ln31_2_fu_587_p3;
+wire   [13:0] zext_ln38_cast_fu_533_p3;
+wire   [13:0] select_ln38_1_fu_595_p3;
+wire   [13:0] add_ln38_1_fu_603_p2;
+wire   [13:0] zext_ln38_fu_622_p1;
+wire   [13:0] add_ln38_2_fu_626_p2;
+wire   [12:0] tmp_3_fu_637_p3;
+wire   [13:0] zext_ln38_2_fu_645_p1;
+wire   [13:0] add_ln38_3_fu_649_p2;
+wire   [38:0] add_ln33_fu_660_p2;
+wire  signed [31:0] mul_ln38_fu_674_p0;
+wire  signed [31:0] mul_ln38_fu_674_p1;
+wire   [31:0] mul_ln38_fu_674_p2;
+reg   [26:0] ap_NS_fsm;
+reg    ap_idle_pp0;
+wire    ap_enable_pp0;
+reg    ap_idle_pp1;
+wire    ap_enable_pp1;
+reg    ap_idle_pp3;
+wire    ap_enable_pp3;
+wire   [69:0] mul_ln31_fu_485_p00;
+wire   [69:0] mul_ln31_fu_485_p10;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 27'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp1_iter1 = 1'b0;
+#0 ap_enable_reg_pp3_iter2 = 1'b0;
+#0 ap_enable_reg_pp0_iter0 = 1'b0;
+#0 ap_enable_reg_pp1_iter0 = 1'b0;
+#0 ap_enable_reg_pp3_iter0 = 1'b0;
+#0 ap_enable_reg_pp3_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp1_iter2 = 1'b0;
+end
+
+mmult_params_s_axi #(
+    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PARAMS_ADDR_WIDTH ),
+    .C_S_AXI_DATA_WIDTH( C_S_AXI_PARAMS_DATA_WIDTH ))
+mmult_params_s_axi_U(
+    .AWVALID(s_axi_params_AWVALID),
+    .AWREADY(s_axi_params_AWREADY),
+    .AWADDR(s_axi_params_AWADDR),
+    .WVALID(s_axi_params_WVALID),
+    .WREADY(s_axi_params_WREADY),
+    .WDATA(s_axi_params_WDATA),
+    .WSTRB(s_axi_params_WSTRB),
+    .ARVALID(s_axi_params_ARVALID),
+    .ARREADY(s_axi_params_ARREADY),
+    .ARADDR(s_axi_params_ARADDR),
+    .RVALID(s_axi_params_RVALID),
+    .RREADY(s_axi_params_RREADY),
+    .RDATA(s_axi_params_RDATA),
+    .RRESP(s_axi_params_RRESP),
+    .BVALID(s_axi_params_BVALID),
+    .BREADY(s_axi_params_BREADY),
+    .BRESP(s_axi_params_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .in1(in1),
+    .in2(in2),
+    .out_r(out_r),
+    .dim(dim)
+);
+
+mmult_in1_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN1_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN1_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN1_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN1_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN1_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN1_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN1_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN1_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN1_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN1_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN1_MEM_CACHE_VALUE ))
+mmult_in1_mem_m_axi_U(
+    .AWVALID(m_axi_in1_mem_AWVALID),
+    .AWREADY(m_axi_in1_mem_AWREADY),
+    .AWADDR(m_axi_in1_mem_AWADDR),
+    .AWID(m_axi_in1_mem_AWID),
+    .AWLEN(m_axi_in1_mem_AWLEN),
+    .AWSIZE(m_axi_in1_mem_AWSIZE),
+    .AWBURST(m_axi_in1_mem_AWBURST),
+    .AWLOCK(m_axi_in1_mem_AWLOCK),
+    .AWCACHE(m_axi_in1_mem_AWCACHE),
+    .AWPROT(m_axi_in1_mem_AWPROT),
+    .AWQOS(m_axi_in1_mem_AWQOS),
+    .AWREGION(m_axi_in1_mem_AWREGION),
+    .AWUSER(m_axi_in1_mem_AWUSER),
+    .WVALID(m_axi_in1_mem_WVALID),
+    .WREADY(m_axi_in1_mem_WREADY),
+    .WDATA(m_axi_in1_mem_WDATA),
+    .WSTRB(m_axi_in1_mem_WSTRB),
+    .WLAST(m_axi_in1_mem_WLAST),
+    .WID(m_axi_in1_mem_WID),
+    .WUSER(m_axi_in1_mem_WUSER),
+    .ARVALID(m_axi_in1_mem_ARVALID),
+    .ARREADY(m_axi_in1_mem_ARREADY),
+    .ARADDR(m_axi_in1_mem_ARADDR),
+    .ARID(m_axi_in1_mem_ARID),
+    .ARLEN(m_axi_in1_mem_ARLEN),
+    .ARSIZE(m_axi_in1_mem_ARSIZE),
+    .ARBURST(m_axi_in1_mem_ARBURST),
+    .ARLOCK(m_axi_in1_mem_ARLOCK),
+    .ARCACHE(m_axi_in1_mem_ARCACHE),
+    .ARPROT(m_axi_in1_mem_ARPROT),
+    .ARQOS(m_axi_in1_mem_ARQOS),
+    .ARREGION(m_axi_in1_mem_ARREGION),
+    .ARUSER(m_axi_in1_mem_ARUSER),
+    .RVALID(m_axi_in1_mem_RVALID),
+    .RREADY(m_axi_in1_mem_RREADY),
+    .RDATA(m_axi_in1_mem_RDATA),
+    .RLAST(m_axi_in1_mem_RLAST),
+    .RID(m_axi_in1_mem_RID),
+    .RUSER(m_axi_in1_mem_RUSER),
+    .RRESP(m_axi_in1_mem_RRESP),
+    .BVALID(m_axi_in1_mem_BVALID),
+    .BREADY(m_axi_in1_mem_BREADY),
+    .BRESP(m_axi_in1_mem_BRESP),
+    .BID(m_axi_in1_mem_BID),
+    .BUSER(m_axi_in1_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in1_mem_ARVALID),
+    .I_ARREADY(in1_mem_ARREADY),
+    .I_ARADDR(in1_mem_ARADDR),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in1_mem_RVALID),
+    .I_RREADY(in1_mem_RREADY),
+    .I_RDATA(in1_mem_RDATA),
+    .I_RID(in1_mem_RID),
+    .I_RUSER(in1_mem_RUSER),
+    .I_RRESP(in1_mem_RRESP),
+    .I_RLAST(in1_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in1_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in1_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in1_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in1_mem_BRESP),
+    .I_BID(in1_mem_BID),
+    .I_BUSER(in1_mem_BUSER)
+);
+
+mmult_in2_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN2_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN2_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN2_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN2_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN2_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN2_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN2_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN2_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN2_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN2_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN2_MEM_CACHE_VALUE ))
+mmult_in2_mem_m_axi_U(
+    .AWVALID(m_axi_in2_mem_AWVALID),
+    .AWREADY(m_axi_in2_mem_AWREADY),
+    .AWADDR(m_axi_in2_mem_AWADDR),
+    .AWID(m_axi_in2_mem_AWID),
+    .AWLEN(m_axi_in2_mem_AWLEN),
+    .AWSIZE(m_axi_in2_mem_AWSIZE),
+    .AWBURST(m_axi_in2_mem_AWBURST),
+    .AWLOCK(m_axi_in2_mem_AWLOCK),
+    .AWCACHE(m_axi_in2_mem_AWCACHE),
+    .AWPROT(m_axi_in2_mem_AWPROT),
+    .AWQOS(m_axi_in2_mem_AWQOS),
+    .AWREGION(m_axi_in2_mem_AWREGION),
+    .AWUSER(m_axi_in2_mem_AWUSER),
+    .WVALID(m_axi_in2_mem_WVALID),
+    .WREADY(m_axi_in2_mem_WREADY),
+    .WDATA(m_axi_in2_mem_WDATA),
+    .WSTRB(m_axi_in2_mem_WSTRB),
+    .WLAST(m_axi_in2_mem_WLAST),
+    .WID(m_axi_in2_mem_WID),
+    .WUSER(m_axi_in2_mem_WUSER),
+    .ARVALID(m_axi_in2_mem_ARVALID),
+    .ARREADY(m_axi_in2_mem_ARREADY),
+    .ARADDR(m_axi_in2_mem_ARADDR),
+    .ARID(m_axi_in2_mem_ARID),
+    .ARLEN(m_axi_in2_mem_ARLEN),
+    .ARSIZE(m_axi_in2_mem_ARSIZE),
+    .ARBURST(m_axi_in2_mem_ARBURST),
+    .ARLOCK(m_axi_in2_mem_ARLOCK),
+    .ARCACHE(m_axi_in2_mem_ARCACHE),
+    .ARPROT(m_axi_in2_mem_ARPROT),
+    .ARQOS(m_axi_in2_mem_ARQOS),
+    .ARREGION(m_axi_in2_mem_ARREGION),
+    .ARUSER(m_axi_in2_mem_ARUSER),
+    .RVALID(m_axi_in2_mem_RVALID),
+    .RREADY(m_axi_in2_mem_RREADY),
+    .RDATA(m_axi_in2_mem_RDATA),
+    .RLAST(m_axi_in2_mem_RLAST),
+    .RID(m_axi_in2_mem_RID),
+    .RUSER(m_axi_in2_mem_RUSER),
+    .RRESP(m_axi_in2_mem_RRESP),
+    .BVALID(m_axi_in2_mem_BVALID),
+    .BREADY(m_axi_in2_mem_BREADY),
+    .BRESP(m_axi_in2_mem_BRESP),
+    .BID(m_axi_in2_mem_BID),
+    .BUSER(m_axi_in2_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in2_mem_ARVALID),
+    .I_ARREADY(in2_mem_ARREADY),
+    .I_ARADDR(in2_mem_addr_reg_742),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in2_mem_RVALID),
+    .I_RREADY(in2_mem_RREADY),
+    .I_RDATA(in2_mem_RDATA),
+    .I_RID(in2_mem_RID),
+    .I_RUSER(in2_mem_RUSER),
+    .I_RRESP(in2_mem_RRESP),
+    .I_RLAST(in2_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in2_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in2_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in2_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in2_mem_BRESP),
+    .I_BID(in2_mem_BID),
+    .I_BUSER(in2_mem_BUSER)
+);
+
+mmult_out_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_OUT_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_OUT_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_OUT_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_OUT_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_OUT_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_OUT_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_OUT_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_OUT_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_OUT_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_OUT_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_OUT_MEM_CACHE_VALUE ))
+mmult_out_mem_m_axi_U(
+    .AWVALID(m_axi_out_mem_AWVALID),
+    .AWREADY(m_axi_out_mem_AWREADY),
+    .AWADDR(m_axi_out_mem_AWADDR),
+    .AWID(m_axi_out_mem_AWID),
+    .AWLEN(m_axi_out_mem_AWLEN),
+    .AWSIZE(m_axi_out_mem_AWSIZE),
+    .AWBURST(m_axi_out_mem_AWBURST),
+    .AWLOCK(m_axi_out_mem_AWLOCK),
+    .AWCACHE(m_axi_out_mem_AWCACHE),
+    .AWPROT(m_axi_out_mem_AWPROT),
+    .AWQOS(m_axi_out_mem_AWQOS),
+    .AWREGION(m_axi_out_mem_AWREGION),
+    .AWUSER(m_axi_out_mem_AWUSER),
+    .WVALID(m_axi_out_mem_WVALID),
+    .WREADY(m_axi_out_mem_WREADY),
+    .WDATA(m_axi_out_mem_WDATA),
+    .WSTRB(m_axi_out_mem_WSTRB),
+    .WLAST(m_axi_out_mem_WLAST),
+    .WID(m_axi_out_mem_WID),
+    .WUSER(m_axi_out_mem_WUSER),
+    .ARVALID(m_axi_out_mem_ARVALID),
+    .ARREADY(m_axi_out_mem_ARREADY),
+    .ARADDR(m_axi_out_mem_ARADDR),
+    .ARID(m_axi_out_mem_ARID),
+    .ARLEN(m_axi_out_mem_ARLEN),
+    .ARSIZE(m_axi_out_mem_ARSIZE),
+    .ARBURST(m_axi_out_mem_ARBURST),
+    .ARLOCK(m_axi_out_mem_ARLOCK),
+    .ARCACHE(m_axi_out_mem_ARCACHE),
+    .ARPROT(m_axi_out_mem_ARPROT),
+    .ARQOS(m_axi_out_mem_ARQOS),
+    .ARREGION(m_axi_out_mem_ARREGION),
+    .ARUSER(m_axi_out_mem_ARUSER),
+    .RVALID(m_axi_out_mem_RVALID),
+    .RREADY(m_axi_out_mem_RREADY),
+    .RDATA(m_axi_out_mem_RDATA),
+    .RLAST(m_axi_out_mem_RLAST),
+    .RID(m_axi_out_mem_RID),
+    .RUSER(m_axi_out_mem_RUSER),
+    .RRESP(m_axi_out_mem_RRESP),
+    .BVALID(m_axi_out_mem_BVALID),
+    .BREADY(m_axi_out_mem_BREADY),
+    .BRESP(m_axi_out_mem_BRESP),
+    .BID(m_axi_out_mem_BID),
+    .BUSER(m_axi_out_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(1'b0),
+    .I_ARREADY(out_mem_ARREADY),
+    .I_ARADDR(32'd0),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd0),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(out_mem_RVALID),
+    .I_RREADY(1'b0),
+    .I_RDATA(out_mem_RDATA),
+    .I_RID(out_mem_RID),
+    .I_RUSER(out_mem_RUSER),
+    .I_RRESP(out_mem_RRESP),
+    .I_RLAST(out_mem_RLAST),
+    .I_AWVALID(out_mem_AWVALID),
+    .I_AWREADY(out_mem_AWREADY),
+    .I_AWADDR(out_mem_addr_reg_736),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd4096),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(out_mem_WVALID),
+    .I_WREADY(out_mem_WREADY),
+    .I_WDATA(out_loc_load_reg_848),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd15),
+    .I_BVALID(out_mem_BVALID),
+    .I_BREADY(out_mem_BREADY),
+    .I_BRESP(out_mem_BRESP),
+    .I_BID(out_mem_BID),
+    .I_BUSER(out_mem_BUSER)
+);
+
+mmult_in1_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+in1_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_address0),
+    .ce0(in1_loc_ce0),
+    .we0(in1_loc_we0),
+    .d0(in1_mem_addr_read_reg_757),
+    .q0(in1_loc_q0)
+);
+
+mmult_in1_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+in2_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_address0),
+    .ce0(in2_loc_ce0),
+    .we0(in2_loc_we0),
+    .d0(in2_mem_addr_read_reg_771),
+    .q0(in2_loc_q0)
+);
+
+mmult_in1_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+out_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(out_loc_address0),
+    .ce0(out_loc_ce0),
+    .we0(out_loc_we0),
+    .d0(out_loc_d0),
+    .q0(out_loc_q0)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter0 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state9) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_enable_reg_pp0_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp0_exit_iter0_state9)) begin
+                ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state9);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter0 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp1_stage0_subdone) & (1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+            ap_enable_reg_pp1_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp1_exit_iter0_state19)) begin
+                ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter0 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp3_stage0_subdone) & (1'b1 == ap_condition_pp3_exit_iter0_state26) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+            ap_enable_reg_pp3_iter0 <= 1'b0;
+        end else if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+            ap_enable_reg_pp3_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp3_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp3_exit_iter0_state26)) begin
+                ap_enable_reg_pp3_iter1 <= (1'b1 ^ ap_condition_pp3_exit_iter0_state26);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp3_iter1 <= ap_enable_reg_pp3_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp3_stage0_subdone)) begin
+            ap_enable_reg_pp3_iter2 <= ap_enable_reg_pp3_iter1;
+        end else if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+            ap_enable_reg_pp3_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        i_0_reg_320 <= select_ln31_1_reg_794;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        i_0_reg_320 <= 31'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        indvar_flatten15_reg_309 <= add_ln31_reg_789;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        indvar_flatten15_reg_309 <= 70'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        indvar_flatten_reg_331 <= select_ln33_1_reg_824;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        indvar_flatten_reg_331 <= 39'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        j_0_reg_342 <= select_ln33_reg_809;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        j_0_reg_342 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        k_0_reg_353 <= k_fu_687_p2;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        k_0_reg_353 <= 7'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_reg_748 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        phi_ln27_reg_285 <= add_ln27_reg_752;
+    end else if ((1'b1 == ap_CS_fsm_state8)) begin
+        phi_ln27_reg_285 <= 13'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        phi_ln28_reg_297 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_reg_762 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        phi_ln28_reg_297 <= add_ln28_reg_766;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+        phi_ln42_reg_364 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_fu_692_p2 == 1'd0) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        phi_ln42_reg_364 <= add_ln42_fu_698_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        add_ln27_reg_752 <= add_ln27_fu_439_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        add_ln28_reg_766 <= add_ln28_fu_456_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        add_ln31_reg_789 <= add_ln31_fu_496_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        dim_read_reg_709 <= dim;
+        in3_reg_725 <= {{in1[31:2]}};
+        in_reg_720 <= {{in2[31:2]}};
+        out5_reg_715 <= {{out_r[31:2]}};
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        icmp_ln27_reg_748 <= icmp_ln27_fu_433_p2;
+        icmp_ln27_reg_748_pp0_iter1_reg <= icmp_ln27_reg_748;
+        phi_ln27_reg_285_pp0_iter1_reg <= phi_ln27_reg_285;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        icmp_ln28_reg_762 <= icmp_ln28_fu_450_p2;
+        icmp_ln28_reg_762_pp1_iter1_reg <= icmp_ln28_reg_762;
+        phi_ln28_reg_297_pp1_iter1_reg <= phi_ln28_reg_297;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp3_stage0_11001) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        icmp_ln42_reg_834 <= icmp_ln42_fu_692_p2;
+        icmp_ln42_reg_834_pp3_iter1_reg <= icmp_ln42_reg_834;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_reg_748 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_addr_read_reg_757 <= in1_mem_RDATA;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_reg_762 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_addr_read_reg_771 <= in2_mem_RDATA;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        in2_mem_addr_reg_742[29 : 0] <= empty_5_fu_424_p1[29 : 0];
+        out_mem_addr_reg_736[29 : 0] <= empty_fu_415_p1[29 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state22)) begin
+        mul_ln31_reg_781[69 : 6] <= mul_ln31_fu_485_p2[69 : 6];
+        zext_ln31_reg_776[37 : 6] <= zext_ln31_fu_474_p1[37 : 6];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln31_fu_491_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+        out_loc_addr_reg_804 <= sext_ln38_fu_609_p1;
+        select_ln31_1_reg_794 <= select_ln31_1_fu_521_p3;
+        select_ln33_1_reg_824 <= select_ln33_1_fu_666_p3;
+        select_ln33_reg_809 <= select_ln33_fu_614_p3;
+        select_ln38_reg_799 <= select_ln38_fu_571_p3;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_reg_834 == 1'd0) & (ap_enable_reg_pp3_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        out_loc_load_reg_848 <= out_loc_q0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln27_fu_433_p2 == 1'd1)) begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b1;
+    end else begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln28_fu_450_p2 == 1'd1)) begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b1;
+    end else begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln42_fu_692_p2 == 1'd1)) begin
+        ap_condition_pp3_exit_iter0_state26 = 1'b1;
+    end else begin
+        ap_condition_pp3_exit_iter0_state26 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state33))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp1_iter2 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0))) begin
+        ap_idle_pp1 = 1'b1;
+    end else begin
+        ap_idle_pp1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter0 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b0))) begin
+        ap_idle_pp3 = 1'b1;
+    end else begin
+        ap_idle_pp3 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln27_reg_748 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_phi_mux_phi_ln27_phi_fu_289_p4 = add_ln27_reg_752;
+    end else begin
+        ap_phi_mux_phi_ln27_phi_fu_289_p4 = phi_ln27_reg_285;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0) & (icmp_ln28_reg_762 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        ap_phi_mux_phi_ln28_phi_fu_301_p4 = add_ln28_reg_766;
+    end else begin
+        ap_phi_mux_phi_ln28_phi_fu_301_p4 = phi_ln28_reg_297;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state33))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_address0 = zext_ln38_1_fu_632_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_address0 = zext_ln27_fu_445_p1;
+    end else begin
+        in1_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state23) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_ce0 = 1'b1;
+    end else begin
+        in1_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_reg_748_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_we0 = 1'b1;
+    end else begin
+        in1_loc_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        in1_mem_ARVALID = 1'b1;
+    end else begin
+        in1_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_reg_748 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_RREADY = 1'b1;
+    end else begin
+        in1_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        in1_mem_blk_n_AR = m_axi_in1_mem_ARREADY;
+    end else begin
+        in1_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln27_reg_748 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_blk_n_R = m_axi_in1_mem_RVALID;
+    end else begin
+        in1_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in2_loc_address0 = sext_ln38_1_fu_655_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_address0 = zext_ln28_fu_462_p1;
+    end else begin
+        in2_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state23) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_ce0 = 1'b1;
+    end else begin
+        in2_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_reg_762_pp1_iter1_reg == 1'd0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_we0 = 1'b1;
+    end else begin
+        in2_loc_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+        in2_mem_ARVALID = 1'b1;
+    end else begin
+        in2_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_reg_762 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_RREADY = 1'b1;
+    end else begin
+        in2_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state12)) begin
+        in2_mem_blk_n_AR = m_axi_in2_mem_ARREADY;
+    end else begin
+        in2_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0) & (icmp_ln28_reg_762 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_blk_n_R = m_axi_in2_mem_RVALID;
+    end else begin
+        in2_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp3_stage0) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        out_loc_address0 = zext_ln42_fu_704_p1;
+    end else if ((1'b1 == ap_CS_fsm_state24)) begin
+        out_loc_address0 = out_loc_addr_reg_804;
+    end else if ((1'b1 == ap_CS_fsm_state23)) begin
+        out_loc_address0 = sext_ln38_fu_609_p1;
+    end else begin
+        out_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state24) | (1'b1 == ap_CS_fsm_state23) | ((1'b0 == ap_block_pp3_stage0_11001) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0)))) begin
+        out_loc_ce0 = 1'b1;
+    end else begin
+        out_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        out_loc_we0 = 1'b1;
+    end else begin
+        out_loc_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+        out_mem_AWVALID = 1'b1;
+    end else begin
+        out_mem_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state33))) begin
+        out_mem_BREADY = 1'b1;
+    end else begin
+        out_mem_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_reg_834_pp3_iter1_reg == 1'd0) & (ap_enable_reg_pp3_iter2 == 1'b1))) begin
+        out_mem_WVALID = 1'b1;
+    end else begin
+        out_mem_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        out_mem_blk_n_AW = m_axi_out_mem_AWREADY;
+    end else begin
+        out_mem_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state33)) begin
+        out_mem_blk_n_B = m_axi_out_mem_BVALID;
+    end else begin
+        out_mem_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp3_stage0) & (icmp_ln42_reg_834_pp3_iter1_reg == 1'd0) & (ap_enable_reg_pp3_iter2 == 1'b1))) begin
+        out_mem_blk_n_W = m_axi_out_mem_WREADY;
+    end else begin
+        out_mem_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        ap_ST_fsm_pp0_stage0 : begin
+            if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln27_fu_433_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln27_fu_433_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end
+        end
+        ap_ST_fsm_state12 : begin
+            if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+                ap_NS_fsm = ap_ST_fsm_state13;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end
+        end
+        ap_ST_fsm_state13 : begin
+            ap_NS_fsm = ap_ST_fsm_state14;
+        end
+        ap_ST_fsm_state14 : begin
+            ap_NS_fsm = ap_ST_fsm_state15;
+        end
+        ap_ST_fsm_state15 : begin
+            ap_NS_fsm = ap_ST_fsm_state16;
+        end
+        ap_ST_fsm_state16 : begin
+            ap_NS_fsm = ap_ST_fsm_state17;
+        end
+        ap_ST_fsm_state17 : begin
+            ap_NS_fsm = ap_ST_fsm_state18;
+        end
+        ap_ST_fsm_state18 : begin
+            ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+        end
+        ap_ST_fsm_pp1_stage0 : begin
+            if ((~((1'b0 == ap_block_pp1_stage0_subdone) & (icmp_ln28_fu_450_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end else if ((((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp1_stage0_subdone) & (icmp_ln28_fu_450_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_state22;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end
+        end
+        ap_ST_fsm_state22 : begin
+            ap_NS_fsm = ap_ST_fsm_state23;
+        end
+        ap_ST_fsm_state23 : begin
+            if (((icmp_ln31_fu_491_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+                ap_NS_fsm = ap_ST_fsm_state24;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state25;
+            end
+        end
+        ap_ST_fsm_state24 : begin
+            ap_NS_fsm = ap_ST_fsm_state23;
+        end
+        ap_ST_fsm_state25 : begin
+            if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state25))) begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state25;
+            end
+        end
+        ap_ST_fsm_pp3_stage0 : begin
+            if ((~((1'b0 == ap_block_pp3_stage0_subdone) & (ap_enable_reg_pp3_iter1 == 1'b0) & (icmp_ln42_fu_692_p2 == 1'd1) & (ap_enable_reg_pp3_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp3_stage0_subdone) & (ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end else if ((((1'b0 == ap_block_pp3_stage0_subdone) & (ap_enable_reg_pp3_iter1 == 1'b0) & (icmp_ln42_fu_692_p2 == 1'd1) & (ap_enable_reg_pp3_iter0 == 1'b1)) | ((1'b0 == ap_block_pp3_stage0_subdone) & (ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_state29;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end
+        end
+        ap_ST_fsm_state29 : begin
+            ap_NS_fsm = ap_ST_fsm_state30;
+        end
+        ap_ST_fsm_state30 : begin
+            ap_NS_fsm = ap_ST_fsm_state31;
+        end
+        ap_ST_fsm_state31 : begin
+            ap_NS_fsm = ap_ST_fsm_state32;
+        end
+        ap_ST_fsm_state32 : begin
+            ap_NS_fsm = ap_ST_fsm_state33;
+        end
+        ap_ST_fsm_state33 : begin
+            if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state33))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state33;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln27_fu_439_p2 = (ap_phi_mux_phi_ln27_phi_fu_289_p4 + 13'd1);
+
+assign add_ln28_fu_456_p2 = (ap_phi_mux_phi_ln28_phi_fu_301_p4 + 13'd1);
+
+assign add_ln31_fu_496_p2 = (indvar_flatten15_reg_309 + 70'd1);
+
+assign add_ln33_fu_660_p2 = (39'd1 + indvar_flatten_reg_331);
+
+assign add_ln38_1_fu_603_p2 = (zext_ln38_cast_fu_533_p3 + select_ln38_1_fu_595_p3);
+
+assign add_ln38_2_fu_626_p2 = (zext_ln38_cast_fu_533_p3 + zext_ln38_fu_622_p1);
+
+assign add_ln38_3_fu_649_p2 = (zext_ln38_2_fu_645_p1 + select_ln38_1_fu_595_p3);
+
+assign add_ln42_fu_698_p2 = (phi_ln42_reg_364 + 13'd1);
+
+assign and_ln31_fu_553_p2 = (xor_ln31_fu_541_p2 & icmp_ln35_fu_547_p2);
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd8];
+
+assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd16];
+
+assign ap_CS_fsm_pp3_stage0 = ap_CS_fsm[32'd21];
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state12 = ap_CS_fsm[32'd9];
+
+assign ap_CS_fsm_state18 = ap_CS_fsm[32'd15];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state22 = ap_CS_fsm[32'd17];
+
+assign ap_CS_fsm_state23 = ap_CS_fsm[32'd18];
+
+assign ap_CS_fsm_state24 = ap_CS_fsm[32'd19];
+
+assign ap_CS_fsm_state25 = ap_CS_fsm[32'd20];
+
+assign ap_CS_fsm_state33 = ap_CS_fsm[32'd26];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = ((in1_mem_RVALID == 1'b0) & (icmp_ln27_reg_748 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = ((in1_mem_RVALID == 1'b0) & (icmp_ln27_reg_748 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp1_stage0_11001 = ((in2_mem_RVALID == 1'b0) & (icmp_ln28_reg_762 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp1_stage0_subdone = ((in2_mem_RVALID == 1'b0) & (icmp_ln28_reg_762 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+assign ap_block_pp3_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp3_stage0_01001 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp3_stage0_11001 = ((1'b1 == ap_block_state28_io) & (ap_enable_reg_pp3_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp3_stage0_subdone = ((1'b1 == ap_block_state28_io) & (ap_enable_reg_pp3_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state10_pp0_stage0_iter1 = ((in1_mem_RVALID == 1'b0) & (icmp_ln27_reg_748 == 1'd0));
+end
+
+assign ap_block_state11_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state20_pp1_stage0_iter1 = ((in2_mem_RVALID == 1'b0) & (icmp_ln28_reg_762 == 1'd0));
+end
+
+assign ap_block_state21_pp1_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state26_pp3_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state27_pp3_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state28_io = ((out_mem_WREADY == 1'b0) & (icmp_ln42_reg_834_pp3_iter1_reg == 1'd0));
+end
+
+assign ap_block_state28_pp3_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state9_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
+
+assign ap_enable_pp3 = (ap_idle_pp3 ^ 1'b1);
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign empty_5_fu_424_p1 = in_reg_720;
+
+assign empty_6_fu_405_p1 = in3_reg_725;
+
+assign empty_fu_415_p1 = out5_reg_715;
+
+assign i_fu_502_p2 = (31'd1 + i_0_reg_320);
+
+assign icmp_ln27_fu_433_p2 = ((ap_phi_mux_phi_ln27_phi_fu_289_p4 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln28_fu_450_p2 = ((ap_phi_mux_phi_ln28_phi_fu_301_p4 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln31_fu_491_p2 = ((indvar_flatten15_reg_309 == mul_ln31_reg_781) ? 1'b1 : 1'b0);
+
+assign icmp_ln33_fu_508_p2 = ((indvar_flatten_reg_331 == zext_ln31_reg_776) ? 1'b1 : 1'b0);
+
+assign icmp_ln35_fu_547_p2 = ((k_0_reg_353 == 7'd64) ? 1'b1 : 1'b0);
+
+assign icmp_ln42_fu_692_p2 = ((phi_ln42_reg_364 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign in1_mem_ARADDR = empty_6_fu_405_p1;
+
+assign j_fu_559_p2 = (32'd1 + select_ln31_fu_513_p3);
+
+assign k_fu_687_p2 = (7'd1 + select_ln38_reg_799);
+
+assign mul_ln31_fu_485_p0 = mul_ln31_fu_485_p00;
+
+assign mul_ln31_fu_485_p00 = dim_read_reg_709;
+
+assign mul_ln31_fu_485_p1 = mul_ln31_fu_485_p10;
+
+assign mul_ln31_fu_485_p10 = tmp_fu_467_p3;
+
+assign mul_ln31_fu_485_p2 = (mul_ln31_fu_485_p0 * mul_ln31_fu_485_p1);
+
+assign mul_ln38_fu_674_p0 = in2_loc_q0;
+
+assign mul_ln38_fu_674_p1 = in1_loc_q0;
+
+assign mul_ln38_fu_674_p2 = ($signed(mul_ln38_fu_674_p0) * $signed(mul_ln38_fu_674_p1));
+
+assign or_ln38_fu_565_p2 = (icmp_ln33_fu_508_p2 | and_ln31_fu_553_p2);
+
+assign out_loc_d0 = (mul_ln38_fu_674_p2 + out_loc_q0);
+
+assign select_ln31_1_fu_521_p3 = ((icmp_ln33_fu_508_p2[0:0] === 1'b1) ? i_fu_502_p2 : i_0_reg_320);
+
+assign select_ln31_2_fu_587_p3 = ((icmp_ln33_fu_508_p2[0:0] === 1'b1) ? 14'd0 : trunc_ln38_2_fu_583_p1);
+
+assign select_ln31_fu_513_p3 = ((icmp_ln33_fu_508_p2[0:0] === 1'b1) ? 32'd0 : j_0_reg_342);
+
+assign select_ln33_1_fu_666_p3 = ((icmp_ln33_fu_508_p2[0:0] === 1'b1) ? 39'd1 : add_ln33_fu_660_p2);
+
+assign select_ln33_fu_614_p3 = ((and_ln31_fu_553_p2[0:0] === 1'b1) ? j_fu_559_p2 : select_ln31_fu_513_p3);
+
+assign select_ln38_1_fu_595_p3 = ((and_ln31_fu_553_p2[0:0] === 1'b1) ? trunc_ln38_1_fu_579_p1 : select_ln31_2_fu_587_p3);
+
+assign select_ln38_fu_571_p3 = ((or_ln38_fu_565_p2[0:0] === 1'b1) ? 7'd0 : k_0_reg_353);
+
+assign sext_ln38_1_fu_655_p1 = $signed(add_ln38_3_fu_649_p2);
+
+assign sext_ln38_fu_609_p1 = $signed(add_ln38_1_fu_603_p2);
+
+assign tmp_3_fu_637_p3 = {{select_ln38_fu_571_p3}, {6'd0}};
+
+assign tmp_fu_467_p3 = {{dim_read_reg_709}, {6'd0}};
+
+assign trunc_ln38_1_fu_579_p1 = j_fu_559_p2[13:0];
+
+assign trunc_ln38_2_fu_583_p1 = j_0_reg_342[13:0];
+
+assign trunc_ln38_fu_529_p1 = select_ln31_1_fu_521_p3[7:0];
+
+assign xor_ln31_fu_541_p2 = (icmp_ln33_fu_508_p2 ^ 1'd1);
+
+assign zext_ln27_fu_445_p1 = phi_ln27_reg_285_pp0_iter1_reg;
+
+assign zext_ln28_fu_462_p1 = phi_ln28_reg_297_pp1_iter1_reg;
+
+assign zext_ln31_fu_474_p1 = tmp_fu_467_p3;
+
+assign zext_ln38_1_fu_632_p1 = add_ln38_2_fu_626_p2;
+
+assign zext_ln38_2_fu_645_p1 = tmp_3_fu_637_p3;
+
+assign zext_ln38_cast_fu_533_p3 = {{trunc_ln38_fu_529_p1}, {6'd0}};
+
+assign zext_ln38_fu_622_p1 = select_ln38_fu_571_p3;
+
+assign zext_ln42_fu_704_p1 = phi_ln42_reg_364;
+
+always @ (posedge ap_clk) begin
+    out_mem_addr_reg_736[31:30] <= 2'b00;
+    in2_mem_addr_reg_742[31:30] <= 2'b00;
+    zext_ln31_reg_776[5:0] <= 6'b000000;
+    zext_ln31_reg_776[38] <= 1'b0;
+    mul_ln31_reg_781[5:0] <= 6'b000000;
+end
+
+endmodule //mmult
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in1_loc.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in1_loc.v
new file mode 100755
index 0000000..900452c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in1_loc.v
@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_in1_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_in1_loc_ram mmult_in1_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in1_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in1_mem_m_axi.v
new file mode 100755
index 0000000..81f7248
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in1_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in1_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in1_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in1_mem_m_axi_write
+mmult_in1_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in1_mem_m_axi_read
+mmult_in1_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in1_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in1_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in1_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in1_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in1_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in2_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in2_mem_m_axi.v
new file mode 100755
index 0000000..a2eab07
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in2_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in2_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in2_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in2_mem_m_axi_write
+mmult_in2_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in2_mem_m_axi_read
+mmult_in2_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in2_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in2_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in2_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in2_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in2_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_out_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_out_mem_m_axi.v
new file mode 100755
index 0000000..cc472db
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_out_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_out_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_out_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_out_mem_m_axi_write
+mmult_out_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_out_mem_m_axi_read
+mmult_out_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_out_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_out_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_out_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_out_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_out_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_params_s_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_params_s_axi.v
new file mode 100755
index 0000000..d470352
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_params_s_axi.v
@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult.vhd
new file mode 100755
index 0000000..2d2d93d
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult.vhd
@@ -0,0 +1,2337 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+-- Version: 2020.1
+-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult is
+generic (
+    C_M_AXI_IN1_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_S_AXI_PARAMS_ADDR_WIDTH : INTEGER := 6;
+    C_S_AXI_PARAMS_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_IN2_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_OUT_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_CACHE_VALUE : INTEGER := 3 );
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    m_axi_in1_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in1_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_WREADY : IN STD_LOGIC;
+    m_axi_in1_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in1_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in1_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in1_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RVALID : IN STD_LOGIC;
+    m_axi_in1_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_RLAST : IN STD_LOGIC;
+    m_axi_in1_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BVALID : IN STD_LOGIC;
+    m_axi_in1_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in2_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_WREADY : IN STD_LOGIC;
+    m_axi_in2_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in2_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in2_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in2_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RVALID : IN STD_LOGIC;
+    m_axi_in2_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_RLAST : IN STD_LOGIC;
+    m_axi_in2_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BVALID : IN STD_LOGIC;
+    m_axi_in2_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_out_mem_AWREADY : IN STD_LOGIC;
+    m_axi_out_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_WVALID : OUT STD_LOGIC;
+    m_axi_out_mem_WREADY : IN STD_LOGIC;
+    m_axi_out_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_out_mem_WLAST : OUT STD_LOGIC;
+    m_axi_out_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_out_mem_ARREADY : IN STD_LOGIC;
+    m_axi_out_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RVALID : IN STD_LOGIC;
+    m_axi_out_mem_RREADY : OUT STD_LOGIC;
+    m_axi_out_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_RLAST : IN STD_LOGIC;
+    m_axi_out_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BVALID : IN STD_LOGIC;
+    m_axi_out_mem_BREADY : OUT STD_LOGIC;
+    m_axi_out_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_BUSER_WIDTH-1 downto 0);
+    s_axi_params_AWVALID : IN STD_LOGIC;
+    s_axi_params_AWREADY : OUT STD_LOGIC;
+    s_axi_params_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_WVALID : IN STD_LOGIC;
+    s_axi_params_WREADY : OUT STD_LOGIC;
+    s_axi_params_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH/8-1 downto 0);
+    s_axi_params_ARVALID : IN STD_LOGIC;
+    s_axi_params_ARREADY : OUT STD_LOGIC;
+    s_axi_params_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_RVALID : OUT STD_LOGIC;
+    s_axi_params_RREADY : IN STD_LOGIC;
+    s_axi_params_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    s_axi_params_BVALID : OUT STD_LOGIC;
+    s_axi_params_BREADY : IN STD_LOGIC;
+    s_axi_params_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    interrupt : OUT STD_LOGIC );
+end;
+
+
+architecture behav of mmult is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=536604,HLS_SYN_TPT=none,HLS_SYN_MEM=30,HLS_SYN_DSP=8,HLS_SYN_FF=2601,HLS_SYN_LUT=3166,HLS_VERSION=2020_1}";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000000000001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000000000010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000000000100";
+    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000000001000";
+    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000000010000";
+    constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000000100000";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000001000000";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000010000000";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000100000000";
+    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000001000000000";
+    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000010000000000";
+    constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000100000000000";
+    constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000001000000000000";
+    constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000010000000000000";
+    constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000100000000000000";
+    constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (26 downto 0) := "000000000001000000000000000";
+    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (26 downto 0) := "000000000010000000000000000";
+    constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (26 downto 0) := "000000000100000000000000000";
+    constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (26 downto 0) := "000000001000000000000000000";
+    constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (26 downto 0) := "000000010000000000000000000";
+    constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (26 downto 0) := "000000100000000000000000000";
+    constant ap_ST_fsm_pp3_stage0 : STD_LOGIC_VECTOR (26 downto 0) := "000001000000000000000000000";
+    constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (26 downto 0) := "000010000000000000000000000";
+    constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (26 downto 0) := "000100000000000000000000000";
+    constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (26 downto 0) := "001000000000000000000000000";
+    constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (26 downto 0) := "010000000000000000000000000";
+    constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (26 downto 0) := "100000000000000000000000000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
+    constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
+    constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
+    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
+    constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
+    constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
+    constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
+    constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
+    constant ap_const_lv70_0 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
+    constant ap_const_lv39_0 : STD_LOGIC_VECTOR (38 downto 0) := "000000000000000000000000000000000000000";
+    constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
+    constant ap_const_lv32_1000 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000001000000000000";
+    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
+    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv13_1000 : STD_LOGIC_VECTOR (12 downto 0) := "1000000000000";
+    constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
+    constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
+    constant ap_const_lv70_1 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
+    constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
+    constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
+    constant ap_const_lv39_1 : STD_LOGIC_VECTOR (38 downto 0) := "000000000000000000000000000000000000001";
+    constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal ap_start : STD_LOGIC;
+    signal ap_done : STD_LOGIC;
+    signal ap_idle : STD_LOGIC;
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000000000001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal ap_ready : STD_LOGIC;
+    signal in1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_r : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal in1_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal icmp_ln27_reg_748 : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state12 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
+    signal in2_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
+    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp1_stage0 : BOOLEAN;
+    signal icmp_ln28_reg_762 : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_AW : STD_LOGIC;
+    signal ap_CS_fsm_state25 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
+    signal out_mem_blk_n_W : STD_LOGIC;
+    signal ap_enable_reg_pp3_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp3_stage0 : BOOLEAN;
+    signal icmp_ln42_reg_834 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln42_reg_834_pp3_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_B : STD_LOGIC;
+    signal ap_CS_fsm_state33 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
+    signal in1_mem_AWREADY : STD_LOGIC;
+    signal in1_mem_WREADY : STD_LOGIC;
+    signal in1_mem_ARVALID : STD_LOGIC;
+    signal in1_mem_ARREADY : STD_LOGIC;
+    signal in1_mem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RVALID : STD_LOGIC;
+    signal in1_mem_RREADY : STD_LOGIC;
+    signal in1_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RLAST : STD_LOGIC;
+    signal in1_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BVALID : STD_LOGIC;
+    signal in1_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_AWREADY : STD_LOGIC;
+    signal in2_mem_WREADY : STD_LOGIC;
+    signal in2_mem_ARVALID : STD_LOGIC;
+    signal in2_mem_ARREADY : STD_LOGIC;
+    signal in2_mem_RVALID : STD_LOGIC;
+    signal in2_mem_RREADY : STD_LOGIC;
+    signal in2_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_RLAST : STD_LOGIC;
+    signal in2_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BVALID : STD_LOGIC;
+    signal in2_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_AWVALID : STD_LOGIC;
+    signal out_mem_AWREADY : STD_LOGIC;
+    signal out_mem_WVALID : STD_LOGIC;
+    signal out_mem_WREADY : STD_LOGIC;
+    signal out_mem_ARREADY : STD_LOGIC;
+    signal out_mem_RVALID : STD_LOGIC;
+    signal out_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_RLAST : STD_LOGIC;
+    signal out_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BVALID : STD_LOGIC;
+    signal out_mem_BREADY : STD_LOGIC;
+    signal out_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal phi_ln27_reg_285 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln27_reg_285_pp0_iter1_reg : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_block_state9_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state11_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal phi_ln28_reg_297 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln28_reg_297_pp1_iter1_reg : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_block_state19_pp1_stage0_iter0 : BOOLEAN;
+    signal ap_block_state20_pp1_stage0_iter1 : BOOLEAN;
+    signal ap_block_state21_pp1_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp1_stage0_11001 : BOOLEAN;
+    signal phi_ln42_reg_364 : STD_LOGIC_VECTOR (12 downto 0);
+    signal dim_read_reg_709 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out5_reg_715 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in_reg_720 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in3_reg_725 : STD_LOGIC_VECTOR (29 downto 0);
+    signal out_mem_addr_reg_736 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
+    signal in2_mem_addr_reg_742 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln27_fu_433_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln27_reg_748_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln27_fu_439_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal add_ln27_reg_752 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal in1_mem_addr_read_reg_757 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln28_fu_450_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln28_reg_762_pp1_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln28_fu_456_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal add_ln28_reg_766 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
+    signal in2_mem_addr_read_reg_771 : STD_LOGIC_VECTOR (31 downto 0);
+    signal zext_ln31_fu_474_p1 : STD_LOGIC_VECTOR (38 downto 0);
+    signal zext_ln31_reg_776 : STD_LOGIC_VECTOR (38 downto 0);
+    signal ap_CS_fsm_state22 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
+    signal mul_ln31_fu_485_p2 : STD_LOGIC_VECTOR (69 downto 0);
+    signal mul_ln31_reg_781 : STD_LOGIC_VECTOR (69 downto 0);
+    signal add_ln31_fu_496_p2 : STD_LOGIC_VECTOR (69 downto 0);
+    signal add_ln31_reg_789 : STD_LOGIC_VECTOR (69 downto 0);
+    signal ap_CS_fsm_state23 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state23 : signal is "none";
+    signal select_ln31_1_fu_521_p3 : STD_LOGIC_VECTOR (30 downto 0);
+    signal select_ln31_1_reg_794 : STD_LOGIC_VECTOR (30 downto 0);
+    signal icmp_ln31_fu_491_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal select_ln38_fu_571_p3 : STD_LOGIC_VECTOR (6 downto 0);
+    signal select_ln38_reg_799 : STD_LOGIC_VECTOR (6 downto 0);
+    signal out_loc_addr_reg_804 : STD_LOGIC_VECTOR (11 downto 0);
+    signal select_ln33_fu_614_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln33_reg_809 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln33_1_fu_666_p3 : STD_LOGIC_VECTOR (38 downto 0);
+    signal select_ln33_1_reg_824 : STD_LOGIC_VECTOR (38 downto 0);
+    signal k_fu_687_p2 : STD_LOGIC_VECTOR (6 downto 0);
+    signal ap_CS_fsm_state24 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state24 : signal is "none";
+    signal icmp_ln42_fu_692_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp3_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp3_stage0 : signal is "none";
+    signal ap_block_state26_pp3_stage0_iter0 : BOOLEAN;
+    signal ap_block_state27_pp3_stage0_iter1 : BOOLEAN;
+    signal ap_block_state28_pp3_stage0_iter2 : BOOLEAN;
+    signal ap_block_state28_io : BOOLEAN;
+    signal ap_block_pp3_stage0_11001 : BOOLEAN;
+    signal add_ln42_fu_698_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp3_iter0 : STD_LOGIC := '0';
+    signal out_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_load_reg_848 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp3_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state9 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_CS_fsm_state18 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
+    signal ap_block_pp1_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp1_exit_iter0_state19 : STD_LOGIC;
+    signal ap_enable_reg_pp1_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp3_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp3_exit_iter0_state26 : STD_LOGIC;
+    signal in1_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal in1_loc_ce0 : STD_LOGIC;
+    signal in1_loc_we0 : STD_LOGIC;
+    signal in1_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal in2_loc_ce0 : STD_LOGIC;
+    signal in2_loc_we0 : STD_LOGIC;
+    signal in2_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_ce0 : STD_LOGIC;
+    signal out_loc_we0 : STD_LOGIC;
+    signal out_loc_d0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_phi_mux_phi_ln27_phi_fu_289_p4 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_phi_mux_phi_ln28_phi_fu_301_p4 : STD_LOGIC_VECTOR (12 downto 0);
+    signal indvar_flatten15_reg_309 : STD_LOGIC_VECTOR (69 downto 0);
+    signal i_0_reg_320 : STD_LOGIC_VECTOR (30 downto 0);
+    signal indvar_flatten_reg_331 : STD_LOGIC_VECTOR (38 downto 0);
+    signal j_0_reg_342 : STD_LOGIC_VECTOR (31 downto 0);
+    signal k_0_reg_353 : STD_LOGIC_VECTOR (6 downto 0);
+    signal zext_ln27_fu_445_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln28_fu_462_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_fu_609_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln38_1_fu_632_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_1_fu_655_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln42_fu_704_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_6_fu_405_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_fu_415_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_5_fu_424_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp3_stage0_01001 : BOOLEAN;
+    signal tmp_fu_467_p3 : STD_LOGIC_VECTOR (37 downto 0);
+    signal mul_ln31_fu_485_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln31_fu_485_p1 : STD_LOGIC_VECTOR (37 downto 0);
+    signal icmp_ln33_fu_508_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal i_fu_502_p2 : STD_LOGIC_VECTOR (30 downto 0);
+    signal trunc_ln38_fu_529_p1 : STD_LOGIC_VECTOR (7 downto 0);
+    signal icmp_ln35_fu_547_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal xor_ln31_fu_541_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal select_ln31_fu_513_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal and_ln31_fu_553_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal or_ln38_fu_565_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_fu_559_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal trunc_ln38_2_fu_583_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal trunc_ln38_1_fu_579_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal select_ln31_2_fu_587_p3 : STD_LOGIC_VECTOR (13 downto 0);
+    signal zext_ln38_cast_fu_533_p3 : STD_LOGIC_VECTOR (13 downto 0);
+    signal select_ln38_1_fu_595_p3 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_1_fu_603_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal zext_ln38_fu_622_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_2_fu_626_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal tmp_3_fu_637_p3 : STD_LOGIC_VECTOR (12 downto 0);
+    signal zext_ln38_2_fu_645_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_3_fu_649_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln33_fu_660_p2 : STD_LOGIC_VECTOR (38 downto 0);
+    signal mul_ln38_fu_674_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_fu_674_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_fu_674_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (26 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal ap_idle_pp1 : STD_LOGIC;
+    signal ap_enable_pp1 : STD_LOGIC;
+    signal ap_idle_pp3 : STD_LOGIC;
+    signal ap_enable_pp3 : STD_LOGIC;
+    signal mul_ln31_fu_485_p00 : STD_LOGIC_VECTOR (69 downto 0);
+    signal mul_ln31_fu_485_p10 : STD_LOGIC_VECTOR (69 downto 0);
+
+    component mmult_in1_loc IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_params_s_axi IS
+    generic (
+        C_S_AXI_ADDR_WIDTH : INTEGER;
+        C_S_AXI_DATA_WIDTH : INTEGER );
+    port (
+        AWVALID : IN STD_LOGIC;
+        AWREADY : OUT STD_LOGIC;
+        AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        WVALID : IN STD_LOGIC;
+        WREADY : OUT STD_LOGIC;
+        WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
+        ARVALID : IN STD_LOGIC;
+        ARREADY : OUT STD_LOGIC;
+        ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        RVALID : OUT STD_LOGIC;
+        RREADY : IN STD_LOGIC;
+        RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : OUT STD_LOGIC;
+        BREADY : IN STD_LOGIC;
+        BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        ap_start : OUT STD_LOGIC;
+        interrupt : OUT STD_LOGIC;
+        ap_ready : IN STD_LOGIC;
+        ap_done : IN STD_LOGIC;
+        ap_idle : IN STD_LOGIC;
+        in1 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        in2 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        out_r : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dim : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_in2_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_out_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+
+begin
+    mmult_params_s_axi_U : component mmult_params_s_axi
+    generic map (
+        C_S_AXI_ADDR_WIDTH => C_S_AXI_PARAMS_ADDR_WIDTH,
+        C_S_AXI_DATA_WIDTH => C_S_AXI_PARAMS_DATA_WIDTH)
+    port map (
+        AWVALID => s_axi_params_AWVALID,
+        AWREADY => s_axi_params_AWREADY,
+        AWADDR => s_axi_params_AWADDR,
+        WVALID => s_axi_params_WVALID,
+        WREADY => s_axi_params_WREADY,
+        WDATA => s_axi_params_WDATA,
+        WSTRB => s_axi_params_WSTRB,
+        ARVALID => s_axi_params_ARVALID,
+        ARREADY => s_axi_params_ARREADY,
+        ARADDR => s_axi_params_ARADDR,
+        RVALID => s_axi_params_RVALID,
+        RREADY => s_axi_params_RREADY,
+        RDATA => s_axi_params_RDATA,
+        RRESP => s_axi_params_RRESP,
+        BVALID => s_axi_params_BVALID,
+        BREADY => s_axi_params_BREADY,
+        BRESP => s_axi_params_BRESP,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        ap_start => ap_start,
+        interrupt => interrupt,
+        ap_ready => ap_ready,
+        ap_done => ap_done,
+        ap_idle => ap_idle,
+        in1 => in1,
+        in2 => in2,
+        out_r => out_r,
+        dim => dim);
+
+    mmult_in1_mem_m_axi_U : component mmult_in1_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN1_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN1_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN1_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN1_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN1_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN1_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN1_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN1_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN1_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN1_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN1_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in1_mem_AWVALID,
+        AWREADY => m_axi_in1_mem_AWREADY,
+        AWADDR => m_axi_in1_mem_AWADDR,
+        AWID => m_axi_in1_mem_AWID,
+        AWLEN => m_axi_in1_mem_AWLEN,
+        AWSIZE => m_axi_in1_mem_AWSIZE,
+        AWBURST => m_axi_in1_mem_AWBURST,
+        AWLOCK => m_axi_in1_mem_AWLOCK,
+        AWCACHE => m_axi_in1_mem_AWCACHE,
+        AWPROT => m_axi_in1_mem_AWPROT,
+        AWQOS => m_axi_in1_mem_AWQOS,
+        AWREGION => m_axi_in1_mem_AWREGION,
+        AWUSER => m_axi_in1_mem_AWUSER,
+        WVALID => m_axi_in1_mem_WVALID,
+        WREADY => m_axi_in1_mem_WREADY,
+        WDATA => m_axi_in1_mem_WDATA,
+        WSTRB => m_axi_in1_mem_WSTRB,
+        WLAST => m_axi_in1_mem_WLAST,
+        WID => m_axi_in1_mem_WID,
+        WUSER => m_axi_in1_mem_WUSER,
+        ARVALID => m_axi_in1_mem_ARVALID,
+        ARREADY => m_axi_in1_mem_ARREADY,
+        ARADDR => m_axi_in1_mem_ARADDR,
+        ARID => m_axi_in1_mem_ARID,
+        ARLEN => m_axi_in1_mem_ARLEN,
+        ARSIZE => m_axi_in1_mem_ARSIZE,
+        ARBURST => m_axi_in1_mem_ARBURST,
+        ARLOCK => m_axi_in1_mem_ARLOCK,
+        ARCACHE => m_axi_in1_mem_ARCACHE,
+        ARPROT => m_axi_in1_mem_ARPROT,
+        ARQOS => m_axi_in1_mem_ARQOS,
+        ARREGION => m_axi_in1_mem_ARREGION,
+        ARUSER => m_axi_in1_mem_ARUSER,
+        RVALID => m_axi_in1_mem_RVALID,
+        RREADY => m_axi_in1_mem_RREADY,
+        RDATA => m_axi_in1_mem_RDATA,
+        RLAST => m_axi_in1_mem_RLAST,
+        RID => m_axi_in1_mem_RID,
+        RUSER => m_axi_in1_mem_RUSER,
+        RRESP => m_axi_in1_mem_RRESP,
+        BVALID => m_axi_in1_mem_BVALID,
+        BREADY => m_axi_in1_mem_BREADY,
+        BRESP => m_axi_in1_mem_BRESP,
+        BID => m_axi_in1_mem_BID,
+        BUSER => m_axi_in1_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in1_mem_ARVALID,
+        I_ARREADY => in1_mem_ARREADY,
+        I_ARADDR => in1_mem_ARADDR,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in1_mem_RVALID,
+        I_RREADY => in1_mem_RREADY,
+        I_RDATA => in1_mem_RDATA,
+        I_RID => in1_mem_RID,
+        I_RUSER => in1_mem_RUSER,
+        I_RRESP => in1_mem_RRESP,
+        I_RLAST => in1_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in1_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in1_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in1_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in1_mem_BRESP,
+        I_BID => in1_mem_BID,
+        I_BUSER => in1_mem_BUSER);
+
+    mmult_in2_mem_m_axi_U : component mmult_in2_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN2_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN2_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN2_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN2_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN2_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN2_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN2_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN2_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN2_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN2_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN2_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in2_mem_AWVALID,
+        AWREADY => m_axi_in2_mem_AWREADY,
+        AWADDR => m_axi_in2_mem_AWADDR,
+        AWID => m_axi_in2_mem_AWID,
+        AWLEN => m_axi_in2_mem_AWLEN,
+        AWSIZE => m_axi_in2_mem_AWSIZE,
+        AWBURST => m_axi_in2_mem_AWBURST,
+        AWLOCK => m_axi_in2_mem_AWLOCK,
+        AWCACHE => m_axi_in2_mem_AWCACHE,
+        AWPROT => m_axi_in2_mem_AWPROT,
+        AWQOS => m_axi_in2_mem_AWQOS,
+        AWREGION => m_axi_in2_mem_AWREGION,
+        AWUSER => m_axi_in2_mem_AWUSER,
+        WVALID => m_axi_in2_mem_WVALID,
+        WREADY => m_axi_in2_mem_WREADY,
+        WDATA => m_axi_in2_mem_WDATA,
+        WSTRB => m_axi_in2_mem_WSTRB,
+        WLAST => m_axi_in2_mem_WLAST,
+        WID => m_axi_in2_mem_WID,
+        WUSER => m_axi_in2_mem_WUSER,
+        ARVALID => m_axi_in2_mem_ARVALID,
+        ARREADY => m_axi_in2_mem_ARREADY,
+        ARADDR => m_axi_in2_mem_ARADDR,
+        ARID => m_axi_in2_mem_ARID,
+        ARLEN => m_axi_in2_mem_ARLEN,
+        ARSIZE => m_axi_in2_mem_ARSIZE,
+        ARBURST => m_axi_in2_mem_ARBURST,
+        ARLOCK => m_axi_in2_mem_ARLOCK,
+        ARCACHE => m_axi_in2_mem_ARCACHE,
+        ARPROT => m_axi_in2_mem_ARPROT,
+        ARQOS => m_axi_in2_mem_ARQOS,
+        ARREGION => m_axi_in2_mem_ARREGION,
+        ARUSER => m_axi_in2_mem_ARUSER,
+        RVALID => m_axi_in2_mem_RVALID,
+        RREADY => m_axi_in2_mem_RREADY,
+        RDATA => m_axi_in2_mem_RDATA,
+        RLAST => m_axi_in2_mem_RLAST,
+        RID => m_axi_in2_mem_RID,
+        RUSER => m_axi_in2_mem_RUSER,
+        RRESP => m_axi_in2_mem_RRESP,
+        BVALID => m_axi_in2_mem_BVALID,
+        BREADY => m_axi_in2_mem_BREADY,
+        BRESP => m_axi_in2_mem_BRESP,
+        BID => m_axi_in2_mem_BID,
+        BUSER => m_axi_in2_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in2_mem_ARVALID,
+        I_ARREADY => in2_mem_ARREADY,
+        I_ARADDR => in2_mem_addr_reg_742,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in2_mem_RVALID,
+        I_RREADY => in2_mem_RREADY,
+        I_RDATA => in2_mem_RDATA,
+        I_RID => in2_mem_RID,
+        I_RUSER => in2_mem_RUSER,
+        I_RRESP => in2_mem_RRESP,
+        I_RLAST => in2_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in2_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in2_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in2_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in2_mem_BRESP,
+        I_BID => in2_mem_BID,
+        I_BUSER => in2_mem_BUSER);
+
+    mmult_out_mem_m_axi_U : component mmult_out_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_OUT_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_OUT_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_OUT_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_OUT_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_OUT_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_OUT_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_OUT_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_OUT_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_OUT_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_OUT_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_OUT_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_out_mem_AWVALID,
+        AWREADY => m_axi_out_mem_AWREADY,
+        AWADDR => m_axi_out_mem_AWADDR,
+        AWID => m_axi_out_mem_AWID,
+        AWLEN => m_axi_out_mem_AWLEN,
+        AWSIZE => m_axi_out_mem_AWSIZE,
+        AWBURST => m_axi_out_mem_AWBURST,
+        AWLOCK => m_axi_out_mem_AWLOCK,
+        AWCACHE => m_axi_out_mem_AWCACHE,
+        AWPROT => m_axi_out_mem_AWPROT,
+        AWQOS => m_axi_out_mem_AWQOS,
+        AWREGION => m_axi_out_mem_AWREGION,
+        AWUSER => m_axi_out_mem_AWUSER,
+        WVALID => m_axi_out_mem_WVALID,
+        WREADY => m_axi_out_mem_WREADY,
+        WDATA => m_axi_out_mem_WDATA,
+        WSTRB => m_axi_out_mem_WSTRB,
+        WLAST => m_axi_out_mem_WLAST,
+        WID => m_axi_out_mem_WID,
+        WUSER => m_axi_out_mem_WUSER,
+        ARVALID => m_axi_out_mem_ARVALID,
+        ARREADY => m_axi_out_mem_ARREADY,
+        ARADDR => m_axi_out_mem_ARADDR,
+        ARID => m_axi_out_mem_ARID,
+        ARLEN => m_axi_out_mem_ARLEN,
+        ARSIZE => m_axi_out_mem_ARSIZE,
+        ARBURST => m_axi_out_mem_ARBURST,
+        ARLOCK => m_axi_out_mem_ARLOCK,
+        ARCACHE => m_axi_out_mem_ARCACHE,
+        ARPROT => m_axi_out_mem_ARPROT,
+        ARQOS => m_axi_out_mem_ARQOS,
+        ARREGION => m_axi_out_mem_ARREGION,
+        ARUSER => m_axi_out_mem_ARUSER,
+        RVALID => m_axi_out_mem_RVALID,
+        RREADY => m_axi_out_mem_RREADY,
+        RDATA => m_axi_out_mem_RDATA,
+        RLAST => m_axi_out_mem_RLAST,
+        RID => m_axi_out_mem_RID,
+        RUSER => m_axi_out_mem_RUSER,
+        RRESP => m_axi_out_mem_RRESP,
+        BVALID => m_axi_out_mem_BVALID,
+        BREADY => m_axi_out_mem_BREADY,
+        BRESP => m_axi_out_mem_BRESP,
+        BID => m_axi_out_mem_BID,
+        BUSER => m_axi_out_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => ap_const_logic_0,
+        I_ARREADY => out_mem_ARREADY,
+        I_ARADDR => ap_const_lv32_0,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_0,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => out_mem_RVALID,
+        I_RREADY => ap_const_logic_0,
+        I_RDATA => out_mem_RDATA,
+        I_RID => out_mem_RID,
+        I_RUSER => out_mem_RUSER,
+        I_RRESP => out_mem_RRESP,
+        I_RLAST => out_mem_RLAST,
+        I_AWVALID => out_mem_AWVALID,
+        I_AWREADY => out_mem_AWREADY,
+        I_AWADDR => out_mem_addr_reg_736,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_1000,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => out_mem_WVALID,
+        I_WREADY => out_mem_WREADY,
+        I_WDATA => out_loc_load_reg_848,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_F,
+        I_BVALID => out_mem_BVALID,
+        I_BREADY => out_mem_BREADY,
+        I_BRESP => out_mem_BRESP,
+        I_BID => out_mem_BID,
+        I_BUSER => out_mem_BUSER);
+
+    in1_loc_U : component mmult_in1_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_address0,
+        ce0 => in1_loc_ce0,
+        we0 => in1_loc_we0,
+        d0 => in1_mem_addr_read_reg_757,
+        q0 => in1_loc_q0);
+
+    in2_loc_U : component mmult_in1_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_address0,
+        ce0 => in2_loc_ce0,
+        we0 => in2_loc_we0,
+        d0 => in2_mem_addr_read_reg_771,
+        q0 => in2_loc_q0);
+
+    out_loc_U : component mmult_in1_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => out_loc_address0,
+        ce0 => out_loc_ce0,
+        we0 => out_loc_we0,
+        d0 => out_loc_d0,
+        q0 => out_loc_q0);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state9);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19)) then 
+                        ap_enable_reg_pp1_iter1 <= (ap_const_logic_1 xor ap_condition_pp1_exit_iter0_state19);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp3_exit_iter0_state26) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then 
+                    ap_enable_reg_pp3_iter0 <= ap_const_logic_0;
+                elsif (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then 
+                    ap_enable_reg_pp3_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp3_exit_iter0_state26)) then 
+                        ap_enable_reg_pp3_iter1 <= (ap_const_logic_1 xor ap_condition_pp3_exit_iter0_state26);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp3_iter1 <= ap_enable_reg_pp3_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) then 
+                    ap_enable_reg_pp3_iter2 <= ap_enable_reg_pp3_iter1;
+                elsif (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then 
+                    ap_enable_reg_pp3_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0_reg_320_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                i_0_reg_320 <= select_ln31_1_reg_794;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                i_0_reg_320 <= ap_const_lv31_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten15_reg_309_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                indvar_flatten15_reg_309 <= add_ln31_reg_789;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                indvar_flatten15_reg_309 <= ap_const_lv70_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_331_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                indvar_flatten_reg_331 <= select_ln33_1_reg_824;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                indvar_flatten_reg_331 <= ap_const_lv39_0;
+            end if; 
+        end if;
+    end process;
+
+    j_0_reg_342_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                j_0_reg_342 <= select_ln33_reg_809;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                j_0_reg_342 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    k_0_reg_353_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                k_0_reg_353 <= k_fu_687_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                k_0_reg_353 <= ap_const_lv7_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln27_reg_285_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_reg_748 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                phi_ln27_reg_285 <= add_ln27_reg_752;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                phi_ln27_reg_285 <= ap_const_lv13_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln28_reg_297_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                phi_ln28_reg_297 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_reg_762 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+                phi_ln28_reg_297 <= add_ln28_reg_766;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln42_reg_364_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then 
+                phi_ln42_reg_364 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_fu_692_p2 = ap_const_lv1_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then 
+                phi_ln42_reg_364 <= add_ln42_fu_698_p2;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                add_ln27_reg_752 <= add_ln27_fu_439_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                add_ln28_reg_766 <= add_ln28_fu_456_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state23)) then
+                add_ln31_reg_789 <= add_ln31_fu_496_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                dim_read_reg_709 <= dim;
+                in3_reg_725 <= in1(31 downto 2);
+                in_reg_720 <= in2(31 downto 2);
+                out5_reg_715 <= out_r(31 downto 2);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                icmp_ln27_reg_748 <= icmp_ln27_fu_433_p2;
+                icmp_ln27_reg_748_pp0_iter1_reg <= icmp_ln27_reg_748;
+                phi_ln27_reg_285_pp0_iter1_reg <= phi_ln27_reg_285;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                icmp_ln28_reg_762 <= icmp_ln28_fu_450_p2;
+                icmp_ln28_reg_762_pp1_iter1_reg <= icmp_ln28_reg_762;
+                phi_ln28_reg_297_pp1_iter1_reg <= phi_ln28_reg_297;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then
+                icmp_ln42_reg_834 <= icmp_ln42_fu_692_p2;
+                icmp_ln42_reg_834_pp3_iter1_reg <= icmp_ln42_reg_834;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_reg_748 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                in1_mem_addr_read_reg_757 <= in1_mem_RDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_reg_762 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                in2_mem_addr_read_reg_771 <= in2_mem_RDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
+                    in2_mem_addr_reg_742(29 downto 0) <= empty_5_fu_424_p1(32 - 1 downto 0)(29 downto 0);
+                    out_mem_addr_reg_736(29 downto 0) <= empty_fu_415_p1(32 - 1 downto 0)(29 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state22)) then
+                    mul_ln31_reg_781(69 downto 6) <= mul_ln31_fu_485_p2(69 downto 6);
+                    zext_ln31_reg_776(37 downto 6) <= zext_ln31_fu_474_p1(37 downto 6);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln31_fu_491_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                out_loc_addr_reg_804 <= sext_ln38_fu_609_p1(12 - 1 downto 0);
+                select_ln31_1_reg_794 <= select_ln31_1_fu_521_p3;
+                select_ln33_1_reg_824 <= select_ln33_1_fu_666_p3;
+                select_ln33_reg_809 <= select_ln33_fu_614_p3;
+                select_ln38_reg_799 <= select_ln38_fu_571_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_reg_834 = ap_const_lv1_0) and (ap_enable_reg_pp3_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then
+                out_loc_load_reg_848 <= out_loc_q0;
+            end if;
+        end if;
+    end process;
+    out_mem_addr_reg_736(31 downto 30) <= "00";
+    in2_mem_addr_reg_742(31 downto 30) <= "00";
+    zext_ln31_reg_776(5 downto 0) <= "000000";
+    zext_ln31_reg_776(38) <= '0';
+    mul_ln31_reg_781(5 downto 0) <= "000000";
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_enable_reg_pp0_iter1, ap_CS_fsm_state12, ap_enable_reg_pp1_iter1, ap_CS_fsm_state25, ap_enable_reg_pp3_iter2, ap_CS_fsm_state33, in1_mem_ARREADY, in2_mem_ARREADY, out_mem_AWREADY, out_mem_BVALID, icmp_ln27_fu_433_p2, ap_enable_reg_pp0_iter0, icmp_ln28_fu_450_p2, ap_enable_reg_pp1_iter0, ap_CS_fsm_state23, icmp_ln31_fu_491_p2, icmp_ln42_fu_692_p2, ap_enable_reg_pp3_iter0, ap_enable_reg_pp3_iter1, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter2, ap_block_pp1_stage0_subdone, ap_enable_reg_pp1_iter2, ap_block_pp3_stage0_subdone)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when ap_ST_fsm_state3 => 
+                ap_NS_fsm <= ap_ST_fsm_state4;
+            when ap_ST_fsm_state4 => 
+                ap_NS_fsm <= ap_ST_fsm_state5;
+            when ap_ST_fsm_state5 => 
+                ap_NS_fsm <= ap_ST_fsm_state6;
+            when ap_ST_fsm_state6 => 
+                ap_NS_fsm <= ap_ST_fsm_state7;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state8;
+            when ap_ST_fsm_state8 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (icmp_ln27_fu_433_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (icmp_ln27_fu_433_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state12 => 
+                if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then
+                    ap_NS_fsm <= ap_ST_fsm_state13;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                end if;
+            when ap_ST_fsm_state13 => 
+                ap_NS_fsm <= ap_ST_fsm_state14;
+            when ap_ST_fsm_state14 => 
+                ap_NS_fsm <= ap_ST_fsm_state15;
+            when ap_ST_fsm_state15 => 
+                ap_NS_fsm <= ap_ST_fsm_state16;
+            when ap_ST_fsm_state16 => 
+                ap_NS_fsm <= ap_ST_fsm_state17;
+            when ap_ST_fsm_state17 => 
+                ap_NS_fsm <= ap_ST_fsm_state18;
+            when ap_ST_fsm_state18 => 
+                ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+            when ap_ST_fsm_pp1_stage0 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (icmp_ln28_fu_450_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                elsif ((((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (icmp_ln28_fu_450_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state22;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                end if;
+            when ap_ST_fsm_state22 => 
+                ap_NS_fsm <= ap_ST_fsm_state23;
+            when ap_ST_fsm_state23 => 
+                if (((icmp_ln31_fu_491_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                    ap_NS_fsm <= ap_ST_fsm_state24;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state25;
+                end if;
+            when ap_ST_fsm_state24 => 
+                ap_NS_fsm <= ap_ST_fsm_state23;
+            when ap_ST_fsm_state25 => 
+                if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state25;
+                end if;
+            when ap_ST_fsm_pp3_stage0 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (icmp_ln42_fu_692_p2 = ap_const_lv1_1) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                elsif ((((ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (icmp_ln42_fu_692_p2 = ap_const_lv1_1) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state29;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                end if;
+            when ap_ST_fsm_state29 => 
+                ap_NS_fsm <= ap_ST_fsm_state30;
+            when ap_ST_fsm_state30 => 
+                ap_NS_fsm <= ap_ST_fsm_state31;
+            when ap_ST_fsm_state31 => 
+                ap_NS_fsm <= ap_ST_fsm_state32;
+            when ap_ST_fsm_state32 => 
+                ap_NS_fsm <= ap_ST_fsm_state33;
+            when ap_ST_fsm_state33 => 
+                if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state33))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state33;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXX";
+        end case;
+    end process;
+    add_ln27_fu_439_p2 <= std_logic_vector(unsigned(ap_phi_mux_phi_ln27_phi_fu_289_p4) + unsigned(ap_const_lv13_1));
+    add_ln28_fu_456_p2 <= std_logic_vector(unsigned(ap_phi_mux_phi_ln28_phi_fu_301_p4) + unsigned(ap_const_lv13_1));
+    add_ln31_fu_496_p2 <= std_logic_vector(unsigned(indvar_flatten15_reg_309) + unsigned(ap_const_lv70_1));
+    add_ln33_fu_660_p2 <= std_logic_vector(unsigned(ap_const_lv39_1) + unsigned(indvar_flatten_reg_331));
+    add_ln38_1_fu_603_p2 <= std_logic_vector(unsigned(zext_ln38_cast_fu_533_p3) + unsigned(select_ln38_1_fu_595_p3));
+    add_ln38_2_fu_626_p2 <= std_logic_vector(unsigned(zext_ln38_cast_fu_533_p3) + unsigned(zext_ln38_fu_622_p1));
+    add_ln38_3_fu_649_p2 <= std_logic_vector(unsigned(zext_ln38_2_fu_645_p1) + unsigned(select_ln38_1_fu_595_p3));
+    add_ln42_fu_698_p2 <= std_logic_vector(unsigned(phi_ln42_reg_364) + unsigned(ap_const_lv13_1));
+    and_ln31_fu_553_p2 <= (xor_ln31_fu_541_p2 and icmp_ln35_fu_547_p2);
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(8);
+    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(16);
+    ap_CS_fsm_pp3_stage0 <= ap_CS_fsm(21);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state12 <= ap_CS_fsm(9);
+    ap_CS_fsm_state18 <= ap_CS_fsm(15);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state22 <= ap_CS_fsm(17);
+    ap_CS_fsm_state23 <= ap_CS_fsm(18);
+    ap_CS_fsm_state24 <= ap_CS_fsm(19);
+    ap_CS_fsm_state25 <= ap_CS_fsm(20);
+    ap_CS_fsm_state33 <= ap_CS_fsm(26);
+    ap_CS_fsm_state8 <= ap_CS_fsm(7);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_11001_assign_proc : process(ap_enable_reg_pp0_iter1, icmp_ln27_reg_748, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_11001 <= ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln27_reg_748 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(ap_enable_reg_pp0_iter1, icmp_ln27_reg_748, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_subdone <= ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln27_reg_748 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp1_stage0_11001_assign_proc : process(ap_enable_reg_pp1_iter1, icmp_ln28_reg_762, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_11001 <= ((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln28_reg_762 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp1_stage0_subdone_assign_proc : process(ap_enable_reg_pp1_iter1, icmp_ln28_reg_762, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_subdone <= ((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln28_reg_762 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp3_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp3_stage0_01001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp3_stage0_11001_assign_proc : process(ap_enable_reg_pp3_iter2, ap_block_state28_io)
+    begin
+                ap_block_pp3_stage0_11001 <= ((ap_const_boolean_1 = ap_block_state28_io) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp3_stage0_subdone_assign_proc : process(ap_enable_reg_pp3_iter2, ap_block_state28_io)
+    begin
+                ap_block_pp3_stage0_subdone <= ((ap_const_boolean_1 = ap_block_state28_io) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state10_pp0_stage0_iter1_assign_proc : process(icmp_ln27_reg_748, in1_mem_RVALID)
+    begin
+                ap_block_state10_pp0_stage0_iter1 <= ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln27_reg_748 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state11_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state19_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state20_pp1_stage0_iter1_assign_proc : process(icmp_ln28_reg_762, in2_mem_RVALID)
+    begin
+                ap_block_state20_pp1_stage0_iter1 <= ((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln28_reg_762 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state21_pp1_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state26_pp3_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state27_pp3_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state28_io_assign_proc : process(icmp_ln42_reg_834_pp3_iter1_reg, out_mem_WREADY)
+    begin
+                ap_block_state28_io <= ((out_mem_WREADY = ap_const_logic_0) and (icmp_ln42_reg_834_pp3_iter1_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state28_pp3_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state9_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state9_assign_proc : process(icmp_ln27_fu_433_p2)
+    begin
+        if ((icmp_ln27_fu_433_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp1_exit_iter0_state19_assign_proc : process(icmp_ln28_fu_450_p2)
+    begin
+        if ((icmp_ln28_fu_450_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_1;
+        else 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp3_exit_iter0_state26_assign_proc : process(icmp_ln42_fu_692_p2)
+    begin
+        if ((icmp_ln42_fu_692_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp3_exit_iter0_state26 <= ap_const_logic_1;
+        else 
+            ap_condition_pp3_exit_iter0_state26 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_CS_fsm_state33, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state33))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
+    ap_enable_pp3 <= (ap_idle_pp3 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_enable_reg_pp1_iter2 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))) then 
+            ap_idle_pp1 <= ap_const_logic_1;
+        else 
+            ap_idle_pp1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp3_assign_proc : process(ap_enable_reg_pp3_iter2, ap_enable_reg_pp3_iter0, ap_enable_reg_pp3_iter1)
+    begin
+        if (((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp3 <= ap_const_logic_1;
+        else 
+            ap_idle_pp3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_phi_ln27_phi_fu_289_p4_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, icmp_ln27_reg_748, phi_ln27_reg_285, add_ln27_reg_752)
+    begin
+        if (((icmp_ln27_reg_748 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            ap_phi_mux_phi_ln27_phi_fu_289_p4 <= add_ln27_reg_752;
+        else 
+            ap_phi_mux_phi_ln27_phi_fu_289_p4 <= phi_ln27_reg_285;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_phi_ln28_phi_fu_301_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, icmp_ln28_reg_762, phi_ln28_reg_297, add_ln28_reg_766)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (icmp_ln28_reg_762 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            ap_phi_mux_phi_ln28_phi_fu_301_p4 <= add_ln28_reg_766;
+        else 
+            ap_phi_mux_phi_ln28_phi_fu_301_p4 <= phi_ln28_reg_297;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state33, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state33))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    empty_5_fu_424_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in_reg_720),64));
+    empty_6_fu_405_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in3_reg_725),64));
+    empty_fu_415_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(out5_reg_715),64));
+    i_fu_502_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(i_0_reg_320));
+    icmp_ln27_fu_433_p2 <= "1" when (ap_phi_mux_phi_ln27_phi_fu_289_p4 = ap_const_lv13_1000) else "0";
+    icmp_ln28_fu_450_p2 <= "1" when (ap_phi_mux_phi_ln28_phi_fu_301_p4 = ap_const_lv13_1000) else "0";
+    icmp_ln31_fu_491_p2 <= "1" when (indvar_flatten15_reg_309 = mul_ln31_reg_781) else "0";
+    icmp_ln33_fu_508_p2 <= "1" when (indvar_flatten_reg_331 = zext_ln31_reg_776) else "0";
+    icmp_ln35_fu_547_p2 <= "1" when (k_0_reg_353 = ap_const_lv7_40) else "0";
+    icmp_ln42_fu_692_p2 <= "1" when (phi_ln42_reg_364 = ap_const_lv13_1000) else "0";
+
+    in1_loc_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_445_p1, zext_ln38_1_fu_632_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_address0 <= zext_ln38_1_fu_632_p1(12 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_address0 <= zext_ln27_fu_445_p1(12 - 1 downto 0);
+        else 
+            in1_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state23) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_we0_assign_proc : process(ap_block_pp0_stage0_11001, icmp_ln27_reg_748_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_reg_748_pp0_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    in1_mem_ARADDR <= empty_6_fu_405_p1(32 - 1 downto 0);
+
+    in1_mem_ARVALID_assign_proc : process(ap_CS_fsm_state2, in1_mem_ARREADY)
+    begin
+        if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            in1_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in1_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, icmp_ln27_reg_748, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_reg_748 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_RREADY <= ap_const_logic_1;
+        else 
+            in1_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_AR_assign_proc : process(m_axi_in1_mem_ARREADY, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            in1_mem_blk_n_AR <= m_axi_in1_mem_ARREADY;
+        else 
+            in1_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_R_assign_proc : process(m_axi_in1_mem_RVALID, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, icmp_ln27_reg_748)
+    begin
+        if (((icmp_ln27_reg_748 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_blk_n_R <= m_axi_in1_mem_RVALID;
+        else 
+            in1_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_loc_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state23, ap_enable_reg_pp1_iter2, zext_ln28_fu_462_p1, sext_ln38_1_fu_655_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in2_loc_address0 <= sext_ln38_1_fu_655_p1(12 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_address0 <= zext_ln28_fu_462_p1(12 - 1 downto 0);
+        else 
+            in2_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state23, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state23) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_we0_assign_proc : process(ap_block_pp1_stage0_11001, icmp_ln28_reg_762_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_reg_762_pp1_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_ARVALID_assign_proc : process(ap_CS_fsm_state12, in2_mem_ARREADY)
+    begin
+        if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then 
+            in2_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in2_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_RREADY_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, icmp_ln28_reg_762, ap_block_pp1_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_reg_762 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_RREADY <= ap_const_logic_1;
+        else 
+            in2_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_AR_assign_proc : process(m_axi_in2_mem_ARREADY, ap_CS_fsm_state12)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state12)) then 
+            in2_mem_blk_n_AR <= m_axi_in2_mem_ARREADY;
+        else 
+            in2_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_R_assign_proc : process(m_axi_in2_mem_RVALID, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, icmp_ln28_reg_762)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (icmp_ln28_reg_762 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_blk_n_R <= m_axi_in2_mem_RVALID;
+        else 
+            in2_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    j_fu_559_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(select_ln31_fu_513_p3));
+    k_fu_687_p2 <= std_logic_vector(unsigned(ap_const_lv7_1) + unsigned(select_ln38_reg_799));
+    mul_ln31_fu_485_p0 <= mul_ln31_fu_485_p00(32 - 1 downto 0);
+    mul_ln31_fu_485_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(dim_read_reg_709),70));
+    mul_ln31_fu_485_p1 <= mul_ln31_fu_485_p10(38 - 1 downto 0);
+    mul_ln31_fu_485_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_467_p3),70));
+    mul_ln31_fu_485_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(mul_ln31_fu_485_p0) * unsigned(mul_ln31_fu_485_p1), 70));
+    mul_ln38_fu_674_p0 <= in2_loc_q0;
+    mul_ln38_fu_674_p1 <= in1_loc_q0;
+    mul_ln38_fu_674_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_fu_674_p0) * signed(mul_ln38_fu_674_p1))), 32));
+    or_ln38_fu_565_p2 <= (icmp_ln33_fu_508_p2 or and_ln31_fu_553_p2);
+
+    out_loc_address0_assign_proc : process(ap_block_pp3_stage0, ap_CS_fsm_state23, out_loc_addr_reg_804, ap_CS_fsm_state24, ap_CS_fsm_pp3_stage0, ap_enable_reg_pp3_iter0, sext_ln38_fu_609_p1, zext_ln42_fu_704_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp3_stage0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then 
+            out_loc_address0 <= zext_ln42_fu_704_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+            out_loc_address0 <= out_loc_addr_reg_804;
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            out_loc_address0 <= sext_ln38_fu_609_p1(12 - 1 downto 0);
+        else 
+            out_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    out_loc_ce0_assign_proc : process(ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_pp3_stage0, ap_block_pp3_stage0_11001, ap_enable_reg_pp3_iter0)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state23) or ((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0)))) then 
+            out_loc_ce0 <= ap_const_logic_1;
+        else 
+            out_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    out_loc_d0 <= std_logic_vector(unsigned(mul_ln38_fu_674_p2) + unsigned(out_loc_q0));
+
+    out_loc_we0_assign_proc : process(ap_CS_fsm_state24)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+            out_loc_we0 <= ap_const_logic_1;
+        else 
+            out_loc_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_AWVALID_assign_proc : process(ap_CS_fsm_state25, out_mem_AWREADY)
+    begin
+        if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then 
+            out_mem_AWVALID <= ap_const_logic_1;
+        else 
+            out_mem_AWVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_BREADY_assign_proc : process(ap_CS_fsm_state33, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state33))) then 
+            out_mem_BREADY <= ap_const_logic_1;
+        else 
+            out_mem_BREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_WVALID_assign_proc : process(ap_enable_reg_pp3_iter2, icmp_ln42_reg_834_pp3_iter1_reg, ap_block_pp3_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_reg_834_pp3_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1))) then 
+            out_mem_WVALID <= ap_const_logic_1;
+        else 
+            out_mem_WVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AW_assign_proc : process(m_axi_out_mem_AWREADY, ap_CS_fsm_state25)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            out_mem_blk_n_AW <= m_axi_out_mem_AWREADY;
+        else 
+            out_mem_blk_n_AW <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_B_assign_proc : process(m_axi_out_mem_BVALID, ap_CS_fsm_state33)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state33)) then 
+            out_mem_blk_n_B <= m_axi_out_mem_BVALID;
+        else 
+            out_mem_blk_n_B <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_W_assign_proc : process(m_axi_out_mem_WREADY, ap_enable_reg_pp3_iter2, ap_block_pp3_stage0, icmp_ln42_reg_834_pp3_iter1_reg)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp3_stage0) and (icmp_ln42_reg_834_pp3_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1))) then 
+            out_mem_blk_n_W <= m_axi_out_mem_WREADY;
+        else 
+            out_mem_blk_n_W <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    select_ln31_1_fu_521_p3 <= 
+        i_fu_502_p2 when (icmp_ln33_fu_508_p2(0) = '1') else 
+        i_0_reg_320;
+    select_ln31_2_fu_587_p3 <= 
+        ap_const_lv14_0 when (icmp_ln33_fu_508_p2(0) = '1') else 
+        trunc_ln38_2_fu_583_p1;
+    select_ln31_fu_513_p3 <= 
+        ap_const_lv32_0 when (icmp_ln33_fu_508_p2(0) = '1') else 
+        j_0_reg_342;
+    select_ln33_1_fu_666_p3 <= 
+        ap_const_lv39_1 when (icmp_ln33_fu_508_p2(0) = '1') else 
+        add_ln33_fu_660_p2;
+    select_ln33_fu_614_p3 <= 
+        j_fu_559_p2 when (and_ln31_fu_553_p2(0) = '1') else 
+        select_ln31_fu_513_p3;
+    select_ln38_1_fu_595_p3 <= 
+        trunc_ln38_1_fu_579_p1 when (and_ln31_fu_553_p2(0) = '1') else 
+        select_ln31_2_fu_587_p3;
+    select_ln38_fu_571_p3 <= 
+        ap_const_lv7_0 when (or_ln38_fu_565_p2(0) = '1') else 
+        k_0_reg_353;
+        sext_ln38_1_fu_655_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_3_fu_649_p2),64));
+
+        sext_ln38_fu_609_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_1_fu_603_p2),64));
+
+    tmp_3_fu_637_p3 <= (select_ln38_fu_571_p3 & ap_const_lv6_0);
+    tmp_fu_467_p3 <= (dim_read_reg_709 & ap_const_lv6_0);
+    trunc_ln38_1_fu_579_p1 <= j_fu_559_p2(14 - 1 downto 0);
+    trunc_ln38_2_fu_583_p1 <= j_0_reg_342(14 - 1 downto 0);
+    trunc_ln38_fu_529_p1 <= select_ln31_1_fu_521_p3(8 - 1 downto 0);
+    xor_ln31_fu_541_p2 <= (icmp_ln33_fu_508_p2 xor ap_const_lv1_1);
+    zext_ln27_fu_445_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln27_reg_285_pp0_iter1_reg),64));
+    zext_ln28_fu_462_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln28_reg_297_pp1_iter1_reg),64));
+    zext_ln31_fu_474_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_467_p3),39));
+    zext_ln38_1_fu_632_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln38_2_fu_626_p2),64));
+    zext_ln38_2_fu_645_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_3_fu_637_p3),14));
+    zext_ln38_cast_fu_533_p3 <= (trunc_ln38_fu_529_p1 & ap_const_lv6_0);
+    zext_ln38_fu_622_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(select_ln38_fu_571_p3),14));
+    zext_ln42_fu_704_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln42_reg_364),64));
+end behav;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in1_loc.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in1_loc.vhd
new file mode 100755
index 0000000..ccbf7ef
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in1_loc.vhd
@@ -0,0 +1,112 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_in1_loc_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 12; 
+            MEM_SIZE    : integer := 4096
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_in1_loc_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_in1_loc is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 4096;
+        AddressWidth : INTEGER := 12);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_in1_loc is
+    component mmult_in1_loc_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_in1_loc_ram_U :  component mmult_in1_loc_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in1_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in1_mem_m_axi.vhd
new file mode 100755
index 0000000..5d4f5b4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in1_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi;
+
+architecture behave of mmult_in1_mem_m_axi is
+    component mmult_in1_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_write;
+
+    component mmult_in1_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_read;
+
+    component mmult_in1_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in1_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in1_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in1_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in1_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in1_mem_m_axi_fifo;
+
+architecture behave of mmult_in1_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in1_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in1_mem_m_axi_decoder;
+
+architecture behav of mmult_in1_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in1_mem_m_axi_throttl;
+
+architecture behav of mmult_in1_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in1_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in1_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_read;
+
+architecture behave of mmult_in1_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_write;
+
+architecture behave of mmult_in1_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in1_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in1_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in2_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in2_mem_m_axi.vhd
new file mode 100755
index 0000000..84687e2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in2_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi;
+
+architecture behave of mmult_in2_mem_m_axi is
+    component mmult_in2_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_write;
+
+    component mmult_in2_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_read;
+
+    component mmult_in2_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in2_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in2_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in2_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in2_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in2_mem_m_axi_fifo;
+
+architecture behave of mmult_in2_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in2_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in2_mem_m_axi_decoder;
+
+architecture behav of mmult_in2_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in2_mem_m_axi_throttl;
+
+architecture behav of mmult_in2_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in2_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in2_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_read;
+
+architecture behave of mmult_in2_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_write;
+
+architecture behave of mmult_in2_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in2_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in2_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_out_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_out_mem_m_axi.vhd
new file mode 100755
index 0000000..f2bd717
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_out_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi;
+
+architecture behave of mmult_out_mem_m_axi is
+    component mmult_out_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_write;
+
+    component mmult_out_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_read;
+
+    component mmult_out_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_out_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_out_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_out_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi_reg_slice;
+
+architecture behave of mmult_out_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_out_mem_m_axi_fifo;
+
+architecture behave of mmult_out_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_out_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_out_mem_m_axi_decoder;
+
+architecture behav of mmult_out_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_out_mem_m_axi_throttl;
+
+architecture behav of mmult_out_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_out_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_out_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_read;
+
+architecture behave of mmult_out_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_write;
+
+architecture behave of mmult_out_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_out_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_out_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_params_s_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_params_s_axi.vhd
new file mode 100755
index 0000000..1f9adde
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_params_s_axi.vhd
@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/misc/logo.png b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/misc/logo.png
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diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/xgui/mmult_v3_0.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/xgui/mmult_v3_0.tcl
new file mode 100755
index 0000000..0276fbf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_4/xgui/mmult_v3_0.tcl
@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/component.xml b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/component.xml
new file mode 100755
index 0000000..a5aa6ac
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/component.xml
@@ -0,0 +1,5578 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>hls</spirit:library>
+  <spirit:name>mmult</spirit:name>
+  <spirit:version>4.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_params"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.ADDR_WIDTH">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi_params:m_axi_in1_mem:m_axi_in2_mem:m_axi_out_mem</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interrupt</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in1_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in1_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in2_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in2_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_out_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_out_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in1_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in2_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_out_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_BASE_PARAM">C_S_AXI_PARAMS_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_HIGH_PARAM">C_S_AXI_PARAMS_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>CTRL</spirit:name>
+          <spirit:displayName>CTRL</spirit:displayName>
+          <spirit:description>Control signals</spirit:description>
+          <spirit:addressOffset>0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>AP_START</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_start&apos;.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_DONE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_done&apos;.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_IDLE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_idle&apos;.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_READY</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_ready&apos;.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_1</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">3</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AUTO_RESTART</spirit:name>
+            <spirit:description>Control signal Register for &apos;auto_restart&apos;.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_2</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">24</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GIER</spirit:name>
+          <spirit:displayName>GIER</spirit:displayName>
+          <spirit:description>Global Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>4</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Enable</spirit:name>
+            <spirit:description>Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">31</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_IER</spirit:name>
+          <spirit:displayName>IP_IER</spirit:displayName>
+          <spirit:description>IP Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>8</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 0 (ap_done) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 1 (ap_ready) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_ISR</spirit:name>
+          <spirit:displayName>IP_ISR</spirit:displayName>
+          <spirit:description>IP Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>12</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_ST</spirit:name>
+            <spirit:description>Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 input interrupt, 1 = Channel 0 input interrup</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_ST</spirit:name>
+            <spirit:description>Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 input interrupt, 1 = Channel 1 input interrup</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:name>in1</spirit:name>
+          <spirit:displayName>in1</spirit:displayName>
+          <spirit:description>Data signal of in1</spirit:description>
+          <spirit:addressOffset>16</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+          <spirit:field>
+            <spirit:name>in1</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of in1</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:name>in2</spirit:name>
+          <spirit:displayName>in2</spirit:displayName>
+          <spirit:description>Data signal of in2</spirit:description>
+          <spirit:addressOffset>24</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+          <spirit:field>
+            <spirit:name>in2</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of in2</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:displayName>out_r</spirit:displayName>
+          <spirit:description>Data signal of out_r</spirit:description>
+          <spirit:addressOffset>32</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+            <spirit:name>out_r</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of out_r</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:access>write-only</spirit:access>
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+            <spirit:value spirit:format="long">0</spirit:value>
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+          <spirit:field>
+            <spirit:name>dim</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of dim</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE" spirit:order="11" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE" spirit:order="12" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE" spirit:order="13" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" spirit:order="14" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH" spirit:order="15" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="16" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" spirit:order="17" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH" spirit:order="18" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH" spirit:order="19" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH" spirit:order="20" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH" spirit:order="21" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH" spirit:order="22" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE" spirit:order="23" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE" spirit:order="24" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE" spirit:order="25" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" spirit:order="26" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH" spirit:order="27" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="28" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" spirit:order="29" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH" spirit:order="30" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH" spirit:order="31" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH" spirit:order="32" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH" spirit:order="33" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH" spirit:order="34" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE" spirit:order="35" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE" spirit:order="36" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE" spirit:order="37" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mmult_v4_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>clk_period</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.clk_period" spirit:order="38">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>machine</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.machine" spirit:order="39">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>combinational</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.combinational" spirit:order="40">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>latency</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.latency" spirit:order="41">153755</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>II</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.II" spirit:order="42">x</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/VIVADO_HLS_IP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>Mmult</xilinx:displayName>
+      <xilinx:definitionSource>HLS</xilinx:definitionSource>
+      <xilinx:coreRevision>2105141705</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2021-05-14T15:05:48Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b5dd57e8"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="c6fd4807"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5ce530f0"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3ea48f51"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="7681d788"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c9a673dd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="7704d09b"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/constraints/mmult_ooc.xdc b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/constraints/mmult_ooc.xdc
new file mode 100755
index 0000000..2ed5eee
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/constraints/mmult_ooc.xdc
@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/doc/ReleaseNotes.txt b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/doc/ReleaseNotes.txt
new file mode 100755
index 0000000..48cc01b
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/doc/ReleaseNotes.txt
@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/data/mmult.mdd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/data/mmult.mdd
new file mode 100755
index 0000000..fd11f42
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/data/mmult.mdd
@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v4_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 4.0;
+
+END driver
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/data/mmult.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/data/mmult.tcl
new file mode 100755
index 0000000..0de7a9c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/data/mmult.tcl
@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/Makefile b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/Makefile
new file mode 100755
index 0000000..7f76086
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/Makefile
@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult.c
new file mode 100755
index 0000000..fb9a1fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult.c
@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult.h
new file mode 100755
index 0000000..4983669
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult.h
@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_hw.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_hw.h
new file mode 100755
index 0000000..3a0a2a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_hw.h
@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_linux.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_linux.c
new file mode 100755
index 0000000..c8dbb33
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_linux.c
@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_sinit.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_sinit.c
new file mode 100755
index 0000000..f099590
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_sinit.c
@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult.v
new file mode 100755
index 0000000..ddacaec
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult.v
@@ -0,0 +1,4497 @@
+// ==============================================================
+// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+// Version: 2020.1
+// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+// 
+// ===========================================================
+
+`timescale 1 ns / 1 ps 
+
+(* CORE_GENERATION_INFO="mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=153755,HLS_SYN_TPT=none,HLS_SYN_MEM=30,HLS_SYN_DSP=192,HLS_SYN_FF=6462,HLS_SYN_LUT=10635,HLS_VERSION=2020_1}" *)
+
+module mmult (
+        ap_clk,
+        ap_rst_n,
+        m_axi_in1_mem_AWVALID,
+        m_axi_in1_mem_AWREADY,
+        m_axi_in1_mem_AWADDR,
+        m_axi_in1_mem_AWID,
+        m_axi_in1_mem_AWLEN,
+        m_axi_in1_mem_AWSIZE,
+        m_axi_in1_mem_AWBURST,
+        m_axi_in1_mem_AWLOCK,
+        m_axi_in1_mem_AWCACHE,
+        m_axi_in1_mem_AWPROT,
+        m_axi_in1_mem_AWQOS,
+        m_axi_in1_mem_AWREGION,
+        m_axi_in1_mem_AWUSER,
+        m_axi_in1_mem_WVALID,
+        m_axi_in1_mem_WREADY,
+        m_axi_in1_mem_WDATA,
+        m_axi_in1_mem_WSTRB,
+        m_axi_in1_mem_WLAST,
+        m_axi_in1_mem_WID,
+        m_axi_in1_mem_WUSER,
+        m_axi_in1_mem_ARVALID,
+        m_axi_in1_mem_ARREADY,
+        m_axi_in1_mem_ARADDR,
+        m_axi_in1_mem_ARID,
+        m_axi_in1_mem_ARLEN,
+        m_axi_in1_mem_ARSIZE,
+        m_axi_in1_mem_ARBURST,
+        m_axi_in1_mem_ARLOCK,
+        m_axi_in1_mem_ARCACHE,
+        m_axi_in1_mem_ARPROT,
+        m_axi_in1_mem_ARQOS,
+        m_axi_in1_mem_ARREGION,
+        m_axi_in1_mem_ARUSER,
+        m_axi_in1_mem_RVALID,
+        m_axi_in1_mem_RREADY,
+        m_axi_in1_mem_RDATA,
+        m_axi_in1_mem_RLAST,
+        m_axi_in1_mem_RID,
+        m_axi_in1_mem_RUSER,
+        m_axi_in1_mem_RRESP,
+        m_axi_in1_mem_BVALID,
+        m_axi_in1_mem_BREADY,
+        m_axi_in1_mem_BRESP,
+        m_axi_in1_mem_BID,
+        m_axi_in1_mem_BUSER,
+        m_axi_in2_mem_AWVALID,
+        m_axi_in2_mem_AWREADY,
+        m_axi_in2_mem_AWADDR,
+        m_axi_in2_mem_AWID,
+        m_axi_in2_mem_AWLEN,
+        m_axi_in2_mem_AWSIZE,
+        m_axi_in2_mem_AWBURST,
+        m_axi_in2_mem_AWLOCK,
+        m_axi_in2_mem_AWCACHE,
+        m_axi_in2_mem_AWPROT,
+        m_axi_in2_mem_AWQOS,
+        m_axi_in2_mem_AWREGION,
+        m_axi_in2_mem_AWUSER,
+        m_axi_in2_mem_WVALID,
+        m_axi_in2_mem_WREADY,
+        m_axi_in2_mem_WDATA,
+        m_axi_in2_mem_WSTRB,
+        m_axi_in2_mem_WLAST,
+        m_axi_in2_mem_WID,
+        m_axi_in2_mem_WUSER,
+        m_axi_in2_mem_ARVALID,
+        m_axi_in2_mem_ARREADY,
+        m_axi_in2_mem_ARADDR,
+        m_axi_in2_mem_ARID,
+        m_axi_in2_mem_ARLEN,
+        m_axi_in2_mem_ARSIZE,
+        m_axi_in2_mem_ARBURST,
+        m_axi_in2_mem_ARLOCK,
+        m_axi_in2_mem_ARCACHE,
+        m_axi_in2_mem_ARPROT,
+        m_axi_in2_mem_ARQOS,
+        m_axi_in2_mem_ARREGION,
+        m_axi_in2_mem_ARUSER,
+        m_axi_in2_mem_RVALID,
+        m_axi_in2_mem_RREADY,
+        m_axi_in2_mem_RDATA,
+        m_axi_in2_mem_RLAST,
+        m_axi_in2_mem_RID,
+        m_axi_in2_mem_RUSER,
+        m_axi_in2_mem_RRESP,
+        m_axi_in2_mem_BVALID,
+        m_axi_in2_mem_BREADY,
+        m_axi_in2_mem_BRESP,
+        m_axi_in2_mem_BID,
+        m_axi_in2_mem_BUSER,
+        m_axi_out_mem_AWVALID,
+        m_axi_out_mem_AWREADY,
+        m_axi_out_mem_AWADDR,
+        m_axi_out_mem_AWID,
+        m_axi_out_mem_AWLEN,
+        m_axi_out_mem_AWSIZE,
+        m_axi_out_mem_AWBURST,
+        m_axi_out_mem_AWLOCK,
+        m_axi_out_mem_AWCACHE,
+        m_axi_out_mem_AWPROT,
+        m_axi_out_mem_AWQOS,
+        m_axi_out_mem_AWREGION,
+        m_axi_out_mem_AWUSER,
+        m_axi_out_mem_WVALID,
+        m_axi_out_mem_WREADY,
+        m_axi_out_mem_WDATA,
+        m_axi_out_mem_WSTRB,
+        m_axi_out_mem_WLAST,
+        m_axi_out_mem_WID,
+        m_axi_out_mem_WUSER,
+        m_axi_out_mem_ARVALID,
+        m_axi_out_mem_ARREADY,
+        m_axi_out_mem_ARADDR,
+        m_axi_out_mem_ARID,
+        m_axi_out_mem_ARLEN,
+        m_axi_out_mem_ARSIZE,
+        m_axi_out_mem_ARBURST,
+        m_axi_out_mem_ARLOCK,
+        m_axi_out_mem_ARCACHE,
+        m_axi_out_mem_ARPROT,
+        m_axi_out_mem_ARQOS,
+        m_axi_out_mem_ARREGION,
+        m_axi_out_mem_ARUSER,
+        m_axi_out_mem_RVALID,
+        m_axi_out_mem_RREADY,
+        m_axi_out_mem_RDATA,
+        m_axi_out_mem_RLAST,
+        m_axi_out_mem_RID,
+        m_axi_out_mem_RUSER,
+        m_axi_out_mem_RRESP,
+        m_axi_out_mem_BVALID,
+        m_axi_out_mem_BREADY,
+        m_axi_out_mem_BRESP,
+        m_axi_out_mem_BID,
+        m_axi_out_mem_BUSER,
+        s_axi_params_AWVALID,
+        s_axi_params_AWREADY,
+        s_axi_params_AWADDR,
+        s_axi_params_WVALID,
+        s_axi_params_WREADY,
+        s_axi_params_WDATA,
+        s_axi_params_WSTRB,
+        s_axi_params_ARVALID,
+        s_axi_params_ARREADY,
+        s_axi_params_ARADDR,
+        s_axi_params_RVALID,
+        s_axi_params_RREADY,
+        s_axi_params_RDATA,
+        s_axi_params_RRESP,
+        s_axi_params_BVALID,
+        s_axi_params_BREADY,
+        s_axi_params_BRESP,
+        interrupt
+);
+
+parameter    ap_ST_fsm_state1 = 91'd1;
+parameter    ap_ST_fsm_state2 = 91'd2;
+parameter    ap_ST_fsm_state3 = 91'd4;
+parameter    ap_ST_fsm_state4 = 91'd8;
+parameter    ap_ST_fsm_state5 = 91'd16;
+parameter    ap_ST_fsm_state6 = 91'd32;
+parameter    ap_ST_fsm_state7 = 91'd64;
+parameter    ap_ST_fsm_state8 = 91'd128;
+parameter    ap_ST_fsm_pp0_stage0 = 91'd256;
+parameter    ap_ST_fsm_state12 = 91'd512;
+parameter    ap_ST_fsm_state13 = 91'd1024;
+parameter    ap_ST_fsm_state14 = 91'd2048;
+parameter    ap_ST_fsm_state15 = 91'd4096;
+parameter    ap_ST_fsm_state16 = 91'd8192;
+parameter    ap_ST_fsm_state17 = 91'd16384;
+parameter    ap_ST_fsm_state18 = 91'd32768;
+parameter    ap_ST_fsm_pp1_stage0 = 91'd65536;
+parameter    ap_ST_fsm_state22 = 91'd131072;
+parameter    ap_ST_fsm_state23 = 91'd262144;
+parameter    ap_ST_fsm_state24 = 91'd524288;
+parameter    ap_ST_fsm_state25 = 91'd1048576;
+parameter    ap_ST_fsm_state26 = 91'd2097152;
+parameter    ap_ST_fsm_state27 = 91'd4194304;
+parameter    ap_ST_fsm_state28 = 91'd8388608;
+parameter    ap_ST_fsm_state29 = 91'd16777216;
+parameter    ap_ST_fsm_state30 = 91'd33554432;
+parameter    ap_ST_fsm_state31 = 91'd67108864;
+parameter    ap_ST_fsm_state32 = 91'd134217728;
+parameter    ap_ST_fsm_state33 = 91'd268435456;
+parameter    ap_ST_fsm_state34 = 91'd536870912;
+parameter    ap_ST_fsm_state35 = 91'd1073741824;
+parameter    ap_ST_fsm_state36 = 91'd2147483648;
+parameter    ap_ST_fsm_state37 = 91'd4294967296;
+parameter    ap_ST_fsm_state38 = 91'd8589934592;
+parameter    ap_ST_fsm_state39 = 91'd17179869184;
+parameter    ap_ST_fsm_state40 = 91'd34359738368;
+parameter    ap_ST_fsm_state41 = 91'd68719476736;
+parameter    ap_ST_fsm_state42 = 91'd137438953472;
+parameter    ap_ST_fsm_state43 = 91'd274877906944;
+parameter    ap_ST_fsm_state44 = 91'd549755813888;
+parameter    ap_ST_fsm_state45 = 91'd1099511627776;
+parameter    ap_ST_fsm_state46 = 91'd2199023255552;
+parameter    ap_ST_fsm_state47 = 91'd4398046511104;
+parameter    ap_ST_fsm_state48 = 91'd8796093022208;
+parameter    ap_ST_fsm_state49 = 91'd17592186044416;
+parameter    ap_ST_fsm_state50 = 91'd35184372088832;
+parameter    ap_ST_fsm_state51 = 91'd70368744177664;
+parameter    ap_ST_fsm_state52 = 91'd140737488355328;
+parameter    ap_ST_fsm_state53 = 91'd281474976710656;
+parameter    ap_ST_fsm_state54 = 91'd562949953421312;
+parameter    ap_ST_fsm_state55 = 91'd1125899906842624;
+parameter    ap_ST_fsm_state56 = 91'd2251799813685248;
+parameter    ap_ST_fsm_state57 = 91'd4503599627370496;
+parameter    ap_ST_fsm_state58 = 91'd9007199254740992;
+parameter    ap_ST_fsm_state59 = 91'd18014398509481984;
+parameter    ap_ST_fsm_state60 = 91'd36028797018963968;
+parameter    ap_ST_fsm_state61 = 91'd72057594037927936;
+parameter    ap_ST_fsm_state62 = 91'd144115188075855872;
+parameter    ap_ST_fsm_state63 = 91'd288230376151711744;
+parameter    ap_ST_fsm_state64 = 91'd576460752303423488;
+parameter    ap_ST_fsm_state65 = 91'd1152921504606846976;
+parameter    ap_ST_fsm_state66 = 91'd2305843009213693952;
+parameter    ap_ST_fsm_state67 = 91'd4611686018427387904;
+parameter    ap_ST_fsm_state68 = 91'd9223372036854775808;
+parameter    ap_ST_fsm_state69 = 91'd18446744073709551616;
+parameter    ap_ST_fsm_state70 = 91'd36893488147419103232;
+parameter    ap_ST_fsm_state71 = 91'd73786976294838206464;
+parameter    ap_ST_fsm_state72 = 91'd147573952589676412928;
+parameter    ap_ST_fsm_state73 = 91'd295147905179352825856;
+parameter    ap_ST_fsm_state74 = 91'd590295810358705651712;
+parameter    ap_ST_fsm_state75 = 91'd1180591620717411303424;
+parameter    ap_ST_fsm_state76 = 91'd2361183241434822606848;
+parameter    ap_ST_fsm_state77 = 91'd4722366482869645213696;
+parameter    ap_ST_fsm_state78 = 91'd9444732965739290427392;
+parameter    ap_ST_fsm_state79 = 91'd18889465931478580854784;
+parameter    ap_ST_fsm_state80 = 91'd37778931862957161709568;
+parameter    ap_ST_fsm_state81 = 91'd75557863725914323419136;
+parameter    ap_ST_fsm_state82 = 91'd151115727451828646838272;
+parameter    ap_ST_fsm_state83 = 91'd302231454903657293676544;
+parameter    ap_ST_fsm_state84 = 91'd604462909807314587353088;
+parameter    ap_ST_fsm_state85 = 91'd1208925819614629174706176;
+parameter    ap_ST_fsm_state86 = 91'd2417851639229258349412352;
+parameter    ap_ST_fsm_state87 = 91'd4835703278458516698824704;
+parameter    ap_ST_fsm_state88 = 91'd9671406556917033397649408;
+parameter    ap_ST_fsm_state89 = 91'd19342813113834066795298816;
+parameter    ap_ST_fsm_pp2_stage0 = 91'd38685626227668133590597632;
+parameter    ap_ST_fsm_state93 = 91'd77371252455336267181195264;
+parameter    ap_ST_fsm_state94 = 91'd154742504910672534362390528;
+parameter    ap_ST_fsm_state95 = 91'd309485009821345068724781056;
+parameter    ap_ST_fsm_state96 = 91'd618970019642690137449562112;
+parameter    ap_ST_fsm_state97 = 91'd1237940039285380274899124224;
+parameter    C_S_AXI_PARAMS_DATA_WIDTH = 32;
+parameter    C_S_AXI_PARAMS_ADDR_WIDTH = 6;
+parameter    C_S_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_OUT_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_CACHE_VALUE = 3;
+
+parameter C_S_AXI_PARAMS_WSTRB_WIDTH = (32 / 8);
+parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN1_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN2_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_OUT_MEM_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+output   m_axi_in1_mem_AWVALID;
+input   m_axi_in1_mem_AWREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_AWADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_AWID;
+output  [7:0] m_axi_in1_mem_AWLEN;
+output  [2:0] m_axi_in1_mem_AWSIZE;
+output  [1:0] m_axi_in1_mem_AWBURST;
+output  [1:0] m_axi_in1_mem_AWLOCK;
+output  [3:0] m_axi_in1_mem_AWCACHE;
+output  [2:0] m_axi_in1_mem_AWPROT;
+output  [3:0] m_axi_in1_mem_AWQOS;
+output  [3:0] m_axi_in1_mem_AWREGION;
+output  [C_M_AXI_IN1_MEM_AWUSER_WIDTH - 1:0] m_axi_in1_mem_AWUSER;
+output   m_axi_in1_mem_WVALID;
+input   m_axi_in1_mem_WREADY;
+output  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_WDATA;
+output  [C_M_AXI_IN1_MEM_WSTRB_WIDTH - 1:0] m_axi_in1_mem_WSTRB;
+output   m_axi_in1_mem_WLAST;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_WID;
+output  [C_M_AXI_IN1_MEM_WUSER_WIDTH - 1:0] m_axi_in1_mem_WUSER;
+output   m_axi_in1_mem_ARVALID;
+input   m_axi_in1_mem_ARREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_ARADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_ARID;
+output  [7:0] m_axi_in1_mem_ARLEN;
+output  [2:0] m_axi_in1_mem_ARSIZE;
+output  [1:0] m_axi_in1_mem_ARBURST;
+output  [1:0] m_axi_in1_mem_ARLOCK;
+output  [3:0] m_axi_in1_mem_ARCACHE;
+output  [2:0] m_axi_in1_mem_ARPROT;
+output  [3:0] m_axi_in1_mem_ARQOS;
+output  [3:0] m_axi_in1_mem_ARREGION;
+output  [C_M_AXI_IN1_MEM_ARUSER_WIDTH - 1:0] m_axi_in1_mem_ARUSER;
+input   m_axi_in1_mem_RVALID;
+output   m_axi_in1_mem_RREADY;
+input  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_RDATA;
+input   m_axi_in1_mem_RLAST;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_RID;
+input  [C_M_AXI_IN1_MEM_RUSER_WIDTH - 1:0] m_axi_in1_mem_RUSER;
+input  [1:0] m_axi_in1_mem_RRESP;
+input   m_axi_in1_mem_BVALID;
+output   m_axi_in1_mem_BREADY;
+input  [1:0] m_axi_in1_mem_BRESP;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_BID;
+input  [C_M_AXI_IN1_MEM_BUSER_WIDTH - 1:0] m_axi_in1_mem_BUSER;
+output   m_axi_in2_mem_AWVALID;
+input   m_axi_in2_mem_AWREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_AWADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_AWID;
+output  [7:0] m_axi_in2_mem_AWLEN;
+output  [2:0] m_axi_in2_mem_AWSIZE;
+output  [1:0] m_axi_in2_mem_AWBURST;
+output  [1:0] m_axi_in2_mem_AWLOCK;
+output  [3:0] m_axi_in2_mem_AWCACHE;
+output  [2:0] m_axi_in2_mem_AWPROT;
+output  [3:0] m_axi_in2_mem_AWQOS;
+output  [3:0] m_axi_in2_mem_AWREGION;
+output  [C_M_AXI_IN2_MEM_AWUSER_WIDTH - 1:0] m_axi_in2_mem_AWUSER;
+output   m_axi_in2_mem_WVALID;
+input   m_axi_in2_mem_WREADY;
+output  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_WDATA;
+output  [C_M_AXI_IN2_MEM_WSTRB_WIDTH - 1:0] m_axi_in2_mem_WSTRB;
+output   m_axi_in2_mem_WLAST;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_WID;
+output  [C_M_AXI_IN2_MEM_WUSER_WIDTH - 1:0] m_axi_in2_mem_WUSER;
+output   m_axi_in2_mem_ARVALID;
+input   m_axi_in2_mem_ARREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_ARADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_ARID;
+output  [7:0] m_axi_in2_mem_ARLEN;
+output  [2:0] m_axi_in2_mem_ARSIZE;
+output  [1:0] m_axi_in2_mem_ARBURST;
+output  [1:0] m_axi_in2_mem_ARLOCK;
+output  [3:0] m_axi_in2_mem_ARCACHE;
+output  [2:0] m_axi_in2_mem_ARPROT;
+output  [3:0] m_axi_in2_mem_ARQOS;
+output  [3:0] m_axi_in2_mem_ARREGION;
+output  [C_M_AXI_IN2_MEM_ARUSER_WIDTH - 1:0] m_axi_in2_mem_ARUSER;
+input   m_axi_in2_mem_RVALID;
+output   m_axi_in2_mem_RREADY;
+input  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_RDATA;
+input   m_axi_in2_mem_RLAST;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_RID;
+input  [C_M_AXI_IN2_MEM_RUSER_WIDTH - 1:0] m_axi_in2_mem_RUSER;
+input  [1:0] m_axi_in2_mem_RRESP;
+input   m_axi_in2_mem_BVALID;
+output   m_axi_in2_mem_BREADY;
+input  [1:0] m_axi_in2_mem_BRESP;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_BID;
+input  [C_M_AXI_IN2_MEM_BUSER_WIDTH - 1:0] m_axi_in2_mem_BUSER;
+output   m_axi_out_mem_AWVALID;
+input   m_axi_out_mem_AWREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_AWADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_AWID;
+output  [7:0] m_axi_out_mem_AWLEN;
+output  [2:0] m_axi_out_mem_AWSIZE;
+output  [1:0] m_axi_out_mem_AWBURST;
+output  [1:0] m_axi_out_mem_AWLOCK;
+output  [3:0] m_axi_out_mem_AWCACHE;
+output  [2:0] m_axi_out_mem_AWPROT;
+output  [3:0] m_axi_out_mem_AWQOS;
+output  [3:0] m_axi_out_mem_AWREGION;
+output  [C_M_AXI_OUT_MEM_AWUSER_WIDTH - 1:0] m_axi_out_mem_AWUSER;
+output   m_axi_out_mem_WVALID;
+input   m_axi_out_mem_WREADY;
+output  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_WDATA;
+output  [C_M_AXI_OUT_MEM_WSTRB_WIDTH - 1:0] m_axi_out_mem_WSTRB;
+output   m_axi_out_mem_WLAST;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_WID;
+output  [C_M_AXI_OUT_MEM_WUSER_WIDTH - 1:0] m_axi_out_mem_WUSER;
+output   m_axi_out_mem_ARVALID;
+input   m_axi_out_mem_ARREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_ARADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_ARID;
+output  [7:0] m_axi_out_mem_ARLEN;
+output  [2:0] m_axi_out_mem_ARSIZE;
+output  [1:0] m_axi_out_mem_ARBURST;
+output  [1:0] m_axi_out_mem_ARLOCK;
+output  [3:0] m_axi_out_mem_ARCACHE;
+output  [2:0] m_axi_out_mem_ARPROT;
+output  [3:0] m_axi_out_mem_ARQOS;
+output  [3:0] m_axi_out_mem_ARREGION;
+output  [C_M_AXI_OUT_MEM_ARUSER_WIDTH - 1:0] m_axi_out_mem_ARUSER;
+input   m_axi_out_mem_RVALID;
+output   m_axi_out_mem_RREADY;
+input  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_RDATA;
+input   m_axi_out_mem_RLAST;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_RID;
+input  [C_M_AXI_OUT_MEM_RUSER_WIDTH - 1:0] m_axi_out_mem_RUSER;
+input  [1:0] m_axi_out_mem_RRESP;
+input   m_axi_out_mem_BVALID;
+output   m_axi_out_mem_BREADY;
+input  [1:0] m_axi_out_mem_BRESP;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_BID;
+input  [C_M_AXI_OUT_MEM_BUSER_WIDTH - 1:0] m_axi_out_mem_BUSER;
+input   s_axi_params_AWVALID;
+output   s_axi_params_AWREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_AWADDR;
+input   s_axi_params_WVALID;
+output   s_axi_params_WREADY;
+input  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_WDATA;
+input  [C_S_AXI_PARAMS_WSTRB_WIDTH - 1:0] s_axi_params_WSTRB;
+input   s_axi_params_ARVALID;
+output   s_axi_params_ARREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_ARADDR;
+output   s_axi_params_RVALID;
+input   s_axi_params_RREADY;
+output  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_RDATA;
+output  [1:0] s_axi_params_RRESP;
+output   s_axi_params_BVALID;
+input   s_axi_params_BREADY;
+output  [1:0] s_axi_params_BRESP;
+output   interrupt;
+
+ reg    ap_rst_n_inv;
+wire    ap_start;
+reg    ap_done;
+reg    ap_idle;
+(* fsm_encoding = "none" *) reg   [90:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    ap_ready;
+wire   [31:0] in1;
+wire   [31:0] in2;
+wire   [31:0] out_r;
+wire   [31:0] dim;
+reg    in1_mem_blk_n_AR;
+wire    ap_CS_fsm_state2;
+reg    in1_mem_blk_n_R;
+wire    ap_CS_fsm_pp0_stage0;
+reg    ap_enable_reg_pp0_iter1;
+wire    ap_block_pp0_stage0;
+reg   [0:0] icmp_ln27_reg_3840;
+reg    in2_mem_blk_n_AR;
+wire    ap_CS_fsm_state12;
+reg    in2_mem_blk_n_R;
+wire    ap_CS_fsm_pp1_stage0;
+reg    ap_enable_reg_pp1_iter1;
+wire    ap_block_pp1_stage0;
+reg   [0:0] icmp_ln28_reg_3854;
+reg    out_mem_blk_n_AW;
+wire    ap_CS_fsm_state23;
+wire   [0:0] icmp_ln31_fu_1563_p2;
+reg    out_mem_blk_n_W;
+reg    ap_enable_reg_pp2_iter2;
+wire    ap_block_pp2_stage0;
+reg   [0:0] icmp_ln42_reg_5307;
+reg   [0:0] icmp_ln42_reg_5307_pp2_iter1_reg;
+reg    out_mem_blk_n_B;
+wire    ap_CS_fsm_state97;
+wire    in1_mem_AWREADY;
+wire    in1_mem_WREADY;
+reg    in1_mem_ARVALID;
+wire    in1_mem_ARREADY;
+wire   [31:0] in1_mem_ARADDR;
+wire    in1_mem_RVALID;
+reg    in1_mem_RREADY;
+wire   [31:0] in1_mem_RDATA;
+wire    in1_mem_RLAST;
+wire   [0:0] in1_mem_RID;
+wire   [0:0] in1_mem_RUSER;
+wire   [1:0] in1_mem_RRESP;
+wire    in1_mem_BVALID;
+wire   [1:0] in1_mem_BRESP;
+wire   [0:0] in1_mem_BID;
+wire   [0:0] in1_mem_BUSER;
+wire    in2_mem_AWREADY;
+wire    in2_mem_WREADY;
+reg    in2_mem_ARVALID;
+wire    in2_mem_ARREADY;
+wire    in2_mem_RVALID;
+reg    in2_mem_RREADY;
+wire   [31:0] in2_mem_RDATA;
+wire    in2_mem_RLAST;
+wire   [0:0] in2_mem_RID;
+wire   [0:0] in2_mem_RUSER;
+wire   [1:0] in2_mem_RRESP;
+wire    in2_mem_BVALID;
+wire   [1:0] in2_mem_BRESP;
+wire   [0:0] in2_mem_BID;
+wire   [0:0] in2_mem_BUSER;
+reg    out_mem_AWVALID;
+wire    out_mem_AWREADY;
+reg    out_mem_WVALID;
+wire    out_mem_WREADY;
+wire    out_mem_ARREADY;
+wire    out_mem_RVALID;
+wire   [31:0] out_mem_RDATA;
+wire    out_mem_RLAST;
+wire   [0:0] out_mem_RID;
+wire   [0:0] out_mem_RUSER;
+wire   [1:0] out_mem_RRESP;
+wire    out_mem_BVALID;
+reg    out_mem_BREADY;
+wire   [1:0] out_mem_BRESP;
+wire   [0:0] out_mem_BID;
+wire   [0:0] out_mem_BUSER;
+reg   [12:0] phi_ln27_reg_1410;
+reg   [12:0] phi_ln27_reg_1410_pp0_iter1_reg;
+wire    ap_block_state9_pp0_stage0_iter0;
+reg    ap_block_state10_pp0_stage0_iter1;
+wire    ap_block_state11_pp0_stage0_iter2;
+reg    ap_block_pp0_stage0_11001;
+reg   [12:0] phi_ln28_reg_1422;
+reg   [12:0] phi_ln28_reg_1422_pp1_iter1_reg;
+wire    ap_block_state19_pp1_stage0_iter0;
+reg    ap_block_state20_pp1_stage0_iter1;
+wire    ap_block_state21_pp1_stage0_iter2;
+reg    ap_block_pp1_stage0_11001;
+reg   [12:0] phi_ln42_reg_1456;
+reg   [31:0] dim_read_reg_3801;
+reg   [29:0] out5_reg_3807;
+reg   [29:0] in_reg_3812;
+reg   [29:0] in3_reg_3817;
+reg   [31:0] out_mem_addr_reg_3828;
+wire    ap_CS_fsm_state8;
+reg   [31:0] in2_mem_addr_reg_3834;
+wire   [0:0] icmp_ln27_fu_1525_p2;
+reg   [0:0] icmp_ln27_reg_3840_pp0_iter1_reg;
+wire   [12:0] add_ln27_fu_1531_p2;
+reg   [12:0] add_ln27_reg_3844;
+reg    ap_enable_reg_pp0_iter0;
+reg   [31:0] in1_mem_addr_read_reg_3849;
+wire   [0:0] icmp_ln28_fu_1542_p2;
+reg   [0:0] icmp_ln28_reg_3854_pp1_iter1_reg;
+wire   [12:0] add_ln28_fu_1548_p2;
+reg   [12:0] add_ln28_reg_3858;
+reg    ap_enable_reg_pp1_iter0;
+reg   [31:0] in2_mem_addr_read_reg_3863;
+reg    ap_block_state23_io;
+wire   [30:0] i_fu_1568_p2;
+reg   [30:0] i_reg_3872;
+wire   [36:0] tmp_2_fu_1574_p3;
+reg   [36:0] tmp_2_reg_3877;
+wire   [7:0] trunc_ln38_fu_1587_p1;
+reg   [7:0] trunc_ln38_reg_3943;
+wire    ap_CS_fsm_state24;
+wire   [31:0] in1_loc_q0;
+reg  signed [31:0] in1_loc_load_reg_3968;
+wire   [31:0] in1_loc_q1;
+reg  signed [31:0] in1_loc_load_1_reg_3973;
+wire    ap_CS_fsm_state25;
+reg  signed [31:0] in1_loc_load_2_reg_3988;
+reg  signed [31:0] in1_loc_load_3_reg_3993;
+wire    ap_CS_fsm_state26;
+reg  signed [31:0] in1_loc_load_4_reg_4008;
+reg  signed [31:0] in1_loc_load_5_reg_4013;
+wire    ap_CS_fsm_state27;
+reg  signed [31:0] in1_loc_load_6_reg_4028;
+reg  signed [31:0] in1_loc_load_7_reg_4033;
+wire    ap_CS_fsm_state28;
+reg  signed [31:0] in1_loc_load_8_reg_4048;
+reg  signed [31:0] in1_loc_load_9_reg_4053;
+wire    ap_CS_fsm_state29;
+reg  signed [31:0] in1_loc_load_10_reg_4068;
+reg  signed [31:0] in1_loc_load_11_reg_4073;
+wire    ap_CS_fsm_state30;
+reg  signed [31:0] in1_loc_load_12_reg_4088;
+reg  signed [31:0] in1_loc_load_13_reg_4093;
+wire    ap_CS_fsm_state31;
+reg  signed [31:0] in1_loc_load_14_reg_4108;
+reg  signed [31:0] in1_loc_load_15_reg_4113;
+wire    ap_CS_fsm_state32;
+reg  signed [31:0] in1_loc_load_16_reg_4128;
+reg  signed [31:0] in1_loc_load_17_reg_4133;
+wire    ap_CS_fsm_state33;
+reg  signed [31:0] in1_loc_load_18_reg_4148;
+reg  signed [31:0] in1_loc_load_19_reg_4153;
+wire    ap_CS_fsm_state34;
+reg  signed [31:0] in1_loc_load_20_reg_4168;
+reg  signed [31:0] in1_loc_load_21_reg_4173;
+wire    ap_CS_fsm_state35;
+reg  signed [31:0] in1_loc_load_22_reg_4188;
+reg  signed [31:0] in1_loc_load_23_reg_4193;
+wire    ap_CS_fsm_state36;
+reg  signed [31:0] in1_loc_load_24_reg_4208;
+reg  signed [31:0] in1_loc_load_25_reg_4213;
+wire    ap_CS_fsm_state37;
+reg  signed [31:0] in1_loc_load_26_reg_4228;
+reg  signed [31:0] in1_loc_load_27_reg_4233;
+wire    ap_CS_fsm_state38;
+reg  signed [31:0] in1_loc_load_28_reg_4248;
+reg  signed [31:0] in1_loc_load_29_reg_4253;
+wire    ap_CS_fsm_state39;
+reg  signed [31:0] in1_loc_load_30_reg_4268;
+reg  signed [31:0] in1_loc_load_31_reg_4273;
+wire    ap_CS_fsm_state40;
+reg  signed [31:0] in1_loc_load_32_reg_4288;
+reg  signed [31:0] in1_loc_load_33_reg_4293;
+wire    ap_CS_fsm_state41;
+reg  signed [31:0] in1_loc_load_34_reg_4308;
+reg  signed [31:0] in1_loc_load_35_reg_4313;
+wire    ap_CS_fsm_state42;
+reg  signed [31:0] in1_loc_load_36_reg_4328;
+reg  signed [31:0] in1_loc_load_37_reg_4333;
+wire    ap_CS_fsm_state43;
+reg  signed [31:0] in1_loc_load_38_reg_4348;
+reg  signed [31:0] in1_loc_load_39_reg_4353;
+wire    ap_CS_fsm_state44;
+reg  signed [31:0] in1_loc_load_40_reg_4368;
+reg  signed [31:0] in1_loc_load_41_reg_4373;
+wire    ap_CS_fsm_state45;
+reg  signed [31:0] in1_loc_load_42_reg_4388;
+reg  signed [31:0] in1_loc_load_43_reg_4393;
+wire    ap_CS_fsm_state46;
+reg  signed [31:0] in1_loc_load_44_reg_4408;
+reg  signed [31:0] in1_loc_load_45_reg_4413;
+wire    ap_CS_fsm_state47;
+reg  signed [31:0] in1_loc_load_46_reg_4428;
+reg  signed [31:0] in1_loc_load_47_reg_4433;
+wire    ap_CS_fsm_state48;
+reg  signed [31:0] in1_loc_load_48_reg_4448;
+reg  signed [31:0] in1_loc_load_49_reg_4453;
+wire    ap_CS_fsm_state49;
+reg  signed [31:0] in1_loc_load_50_reg_4468;
+reg  signed [31:0] in1_loc_load_51_reg_4473;
+wire    ap_CS_fsm_state50;
+reg  signed [31:0] in1_loc_load_52_reg_4488;
+reg  signed [31:0] in1_loc_load_53_reg_4493;
+wire    ap_CS_fsm_state51;
+reg  signed [31:0] in1_loc_load_54_reg_4508;
+reg  signed [31:0] in1_loc_load_55_reg_4513;
+wire    ap_CS_fsm_state52;
+reg  signed [31:0] in1_loc_load_56_reg_4528;
+reg  signed [31:0] in1_loc_load_57_reg_4533;
+wire    ap_CS_fsm_state53;
+reg  signed [31:0] in1_loc_load_58_reg_4548;
+reg  signed [31:0] in1_loc_load_59_reg_4553;
+wire    ap_CS_fsm_state54;
+reg  signed [31:0] in1_loc_load_60_reg_4568;
+reg  signed [31:0] in1_loc_load_61_reg_4573;
+wire   [13:0] zext_ln38_cast_fu_2474_p3;
+reg   [13:0] zext_ln38_cast_reg_4578;
+wire    ap_CS_fsm_state55;
+reg  signed [31:0] in1_loc_load_62_reg_4583;
+reg  signed [31:0] in1_loc_load_63_reg_4588;
+wire   [31:0] j_fu_2486_p2;
+reg   [31:0] j_reg_4596;
+wire    ap_CS_fsm_state56;
+wire   [13:0] trunc_ln38_1_fu_2497_p1;
+reg   [13:0] trunc_ln38_1_reg_4601;
+wire   [0:0] icmp_ln33_fu_2481_p2;
+reg   [11:0] out_loc_addr_reg_4677;
+wire    ap_CS_fsm_state57;
+wire   [31:0] mul_ln38_fu_2542_p2;
+reg   [31:0] mul_ln38_reg_4692;
+wire   [31:0] mul_ln38_1_fu_2547_p2;
+reg   [31:0] mul_ln38_1_reg_4697;
+wire    ap_CS_fsm_state58;
+wire   [31:0] mul_ln38_3_fu_2577_p2;
+reg   [31:0] mul_ln38_3_reg_4712;
+wire   [31:0] add_ln38_2_fu_2592_p2;
+reg   [31:0] add_ln38_2_reg_4717;
+wire    ap_CS_fsm_state59;
+wire   [31:0] mul_ln38_5_fu_2623_p2;
+reg   [31:0] mul_ln38_5_reg_4732;
+wire   [31:0] add_ln38_3_fu_2628_p2;
+reg   [31:0] add_ln38_3_reg_4737;
+wire    ap_CS_fsm_state60;
+wire   [31:0] mul_ln38_7_fu_2658_p2;
+reg   [31:0] mul_ln38_7_reg_4752;
+wire   [31:0] add_ln38_6_fu_2673_p2;
+reg   [31:0] add_ln38_6_reg_4757;
+wire    ap_CS_fsm_state61;
+wire   [31:0] mul_ln38_9_fu_2703_p2;
+reg   [31:0] mul_ln38_9_reg_4772;
+wire   [31:0] add_ln38_7_fu_2708_p2;
+reg   [31:0] add_ln38_7_reg_4777;
+wire    ap_CS_fsm_state62;
+wire   [31:0] mul_ln38_11_fu_2738_p2;
+reg   [31:0] mul_ln38_11_reg_4792;
+wire   [31:0] add_ln38_9_fu_2748_p2;
+reg   [31:0] add_ln38_9_reg_4797;
+wire    ap_CS_fsm_state63;
+wire   [31:0] mul_ln38_13_fu_2778_p2;
+reg   [31:0] mul_ln38_13_reg_4812;
+wire   [31:0] add_ln38_10_fu_2783_p2;
+reg   [31:0] add_ln38_10_reg_4817;
+wire    ap_CS_fsm_state64;
+wire   [31:0] mul_ln38_15_fu_2813_p2;
+reg   [31:0] mul_ln38_15_reg_4832;
+wire   [31:0] add_ln38_14_fu_2833_p2;
+reg   [31:0] add_ln38_14_reg_4837;
+wire    ap_CS_fsm_state65;
+wire   [31:0] mul_ln38_17_fu_2863_p2;
+reg   [31:0] mul_ln38_17_reg_4852;
+wire   [31:0] add_ln38_15_fu_2868_p2;
+reg   [31:0] add_ln38_15_reg_4857;
+wire    ap_CS_fsm_state66;
+wire   [31:0] mul_ln38_19_fu_2898_p2;
+reg   [31:0] mul_ln38_19_reg_4872;
+wire   [31:0] add_ln38_17_fu_2908_p2;
+reg   [31:0] add_ln38_17_reg_4877;
+wire    ap_CS_fsm_state67;
+wire   [31:0] mul_ln38_21_fu_2938_p2;
+reg   [31:0] mul_ln38_21_reg_4892;
+wire   [31:0] add_ln38_18_fu_2943_p2;
+reg   [31:0] add_ln38_18_reg_4897;
+wire    ap_CS_fsm_state68;
+wire   [31:0] mul_ln38_23_fu_2973_p2;
+reg   [31:0] mul_ln38_23_reg_4912;
+wire   [31:0] add_ln38_21_fu_2988_p2;
+reg   [31:0] add_ln38_21_reg_4917;
+wire    ap_CS_fsm_state69;
+wire   [31:0] mul_ln38_25_fu_3018_p2;
+reg   [31:0] mul_ln38_25_reg_4932;
+wire   [31:0] add_ln38_22_fu_3023_p2;
+reg   [31:0] add_ln38_22_reg_4937;
+wire    ap_CS_fsm_state70;
+wire   [31:0] mul_ln38_27_fu_3053_p2;
+reg   [31:0] mul_ln38_27_reg_4952;
+wire   [31:0] add_ln38_24_fu_3063_p2;
+reg   [31:0] add_ln38_24_reg_4957;
+wire    ap_CS_fsm_state71;
+wire   [31:0] mul_ln38_29_fu_3093_p2;
+reg   [31:0] mul_ln38_29_reg_4972;
+wire   [31:0] add_ln38_25_fu_3098_p2;
+reg   [31:0] add_ln38_25_reg_4977;
+wire    ap_CS_fsm_state72;
+wire   [31:0] mul_ln38_31_fu_3128_p2;
+reg   [31:0] mul_ln38_31_reg_4992;
+wire   [31:0] add_ln38_30_fu_3153_p2;
+reg   [31:0] add_ln38_30_reg_4997;
+wire    ap_CS_fsm_state73;
+wire   [31:0] mul_ln38_33_fu_3183_p2;
+reg   [31:0] mul_ln38_33_reg_5012;
+wire   [31:0] add_ln38_31_fu_3188_p2;
+reg   [31:0] add_ln38_31_reg_5017;
+wire    ap_CS_fsm_state74;
+wire   [31:0] mul_ln38_35_fu_3218_p2;
+reg   [31:0] mul_ln38_35_reg_5032;
+wire   [31:0] add_ln38_33_fu_3228_p2;
+reg   [31:0] add_ln38_33_reg_5037;
+wire    ap_CS_fsm_state75;
+wire   [31:0] mul_ln38_37_fu_3258_p2;
+reg   [31:0] mul_ln38_37_reg_5052;
+wire   [31:0] add_ln38_34_fu_3263_p2;
+reg   [31:0] add_ln38_34_reg_5057;
+wire    ap_CS_fsm_state76;
+wire   [31:0] mul_ln38_39_fu_3293_p2;
+reg   [31:0] mul_ln38_39_reg_5072;
+wire   [31:0] add_ln38_37_fu_3308_p2;
+reg   [31:0] add_ln38_37_reg_5077;
+wire    ap_CS_fsm_state77;
+wire   [31:0] mul_ln38_41_fu_3338_p2;
+reg   [31:0] mul_ln38_41_reg_5092;
+wire   [31:0] add_ln38_38_fu_3343_p2;
+reg   [31:0] add_ln38_38_reg_5097;
+wire    ap_CS_fsm_state78;
+wire   [31:0] mul_ln38_43_fu_3373_p2;
+reg   [31:0] mul_ln38_43_reg_5112;
+wire   [31:0] add_ln38_40_fu_3383_p2;
+reg   [31:0] add_ln38_40_reg_5117;
+wire    ap_CS_fsm_state79;
+wire   [31:0] mul_ln38_45_fu_3413_p2;
+reg   [31:0] mul_ln38_45_reg_5132;
+wire   [31:0] add_ln38_41_fu_3418_p2;
+reg   [31:0] add_ln38_41_reg_5137;
+wire    ap_CS_fsm_state80;
+wire   [31:0] mul_ln38_47_fu_3448_p2;
+reg   [31:0] mul_ln38_47_reg_5152;
+wire   [31:0] add_ln38_45_fu_3468_p2;
+reg   [31:0] add_ln38_45_reg_5157;
+wire    ap_CS_fsm_state81;
+wire   [31:0] mul_ln38_49_fu_3498_p2;
+reg   [31:0] mul_ln38_49_reg_5172;
+wire   [31:0] add_ln38_46_fu_3503_p2;
+reg   [31:0] add_ln38_46_reg_5177;
+wire    ap_CS_fsm_state82;
+wire   [31:0] mul_ln38_51_fu_3533_p2;
+reg   [31:0] mul_ln38_51_reg_5192;
+wire   [31:0] add_ln38_48_fu_3543_p2;
+reg   [31:0] add_ln38_48_reg_5197;
+wire    ap_CS_fsm_state83;
+wire   [31:0] mul_ln38_53_fu_3573_p2;
+reg   [31:0] mul_ln38_53_reg_5212;
+wire   [31:0] add_ln38_49_fu_3578_p2;
+reg   [31:0] add_ln38_49_reg_5217;
+wire    ap_CS_fsm_state84;
+wire   [31:0] mul_ln38_55_fu_3608_p2;
+reg   [31:0] mul_ln38_55_reg_5232;
+wire   [31:0] add_ln38_52_fu_3623_p2;
+reg   [31:0] add_ln38_52_reg_5237;
+wire    ap_CS_fsm_state85;
+wire   [31:0] mul_ln38_57_fu_3653_p2;
+reg   [31:0] mul_ln38_57_reg_5252;
+wire   [31:0] add_ln38_53_fu_3658_p2;
+reg   [31:0] add_ln38_53_reg_5257;
+wire    ap_CS_fsm_state86;
+wire   [31:0] mul_ln38_59_fu_3688_p2;
+reg   [31:0] mul_ln38_59_reg_5272;
+wire   [31:0] add_ln38_55_fu_3698_p2;
+reg   [31:0] add_ln38_55_reg_5277;
+wire    ap_CS_fsm_state87;
+wire   [31:0] mul_ln38_61_fu_3728_p2;
+reg   [31:0] mul_ln38_61_reg_5292;
+wire   [31:0] add_ln38_56_fu_3733_p2;
+reg   [31:0] add_ln38_56_reg_5297;
+wire   [31:0] add_ln38_61_fu_3769_p2;
+reg   [31:0] add_ln38_61_reg_5302;
+wire    ap_CS_fsm_state88;
+wire   [0:0] icmp_ln42_fu_3784_p2;
+wire    ap_CS_fsm_pp2_stage0;
+wire    ap_block_state90_pp2_stage0_iter0;
+wire    ap_block_state91_pp2_stage0_iter1;
+wire    ap_block_state92_pp2_stage0_iter2;
+reg    ap_block_state92_io;
+reg    ap_block_pp2_stage0_11001;
+wire   [12:0] add_ln42_fu_3790_p2;
+reg    ap_enable_reg_pp2_iter0;
+wire   [31:0] out_loc_q0;
+reg   [31:0] out_loc_load_reg_5321;
+reg    ap_enable_reg_pp2_iter1;
+reg    ap_block_pp0_stage0_subdone;
+reg    ap_condition_pp0_exit_iter0_state9;
+reg    ap_enable_reg_pp0_iter2;
+wire    ap_CS_fsm_state18;
+reg    ap_block_pp1_stage0_subdone;
+reg    ap_condition_pp1_exit_iter0_state19;
+reg    ap_enable_reg_pp1_iter2;
+reg    ap_block_pp2_stage0_subdone;
+reg    ap_condition_pp2_exit_iter0_state90;
+reg   [11:0] in1_loc_address0;
+reg    in1_loc_ce0;
+reg    in1_loc_we0;
+reg   [11:0] in1_loc_address1;
+reg    in1_loc_ce1;
+reg   [11:0] in2_loc_address0;
+reg    in2_loc_ce0;
+reg    in2_loc_we0;
+wire   [31:0] in2_loc_q0;
+reg   [11:0] in2_loc_address1;
+reg    in2_loc_ce1;
+wire   [31:0] in2_loc_q1;
+reg   [11:0] out_loc_address0;
+reg    out_loc_ce0;
+reg    out_loc_we0;
+wire   [31:0] out_loc_d0;
+reg   [12:0] ap_phi_mux_phi_ln27_phi_fu_1414_p4;
+reg   [12:0] ap_phi_mux_phi_ln28_phi_fu_1426_p4;
+reg   [30:0] i_0_reg_1434;
+wire    ap_CS_fsm_state22;
+reg  signed [31:0] j_0_reg_1445;
+wire    ap_CS_fsm_state89;
+wire   [63:0] zext_ln27_fu_1537_p1;
+wire   [63:0] zext_ln28_fu_1554_p1;
+wire   [63:0] zext_ln38_fu_1582_p1;
+wire   [63:0] tmp_3_fu_1597_p3;
+wire   [63:0] tmp_4_fu_1611_p3;
+wire   [63:0] tmp_5_fu_1625_p3;
+wire   [63:0] tmp_6_fu_1639_p3;
+wire   [63:0] tmp_7_fu_1653_p3;
+wire   [63:0] tmp_8_fu_1667_p3;
+wire   [63:0] tmp_9_fu_1681_p3;
+wire   [63:0] tmp_s_fu_1695_p3;
+wire   [63:0] tmp_10_fu_1709_p3;
+wire   [63:0] tmp_11_fu_1723_p3;
+wire   [63:0] tmp_12_fu_1737_p3;
+wire   [63:0] tmp_13_fu_1751_p3;
+wire   [63:0] tmp_14_fu_1765_p3;
+wire   [63:0] tmp_15_fu_1779_p3;
+wire   [63:0] tmp_16_fu_1793_p3;
+wire   [63:0] tmp_17_fu_1807_p3;
+wire   [63:0] tmp_18_fu_1821_p3;
+wire   [63:0] tmp_19_fu_1835_p3;
+wire   [63:0] tmp_20_fu_1849_p3;
+wire   [63:0] tmp_21_fu_1863_p3;
+wire   [63:0] tmp_22_fu_1877_p3;
+wire   [63:0] tmp_23_fu_1891_p3;
+wire   [63:0] tmp_24_fu_1905_p3;
+wire   [63:0] tmp_25_fu_1919_p3;
+wire   [63:0] tmp_26_fu_1933_p3;
+wire   [63:0] tmp_27_fu_1947_p3;
+wire   [63:0] tmp_28_fu_1961_p3;
+wire   [63:0] tmp_29_fu_1975_p3;
+wire   [63:0] tmp_30_fu_1989_p3;
+wire   [63:0] tmp_31_fu_2003_p3;
+wire   [63:0] tmp_32_fu_2017_p3;
+wire   [63:0] tmp_33_fu_2031_p3;
+wire   [63:0] tmp_34_fu_2045_p3;
+wire   [63:0] tmp_35_fu_2059_p3;
+wire   [63:0] tmp_36_fu_2073_p3;
+wire   [63:0] tmp_37_fu_2087_p3;
+wire   [63:0] tmp_38_fu_2101_p3;
+wire   [63:0] tmp_39_fu_2115_p3;
+wire   [63:0] tmp_40_fu_2129_p3;
+wire   [63:0] tmp_41_fu_2143_p3;
+wire   [63:0] tmp_42_fu_2157_p3;
+wire   [63:0] tmp_43_fu_2171_p3;
+wire   [63:0] tmp_44_fu_2185_p3;
+wire   [63:0] tmp_45_fu_2199_p3;
+wire   [63:0] tmp_46_fu_2213_p3;
+wire   [63:0] tmp_47_fu_2227_p3;
+wire   [63:0] tmp_48_fu_2241_p3;
+wire   [63:0] tmp_49_fu_2255_p3;
+wire   [63:0] tmp_50_fu_2269_p3;
+wire   [63:0] tmp_51_fu_2283_p3;
+wire   [63:0] tmp_52_fu_2297_p3;
+wire   [63:0] tmp_53_fu_2311_p3;
+wire   [63:0] tmp_54_fu_2325_p3;
+wire   [63:0] tmp_55_fu_2339_p3;
+wire   [63:0] tmp_56_fu_2353_p3;
+wire   [63:0] tmp_57_fu_2367_p3;
+wire   [63:0] tmp_58_fu_2381_p3;
+wire   [63:0] tmp_59_fu_2395_p3;
+wire   [63:0] tmp_60_fu_2409_p3;
+wire   [63:0] tmp_61_fu_2423_p3;
+wire   [63:0] tmp_62_fu_2437_p3;
+wire   [63:0] tmp_63_fu_2451_p3;
+wire   [63:0] tmp_64_fu_2465_p3;
+wire  signed [63:0] sext_ln38_fu_2492_p1;
+wire  signed [63:0] sext_ln38_1_fu_2507_p1;
+wire  signed [63:0] sext_ln38_64_fu_2517_p1;
+wire  signed [63:0] sext_ln38_2_fu_2527_p1;
+wire  signed [63:0] sext_ln38_3_fu_2537_p1;
+wire  signed [63:0] sext_ln38_4_fu_2557_p1;
+wire  signed [63:0] sext_ln38_5_fu_2567_p1;
+wire  signed [63:0] sext_ln38_6_fu_2603_p1;
+wire  signed [63:0] sext_ln38_7_fu_2613_p1;
+wire  signed [63:0] sext_ln38_8_fu_2638_p1;
+wire  signed [63:0] sext_ln38_9_fu_2648_p1;
+wire  signed [63:0] sext_ln38_10_fu_2683_p1;
+wire  signed [63:0] sext_ln38_11_fu_2693_p1;
+wire  signed [63:0] sext_ln38_12_fu_2718_p1;
+wire  signed [63:0] sext_ln38_13_fu_2728_p1;
+wire  signed [63:0] sext_ln38_14_fu_2758_p1;
+wire  signed [63:0] sext_ln38_15_fu_2768_p1;
+wire  signed [63:0] sext_ln38_16_fu_2793_p1;
+wire  signed [63:0] sext_ln38_17_fu_2803_p1;
+wire  signed [63:0] sext_ln38_18_fu_2843_p1;
+wire  signed [63:0] sext_ln38_19_fu_2853_p1;
+wire  signed [63:0] sext_ln38_20_fu_2878_p1;
+wire  signed [63:0] sext_ln38_21_fu_2888_p1;
+wire  signed [63:0] sext_ln38_22_fu_2918_p1;
+wire  signed [63:0] sext_ln38_23_fu_2928_p1;
+wire  signed [63:0] sext_ln38_24_fu_2953_p1;
+wire  signed [63:0] sext_ln38_25_fu_2963_p1;
+wire  signed [63:0] sext_ln38_26_fu_2998_p1;
+wire  signed [63:0] sext_ln38_27_fu_3008_p1;
+wire  signed [63:0] sext_ln38_28_fu_3033_p1;
+wire  signed [63:0] sext_ln38_29_fu_3043_p1;
+wire  signed [63:0] sext_ln38_30_fu_3073_p1;
+wire  signed [63:0] sext_ln38_31_fu_3083_p1;
+wire  signed [63:0] sext_ln38_32_fu_3108_p1;
+wire  signed [63:0] sext_ln38_33_fu_3118_p1;
+wire  signed [63:0] sext_ln38_34_fu_3163_p1;
+wire  signed [63:0] sext_ln38_35_fu_3173_p1;
+wire  signed [63:0] sext_ln38_36_fu_3198_p1;
+wire  signed [63:0] sext_ln38_37_fu_3208_p1;
+wire  signed [63:0] sext_ln38_38_fu_3238_p1;
+wire  signed [63:0] sext_ln38_39_fu_3248_p1;
+wire  signed [63:0] sext_ln38_40_fu_3273_p1;
+wire  signed [63:0] sext_ln38_41_fu_3283_p1;
+wire  signed [63:0] sext_ln38_42_fu_3318_p1;
+wire  signed [63:0] sext_ln38_43_fu_3328_p1;
+wire  signed [63:0] sext_ln38_44_fu_3353_p1;
+wire  signed [63:0] sext_ln38_45_fu_3363_p1;
+wire  signed [63:0] sext_ln38_46_fu_3393_p1;
+wire  signed [63:0] sext_ln38_47_fu_3403_p1;
+wire  signed [63:0] sext_ln38_48_fu_3428_p1;
+wire  signed [63:0] sext_ln38_49_fu_3438_p1;
+wire  signed [63:0] sext_ln38_50_fu_3478_p1;
+wire  signed [63:0] sext_ln38_51_fu_3488_p1;
+wire  signed [63:0] sext_ln38_52_fu_3513_p1;
+wire  signed [63:0] sext_ln38_53_fu_3523_p1;
+wire  signed [63:0] sext_ln38_54_fu_3553_p1;
+wire  signed [63:0] sext_ln38_55_fu_3563_p1;
+wire  signed [63:0] sext_ln38_56_fu_3588_p1;
+wire  signed [63:0] sext_ln38_57_fu_3598_p1;
+wire  signed [63:0] sext_ln38_58_fu_3633_p1;
+wire  signed [63:0] sext_ln38_59_fu_3643_p1;
+wire  signed [63:0] sext_ln38_60_fu_3668_p1;
+wire  signed [63:0] sext_ln38_61_fu_3678_p1;
+wire  signed [63:0] sext_ln38_62_fu_3708_p1;
+wire  signed [63:0] sext_ln38_63_fu_3718_p1;
+wire   [63:0] zext_ln42_fu_3796_p1;
+wire   [63:0] empty_6_fu_1497_p1;
+wire   [63:0] empty_fu_1507_p1;
+wire   [63:0] empty_5_fu_1516_p1;
+wire    ap_block_pp2_stage0_01001;
+wire   [31:0] zext_ln31_fu_1559_p1;
+wire   [36:0] or_ln38_fu_1591_p2;
+wire   [36:0] or_ln38_1_fu_1606_p2;
+wire   [36:0] or_ln38_2_fu_1620_p2;
+wire   [36:0] or_ln38_3_fu_1634_p2;
+wire   [36:0] or_ln38_4_fu_1648_p2;
+wire   [36:0] or_ln38_5_fu_1662_p2;
+wire   [36:0] or_ln38_6_fu_1676_p2;
+wire   [36:0] or_ln38_7_fu_1690_p2;
+wire   [36:0] or_ln38_8_fu_1704_p2;
+wire   [36:0] or_ln38_9_fu_1718_p2;
+wire   [36:0] or_ln38_10_fu_1732_p2;
+wire   [36:0] or_ln38_11_fu_1746_p2;
+wire   [36:0] or_ln38_12_fu_1760_p2;
+wire   [36:0] or_ln38_13_fu_1774_p2;
+wire   [36:0] or_ln38_14_fu_1788_p2;
+wire   [36:0] or_ln38_15_fu_1802_p2;
+wire   [36:0] or_ln38_16_fu_1816_p2;
+wire   [36:0] or_ln38_17_fu_1830_p2;
+wire   [36:0] or_ln38_18_fu_1844_p2;
+wire   [36:0] or_ln38_19_fu_1858_p2;
+wire   [36:0] or_ln38_20_fu_1872_p2;
+wire   [36:0] or_ln38_21_fu_1886_p2;
+wire   [36:0] or_ln38_22_fu_1900_p2;
+wire   [36:0] or_ln38_23_fu_1914_p2;
+wire   [36:0] or_ln38_24_fu_1928_p2;
+wire   [36:0] or_ln38_25_fu_1942_p2;
+wire   [36:0] or_ln38_26_fu_1956_p2;
+wire   [36:0] or_ln38_27_fu_1970_p2;
+wire   [36:0] or_ln38_28_fu_1984_p2;
+wire   [36:0] or_ln38_29_fu_1998_p2;
+wire   [36:0] or_ln38_30_fu_2012_p2;
+wire   [36:0] or_ln38_31_fu_2026_p2;
+wire   [36:0] or_ln38_32_fu_2040_p2;
+wire   [36:0] or_ln38_33_fu_2054_p2;
+wire   [36:0] or_ln38_34_fu_2068_p2;
+wire   [36:0] or_ln38_35_fu_2082_p2;
+wire   [36:0] or_ln38_36_fu_2096_p2;
+wire   [36:0] or_ln38_37_fu_2110_p2;
+wire   [36:0] or_ln38_38_fu_2124_p2;
+wire   [36:0] or_ln38_39_fu_2138_p2;
+wire   [36:0] or_ln38_40_fu_2152_p2;
+wire   [36:0] or_ln38_41_fu_2166_p2;
+wire   [36:0] or_ln38_42_fu_2180_p2;
+wire   [36:0] or_ln38_43_fu_2194_p2;
+wire   [36:0] or_ln38_44_fu_2208_p2;
+wire   [36:0] or_ln38_45_fu_2222_p2;
+wire   [36:0] or_ln38_46_fu_2236_p2;
+wire   [36:0] or_ln38_47_fu_2250_p2;
+wire   [36:0] or_ln38_48_fu_2264_p2;
+wire   [36:0] or_ln38_49_fu_2278_p2;
+wire   [36:0] or_ln38_50_fu_2292_p2;
+wire   [36:0] or_ln38_51_fu_2306_p2;
+wire   [36:0] or_ln38_52_fu_2320_p2;
+wire   [36:0] or_ln38_53_fu_2334_p2;
+wire   [36:0] or_ln38_54_fu_2348_p2;
+wire   [36:0] or_ln38_55_fu_2362_p2;
+wire   [36:0] or_ln38_56_fu_2376_p2;
+wire   [36:0] or_ln38_57_fu_2390_p2;
+wire   [36:0] or_ln38_58_fu_2404_p2;
+wire   [36:0] or_ln38_59_fu_2418_p2;
+wire   [36:0] or_ln38_60_fu_2432_p2;
+wire   [36:0] or_ln38_61_fu_2446_p2;
+wire   [36:0] or_ln38_62_fu_2460_p2;
+wire   [13:0] add_ln38_64_fu_2501_p2;
+wire   [13:0] add_ln38_127_fu_2512_p2;
+wire   [13:0] add_ln38_65_fu_2522_p2;
+wire   [13:0] add_ln38_66_fu_2532_p2;
+wire  signed [31:0] mul_ln38_fu_2542_p0;
+wire  signed [31:0] mul_ln38_1_fu_2547_p0;
+wire   [13:0] add_ln38_67_fu_2552_p2;
+wire   [13:0] add_ln38_68_fu_2562_p2;
+wire  signed [31:0] mul_ln38_2_fu_2572_p0;
+wire  signed [31:0] mul_ln38_3_fu_2577_p0;
+wire   [31:0] mul_ln38_2_fu_2572_p2;
+wire   [31:0] add_ln38_fu_2582_p2;
+wire   [31:0] add_ln38_1_fu_2587_p2;
+wire   [13:0] add_ln38_69_fu_2598_p2;
+wire   [13:0] add_ln38_70_fu_2608_p2;
+wire  signed [31:0] mul_ln38_4_fu_2618_p0;
+wire  signed [31:0] mul_ln38_5_fu_2623_p0;
+wire   [31:0] mul_ln38_4_fu_2618_p2;
+wire   [13:0] add_ln38_71_fu_2633_p2;
+wire   [13:0] add_ln38_72_fu_2643_p2;
+wire  signed [31:0] mul_ln38_6_fu_2653_p0;
+wire  signed [31:0] mul_ln38_7_fu_2658_p0;
+wire   [31:0] mul_ln38_6_fu_2653_p2;
+wire   [31:0] add_ln38_4_fu_2663_p2;
+wire   [31:0] add_ln38_5_fu_2668_p2;
+wire   [13:0] add_ln38_73_fu_2678_p2;
+wire   [13:0] add_ln38_74_fu_2688_p2;
+wire  signed [31:0] mul_ln38_8_fu_2698_p0;
+wire  signed [31:0] mul_ln38_9_fu_2703_p0;
+wire   [31:0] mul_ln38_8_fu_2698_p2;
+wire   [13:0] add_ln38_75_fu_2713_p2;
+wire   [13:0] add_ln38_76_fu_2723_p2;
+wire  signed [31:0] mul_ln38_10_fu_2733_p0;
+wire  signed [31:0] mul_ln38_11_fu_2738_p0;
+wire   [31:0] mul_ln38_10_fu_2733_p2;
+wire   [31:0] add_ln38_8_fu_2743_p2;
+wire   [13:0] add_ln38_77_fu_2753_p2;
+wire   [13:0] add_ln38_78_fu_2763_p2;
+wire  signed [31:0] mul_ln38_12_fu_2773_p0;
+wire  signed [31:0] mul_ln38_13_fu_2778_p0;
+wire   [31:0] mul_ln38_12_fu_2773_p2;
+wire   [13:0] add_ln38_79_fu_2788_p2;
+wire   [13:0] add_ln38_80_fu_2798_p2;
+wire  signed [31:0] mul_ln38_14_fu_2808_p0;
+wire  signed [31:0] mul_ln38_15_fu_2813_p0;
+wire   [31:0] mul_ln38_14_fu_2808_p2;
+wire   [31:0] add_ln38_11_fu_2818_p2;
+wire   [31:0] add_ln38_12_fu_2823_p2;
+wire   [31:0] add_ln38_13_fu_2828_p2;
+wire   [13:0] add_ln38_81_fu_2838_p2;
+wire   [13:0] add_ln38_82_fu_2848_p2;
+wire  signed [31:0] mul_ln38_16_fu_2858_p0;
+wire  signed [31:0] mul_ln38_17_fu_2863_p0;
+wire   [31:0] mul_ln38_16_fu_2858_p2;
+wire   [13:0] add_ln38_83_fu_2873_p2;
+wire   [13:0] add_ln38_84_fu_2883_p2;
+wire  signed [31:0] mul_ln38_18_fu_2893_p0;
+wire  signed [31:0] mul_ln38_19_fu_2898_p0;
+wire   [31:0] mul_ln38_18_fu_2893_p2;
+wire   [31:0] add_ln38_16_fu_2903_p2;
+wire   [13:0] add_ln38_85_fu_2913_p2;
+wire   [13:0] add_ln38_86_fu_2923_p2;
+wire  signed [31:0] mul_ln38_20_fu_2933_p0;
+wire  signed [31:0] mul_ln38_21_fu_2938_p0;
+wire   [31:0] mul_ln38_20_fu_2933_p2;
+wire   [13:0] add_ln38_87_fu_2948_p2;
+wire   [13:0] add_ln38_88_fu_2958_p2;
+wire  signed [31:0] mul_ln38_22_fu_2968_p0;
+wire  signed [31:0] mul_ln38_23_fu_2973_p0;
+wire   [31:0] mul_ln38_22_fu_2968_p2;
+wire   [31:0] add_ln38_19_fu_2978_p2;
+wire   [31:0] add_ln38_20_fu_2983_p2;
+wire   [13:0] add_ln38_89_fu_2993_p2;
+wire   [13:0] add_ln38_90_fu_3003_p2;
+wire  signed [31:0] mul_ln38_24_fu_3013_p0;
+wire  signed [31:0] mul_ln38_25_fu_3018_p0;
+wire   [31:0] mul_ln38_24_fu_3013_p2;
+wire   [13:0] add_ln38_91_fu_3028_p2;
+wire   [13:0] add_ln38_92_fu_3038_p2;
+wire  signed [31:0] mul_ln38_26_fu_3048_p0;
+wire  signed [31:0] mul_ln38_27_fu_3053_p0;
+wire   [31:0] mul_ln38_26_fu_3048_p2;
+wire   [31:0] add_ln38_23_fu_3058_p2;
+wire   [13:0] add_ln38_93_fu_3068_p2;
+wire   [13:0] add_ln38_94_fu_3078_p2;
+wire  signed [31:0] mul_ln38_28_fu_3088_p0;
+wire  signed [31:0] mul_ln38_29_fu_3093_p0;
+wire   [31:0] mul_ln38_28_fu_3088_p2;
+wire   [13:0] add_ln38_95_fu_3103_p2;
+wire   [13:0] add_ln38_96_fu_3113_p2;
+wire  signed [31:0] mul_ln38_30_fu_3123_p0;
+wire  signed [31:0] mul_ln38_31_fu_3128_p0;
+wire   [31:0] mul_ln38_30_fu_3123_p2;
+wire   [31:0] add_ln38_26_fu_3133_p2;
+wire   [31:0] add_ln38_27_fu_3138_p2;
+wire   [31:0] add_ln38_28_fu_3143_p2;
+wire   [31:0] add_ln38_29_fu_3148_p2;
+wire   [13:0] add_ln38_97_fu_3158_p2;
+wire   [13:0] add_ln38_98_fu_3168_p2;
+wire  signed [31:0] mul_ln38_32_fu_3178_p0;
+wire  signed [31:0] mul_ln38_33_fu_3183_p0;
+wire   [31:0] mul_ln38_32_fu_3178_p2;
+wire   [13:0] add_ln38_99_fu_3193_p2;
+wire   [13:0] add_ln38_100_fu_3203_p2;
+wire  signed [31:0] mul_ln38_34_fu_3213_p0;
+wire  signed [31:0] mul_ln38_35_fu_3218_p0;
+wire   [31:0] mul_ln38_34_fu_3213_p2;
+wire   [31:0] add_ln38_32_fu_3223_p2;
+wire   [13:0] add_ln38_101_fu_3233_p2;
+wire   [13:0] add_ln38_102_fu_3243_p2;
+wire  signed [31:0] mul_ln38_36_fu_3253_p0;
+wire  signed [31:0] mul_ln38_37_fu_3258_p0;
+wire   [31:0] mul_ln38_36_fu_3253_p2;
+wire   [13:0] add_ln38_103_fu_3268_p2;
+wire   [13:0] add_ln38_104_fu_3278_p2;
+wire  signed [31:0] mul_ln38_38_fu_3288_p0;
+wire  signed [31:0] mul_ln38_39_fu_3293_p0;
+wire   [31:0] mul_ln38_38_fu_3288_p2;
+wire   [31:0] add_ln38_35_fu_3298_p2;
+wire   [31:0] add_ln38_36_fu_3303_p2;
+wire   [13:0] add_ln38_105_fu_3313_p2;
+wire   [13:0] add_ln38_106_fu_3323_p2;
+wire  signed [31:0] mul_ln38_40_fu_3333_p0;
+wire  signed [31:0] mul_ln38_41_fu_3338_p0;
+wire   [31:0] mul_ln38_40_fu_3333_p2;
+wire   [13:0] add_ln38_107_fu_3348_p2;
+wire   [13:0] add_ln38_108_fu_3358_p2;
+wire  signed [31:0] mul_ln38_42_fu_3368_p0;
+wire  signed [31:0] mul_ln38_43_fu_3373_p0;
+wire   [31:0] mul_ln38_42_fu_3368_p2;
+wire   [31:0] add_ln38_39_fu_3378_p2;
+wire   [13:0] add_ln38_109_fu_3388_p2;
+wire   [13:0] add_ln38_110_fu_3398_p2;
+wire  signed [31:0] mul_ln38_44_fu_3408_p0;
+wire  signed [31:0] mul_ln38_45_fu_3413_p0;
+wire   [31:0] mul_ln38_44_fu_3408_p2;
+wire   [13:0] add_ln38_111_fu_3423_p2;
+wire   [13:0] add_ln38_112_fu_3433_p2;
+wire  signed [31:0] mul_ln38_46_fu_3443_p0;
+wire  signed [31:0] mul_ln38_47_fu_3448_p0;
+wire   [31:0] mul_ln38_46_fu_3443_p2;
+wire   [31:0] add_ln38_42_fu_3453_p2;
+wire   [31:0] add_ln38_43_fu_3458_p2;
+wire   [31:0] add_ln38_44_fu_3463_p2;
+wire   [13:0] add_ln38_113_fu_3473_p2;
+wire   [13:0] add_ln38_114_fu_3483_p2;
+wire  signed [31:0] mul_ln38_48_fu_3493_p0;
+wire  signed [31:0] mul_ln38_49_fu_3498_p0;
+wire   [31:0] mul_ln38_48_fu_3493_p2;
+wire   [13:0] add_ln38_115_fu_3508_p2;
+wire   [13:0] add_ln38_116_fu_3518_p2;
+wire  signed [31:0] mul_ln38_50_fu_3528_p0;
+wire  signed [31:0] mul_ln38_51_fu_3533_p0;
+wire   [31:0] mul_ln38_50_fu_3528_p2;
+wire   [31:0] add_ln38_47_fu_3538_p2;
+wire   [13:0] add_ln38_117_fu_3548_p2;
+wire   [13:0] add_ln38_118_fu_3558_p2;
+wire  signed [31:0] mul_ln38_52_fu_3568_p0;
+wire  signed [31:0] mul_ln38_53_fu_3573_p0;
+wire   [31:0] mul_ln38_52_fu_3568_p2;
+wire   [13:0] add_ln38_119_fu_3583_p2;
+wire   [13:0] add_ln38_120_fu_3593_p2;
+wire  signed [31:0] mul_ln38_54_fu_3603_p0;
+wire  signed [31:0] mul_ln38_55_fu_3608_p0;
+wire   [31:0] mul_ln38_54_fu_3603_p2;
+wire   [31:0] add_ln38_50_fu_3613_p2;
+wire   [31:0] add_ln38_51_fu_3618_p2;
+wire   [13:0] add_ln38_121_fu_3628_p2;
+wire   [13:0] add_ln38_122_fu_3638_p2;
+wire  signed [31:0] mul_ln38_56_fu_3648_p0;
+wire  signed [31:0] mul_ln38_57_fu_3653_p0;
+wire   [31:0] mul_ln38_56_fu_3648_p2;
+wire   [13:0] add_ln38_123_fu_3663_p2;
+wire   [13:0] add_ln38_124_fu_3673_p2;
+wire  signed [31:0] mul_ln38_58_fu_3683_p0;
+wire  signed [31:0] mul_ln38_59_fu_3688_p0;
+wire   [31:0] mul_ln38_58_fu_3683_p2;
+wire   [31:0] add_ln38_54_fu_3693_p2;
+wire   [13:0] add_ln38_125_fu_3703_p2;
+wire   [13:0] add_ln38_126_fu_3713_p2;
+wire  signed [31:0] mul_ln38_60_fu_3723_p0;
+wire  signed [31:0] mul_ln38_61_fu_3728_p0;
+wire   [31:0] mul_ln38_60_fu_3723_p2;
+wire  signed [31:0] mul_ln38_62_fu_3738_p0;
+wire  signed [31:0] mul_ln38_63_fu_3743_p0;
+wire   [31:0] mul_ln38_63_fu_3743_p2;
+wire   [31:0] mul_ln38_62_fu_3738_p2;
+wire   [31:0] add_ln38_57_fu_3748_p2;
+wire   [31:0] add_ln38_58_fu_3754_p2;
+wire   [31:0] add_ln38_59_fu_3759_p2;
+wire   [31:0] add_ln38_60_fu_3764_p2;
+wire   [31:0] add_ln38_62_fu_3774_p2;
+reg   [90:0] ap_NS_fsm;
+reg    ap_idle_pp0;
+wire    ap_enable_pp0;
+reg    ap_idle_pp1;
+wire    ap_enable_pp1;
+reg    ap_idle_pp2;
+wire    ap_enable_pp2;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 91'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp1_iter1 = 1'b0;
+#0 ap_enable_reg_pp2_iter2 = 1'b0;
+#0 ap_enable_reg_pp0_iter0 = 1'b0;
+#0 ap_enable_reg_pp1_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp1_iter2 = 1'b0;
+end
+
+mmult_params_s_axi #(
+    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PARAMS_ADDR_WIDTH ),
+    .C_S_AXI_DATA_WIDTH( C_S_AXI_PARAMS_DATA_WIDTH ))
+mmult_params_s_axi_U(
+    .AWVALID(s_axi_params_AWVALID),
+    .AWREADY(s_axi_params_AWREADY),
+    .AWADDR(s_axi_params_AWADDR),
+    .WVALID(s_axi_params_WVALID),
+    .WREADY(s_axi_params_WREADY),
+    .WDATA(s_axi_params_WDATA),
+    .WSTRB(s_axi_params_WSTRB),
+    .ARVALID(s_axi_params_ARVALID),
+    .ARREADY(s_axi_params_ARREADY),
+    .ARADDR(s_axi_params_ARADDR),
+    .RVALID(s_axi_params_RVALID),
+    .RREADY(s_axi_params_RREADY),
+    .RDATA(s_axi_params_RDATA),
+    .RRESP(s_axi_params_RRESP),
+    .BVALID(s_axi_params_BVALID),
+    .BREADY(s_axi_params_BREADY),
+    .BRESP(s_axi_params_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .in1(in1),
+    .in2(in2),
+    .out_r(out_r),
+    .dim(dim)
+);
+
+mmult_in1_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN1_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN1_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN1_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN1_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN1_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN1_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN1_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN1_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN1_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN1_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN1_MEM_CACHE_VALUE ))
+mmult_in1_mem_m_axi_U(
+    .AWVALID(m_axi_in1_mem_AWVALID),
+    .AWREADY(m_axi_in1_mem_AWREADY),
+    .AWADDR(m_axi_in1_mem_AWADDR),
+    .AWID(m_axi_in1_mem_AWID),
+    .AWLEN(m_axi_in1_mem_AWLEN),
+    .AWSIZE(m_axi_in1_mem_AWSIZE),
+    .AWBURST(m_axi_in1_mem_AWBURST),
+    .AWLOCK(m_axi_in1_mem_AWLOCK),
+    .AWCACHE(m_axi_in1_mem_AWCACHE),
+    .AWPROT(m_axi_in1_mem_AWPROT),
+    .AWQOS(m_axi_in1_mem_AWQOS),
+    .AWREGION(m_axi_in1_mem_AWREGION),
+    .AWUSER(m_axi_in1_mem_AWUSER),
+    .WVALID(m_axi_in1_mem_WVALID),
+    .WREADY(m_axi_in1_mem_WREADY),
+    .WDATA(m_axi_in1_mem_WDATA),
+    .WSTRB(m_axi_in1_mem_WSTRB),
+    .WLAST(m_axi_in1_mem_WLAST),
+    .WID(m_axi_in1_mem_WID),
+    .WUSER(m_axi_in1_mem_WUSER),
+    .ARVALID(m_axi_in1_mem_ARVALID),
+    .ARREADY(m_axi_in1_mem_ARREADY),
+    .ARADDR(m_axi_in1_mem_ARADDR),
+    .ARID(m_axi_in1_mem_ARID),
+    .ARLEN(m_axi_in1_mem_ARLEN),
+    .ARSIZE(m_axi_in1_mem_ARSIZE),
+    .ARBURST(m_axi_in1_mem_ARBURST),
+    .ARLOCK(m_axi_in1_mem_ARLOCK),
+    .ARCACHE(m_axi_in1_mem_ARCACHE),
+    .ARPROT(m_axi_in1_mem_ARPROT),
+    .ARQOS(m_axi_in1_mem_ARQOS),
+    .ARREGION(m_axi_in1_mem_ARREGION),
+    .ARUSER(m_axi_in1_mem_ARUSER),
+    .RVALID(m_axi_in1_mem_RVALID),
+    .RREADY(m_axi_in1_mem_RREADY),
+    .RDATA(m_axi_in1_mem_RDATA),
+    .RLAST(m_axi_in1_mem_RLAST),
+    .RID(m_axi_in1_mem_RID),
+    .RUSER(m_axi_in1_mem_RUSER),
+    .RRESP(m_axi_in1_mem_RRESP),
+    .BVALID(m_axi_in1_mem_BVALID),
+    .BREADY(m_axi_in1_mem_BREADY),
+    .BRESP(m_axi_in1_mem_BRESP),
+    .BID(m_axi_in1_mem_BID),
+    .BUSER(m_axi_in1_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in1_mem_ARVALID),
+    .I_ARREADY(in1_mem_ARREADY),
+    .I_ARADDR(in1_mem_ARADDR),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in1_mem_RVALID),
+    .I_RREADY(in1_mem_RREADY),
+    .I_RDATA(in1_mem_RDATA),
+    .I_RID(in1_mem_RID),
+    .I_RUSER(in1_mem_RUSER),
+    .I_RRESP(in1_mem_RRESP),
+    .I_RLAST(in1_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in1_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in1_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in1_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in1_mem_BRESP),
+    .I_BID(in1_mem_BID),
+    .I_BUSER(in1_mem_BUSER)
+);
+
+mmult_in2_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN2_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN2_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN2_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN2_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN2_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN2_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN2_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN2_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN2_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN2_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN2_MEM_CACHE_VALUE ))
+mmult_in2_mem_m_axi_U(
+    .AWVALID(m_axi_in2_mem_AWVALID),
+    .AWREADY(m_axi_in2_mem_AWREADY),
+    .AWADDR(m_axi_in2_mem_AWADDR),
+    .AWID(m_axi_in2_mem_AWID),
+    .AWLEN(m_axi_in2_mem_AWLEN),
+    .AWSIZE(m_axi_in2_mem_AWSIZE),
+    .AWBURST(m_axi_in2_mem_AWBURST),
+    .AWLOCK(m_axi_in2_mem_AWLOCK),
+    .AWCACHE(m_axi_in2_mem_AWCACHE),
+    .AWPROT(m_axi_in2_mem_AWPROT),
+    .AWQOS(m_axi_in2_mem_AWQOS),
+    .AWREGION(m_axi_in2_mem_AWREGION),
+    .AWUSER(m_axi_in2_mem_AWUSER),
+    .WVALID(m_axi_in2_mem_WVALID),
+    .WREADY(m_axi_in2_mem_WREADY),
+    .WDATA(m_axi_in2_mem_WDATA),
+    .WSTRB(m_axi_in2_mem_WSTRB),
+    .WLAST(m_axi_in2_mem_WLAST),
+    .WID(m_axi_in2_mem_WID),
+    .WUSER(m_axi_in2_mem_WUSER),
+    .ARVALID(m_axi_in2_mem_ARVALID),
+    .ARREADY(m_axi_in2_mem_ARREADY),
+    .ARADDR(m_axi_in2_mem_ARADDR),
+    .ARID(m_axi_in2_mem_ARID),
+    .ARLEN(m_axi_in2_mem_ARLEN),
+    .ARSIZE(m_axi_in2_mem_ARSIZE),
+    .ARBURST(m_axi_in2_mem_ARBURST),
+    .ARLOCK(m_axi_in2_mem_ARLOCK),
+    .ARCACHE(m_axi_in2_mem_ARCACHE),
+    .ARPROT(m_axi_in2_mem_ARPROT),
+    .ARQOS(m_axi_in2_mem_ARQOS),
+    .ARREGION(m_axi_in2_mem_ARREGION),
+    .ARUSER(m_axi_in2_mem_ARUSER),
+    .RVALID(m_axi_in2_mem_RVALID),
+    .RREADY(m_axi_in2_mem_RREADY),
+    .RDATA(m_axi_in2_mem_RDATA),
+    .RLAST(m_axi_in2_mem_RLAST),
+    .RID(m_axi_in2_mem_RID),
+    .RUSER(m_axi_in2_mem_RUSER),
+    .RRESP(m_axi_in2_mem_RRESP),
+    .BVALID(m_axi_in2_mem_BVALID),
+    .BREADY(m_axi_in2_mem_BREADY),
+    .BRESP(m_axi_in2_mem_BRESP),
+    .BID(m_axi_in2_mem_BID),
+    .BUSER(m_axi_in2_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in2_mem_ARVALID),
+    .I_ARREADY(in2_mem_ARREADY),
+    .I_ARADDR(in2_mem_addr_reg_3834),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in2_mem_RVALID),
+    .I_RREADY(in2_mem_RREADY),
+    .I_RDATA(in2_mem_RDATA),
+    .I_RID(in2_mem_RID),
+    .I_RUSER(in2_mem_RUSER),
+    .I_RRESP(in2_mem_RRESP),
+    .I_RLAST(in2_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in2_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in2_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in2_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in2_mem_BRESP),
+    .I_BID(in2_mem_BID),
+    .I_BUSER(in2_mem_BUSER)
+);
+
+mmult_out_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_OUT_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_OUT_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_OUT_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_OUT_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_OUT_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_OUT_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_OUT_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_OUT_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_OUT_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_OUT_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_OUT_MEM_CACHE_VALUE ))
+mmult_out_mem_m_axi_U(
+    .AWVALID(m_axi_out_mem_AWVALID),
+    .AWREADY(m_axi_out_mem_AWREADY),
+    .AWADDR(m_axi_out_mem_AWADDR),
+    .AWID(m_axi_out_mem_AWID),
+    .AWLEN(m_axi_out_mem_AWLEN),
+    .AWSIZE(m_axi_out_mem_AWSIZE),
+    .AWBURST(m_axi_out_mem_AWBURST),
+    .AWLOCK(m_axi_out_mem_AWLOCK),
+    .AWCACHE(m_axi_out_mem_AWCACHE),
+    .AWPROT(m_axi_out_mem_AWPROT),
+    .AWQOS(m_axi_out_mem_AWQOS),
+    .AWREGION(m_axi_out_mem_AWREGION),
+    .AWUSER(m_axi_out_mem_AWUSER),
+    .WVALID(m_axi_out_mem_WVALID),
+    .WREADY(m_axi_out_mem_WREADY),
+    .WDATA(m_axi_out_mem_WDATA),
+    .WSTRB(m_axi_out_mem_WSTRB),
+    .WLAST(m_axi_out_mem_WLAST),
+    .WID(m_axi_out_mem_WID),
+    .WUSER(m_axi_out_mem_WUSER),
+    .ARVALID(m_axi_out_mem_ARVALID),
+    .ARREADY(m_axi_out_mem_ARREADY),
+    .ARADDR(m_axi_out_mem_ARADDR),
+    .ARID(m_axi_out_mem_ARID),
+    .ARLEN(m_axi_out_mem_ARLEN),
+    .ARSIZE(m_axi_out_mem_ARSIZE),
+    .ARBURST(m_axi_out_mem_ARBURST),
+    .ARLOCK(m_axi_out_mem_ARLOCK),
+    .ARCACHE(m_axi_out_mem_ARCACHE),
+    .ARPROT(m_axi_out_mem_ARPROT),
+    .ARQOS(m_axi_out_mem_ARQOS),
+    .ARREGION(m_axi_out_mem_ARREGION),
+    .ARUSER(m_axi_out_mem_ARUSER),
+    .RVALID(m_axi_out_mem_RVALID),
+    .RREADY(m_axi_out_mem_RREADY),
+    .RDATA(m_axi_out_mem_RDATA),
+    .RLAST(m_axi_out_mem_RLAST),
+    .RID(m_axi_out_mem_RID),
+    .RUSER(m_axi_out_mem_RUSER),
+    .RRESP(m_axi_out_mem_RRESP),
+    .BVALID(m_axi_out_mem_BVALID),
+    .BREADY(m_axi_out_mem_BREADY),
+    .BRESP(m_axi_out_mem_BRESP),
+    .BID(m_axi_out_mem_BID),
+    .BUSER(m_axi_out_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(1'b0),
+    .I_ARREADY(out_mem_ARREADY),
+    .I_ARADDR(32'd0),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd0),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(out_mem_RVALID),
+    .I_RREADY(1'b0),
+    .I_RDATA(out_mem_RDATA),
+    .I_RID(out_mem_RID),
+    .I_RUSER(out_mem_RUSER),
+    .I_RRESP(out_mem_RRESP),
+    .I_RLAST(out_mem_RLAST),
+    .I_AWVALID(out_mem_AWVALID),
+    .I_AWREADY(out_mem_AWREADY),
+    .I_AWADDR(out_mem_addr_reg_3828),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd4096),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(out_mem_WVALID),
+    .I_WREADY(out_mem_WREADY),
+    .I_WDATA(out_loc_load_reg_5321),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd15),
+    .I_BVALID(out_mem_BVALID),
+    .I_BREADY(out_mem_BREADY),
+    .I_BRESP(out_mem_BRESP),
+    .I_BID(out_mem_BID),
+    .I_BUSER(out_mem_BUSER)
+);
+
+mmult_in1_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+in1_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_address0),
+    .ce0(in1_loc_ce0),
+    .we0(in1_loc_we0),
+    .d0(in1_mem_addr_read_reg_3849),
+    .q0(in1_loc_q0),
+    .address1(in1_loc_address1),
+    .ce1(in1_loc_ce1),
+    .q1(in1_loc_q1)
+);
+
+mmult_in1_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+in2_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_address0),
+    .ce0(in2_loc_ce0),
+    .we0(in2_loc_we0),
+    .d0(in2_mem_addr_read_reg_3863),
+    .q0(in2_loc_q0),
+    .address1(in2_loc_address1),
+    .ce1(in2_loc_ce1),
+    .q1(in2_loc_q1)
+);
+
+mmult_out_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+out_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(out_loc_address0),
+    .ce0(out_loc_ce0),
+    .we0(out_loc_we0),
+    .d0(out_loc_d0),
+    .q0(out_loc_q0)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state9) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_enable_reg_pp0_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp0_exit_iter0_state9)) begin
+                ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state9);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b0 == ap_block_pp1_stage0_subdone))) begin
+            ap_enable_reg_pp1_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp1_exit_iter0_state19)) begin
+                ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_condition_pp2_exit_iter0_state90) & (1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_subdone))) begin
+            ap_enable_reg_pp2_iter0 <= 1'b0;
+        end else if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_1563_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+            ap_enable_reg_pp2_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp2_exit_iter0_state90)) begin
+                ap_enable_reg_pp2_iter1 <= (1'b1 ^ ap_condition_pp2_exit_iter0_state90);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+        end else if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_1563_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+            ap_enable_reg_pp2_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state22)) begin
+        i_0_reg_1434 <= 31'd0;
+    end else if (((icmp_ln33_fu_2481_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state56))) begin
+        i_0_reg_1434 <= i_reg_3872;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state89)) begin
+        j_0_reg_1445 <= j_reg_4596;
+    end else if ((1'b1 == ap_CS_fsm_state55)) begin
+        j_0_reg_1445 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_reg_3840 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        phi_ln27_reg_1410 <= add_ln27_reg_3844;
+    end else if ((1'b1 == ap_CS_fsm_state8)) begin
+        phi_ln27_reg_1410 <= 13'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        phi_ln28_reg_1422 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_reg_3854 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        phi_ln28_reg_1422 <= add_ln28_reg_3858;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_1563_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+        phi_ln42_reg_1456 <= 13'd0;
+    end else if (((icmp_ln42_fu_3784_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_11001))) begin
+        phi_ln42_reg_1456 <= add_ln42_fu_3790_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        add_ln27_reg_3844 <= add_ln27_fu_1531_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        add_ln28_reg_3858 <= add_ln28_fu_1548_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state63)) begin
+        add_ln38_10_reg_4817 <= add_ln38_10_fu_2783_p2;
+        mul_ln38_13_reg_4812 <= mul_ln38_13_fu_2778_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state64)) begin
+        add_ln38_14_reg_4837 <= add_ln38_14_fu_2833_p2;
+        mul_ln38_15_reg_4832 <= mul_ln38_15_fu_2813_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state65)) begin
+        add_ln38_15_reg_4857 <= add_ln38_15_fu_2868_p2;
+        mul_ln38_17_reg_4852 <= mul_ln38_17_fu_2863_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state66)) begin
+        add_ln38_17_reg_4877 <= add_ln38_17_fu_2908_p2;
+        mul_ln38_19_reg_4872 <= mul_ln38_19_fu_2898_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state67)) begin
+        add_ln38_18_reg_4897 <= add_ln38_18_fu_2943_p2;
+        mul_ln38_21_reg_4892 <= mul_ln38_21_fu_2938_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state68)) begin
+        add_ln38_21_reg_4917 <= add_ln38_21_fu_2988_p2;
+        mul_ln38_23_reg_4912 <= mul_ln38_23_fu_2973_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state69)) begin
+        add_ln38_22_reg_4937 <= add_ln38_22_fu_3023_p2;
+        mul_ln38_25_reg_4932 <= mul_ln38_25_fu_3018_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state70)) begin
+        add_ln38_24_reg_4957 <= add_ln38_24_fu_3063_p2;
+        mul_ln38_27_reg_4952 <= mul_ln38_27_fu_3053_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state71)) begin
+        add_ln38_25_reg_4977 <= add_ln38_25_fu_3098_p2;
+        mul_ln38_29_reg_4972 <= mul_ln38_29_fu_3093_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state58)) begin
+        add_ln38_2_reg_4717 <= add_ln38_2_fu_2592_p2;
+        mul_ln38_3_reg_4712 <= mul_ln38_3_fu_2577_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state72)) begin
+        add_ln38_30_reg_4997 <= add_ln38_30_fu_3153_p2;
+        mul_ln38_31_reg_4992 <= mul_ln38_31_fu_3128_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state73)) begin
+        add_ln38_31_reg_5017 <= add_ln38_31_fu_3188_p2;
+        mul_ln38_33_reg_5012 <= mul_ln38_33_fu_3183_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state74)) begin
+        add_ln38_33_reg_5037 <= add_ln38_33_fu_3228_p2;
+        mul_ln38_35_reg_5032 <= mul_ln38_35_fu_3218_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state75)) begin
+        add_ln38_34_reg_5057 <= add_ln38_34_fu_3263_p2;
+        mul_ln38_37_reg_5052 <= mul_ln38_37_fu_3258_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state76)) begin
+        add_ln38_37_reg_5077 <= add_ln38_37_fu_3308_p2;
+        mul_ln38_39_reg_5072 <= mul_ln38_39_fu_3293_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state77)) begin
+        add_ln38_38_reg_5097 <= add_ln38_38_fu_3343_p2;
+        mul_ln38_41_reg_5092 <= mul_ln38_41_fu_3338_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state59)) begin
+        add_ln38_3_reg_4737 <= add_ln38_3_fu_2628_p2;
+        mul_ln38_5_reg_4732 <= mul_ln38_5_fu_2623_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state78)) begin
+        add_ln38_40_reg_5117 <= add_ln38_40_fu_3383_p2;
+        mul_ln38_43_reg_5112 <= mul_ln38_43_fu_3373_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state79)) begin
+        add_ln38_41_reg_5137 <= add_ln38_41_fu_3418_p2;
+        mul_ln38_45_reg_5132 <= mul_ln38_45_fu_3413_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state80)) begin
+        add_ln38_45_reg_5157 <= add_ln38_45_fu_3468_p2;
+        mul_ln38_47_reg_5152 <= mul_ln38_47_fu_3448_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state81)) begin
+        add_ln38_46_reg_5177 <= add_ln38_46_fu_3503_p2;
+        mul_ln38_49_reg_5172 <= mul_ln38_49_fu_3498_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state82)) begin
+        add_ln38_48_reg_5197 <= add_ln38_48_fu_3543_p2;
+        mul_ln38_51_reg_5192 <= mul_ln38_51_fu_3533_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state83)) begin
+        add_ln38_49_reg_5217 <= add_ln38_49_fu_3578_p2;
+        mul_ln38_53_reg_5212 <= mul_ln38_53_fu_3573_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state84)) begin
+        add_ln38_52_reg_5237 <= add_ln38_52_fu_3623_p2;
+        mul_ln38_55_reg_5232 <= mul_ln38_55_fu_3608_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state85)) begin
+        add_ln38_53_reg_5257 <= add_ln38_53_fu_3658_p2;
+        mul_ln38_57_reg_5252 <= mul_ln38_57_fu_3653_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state86)) begin
+        add_ln38_55_reg_5277 <= add_ln38_55_fu_3698_p2;
+        mul_ln38_59_reg_5272 <= mul_ln38_59_fu_3688_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state87)) begin
+        add_ln38_56_reg_5297 <= add_ln38_56_fu_3733_p2;
+        mul_ln38_61_reg_5292 <= mul_ln38_61_fu_3728_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state88)) begin
+        add_ln38_61_reg_5302 <= add_ln38_61_fu_3769_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state60)) begin
+        add_ln38_6_reg_4757 <= add_ln38_6_fu_2673_p2;
+        mul_ln38_7_reg_4752 <= mul_ln38_7_fu_2658_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state61)) begin
+        add_ln38_7_reg_4777 <= add_ln38_7_fu_2708_p2;
+        mul_ln38_9_reg_4772 <= mul_ln38_9_fu_2703_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state62)) begin
+        add_ln38_9_reg_4797 <= add_ln38_9_fu_2748_p2;
+        mul_ln38_11_reg_4792 <= mul_ln38_11_fu_2738_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        dim_read_reg_3801 <= dim;
+        in3_reg_3817 <= {{in1[31:2]}};
+        in_reg_3812 <= {{in2[31:2]}};
+        out5_reg_3807 <= {{out_r[31:2]}};
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23))) begin
+        i_reg_3872 <= i_fu_1568_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        icmp_ln27_reg_3840 <= icmp_ln27_fu_1525_p2;
+        icmp_ln27_reg_3840_pp0_iter1_reg <= icmp_ln27_reg_3840;
+        phi_ln27_reg_1410_pp0_iter1_reg <= phi_ln27_reg_1410;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        icmp_ln28_reg_3854 <= icmp_ln28_fu_1542_p2;
+        icmp_ln28_reg_3854_pp1_iter1_reg <= icmp_ln28_reg_3854;
+        phi_ln28_reg_1422_pp1_iter1_reg <= phi_ln28_reg_1422;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_11001))) begin
+        icmp_ln42_reg_5307 <= icmp_ln42_fu_3784_p2;
+        icmp_ln42_reg_5307_pp2_iter1_reg <= icmp_ln42_reg_5307;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state29)) begin
+        in1_loc_load_10_reg_4068 <= in1_loc_q1;
+        in1_loc_load_11_reg_4073 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state30)) begin
+        in1_loc_load_12_reg_4088 <= in1_loc_q1;
+        in1_loc_load_13_reg_4093 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state31)) begin
+        in1_loc_load_14_reg_4108 <= in1_loc_q1;
+        in1_loc_load_15_reg_4113 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state32)) begin
+        in1_loc_load_16_reg_4128 <= in1_loc_q1;
+        in1_loc_load_17_reg_4133 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state33)) begin
+        in1_loc_load_18_reg_4148 <= in1_loc_q1;
+        in1_loc_load_19_reg_4153 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        in1_loc_load_1_reg_3973 <= in1_loc_q1;
+        in1_loc_load_reg_3968 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state34)) begin
+        in1_loc_load_20_reg_4168 <= in1_loc_q1;
+        in1_loc_load_21_reg_4173 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state35)) begin
+        in1_loc_load_22_reg_4188 <= in1_loc_q1;
+        in1_loc_load_23_reg_4193 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state36)) begin
+        in1_loc_load_24_reg_4208 <= in1_loc_q1;
+        in1_loc_load_25_reg_4213 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state37)) begin
+        in1_loc_load_26_reg_4228 <= in1_loc_q1;
+        in1_loc_load_27_reg_4233 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state38)) begin
+        in1_loc_load_28_reg_4248 <= in1_loc_q1;
+        in1_loc_load_29_reg_4253 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in1_loc_load_2_reg_3988 <= in1_loc_q1;
+        in1_loc_load_3_reg_3993 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state39)) begin
+        in1_loc_load_30_reg_4268 <= in1_loc_q1;
+        in1_loc_load_31_reg_4273 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state40)) begin
+        in1_loc_load_32_reg_4288 <= in1_loc_q1;
+        in1_loc_load_33_reg_4293 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state41)) begin
+        in1_loc_load_34_reg_4308 <= in1_loc_q1;
+        in1_loc_load_35_reg_4313 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state42)) begin
+        in1_loc_load_36_reg_4328 <= in1_loc_q1;
+        in1_loc_load_37_reg_4333 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state43)) begin
+        in1_loc_load_38_reg_4348 <= in1_loc_q1;
+        in1_loc_load_39_reg_4353 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state44)) begin
+        in1_loc_load_40_reg_4368 <= in1_loc_q1;
+        in1_loc_load_41_reg_4373 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state45)) begin
+        in1_loc_load_42_reg_4388 <= in1_loc_q1;
+        in1_loc_load_43_reg_4393 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state46)) begin
+        in1_loc_load_44_reg_4408 <= in1_loc_q1;
+        in1_loc_load_45_reg_4413 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state47)) begin
+        in1_loc_load_46_reg_4428 <= in1_loc_q1;
+        in1_loc_load_47_reg_4433 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state48)) begin
+        in1_loc_load_48_reg_4448 <= in1_loc_q1;
+        in1_loc_load_49_reg_4453 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state26)) begin
+        in1_loc_load_4_reg_4008 <= in1_loc_q1;
+        in1_loc_load_5_reg_4013 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state49)) begin
+        in1_loc_load_50_reg_4468 <= in1_loc_q1;
+        in1_loc_load_51_reg_4473 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state50)) begin
+        in1_loc_load_52_reg_4488 <= in1_loc_q1;
+        in1_loc_load_53_reg_4493 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state51)) begin
+        in1_loc_load_54_reg_4508 <= in1_loc_q1;
+        in1_loc_load_55_reg_4513 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state52)) begin
+        in1_loc_load_56_reg_4528 <= in1_loc_q1;
+        in1_loc_load_57_reg_4533 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state53)) begin
+        in1_loc_load_58_reg_4548 <= in1_loc_q1;
+        in1_loc_load_59_reg_4553 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state54)) begin
+        in1_loc_load_60_reg_4568 <= in1_loc_q1;
+        in1_loc_load_61_reg_4573 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state55)) begin
+        in1_loc_load_62_reg_4583 <= in1_loc_q1;
+        in1_loc_load_63_reg_4588 <= in1_loc_q0;
+        zext_ln38_cast_reg_4578[13 : 6] <= zext_ln38_cast_fu_2474_p3[13 : 6];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state27)) begin
+        in1_loc_load_6_reg_4028 <= in1_loc_q1;
+        in1_loc_load_7_reg_4033 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state28)) begin
+        in1_loc_load_8_reg_4048 <= in1_loc_q1;
+        in1_loc_load_9_reg_4053 <= in1_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_reg_3840 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_addr_read_reg_3849 <= in1_mem_RDATA;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_reg_3854 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_addr_read_reg_3863 <= in2_mem_RDATA;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        in2_mem_addr_reg_3834[29 : 0] <= empty_5_fu_1516_p1[29 : 0];
+        out_mem_addr_reg_3828[29 : 0] <= empty_fu_1507_p1[29 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state56)) begin
+        j_reg_4596 <= j_fu_2486_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state57)) begin
+        mul_ln38_1_reg_4697 <= mul_ln38_1_fu_2547_p2;
+        mul_ln38_reg_4692 <= mul_ln38_fu_2542_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln33_fu_2481_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state56))) begin
+        out_loc_addr_reg_4677 <= sext_ln38_64_fu_2517_p1;
+        trunc_ln38_1_reg_4601 <= trunc_ln38_1_fu_2497_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln42_reg_5307 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_11001))) begin
+        out_loc_load_reg_5321 <= out_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_1563_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state23))) begin
+        tmp_2_reg_3877[36 : 6] <= tmp_2_fu_1574_p3[36 : 6];
+        trunc_ln38_reg_3943 <= trunc_ln38_fu_1587_p1;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln27_fu_1525_p2 == 1'd1)) begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b1;
+    end else begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln28_fu_1542_p2 == 1'd1)) begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b1;
+    end else begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln42_fu_3784_p2 == 1'd1)) begin
+        ap_condition_pp2_exit_iter0_state90 = 1'b1;
+    end else begin
+        ap_condition_pp2_exit_iter0_state90 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state97))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b0))) begin
+        ap_idle_pp1 = 1'b1;
+    end else begin
+        ap_idle_pp1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp2_iter2 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b0) & (ap_enable_reg_pp2_iter0 == 1'b0))) begin
+        ap_idle_pp2 = 1'b1;
+    end else begin
+        ap_idle_pp2 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln27_reg_3840 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_phi_mux_phi_ln27_phi_fu_1414_p4 = add_ln27_reg_3844;
+    end else begin
+        ap_phi_mux_phi_ln27_phi_fu_1414_p4 = phi_ln27_reg_1410;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0) & (icmp_ln28_reg_3854 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        ap_phi_mux_phi_ln28_phi_fu_1426_p4 = add_ln28_reg_3858;
+    end else begin
+        ap_phi_mux_phi_ln28_phi_fu_1426_p4 = phi_ln28_reg_1422;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state97))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state54)) begin
+        in1_loc_address0 = tmp_64_fu_2465_p3;
+    end else if ((1'b1 == ap_CS_fsm_state53)) begin
+        in1_loc_address0 = tmp_62_fu_2437_p3;
+    end else if ((1'b1 == ap_CS_fsm_state52)) begin
+        in1_loc_address0 = tmp_60_fu_2409_p3;
+    end else if ((1'b1 == ap_CS_fsm_state51)) begin
+        in1_loc_address0 = tmp_58_fu_2381_p3;
+    end else if ((1'b1 == ap_CS_fsm_state50)) begin
+        in1_loc_address0 = tmp_56_fu_2353_p3;
+    end else if ((1'b1 == ap_CS_fsm_state49)) begin
+        in1_loc_address0 = tmp_54_fu_2325_p3;
+    end else if ((1'b1 == ap_CS_fsm_state48)) begin
+        in1_loc_address0 = tmp_52_fu_2297_p3;
+    end else if ((1'b1 == ap_CS_fsm_state47)) begin
+        in1_loc_address0 = tmp_50_fu_2269_p3;
+    end else if ((1'b1 == ap_CS_fsm_state46)) begin
+        in1_loc_address0 = tmp_48_fu_2241_p3;
+    end else if ((1'b1 == ap_CS_fsm_state45)) begin
+        in1_loc_address0 = tmp_46_fu_2213_p3;
+    end else if ((1'b1 == ap_CS_fsm_state44)) begin
+        in1_loc_address0 = tmp_44_fu_2185_p3;
+    end else if ((1'b1 == ap_CS_fsm_state43)) begin
+        in1_loc_address0 = tmp_42_fu_2157_p3;
+    end else if ((1'b1 == ap_CS_fsm_state42)) begin
+        in1_loc_address0 = tmp_40_fu_2129_p3;
+    end else if ((1'b1 == ap_CS_fsm_state41)) begin
+        in1_loc_address0 = tmp_38_fu_2101_p3;
+    end else if ((1'b1 == ap_CS_fsm_state40)) begin
+        in1_loc_address0 = tmp_36_fu_2073_p3;
+    end else if ((1'b1 == ap_CS_fsm_state39)) begin
+        in1_loc_address0 = tmp_34_fu_2045_p3;
+    end else if ((1'b1 == ap_CS_fsm_state38)) begin
+        in1_loc_address0 = tmp_32_fu_2017_p3;
+    end else if ((1'b1 == ap_CS_fsm_state37)) begin
+        in1_loc_address0 = tmp_30_fu_1989_p3;
+    end else if ((1'b1 == ap_CS_fsm_state36)) begin
+        in1_loc_address0 = tmp_28_fu_1961_p3;
+    end else if ((1'b1 == ap_CS_fsm_state35)) begin
+        in1_loc_address0 = tmp_26_fu_1933_p3;
+    end else if ((1'b1 == ap_CS_fsm_state34)) begin
+        in1_loc_address0 = tmp_24_fu_1905_p3;
+    end else if ((1'b1 == ap_CS_fsm_state33)) begin
+        in1_loc_address0 = tmp_22_fu_1877_p3;
+    end else if ((1'b1 == ap_CS_fsm_state32)) begin
+        in1_loc_address0 = tmp_20_fu_1849_p3;
+    end else if ((1'b1 == ap_CS_fsm_state31)) begin
+        in1_loc_address0 = tmp_18_fu_1821_p3;
+    end else if ((1'b1 == ap_CS_fsm_state30)) begin
+        in1_loc_address0 = tmp_16_fu_1793_p3;
+    end else if ((1'b1 == ap_CS_fsm_state29)) begin
+        in1_loc_address0 = tmp_14_fu_1765_p3;
+    end else if ((1'b1 == ap_CS_fsm_state28)) begin
+        in1_loc_address0 = tmp_12_fu_1737_p3;
+    end else if ((1'b1 == ap_CS_fsm_state27)) begin
+        in1_loc_address0 = tmp_10_fu_1709_p3;
+    end else if ((1'b1 == ap_CS_fsm_state26)) begin
+        in1_loc_address0 = tmp_9_fu_1681_p3;
+    end else if ((1'b1 == ap_CS_fsm_state25)) begin
+        in1_loc_address0 = tmp_7_fu_1653_p3;
+    end else if ((1'b1 == ap_CS_fsm_state24)) begin
+        in1_loc_address0 = tmp_5_fu_1625_p3;
+    end else if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_address0 = zext_ln38_fu_1582_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_address0 = zext_ln27_fu_1537_p1;
+    end else begin
+        in1_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state54)) begin
+        in1_loc_address1 = tmp_63_fu_2451_p3;
+    end else if ((1'b1 == ap_CS_fsm_state53)) begin
+        in1_loc_address1 = tmp_61_fu_2423_p3;
+    end else if ((1'b1 == ap_CS_fsm_state52)) begin
+        in1_loc_address1 = tmp_59_fu_2395_p3;
+    end else if ((1'b1 == ap_CS_fsm_state51)) begin
+        in1_loc_address1 = tmp_57_fu_2367_p3;
+    end else if ((1'b1 == ap_CS_fsm_state50)) begin
+        in1_loc_address1 = tmp_55_fu_2339_p3;
+    end else if ((1'b1 == ap_CS_fsm_state49)) begin
+        in1_loc_address1 = tmp_53_fu_2311_p3;
+    end else if ((1'b1 == ap_CS_fsm_state48)) begin
+        in1_loc_address1 = tmp_51_fu_2283_p3;
+    end else if ((1'b1 == ap_CS_fsm_state47)) begin
+        in1_loc_address1 = tmp_49_fu_2255_p3;
+    end else if ((1'b1 == ap_CS_fsm_state46)) begin
+        in1_loc_address1 = tmp_47_fu_2227_p3;
+    end else if ((1'b1 == ap_CS_fsm_state45)) begin
+        in1_loc_address1 = tmp_45_fu_2199_p3;
+    end else if ((1'b1 == ap_CS_fsm_state44)) begin
+        in1_loc_address1 = tmp_43_fu_2171_p3;
+    end else if ((1'b1 == ap_CS_fsm_state43)) begin
+        in1_loc_address1 = tmp_41_fu_2143_p3;
+    end else if ((1'b1 == ap_CS_fsm_state42)) begin
+        in1_loc_address1 = tmp_39_fu_2115_p3;
+    end else if ((1'b1 == ap_CS_fsm_state41)) begin
+        in1_loc_address1 = tmp_37_fu_2087_p3;
+    end else if ((1'b1 == ap_CS_fsm_state40)) begin
+        in1_loc_address1 = tmp_35_fu_2059_p3;
+    end else if ((1'b1 == ap_CS_fsm_state39)) begin
+        in1_loc_address1 = tmp_33_fu_2031_p3;
+    end else if ((1'b1 == ap_CS_fsm_state38)) begin
+        in1_loc_address1 = tmp_31_fu_2003_p3;
+    end else if ((1'b1 == ap_CS_fsm_state37)) begin
+        in1_loc_address1 = tmp_29_fu_1975_p3;
+    end else if ((1'b1 == ap_CS_fsm_state36)) begin
+        in1_loc_address1 = tmp_27_fu_1947_p3;
+    end else if ((1'b1 == ap_CS_fsm_state35)) begin
+        in1_loc_address1 = tmp_25_fu_1919_p3;
+    end else if ((1'b1 == ap_CS_fsm_state34)) begin
+        in1_loc_address1 = tmp_23_fu_1891_p3;
+    end else if ((1'b1 == ap_CS_fsm_state33)) begin
+        in1_loc_address1 = tmp_21_fu_1863_p3;
+    end else if ((1'b1 == ap_CS_fsm_state32)) begin
+        in1_loc_address1 = tmp_19_fu_1835_p3;
+    end else if ((1'b1 == ap_CS_fsm_state31)) begin
+        in1_loc_address1 = tmp_17_fu_1807_p3;
+    end else if ((1'b1 == ap_CS_fsm_state30)) begin
+        in1_loc_address1 = tmp_15_fu_1779_p3;
+    end else if ((1'b1 == ap_CS_fsm_state29)) begin
+        in1_loc_address1 = tmp_13_fu_1751_p3;
+    end else if ((1'b1 == ap_CS_fsm_state28)) begin
+        in1_loc_address1 = tmp_11_fu_1723_p3;
+    end else if ((1'b1 == ap_CS_fsm_state27)) begin
+        in1_loc_address1 = tmp_s_fu_1695_p3;
+    end else if ((1'b1 == ap_CS_fsm_state26)) begin
+        in1_loc_address1 = tmp_8_fu_1667_p3;
+    end else if ((1'b1 == ap_CS_fsm_state25)) begin
+        in1_loc_address1 = tmp_6_fu_1639_p3;
+    end else if ((1'b1 == ap_CS_fsm_state24)) begin
+        in1_loc_address1 = tmp_4_fu_1611_p3;
+    end else if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_address1 = tmp_3_fu_1597_p3;
+    end else begin
+        in1_loc_address1 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state51) | (1'b1 == ap_CS_fsm_state50) | (1'b1 == ap_CS_fsm_state49) | (1'b1 == ap_CS_fsm_state48) | (1'b1 == ap_CS_fsm_state47) | (1'b1 == ap_CS_fsm_state46) | (1'b1 == ap_CS_fsm_state45) | (1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state43) | (1'b1 == ap_CS_fsm_state42) | (1'b1 == ap_CS_fsm_state41) | (1'b1 == ap_CS_fsm_state40) | (1'b1 == ap_CS_fsm_state39) | (1'b1 == ap_CS_fsm_state38) | (1'b1 == ap_CS_fsm_state37) | (1'b1 == ap_CS_fsm_state36) | (1'b1 == ap_CS_fsm_state35) | (1'b1 == ap_CS_fsm_state34) | (1'b1 == ap_CS_fsm_state33) | (1'b1 == ap_CS_fsm_state32) | (1'b1 == ap_CS_fsm_state31) | (1'b1 == ap_CS_fsm_state30) | (1'b1 == ap_CS_fsm_state29) | (1'b1 == ap_CS_fsm_state28) | (1'b1 == ap_CS_fsm_state27) | (1'b1 == ap_CS_fsm_state26) | (1'b1 == ap_CS_fsm_state25) | (1'b1 == ap_CS_fsm_state24) | (1'b1 == ap_CS_fsm_state54) | (1'b1 == ap_CS_fsm_state53) | (1'b1 == ap_CS_fsm_state52) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_ce0 = 1'b1;
+    end else begin
+        in1_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state51) | (1'b1 == ap_CS_fsm_state50) | (1'b1 == ap_CS_fsm_state49) | (1'b1 == ap_CS_fsm_state48) | (1'b1 == ap_CS_fsm_state47) | (1'b1 == ap_CS_fsm_state46) | (1'b1 == ap_CS_fsm_state45) | (1'b1 == ap_CS_fsm_state44) | (1'b1 == ap_CS_fsm_state43) | (1'b1 == ap_CS_fsm_state42) | (1'b1 == ap_CS_fsm_state41) | (1'b1 == ap_CS_fsm_state40) | (1'b1 == ap_CS_fsm_state39) | (1'b1 == ap_CS_fsm_state38) | (1'b1 == ap_CS_fsm_state37) | (1'b1 == ap_CS_fsm_state36) | (1'b1 == ap_CS_fsm_state35) | (1'b1 == ap_CS_fsm_state34) | (1'b1 == ap_CS_fsm_state33) | (1'b1 == ap_CS_fsm_state32) | (1'b1 == ap_CS_fsm_state31) | (1'b1 == ap_CS_fsm_state30) | (1'b1 == ap_CS_fsm_state29) | (1'b1 == ap_CS_fsm_state28) | (1'b1 == ap_CS_fsm_state27) | (1'b1 == ap_CS_fsm_state26) | (1'b1 == ap_CS_fsm_state25) | (1'b1 == ap_CS_fsm_state24) | (1'b1 == ap_CS_fsm_state54) | (1'b1 == ap_CS_fsm_state53) | (1'b1 == ap_CS_fsm_state52) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_ce1 = 1'b1;
+    end else begin
+        in1_loc_ce1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_reg_3840_pp0_iter1_reg == 1'd0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_we0 = 1'b1;
+    end else begin
+        in1_loc_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        in1_mem_ARVALID = 1'b1;
+    end else begin
+        in1_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_reg_3840 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_RREADY = 1'b1;
+    end else begin
+        in1_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        in1_mem_blk_n_AR = m_axi_in1_mem_ARREADY;
+    end else begin
+        in1_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln27_reg_3840 == 1'd0) & (1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_blk_n_R = m_axi_in1_mem_RVALID;
+    end else begin
+        in1_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state87)) begin
+        in2_loc_address0 = sext_ln38_63_fu_3718_p1;
+    end else if ((1'b1 == ap_CS_fsm_state86)) begin
+        in2_loc_address0 = sext_ln38_61_fu_3678_p1;
+    end else if ((1'b1 == ap_CS_fsm_state85)) begin
+        in2_loc_address0 = sext_ln38_59_fu_3643_p1;
+    end else if ((1'b1 == ap_CS_fsm_state84)) begin
+        in2_loc_address0 = sext_ln38_57_fu_3598_p1;
+    end else if ((1'b1 == ap_CS_fsm_state83)) begin
+        in2_loc_address0 = sext_ln38_55_fu_3563_p1;
+    end else if ((1'b1 == ap_CS_fsm_state82)) begin
+        in2_loc_address0 = sext_ln38_53_fu_3523_p1;
+    end else if ((1'b1 == ap_CS_fsm_state81)) begin
+        in2_loc_address0 = sext_ln38_51_fu_3488_p1;
+    end else if ((1'b1 == ap_CS_fsm_state80)) begin
+        in2_loc_address0 = sext_ln38_49_fu_3438_p1;
+    end else if ((1'b1 == ap_CS_fsm_state79)) begin
+        in2_loc_address0 = sext_ln38_47_fu_3403_p1;
+    end else if ((1'b1 == ap_CS_fsm_state78)) begin
+        in2_loc_address0 = sext_ln38_45_fu_3363_p1;
+    end else if ((1'b1 == ap_CS_fsm_state77)) begin
+        in2_loc_address0 = sext_ln38_43_fu_3328_p1;
+    end else if ((1'b1 == ap_CS_fsm_state76)) begin
+        in2_loc_address0 = sext_ln38_41_fu_3283_p1;
+    end else if ((1'b1 == ap_CS_fsm_state75)) begin
+        in2_loc_address0 = sext_ln38_39_fu_3248_p1;
+    end else if ((1'b1 == ap_CS_fsm_state74)) begin
+        in2_loc_address0 = sext_ln38_37_fu_3208_p1;
+    end else if ((1'b1 == ap_CS_fsm_state73)) begin
+        in2_loc_address0 = sext_ln38_35_fu_3173_p1;
+    end else if ((1'b1 == ap_CS_fsm_state72)) begin
+        in2_loc_address0 = sext_ln38_33_fu_3118_p1;
+    end else if ((1'b1 == ap_CS_fsm_state71)) begin
+        in2_loc_address0 = sext_ln38_31_fu_3083_p1;
+    end else if ((1'b1 == ap_CS_fsm_state70)) begin
+        in2_loc_address0 = sext_ln38_29_fu_3043_p1;
+    end else if ((1'b1 == ap_CS_fsm_state69)) begin
+        in2_loc_address0 = sext_ln38_27_fu_3008_p1;
+    end else if ((1'b1 == ap_CS_fsm_state68)) begin
+        in2_loc_address0 = sext_ln38_25_fu_2963_p1;
+    end else if ((1'b1 == ap_CS_fsm_state67)) begin
+        in2_loc_address0 = sext_ln38_23_fu_2928_p1;
+    end else if ((1'b1 == ap_CS_fsm_state66)) begin
+        in2_loc_address0 = sext_ln38_21_fu_2888_p1;
+    end else if ((1'b1 == ap_CS_fsm_state65)) begin
+        in2_loc_address0 = sext_ln38_19_fu_2853_p1;
+    end else if ((1'b1 == ap_CS_fsm_state64)) begin
+        in2_loc_address0 = sext_ln38_17_fu_2803_p1;
+    end else if ((1'b1 == ap_CS_fsm_state63)) begin
+        in2_loc_address0 = sext_ln38_15_fu_2768_p1;
+    end else if ((1'b1 == ap_CS_fsm_state62)) begin
+        in2_loc_address0 = sext_ln38_13_fu_2728_p1;
+    end else if ((1'b1 == ap_CS_fsm_state61)) begin
+        in2_loc_address0 = sext_ln38_11_fu_2693_p1;
+    end else if ((1'b1 == ap_CS_fsm_state60)) begin
+        in2_loc_address0 = sext_ln38_9_fu_2648_p1;
+    end else if ((1'b1 == ap_CS_fsm_state59)) begin
+        in2_loc_address0 = sext_ln38_7_fu_2613_p1;
+    end else if ((1'b1 == ap_CS_fsm_state58)) begin
+        in2_loc_address0 = sext_ln38_5_fu_2567_p1;
+    end else if ((1'b1 == ap_CS_fsm_state57)) begin
+        in2_loc_address0 = sext_ln38_3_fu_2537_p1;
+    end else if ((1'b1 == ap_CS_fsm_state56)) begin
+        in2_loc_address0 = sext_ln38_fu_2492_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_address0 = zext_ln28_fu_1554_p1;
+    end else begin
+        in2_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state87)) begin
+        in2_loc_address1 = sext_ln38_62_fu_3708_p1;
+    end else if ((1'b1 == ap_CS_fsm_state86)) begin
+        in2_loc_address1 = sext_ln38_60_fu_3668_p1;
+    end else if ((1'b1 == ap_CS_fsm_state85)) begin
+        in2_loc_address1 = sext_ln38_58_fu_3633_p1;
+    end else if ((1'b1 == ap_CS_fsm_state84)) begin
+        in2_loc_address1 = sext_ln38_56_fu_3588_p1;
+    end else if ((1'b1 == ap_CS_fsm_state83)) begin
+        in2_loc_address1 = sext_ln38_54_fu_3553_p1;
+    end else if ((1'b1 == ap_CS_fsm_state82)) begin
+        in2_loc_address1 = sext_ln38_52_fu_3513_p1;
+    end else if ((1'b1 == ap_CS_fsm_state81)) begin
+        in2_loc_address1 = sext_ln38_50_fu_3478_p1;
+    end else if ((1'b1 == ap_CS_fsm_state80)) begin
+        in2_loc_address1 = sext_ln38_48_fu_3428_p1;
+    end else if ((1'b1 == ap_CS_fsm_state79)) begin
+        in2_loc_address1 = sext_ln38_46_fu_3393_p1;
+    end else if ((1'b1 == ap_CS_fsm_state78)) begin
+        in2_loc_address1 = sext_ln38_44_fu_3353_p1;
+    end else if ((1'b1 == ap_CS_fsm_state77)) begin
+        in2_loc_address1 = sext_ln38_42_fu_3318_p1;
+    end else if ((1'b1 == ap_CS_fsm_state76)) begin
+        in2_loc_address1 = sext_ln38_40_fu_3273_p1;
+    end else if ((1'b1 == ap_CS_fsm_state75)) begin
+        in2_loc_address1 = sext_ln38_38_fu_3238_p1;
+    end else if ((1'b1 == ap_CS_fsm_state74)) begin
+        in2_loc_address1 = sext_ln38_36_fu_3198_p1;
+    end else if ((1'b1 == ap_CS_fsm_state73)) begin
+        in2_loc_address1 = sext_ln38_34_fu_3163_p1;
+    end else if ((1'b1 == ap_CS_fsm_state72)) begin
+        in2_loc_address1 = sext_ln38_32_fu_3108_p1;
+    end else if ((1'b1 == ap_CS_fsm_state71)) begin
+        in2_loc_address1 = sext_ln38_30_fu_3073_p1;
+    end else if ((1'b1 == ap_CS_fsm_state70)) begin
+        in2_loc_address1 = sext_ln38_28_fu_3033_p1;
+    end else if ((1'b1 == ap_CS_fsm_state69)) begin
+        in2_loc_address1 = sext_ln38_26_fu_2998_p1;
+    end else if ((1'b1 == ap_CS_fsm_state68)) begin
+        in2_loc_address1 = sext_ln38_24_fu_2953_p1;
+    end else if ((1'b1 == ap_CS_fsm_state67)) begin
+        in2_loc_address1 = sext_ln38_22_fu_2918_p1;
+    end else if ((1'b1 == ap_CS_fsm_state66)) begin
+        in2_loc_address1 = sext_ln38_20_fu_2878_p1;
+    end else if ((1'b1 == ap_CS_fsm_state65)) begin
+        in2_loc_address1 = sext_ln38_18_fu_2843_p1;
+    end else if ((1'b1 == ap_CS_fsm_state64)) begin
+        in2_loc_address1 = sext_ln38_16_fu_2793_p1;
+    end else if ((1'b1 == ap_CS_fsm_state63)) begin
+        in2_loc_address1 = sext_ln38_14_fu_2758_p1;
+    end else if ((1'b1 == ap_CS_fsm_state62)) begin
+        in2_loc_address1 = sext_ln38_12_fu_2718_p1;
+    end else if ((1'b1 == ap_CS_fsm_state61)) begin
+        in2_loc_address1 = sext_ln38_10_fu_2683_p1;
+    end else if ((1'b1 == ap_CS_fsm_state60)) begin
+        in2_loc_address1 = sext_ln38_8_fu_2638_p1;
+    end else if ((1'b1 == ap_CS_fsm_state59)) begin
+        in2_loc_address1 = sext_ln38_6_fu_2603_p1;
+    end else if ((1'b1 == ap_CS_fsm_state58)) begin
+        in2_loc_address1 = sext_ln38_4_fu_2557_p1;
+    end else if ((1'b1 == ap_CS_fsm_state57)) begin
+        in2_loc_address1 = sext_ln38_2_fu_2527_p1;
+    end else if ((1'b1 == ap_CS_fsm_state56)) begin
+        in2_loc_address1 = sext_ln38_1_fu_2507_p1;
+    end else begin
+        in2_loc_address1 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state87) | (1'b1 == ap_CS_fsm_state86) | (1'b1 == ap_CS_fsm_state85) | (1'b1 == ap_CS_fsm_state84) | (1'b1 == ap_CS_fsm_state83) | (1'b1 == ap_CS_fsm_state82) | (1'b1 == ap_CS_fsm_state81) | (1'b1 == ap_CS_fsm_state80) | (1'b1 == ap_CS_fsm_state79) | (1'b1 == ap_CS_fsm_state78) | (1'b1 == ap_CS_fsm_state77) | (1'b1 == ap_CS_fsm_state76) | (1'b1 == ap_CS_fsm_state75) | (1'b1 == ap_CS_fsm_state74) | (1'b1 == ap_CS_fsm_state73) | (1'b1 == ap_CS_fsm_state72) | (1'b1 == ap_CS_fsm_state71) | (1'b1 == ap_CS_fsm_state70) | (1'b1 == ap_CS_fsm_state69) | (1'b1 == ap_CS_fsm_state68) | (1'b1 == ap_CS_fsm_state67) | (1'b1 == ap_CS_fsm_state66) | (1'b1 == ap_CS_fsm_state65) | (1'b1 == ap_CS_fsm_state64) | (1'b1 == ap_CS_fsm_state63) | (1'b1 == ap_CS_fsm_state62) | (1'b1 == ap_CS_fsm_state61) | (1'b1 == ap_CS_fsm_state60) | (1'b1 == ap_CS_fsm_state59) | (1'b1 == ap_CS_fsm_state58) | (1'b1 == ap_CS_fsm_state57) | (1'b1 == ap_CS_fsm_state56) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_ce0 = 1'b1;
+    end else begin
+        in2_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state87) | (1'b1 == ap_CS_fsm_state86) | (1'b1 == ap_CS_fsm_state85) | (1'b1 == ap_CS_fsm_state84) | (1'b1 == ap_CS_fsm_state83) | (1'b1 == ap_CS_fsm_state82) | (1'b1 == ap_CS_fsm_state81) | (1'b1 == ap_CS_fsm_state80) | (1'b1 == ap_CS_fsm_state79) | (1'b1 == ap_CS_fsm_state78) | (1'b1 == ap_CS_fsm_state77) | (1'b1 == ap_CS_fsm_state76) | (1'b1 == ap_CS_fsm_state75) | (1'b1 == ap_CS_fsm_state74) | (1'b1 == ap_CS_fsm_state73) | (1'b1 == ap_CS_fsm_state72) | (1'b1 == ap_CS_fsm_state71) | (1'b1 == ap_CS_fsm_state70) | (1'b1 == ap_CS_fsm_state69) | (1'b1 == ap_CS_fsm_state68) | (1'b1 == ap_CS_fsm_state67) | (1'b1 == ap_CS_fsm_state66) | (1'b1 == ap_CS_fsm_state65) | (1'b1 == ap_CS_fsm_state64) | (1'b1 == ap_CS_fsm_state63) | (1'b1 == ap_CS_fsm_state62) | (1'b1 == ap_CS_fsm_state61) | (1'b1 == ap_CS_fsm_state60) | (1'b1 == ap_CS_fsm_state59) | (1'b1 == ap_CS_fsm_state58) | (1'b1 == ap_CS_fsm_state57) | (1'b1 == ap_CS_fsm_state56))) begin
+        in2_loc_ce1 = 1'b1;
+    end else begin
+        in2_loc_ce1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_reg_3854_pp1_iter1_reg == 1'd0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_we0 = 1'b1;
+    end else begin
+        in2_loc_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+        in2_mem_ARVALID = 1'b1;
+    end else begin
+        in2_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_reg_3854 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_RREADY = 1'b1;
+    end else begin
+        in2_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state12)) begin
+        in2_mem_blk_n_AR = m_axi_in2_mem_ARREADY;
+    end else begin
+        in2_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0) & (icmp_ln28_reg_3854 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_blk_n_R = m_axi_in2_mem_RVALID;
+    end else begin
+        in2_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        out_loc_address0 = zext_ln42_fu_3796_p1;
+    end else if (((1'b1 == ap_CS_fsm_state89) | (1'b1 == ap_CS_fsm_state57))) begin
+        out_loc_address0 = out_loc_addr_reg_4677;
+    end else begin
+        out_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state89) | (1'b1 == ap_CS_fsm_state57) | ((ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_11001)))) begin
+        out_loc_ce0 = 1'b1;
+    end else begin
+        out_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state89)) begin
+        out_loc_we0 = 1'b1;
+    end else begin
+        out_loc_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_1563_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+        out_mem_AWVALID = 1'b1;
+    end else begin
+        out_mem_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state97))) begin
+        out_mem_BREADY = 1'b1;
+    end else begin
+        out_mem_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln42_reg_5307_pp2_iter1_reg == 1'd0) & (ap_enable_reg_pp2_iter2 == 1'b1) & (1'b0 == ap_block_pp2_stage0_11001))) begin
+        out_mem_WVALID = 1'b1;
+    end else begin
+        out_mem_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln31_fu_1563_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+        out_mem_blk_n_AW = m_axi_out_mem_AWREADY;
+    end else begin
+        out_mem_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state97)) begin
+        out_mem_blk_n_B = m_axi_out_mem_BVALID;
+    end else begin
+        out_mem_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (icmp_ln42_reg_5307_pp2_iter1_reg == 1'd0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        out_mem_blk_n_W = m_axi_out_mem_WREADY;
+    end else begin
+        out_mem_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        ap_ST_fsm_pp0_stage0 : begin
+            if ((~((icmp_ln27_fu_1525_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end else if ((((icmp_ln27_fu_1525_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end
+        end
+        ap_ST_fsm_state12 : begin
+            if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+                ap_NS_fsm = ap_ST_fsm_state13;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end
+        end
+        ap_ST_fsm_state13 : begin
+            ap_NS_fsm = ap_ST_fsm_state14;
+        end
+        ap_ST_fsm_state14 : begin
+            ap_NS_fsm = ap_ST_fsm_state15;
+        end
+        ap_ST_fsm_state15 : begin
+            ap_NS_fsm = ap_ST_fsm_state16;
+        end
+        ap_ST_fsm_state16 : begin
+            ap_NS_fsm = ap_ST_fsm_state17;
+        end
+        ap_ST_fsm_state17 : begin
+            ap_NS_fsm = ap_ST_fsm_state18;
+        end
+        ap_ST_fsm_state18 : begin
+            ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+        end
+        ap_ST_fsm_pp1_stage0 : begin
+            if ((~((icmp_ln28_fu_1542_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)) & ~((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end else if ((((icmp_ln28_fu_1542_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)) | ((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state22;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end
+        end
+        ap_ST_fsm_state22 : begin
+            ap_NS_fsm = ap_ST_fsm_state23;
+        end
+        ap_ST_fsm_state23 : begin
+            if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_1563_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end else if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_1563_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state23))) begin
+                ap_NS_fsm = ap_ST_fsm_state24;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state23;
+            end
+        end
+        ap_ST_fsm_state24 : begin
+            ap_NS_fsm = ap_ST_fsm_state25;
+        end
+        ap_ST_fsm_state25 : begin
+            ap_NS_fsm = ap_ST_fsm_state26;
+        end
+        ap_ST_fsm_state26 : begin
+            ap_NS_fsm = ap_ST_fsm_state27;
+        end
+        ap_ST_fsm_state27 : begin
+            ap_NS_fsm = ap_ST_fsm_state28;
+        end
+        ap_ST_fsm_state28 : begin
+            ap_NS_fsm = ap_ST_fsm_state29;
+        end
+        ap_ST_fsm_state29 : begin
+            ap_NS_fsm = ap_ST_fsm_state30;
+        end
+        ap_ST_fsm_state30 : begin
+            ap_NS_fsm = ap_ST_fsm_state31;
+        end
+        ap_ST_fsm_state31 : begin
+            ap_NS_fsm = ap_ST_fsm_state32;
+        end
+        ap_ST_fsm_state32 : begin
+            ap_NS_fsm = ap_ST_fsm_state33;
+        end
+        ap_ST_fsm_state33 : begin
+            ap_NS_fsm = ap_ST_fsm_state34;
+        end
+        ap_ST_fsm_state34 : begin
+            ap_NS_fsm = ap_ST_fsm_state35;
+        end
+        ap_ST_fsm_state35 : begin
+            ap_NS_fsm = ap_ST_fsm_state36;
+        end
+        ap_ST_fsm_state36 : begin
+            ap_NS_fsm = ap_ST_fsm_state37;
+        end
+        ap_ST_fsm_state37 : begin
+            ap_NS_fsm = ap_ST_fsm_state38;
+        end
+        ap_ST_fsm_state38 : begin
+            ap_NS_fsm = ap_ST_fsm_state39;
+        end
+        ap_ST_fsm_state39 : begin
+            ap_NS_fsm = ap_ST_fsm_state40;
+        end
+        ap_ST_fsm_state40 : begin
+            ap_NS_fsm = ap_ST_fsm_state41;
+        end
+        ap_ST_fsm_state41 : begin
+            ap_NS_fsm = ap_ST_fsm_state42;
+        end
+        ap_ST_fsm_state42 : begin
+            ap_NS_fsm = ap_ST_fsm_state43;
+        end
+        ap_ST_fsm_state43 : begin
+            ap_NS_fsm = ap_ST_fsm_state44;
+        end
+        ap_ST_fsm_state44 : begin
+            ap_NS_fsm = ap_ST_fsm_state45;
+        end
+        ap_ST_fsm_state45 : begin
+            ap_NS_fsm = ap_ST_fsm_state46;
+        end
+        ap_ST_fsm_state46 : begin
+            ap_NS_fsm = ap_ST_fsm_state47;
+        end
+        ap_ST_fsm_state47 : begin
+            ap_NS_fsm = ap_ST_fsm_state48;
+        end
+        ap_ST_fsm_state48 : begin
+            ap_NS_fsm = ap_ST_fsm_state49;
+        end
+        ap_ST_fsm_state49 : begin
+            ap_NS_fsm = ap_ST_fsm_state50;
+        end
+        ap_ST_fsm_state50 : begin
+            ap_NS_fsm = ap_ST_fsm_state51;
+        end
+        ap_ST_fsm_state51 : begin
+            ap_NS_fsm = ap_ST_fsm_state52;
+        end
+        ap_ST_fsm_state52 : begin
+            ap_NS_fsm = ap_ST_fsm_state53;
+        end
+        ap_ST_fsm_state53 : begin
+            ap_NS_fsm = ap_ST_fsm_state54;
+        end
+        ap_ST_fsm_state54 : begin
+            ap_NS_fsm = ap_ST_fsm_state55;
+        end
+        ap_ST_fsm_state55 : begin
+            ap_NS_fsm = ap_ST_fsm_state56;
+        end
+        ap_ST_fsm_state56 : begin
+            if (((icmp_ln33_fu_2481_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state56))) begin
+                ap_NS_fsm = ap_ST_fsm_state23;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state57;
+            end
+        end
+        ap_ST_fsm_state57 : begin
+            ap_NS_fsm = ap_ST_fsm_state58;
+        end
+        ap_ST_fsm_state58 : begin
+            ap_NS_fsm = ap_ST_fsm_state59;
+        end
+        ap_ST_fsm_state59 : begin
+            ap_NS_fsm = ap_ST_fsm_state60;
+        end
+        ap_ST_fsm_state60 : begin
+            ap_NS_fsm = ap_ST_fsm_state61;
+        end
+        ap_ST_fsm_state61 : begin
+            ap_NS_fsm = ap_ST_fsm_state62;
+        end
+        ap_ST_fsm_state62 : begin
+            ap_NS_fsm = ap_ST_fsm_state63;
+        end
+        ap_ST_fsm_state63 : begin
+            ap_NS_fsm = ap_ST_fsm_state64;
+        end
+        ap_ST_fsm_state64 : begin
+            ap_NS_fsm = ap_ST_fsm_state65;
+        end
+        ap_ST_fsm_state65 : begin
+            ap_NS_fsm = ap_ST_fsm_state66;
+        end
+        ap_ST_fsm_state66 : begin
+            ap_NS_fsm = ap_ST_fsm_state67;
+        end
+        ap_ST_fsm_state67 : begin
+            ap_NS_fsm = ap_ST_fsm_state68;
+        end
+        ap_ST_fsm_state68 : begin
+            ap_NS_fsm = ap_ST_fsm_state69;
+        end
+        ap_ST_fsm_state69 : begin
+            ap_NS_fsm = ap_ST_fsm_state70;
+        end
+        ap_ST_fsm_state70 : begin
+            ap_NS_fsm = ap_ST_fsm_state71;
+        end
+        ap_ST_fsm_state71 : begin
+            ap_NS_fsm = ap_ST_fsm_state72;
+        end
+        ap_ST_fsm_state72 : begin
+            ap_NS_fsm = ap_ST_fsm_state73;
+        end
+        ap_ST_fsm_state73 : begin
+            ap_NS_fsm = ap_ST_fsm_state74;
+        end
+        ap_ST_fsm_state74 : begin
+            ap_NS_fsm = ap_ST_fsm_state75;
+        end
+        ap_ST_fsm_state75 : begin
+            ap_NS_fsm = ap_ST_fsm_state76;
+        end
+        ap_ST_fsm_state76 : begin
+            ap_NS_fsm = ap_ST_fsm_state77;
+        end
+        ap_ST_fsm_state77 : begin
+            ap_NS_fsm = ap_ST_fsm_state78;
+        end
+        ap_ST_fsm_state78 : begin
+            ap_NS_fsm = ap_ST_fsm_state79;
+        end
+        ap_ST_fsm_state79 : begin
+            ap_NS_fsm = ap_ST_fsm_state80;
+        end
+        ap_ST_fsm_state80 : begin
+            ap_NS_fsm = ap_ST_fsm_state81;
+        end
+        ap_ST_fsm_state81 : begin
+            ap_NS_fsm = ap_ST_fsm_state82;
+        end
+        ap_ST_fsm_state82 : begin
+            ap_NS_fsm = ap_ST_fsm_state83;
+        end
+        ap_ST_fsm_state83 : begin
+            ap_NS_fsm = ap_ST_fsm_state84;
+        end
+        ap_ST_fsm_state84 : begin
+            ap_NS_fsm = ap_ST_fsm_state85;
+        end
+        ap_ST_fsm_state85 : begin
+            ap_NS_fsm = ap_ST_fsm_state86;
+        end
+        ap_ST_fsm_state86 : begin
+            ap_NS_fsm = ap_ST_fsm_state87;
+        end
+        ap_ST_fsm_state87 : begin
+            ap_NS_fsm = ap_ST_fsm_state88;
+        end
+        ap_ST_fsm_state88 : begin
+            ap_NS_fsm = ap_ST_fsm_state89;
+        end
+        ap_ST_fsm_state89 : begin
+            ap_NS_fsm = ap_ST_fsm_state56;
+        end
+        ap_ST_fsm_pp2_stage0 : begin
+            if ((~((icmp_ln42_fu_3784_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter1 == 1'b0)) & ~((ap_enable_reg_pp2_iter2 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter1 == 1'b0)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end else if ((((ap_enable_reg_pp2_iter2 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter1 == 1'b0)) | ((icmp_ln42_fu_3784_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter1 == 1'b0)))) begin
+                ap_NS_fsm = ap_ST_fsm_state93;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end
+        end
+        ap_ST_fsm_state93 : begin
+            ap_NS_fsm = ap_ST_fsm_state94;
+        end
+        ap_ST_fsm_state94 : begin
+            ap_NS_fsm = ap_ST_fsm_state95;
+        end
+        ap_ST_fsm_state95 : begin
+            ap_NS_fsm = ap_ST_fsm_state96;
+        end
+        ap_ST_fsm_state96 : begin
+            ap_NS_fsm = ap_ST_fsm_state97;
+        end
+        ap_ST_fsm_state97 : begin
+            if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state97))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state97;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln27_fu_1531_p2 = (ap_phi_mux_phi_ln27_phi_fu_1414_p4 + 13'd1);
+
+assign add_ln28_fu_1548_p2 = (ap_phi_mux_phi_ln28_phi_fu_1426_p4 + 13'd1);
+
+assign add_ln38_100_fu_3203_p2 = (14'd2368 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_101_fu_3233_p2 = (14'd2432 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_102_fu_3243_p2 = (14'd2496 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_103_fu_3268_p2 = (14'd2560 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_104_fu_3278_p2 = (14'd2624 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_105_fu_3313_p2 = (14'd2688 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_106_fu_3323_p2 = (14'd2752 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_107_fu_3348_p2 = (14'd2816 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_108_fu_3358_p2 = (14'd2880 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_109_fu_3388_p2 = (14'd2944 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_10_fu_2783_p2 = (mul_ln38_12_fu_2773_p2 + mul_ln38_11_reg_4792);
+
+assign add_ln38_110_fu_3398_p2 = (14'd3008 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_111_fu_3423_p2 = (14'd3072 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_112_fu_3433_p2 = (14'd3136 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_113_fu_3473_p2 = (14'd3200 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_114_fu_3483_p2 = (14'd3264 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_115_fu_3508_p2 = (14'd3328 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_116_fu_3518_p2 = (14'd3392 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_117_fu_3548_p2 = (14'd3456 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_118_fu_3558_p2 = (14'd3520 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_119_fu_3583_p2 = (14'd3584 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_11_fu_2818_p2 = (mul_ln38_14_fu_2808_p2 + mul_ln38_13_reg_4812);
+
+assign add_ln38_120_fu_3593_p2 = (14'd3648 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_121_fu_3628_p2 = (14'd3712 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_122_fu_3638_p2 = (14'd3776 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_123_fu_3663_p2 = (14'd3840 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_124_fu_3673_p2 = (14'd3904 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_125_fu_3703_p2 = (14'd3968 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_126_fu_3713_p2 = (14'd4032 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_127_fu_2512_p2 = (zext_ln38_cast_reg_4578 + trunc_ln38_1_fu_2497_p1);
+
+assign add_ln38_12_fu_2823_p2 = (add_ln38_10_reg_4817 + add_ln38_11_fu_2818_p2);
+
+assign add_ln38_13_fu_2828_p2 = (add_ln38_9_reg_4797 + add_ln38_12_fu_2823_p2);
+
+assign add_ln38_14_fu_2833_p2 = (add_ln38_6_reg_4757 + add_ln38_13_fu_2828_p2);
+
+assign add_ln38_15_fu_2868_p2 = (mul_ln38_16_fu_2858_p2 + mul_ln38_15_reg_4832);
+
+assign add_ln38_16_fu_2903_p2 = (mul_ln38_18_fu_2893_p2 + mul_ln38_17_reg_4852);
+
+assign add_ln38_17_fu_2908_p2 = (add_ln38_15_reg_4857 + add_ln38_16_fu_2903_p2);
+
+assign add_ln38_18_fu_2943_p2 = (mul_ln38_20_fu_2933_p2 + mul_ln38_19_reg_4872);
+
+assign add_ln38_19_fu_2978_p2 = (mul_ln38_22_fu_2968_p2 + mul_ln38_21_reg_4892);
+
+assign add_ln38_1_fu_2587_p2 = (mul_ln38_2_fu_2572_p2 + mul_ln38_1_reg_4697);
+
+assign add_ln38_20_fu_2983_p2 = (add_ln38_18_reg_4897 + add_ln38_19_fu_2978_p2);
+
+assign add_ln38_21_fu_2988_p2 = (add_ln38_17_reg_4877 + add_ln38_20_fu_2983_p2);
+
+assign add_ln38_22_fu_3023_p2 = (mul_ln38_24_fu_3013_p2 + mul_ln38_23_reg_4912);
+
+assign add_ln38_23_fu_3058_p2 = (mul_ln38_26_fu_3048_p2 + mul_ln38_25_reg_4932);
+
+assign add_ln38_24_fu_3063_p2 = (add_ln38_22_reg_4937 + add_ln38_23_fu_3058_p2);
+
+assign add_ln38_25_fu_3098_p2 = (mul_ln38_28_fu_3088_p2 + mul_ln38_27_reg_4952);
+
+assign add_ln38_26_fu_3133_p2 = (mul_ln38_30_fu_3123_p2 + mul_ln38_29_reg_4972);
+
+assign add_ln38_27_fu_3138_p2 = (add_ln38_25_reg_4977 + add_ln38_26_fu_3133_p2);
+
+assign add_ln38_28_fu_3143_p2 = (add_ln38_24_reg_4957 + add_ln38_27_fu_3138_p2);
+
+assign add_ln38_29_fu_3148_p2 = (add_ln38_21_reg_4917 + add_ln38_28_fu_3143_p2);
+
+assign add_ln38_2_fu_2592_p2 = (add_ln38_fu_2582_p2 + add_ln38_1_fu_2587_p2);
+
+assign add_ln38_30_fu_3153_p2 = (add_ln38_14_reg_4837 + add_ln38_29_fu_3148_p2);
+
+assign add_ln38_31_fu_3188_p2 = (mul_ln38_32_fu_3178_p2 + mul_ln38_31_reg_4992);
+
+assign add_ln38_32_fu_3223_p2 = (mul_ln38_34_fu_3213_p2 + mul_ln38_33_reg_5012);
+
+assign add_ln38_33_fu_3228_p2 = (add_ln38_31_reg_5017 + add_ln38_32_fu_3223_p2);
+
+assign add_ln38_34_fu_3263_p2 = (mul_ln38_36_fu_3253_p2 + mul_ln38_35_reg_5032);
+
+assign add_ln38_35_fu_3298_p2 = (mul_ln38_38_fu_3288_p2 + mul_ln38_37_reg_5052);
+
+assign add_ln38_36_fu_3303_p2 = (add_ln38_34_reg_5057 + add_ln38_35_fu_3298_p2);
+
+assign add_ln38_37_fu_3308_p2 = (add_ln38_33_reg_5037 + add_ln38_36_fu_3303_p2);
+
+assign add_ln38_38_fu_3343_p2 = (mul_ln38_40_fu_3333_p2 + mul_ln38_39_reg_5072);
+
+assign add_ln38_39_fu_3378_p2 = (mul_ln38_42_fu_3368_p2 + mul_ln38_41_reg_5092);
+
+assign add_ln38_3_fu_2628_p2 = (mul_ln38_4_fu_2618_p2 + mul_ln38_3_reg_4712);
+
+assign add_ln38_40_fu_3383_p2 = (add_ln38_38_reg_5097 + add_ln38_39_fu_3378_p2);
+
+assign add_ln38_41_fu_3418_p2 = (mul_ln38_44_fu_3408_p2 + mul_ln38_43_reg_5112);
+
+assign add_ln38_42_fu_3453_p2 = (mul_ln38_46_fu_3443_p2 + mul_ln38_45_reg_5132);
+
+assign add_ln38_43_fu_3458_p2 = (add_ln38_41_reg_5137 + add_ln38_42_fu_3453_p2);
+
+assign add_ln38_44_fu_3463_p2 = (add_ln38_40_reg_5117 + add_ln38_43_fu_3458_p2);
+
+assign add_ln38_45_fu_3468_p2 = (add_ln38_37_reg_5077 + add_ln38_44_fu_3463_p2);
+
+assign add_ln38_46_fu_3503_p2 = (mul_ln38_48_fu_3493_p2 + mul_ln38_47_reg_5152);
+
+assign add_ln38_47_fu_3538_p2 = (mul_ln38_50_fu_3528_p2 + mul_ln38_49_reg_5172);
+
+assign add_ln38_48_fu_3543_p2 = (add_ln38_46_reg_5177 + add_ln38_47_fu_3538_p2);
+
+assign add_ln38_49_fu_3578_p2 = (mul_ln38_52_fu_3568_p2 + mul_ln38_51_reg_5192);
+
+assign add_ln38_4_fu_2663_p2 = (mul_ln38_6_fu_2653_p2 + mul_ln38_5_reg_4732);
+
+assign add_ln38_50_fu_3613_p2 = (mul_ln38_54_fu_3603_p2 + mul_ln38_53_reg_5212);
+
+assign add_ln38_51_fu_3618_p2 = (add_ln38_49_reg_5217 + add_ln38_50_fu_3613_p2);
+
+assign add_ln38_52_fu_3623_p2 = (add_ln38_48_reg_5197 + add_ln38_51_fu_3618_p2);
+
+assign add_ln38_53_fu_3658_p2 = (mul_ln38_56_fu_3648_p2 + mul_ln38_55_reg_5232);
+
+assign add_ln38_54_fu_3693_p2 = (mul_ln38_58_fu_3683_p2 + mul_ln38_57_reg_5252);
+
+assign add_ln38_55_fu_3698_p2 = (add_ln38_53_reg_5257 + add_ln38_54_fu_3693_p2);
+
+assign add_ln38_56_fu_3733_p2 = (mul_ln38_60_fu_3723_p2 + mul_ln38_59_reg_5272);
+
+assign add_ln38_57_fu_3748_p2 = (mul_ln38_63_fu_3743_p2 + mul_ln38_62_fu_3738_p2);
+
+assign add_ln38_58_fu_3754_p2 = (mul_ln38_61_reg_5292 + add_ln38_57_fu_3748_p2);
+
+assign add_ln38_59_fu_3759_p2 = (add_ln38_56_reg_5297 + add_ln38_58_fu_3754_p2);
+
+assign add_ln38_5_fu_2668_p2 = (add_ln38_3_reg_4737 + add_ln38_4_fu_2663_p2);
+
+assign add_ln38_60_fu_3764_p2 = (add_ln38_55_reg_5277 + add_ln38_59_fu_3759_p2);
+
+assign add_ln38_61_fu_3769_p2 = (add_ln38_52_reg_5237 + add_ln38_60_fu_3764_p2);
+
+assign add_ln38_62_fu_3774_p2 = (add_ln38_45_reg_5157 + add_ln38_61_reg_5302);
+
+assign add_ln38_64_fu_2501_p2 = (14'd64 + trunc_ln38_1_fu_2497_p1);
+
+assign add_ln38_65_fu_2522_p2 = (14'd128 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_66_fu_2532_p2 = (14'd192 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_67_fu_2552_p2 = (14'd256 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_68_fu_2562_p2 = (14'd320 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_69_fu_2598_p2 = (14'd384 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_6_fu_2673_p2 = (add_ln38_2_reg_4717 + add_ln38_5_fu_2668_p2);
+
+assign add_ln38_70_fu_2608_p2 = (14'd448 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_71_fu_2633_p2 = (14'd512 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_72_fu_2643_p2 = (14'd576 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_73_fu_2678_p2 = (14'd640 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_74_fu_2688_p2 = (14'd704 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_75_fu_2713_p2 = (14'd768 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_76_fu_2723_p2 = (14'd832 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_77_fu_2753_p2 = (14'd896 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_78_fu_2763_p2 = (14'd960 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_79_fu_2788_p2 = (14'd1024 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_7_fu_2708_p2 = (mul_ln38_8_fu_2698_p2 + mul_ln38_7_reg_4752);
+
+assign add_ln38_80_fu_2798_p2 = (14'd1088 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_81_fu_2838_p2 = (14'd1152 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_82_fu_2848_p2 = (14'd1216 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_83_fu_2873_p2 = (14'd1280 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_84_fu_2883_p2 = (14'd1344 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_85_fu_2913_p2 = (14'd1408 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_86_fu_2923_p2 = (14'd1472 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_87_fu_2948_p2 = (14'd1536 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_88_fu_2958_p2 = (14'd1600 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_89_fu_2993_p2 = (14'd1664 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_8_fu_2743_p2 = (mul_ln38_10_fu_2733_p2 + mul_ln38_9_reg_4772);
+
+assign add_ln38_90_fu_3003_p2 = (14'd1728 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_91_fu_3028_p2 = (14'd1792 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_92_fu_3038_p2 = (14'd1856 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_93_fu_3068_p2 = (14'd1920 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_94_fu_3078_p2 = (14'd1984 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_95_fu_3103_p2 = (14'd2048 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_96_fu_3113_p2 = (14'd2112 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_97_fu_3158_p2 = (14'd2176 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_98_fu_3168_p2 = (14'd2240 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_99_fu_3193_p2 = (14'd2304 + trunc_ln38_1_reg_4601);
+
+assign add_ln38_9_fu_2748_p2 = (add_ln38_7_reg_4777 + add_ln38_8_fu_2743_p2);
+
+assign add_ln38_fu_2582_p2 = (mul_ln38_reg_4692 + out_loc_q0);
+
+assign add_ln42_fu_3790_p2 = (phi_ln42_reg_1456 + 13'd1);
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd8];
+
+assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd16];
+
+assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd85];
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state12 = ap_CS_fsm[32'd9];
+
+assign ap_CS_fsm_state18 = ap_CS_fsm[32'd15];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state22 = ap_CS_fsm[32'd17];
+
+assign ap_CS_fsm_state23 = ap_CS_fsm[32'd18];
+
+assign ap_CS_fsm_state24 = ap_CS_fsm[32'd19];
+
+assign ap_CS_fsm_state25 = ap_CS_fsm[32'd20];
+
+assign ap_CS_fsm_state26 = ap_CS_fsm[32'd21];
+
+assign ap_CS_fsm_state27 = ap_CS_fsm[32'd22];
+
+assign ap_CS_fsm_state28 = ap_CS_fsm[32'd23];
+
+assign ap_CS_fsm_state29 = ap_CS_fsm[32'd24];
+
+assign ap_CS_fsm_state30 = ap_CS_fsm[32'd25];
+
+assign ap_CS_fsm_state31 = ap_CS_fsm[32'd26];
+
+assign ap_CS_fsm_state32 = ap_CS_fsm[32'd27];
+
+assign ap_CS_fsm_state33 = ap_CS_fsm[32'd28];
+
+assign ap_CS_fsm_state34 = ap_CS_fsm[32'd29];
+
+assign ap_CS_fsm_state35 = ap_CS_fsm[32'd30];
+
+assign ap_CS_fsm_state36 = ap_CS_fsm[32'd31];
+
+assign ap_CS_fsm_state37 = ap_CS_fsm[32'd32];
+
+assign ap_CS_fsm_state38 = ap_CS_fsm[32'd33];
+
+assign ap_CS_fsm_state39 = ap_CS_fsm[32'd34];
+
+assign ap_CS_fsm_state40 = ap_CS_fsm[32'd35];
+
+assign ap_CS_fsm_state41 = ap_CS_fsm[32'd36];
+
+assign ap_CS_fsm_state42 = ap_CS_fsm[32'd37];
+
+assign ap_CS_fsm_state43 = ap_CS_fsm[32'd38];
+
+assign ap_CS_fsm_state44 = ap_CS_fsm[32'd39];
+
+assign ap_CS_fsm_state45 = ap_CS_fsm[32'd40];
+
+assign ap_CS_fsm_state46 = ap_CS_fsm[32'd41];
+
+assign ap_CS_fsm_state47 = ap_CS_fsm[32'd42];
+
+assign ap_CS_fsm_state48 = ap_CS_fsm[32'd43];
+
+assign ap_CS_fsm_state49 = ap_CS_fsm[32'd44];
+
+assign ap_CS_fsm_state50 = ap_CS_fsm[32'd45];
+
+assign ap_CS_fsm_state51 = ap_CS_fsm[32'd46];
+
+assign ap_CS_fsm_state52 = ap_CS_fsm[32'd47];
+
+assign ap_CS_fsm_state53 = ap_CS_fsm[32'd48];
+
+assign ap_CS_fsm_state54 = ap_CS_fsm[32'd49];
+
+assign ap_CS_fsm_state55 = ap_CS_fsm[32'd50];
+
+assign ap_CS_fsm_state56 = ap_CS_fsm[32'd51];
+
+assign ap_CS_fsm_state57 = ap_CS_fsm[32'd52];
+
+assign ap_CS_fsm_state58 = ap_CS_fsm[32'd53];
+
+assign ap_CS_fsm_state59 = ap_CS_fsm[32'd54];
+
+assign ap_CS_fsm_state60 = ap_CS_fsm[32'd55];
+
+assign ap_CS_fsm_state61 = ap_CS_fsm[32'd56];
+
+assign ap_CS_fsm_state62 = ap_CS_fsm[32'd57];
+
+assign ap_CS_fsm_state63 = ap_CS_fsm[32'd58];
+
+assign ap_CS_fsm_state64 = ap_CS_fsm[32'd59];
+
+assign ap_CS_fsm_state65 = ap_CS_fsm[32'd60];
+
+assign ap_CS_fsm_state66 = ap_CS_fsm[32'd61];
+
+assign ap_CS_fsm_state67 = ap_CS_fsm[32'd62];
+
+assign ap_CS_fsm_state68 = ap_CS_fsm[32'd63];
+
+assign ap_CS_fsm_state69 = ap_CS_fsm[32'd64];
+
+assign ap_CS_fsm_state70 = ap_CS_fsm[32'd65];
+
+assign ap_CS_fsm_state71 = ap_CS_fsm[32'd66];
+
+assign ap_CS_fsm_state72 = ap_CS_fsm[32'd67];
+
+assign ap_CS_fsm_state73 = ap_CS_fsm[32'd68];
+
+assign ap_CS_fsm_state74 = ap_CS_fsm[32'd69];
+
+assign ap_CS_fsm_state75 = ap_CS_fsm[32'd70];
+
+assign ap_CS_fsm_state76 = ap_CS_fsm[32'd71];
+
+assign ap_CS_fsm_state77 = ap_CS_fsm[32'd72];
+
+assign ap_CS_fsm_state78 = ap_CS_fsm[32'd73];
+
+assign ap_CS_fsm_state79 = ap_CS_fsm[32'd74];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+assign ap_CS_fsm_state80 = ap_CS_fsm[32'd75];
+
+assign ap_CS_fsm_state81 = ap_CS_fsm[32'd76];
+
+assign ap_CS_fsm_state82 = ap_CS_fsm[32'd77];
+
+assign ap_CS_fsm_state83 = ap_CS_fsm[32'd78];
+
+assign ap_CS_fsm_state84 = ap_CS_fsm[32'd79];
+
+assign ap_CS_fsm_state85 = ap_CS_fsm[32'd80];
+
+assign ap_CS_fsm_state86 = ap_CS_fsm[32'd81];
+
+assign ap_CS_fsm_state87 = ap_CS_fsm[32'd82];
+
+assign ap_CS_fsm_state88 = ap_CS_fsm[32'd83];
+
+assign ap_CS_fsm_state89 = ap_CS_fsm[32'd84];
+
+assign ap_CS_fsm_state97 = ap_CS_fsm[32'd90];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = ((in1_mem_RVALID == 1'b0) & (icmp_ln27_reg_3840 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = ((in1_mem_RVALID == 1'b0) & (icmp_ln27_reg_3840 == 1'd0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp1_stage0_11001 = ((in2_mem_RVALID == 1'b0) & (icmp_ln28_reg_3854 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp1_stage0_subdone = ((in2_mem_RVALID == 1'b0) & (icmp_ln28_reg_3854 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+assign ap_block_pp2_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp2_stage0_01001 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp2_stage0_11001 = ((ap_enable_reg_pp2_iter2 == 1'b1) & (1'b1 == ap_block_state92_io));
+end
+
+always @ (*) begin
+    ap_block_pp2_stage0_subdone = ((ap_enable_reg_pp2_iter2 == 1'b1) & (1'b1 == ap_block_state92_io));
+end
+
+always @ (*) begin
+    ap_block_state10_pp0_stage0_iter1 = ((in1_mem_RVALID == 1'b0) & (icmp_ln27_reg_3840 == 1'd0));
+end
+
+assign ap_block_state11_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state20_pp1_stage0_iter1 = ((in2_mem_RVALID == 1'b0) & (icmp_ln28_reg_3854 == 1'd0));
+end
+
+assign ap_block_state21_pp1_stage0_iter2 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state23_io = ((out_mem_AWREADY == 1'b0) & (icmp_ln31_fu_1563_p2 == 1'd0));
+end
+
+assign ap_block_state90_pp2_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state91_pp2_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state92_io = ((out_mem_WREADY == 1'b0) & (icmp_ln42_reg_5307_pp2_iter1_reg == 1'd0));
+end
+
+assign ap_block_state92_pp2_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state9_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
+
+assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign empty_5_fu_1516_p1 = in_reg_3812;
+
+assign empty_6_fu_1497_p1 = in3_reg_3817;
+
+assign empty_fu_1507_p1 = out5_reg_3807;
+
+assign i_fu_1568_p2 = (i_0_reg_1434 + 31'd1);
+
+assign icmp_ln27_fu_1525_p2 = ((ap_phi_mux_phi_ln27_phi_fu_1414_p4 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln28_fu_1542_p2 = ((ap_phi_mux_phi_ln28_phi_fu_1426_p4 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln31_fu_1563_p2 = (($signed(zext_ln31_fu_1559_p1) < $signed(dim_read_reg_3801)) ? 1'b1 : 1'b0);
+
+assign icmp_ln33_fu_2481_p2 = ((j_0_reg_1445 == dim_read_reg_3801) ? 1'b1 : 1'b0);
+
+assign icmp_ln42_fu_3784_p2 = ((phi_ln42_reg_1456 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign in1_mem_ARADDR = empty_6_fu_1497_p1;
+
+assign j_fu_2486_p2 = ($signed(j_0_reg_1445) + $signed(32'd1));
+
+assign mul_ln38_10_fu_2733_p0 = in2_loc_q1;
+
+assign mul_ln38_10_fu_2733_p2 = ($signed(mul_ln38_10_fu_2733_p0) * $signed(in1_loc_load_10_reg_4068));
+
+assign mul_ln38_11_fu_2738_p0 = in2_loc_q0;
+
+assign mul_ln38_11_fu_2738_p2 = ($signed(mul_ln38_11_fu_2738_p0) * $signed(in1_loc_load_11_reg_4073));
+
+assign mul_ln38_12_fu_2773_p0 = in2_loc_q1;
+
+assign mul_ln38_12_fu_2773_p2 = ($signed(mul_ln38_12_fu_2773_p0) * $signed(in1_loc_load_12_reg_4088));
+
+assign mul_ln38_13_fu_2778_p0 = in2_loc_q0;
+
+assign mul_ln38_13_fu_2778_p2 = ($signed(mul_ln38_13_fu_2778_p0) * $signed(in1_loc_load_13_reg_4093));
+
+assign mul_ln38_14_fu_2808_p0 = in2_loc_q1;
+
+assign mul_ln38_14_fu_2808_p2 = ($signed(mul_ln38_14_fu_2808_p0) * $signed(in1_loc_load_14_reg_4108));
+
+assign mul_ln38_15_fu_2813_p0 = in2_loc_q0;
+
+assign mul_ln38_15_fu_2813_p2 = ($signed(mul_ln38_15_fu_2813_p0) * $signed(in1_loc_load_15_reg_4113));
+
+assign mul_ln38_16_fu_2858_p0 = in2_loc_q1;
+
+assign mul_ln38_16_fu_2858_p2 = ($signed(mul_ln38_16_fu_2858_p0) * $signed(in1_loc_load_16_reg_4128));
+
+assign mul_ln38_17_fu_2863_p0 = in2_loc_q0;
+
+assign mul_ln38_17_fu_2863_p2 = ($signed(mul_ln38_17_fu_2863_p0) * $signed(in1_loc_load_17_reg_4133));
+
+assign mul_ln38_18_fu_2893_p0 = in2_loc_q1;
+
+assign mul_ln38_18_fu_2893_p2 = ($signed(mul_ln38_18_fu_2893_p0) * $signed(in1_loc_load_18_reg_4148));
+
+assign mul_ln38_19_fu_2898_p0 = in2_loc_q0;
+
+assign mul_ln38_19_fu_2898_p2 = ($signed(mul_ln38_19_fu_2898_p0) * $signed(in1_loc_load_19_reg_4153));
+
+assign mul_ln38_1_fu_2547_p0 = in2_loc_q1;
+
+assign mul_ln38_1_fu_2547_p2 = ($signed(mul_ln38_1_fu_2547_p0) * $signed(in1_loc_load_1_reg_3973));
+
+assign mul_ln38_20_fu_2933_p0 = in2_loc_q1;
+
+assign mul_ln38_20_fu_2933_p2 = ($signed(mul_ln38_20_fu_2933_p0) * $signed(in1_loc_load_20_reg_4168));
+
+assign mul_ln38_21_fu_2938_p0 = in2_loc_q0;
+
+assign mul_ln38_21_fu_2938_p2 = ($signed(mul_ln38_21_fu_2938_p0) * $signed(in1_loc_load_21_reg_4173));
+
+assign mul_ln38_22_fu_2968_p0 = in2_loc_q1;
+
+assign mul_ln38_22_fu_2968_p2 = ($signed(mul_ln38_22_fu_2968_p0) * $signed(in1_loc_load_22_reg_4188));
+
+assign mul_ln38_23_fu_2973_p0 = in2_loc_q0;
+
+assign mul_ln38_23_fu_2973_p2 = ($signed(mul_ln38_23_fu_2973_p0) * $signed(in1_loc_load_23_reg_4193));
+
+assign mul_ln38_24_fu_3013_p0 = in2_loc_q1;
+
+assign mul_ln38_24_fu_3013_p2 = ($signed(mul_ln38_24_fu_3013_p0) * $signed(in1_loc_load_24_reg_4208));
+
+assign mul_ln38_25_fu_3018_p0 = in2_loc_q0;
+
+assign mul_ln38_25_fu_3018_p2 = ($signed(mul_ln38_25_fu_3018_p0) * $signed(in1_loc_load_25_reg_4213));
+
+assign mul_ln38_26_fu_3048_p0 = in2_loc_q1;
+
+assign mul_ln38_26_fu_3048_p2 = ($signed(mul_ln38_26_fu_3048_p0) * $signed(in1_loc_load_26_reg_4228));
+
+assign mul_ln38_27_fu_3053_p0 = in2_loc_q0;
+
+assign mul_ln38_27_fu_3053_p2 = ($signed(mul_ln38_27_fu_3053_p0) * $signed(in1_loc_load_27_reg_4233));
+
+assign mul_ln38_28_fu_3088_p0 = in2_loc_q1;
+
+assign mul_ln38_28_fu_3088_p2 = ($signed(mul_ln38_28_fu_3088_p0) * $signed(in1_loc_load_28_reg_4248));
+
+assign mul_ln38_29_fu_3093_p0 = in2_loc_q0;
+
+assign mul_ln38_29_fu_3093_p2 = ($signed(mul_ln38_29_fu_3093_p0) * $signed(in1_loc_load_29_reg_4253));
+
+assign mul_ln38_2_fu_2572_p0 = in2_loc_q1;
+
+assign mul_ln38_2_fu_2572_p2 = ($signed(mul_ln38_2_fu_2572_p0) * $signed(in1_loc_load_2_reg_3988));
+
+assign mul_ln38_30_fu_3123_p0 = in2_loc_q1;
+
+assign mul_ln38_30_fu_3123_p2 = ($signed(mul_ln38_30_fu_3123_p0) * $signed(in1_loc_load_30_reg_4268));
+
+assign mul_ln38_31_fu_3128_p0 = in2_loc_q0;
+
+assign mul_ln38_31_fu_3128_p2 = ($signed(mul_ln38_31_fu_3128_p0) * $signed(in1_loc_load_31_reg_4273));
+
+assign mul_ln38_32_fu_3178_p0 = in2_loc_q1;
+
+assign mul_ln38_32_fu_3178_p2 = ($signed(mul_ln38_32_fu_3178_p0) * $signed(in1_loc_load_32_reg_4288));
+
+assign mul_ln38_33_fu_3183_p0 = in2_loc_q0;
+
+assign mul_ln38_33_fu_3183_p2 = ($signed(mul_ln38_33_fu_3183_p0) * $signed(in1_loc_load_33_reg_4293));
+
+assign mul_ln38_34_fu_3213_p0 = in2_loc_q1;
+
+assign mul_ln38_34_fu_3213_p2 = ($signed(mul_ln38_34_fu_3213_p0) * $signed(in1_loc_load_34_reg_4308));
+
+assign mul_ln38_35_fu_3218_p0 = in2_loc_q0;
+
+assign mul_ln38_35_fu_3218_p2 = ($signed(mul_ln38_35_fu_3218_p0) * $signed(in1_loc_load_35_reg_4313));
+
+assign mul_ln38_36_fu_3253_p0 = in2_loc_q1;
+
+assign mul_ln38_36_fu_3253_p2 = ($signed(mul_ln38_36_fu_3253_p0) * $signed(in1_loc_load_36_reg_4328));
+
+assign mul_ln38_37_fu_3258_p0 = in2_loc_q0;
+
+assign mul_ln38_37_fu_3258_p2 = ($signed(mul_ln38_37_fu_3258_p0) * $signed(in1_loc_load_37_reg_4333));
+
+assign mul_ln38_38_fu_3288_p0 = in2_loc_q1;
+
+assign mul_ln38_38_fu_3288_p2 = ($signed(mul_ln38_38_fu_3288_p0) * $signed(in1_loc_load_38_reg_4348));
+
+assign mul_ln38_39_fu_3293_p0 = in2_loc_q0;
+
+assign mul_ln38_39_fu_3293_p2 = ($signed(mul_ln38_39_fu_3293_p0) * $signed(in1_loc_load_39_reg_4353));
+
+assign mul_ln38_3_fu_2577_p0 = in2_loc_q0;
+
+assign mul_ln38_3_fu_2577_p2 = ($signed(mul_ln38_3_fu_2577_p0) * $signed(in1_loc_load_3_reg_3993));
+
+assign mul_ln38_40_fu_3333_p0 = in2_loc_q1;
+
+assign mul_ln38_40_fu_3333_p2 = ($signed(mul_ln38_40_fu_3333_p0) * $signed(in1_loc_load_40_reg_4368));
+
+assign mul_ln38_41_fu_3338_p0 = in2_loc_q0;
+
+assign mul_ln38_41_fu_3338_p2 = ($signed(mul_ln38_41_fu_3338_p0) * $signed(in1_loc_load_41_reg_4373));
+
+assign mul_ln38_42_fu_3368_p0 = in2_loc_q1;
+
+assign mul_ln38_42_fu_3368_p2 = ($signed(mul_ln38_42_fu_3368_p0) * $signed(in1_loc_load_42_reg_4388));
+
+assign mul_ln38_43_fu_3373_p0 = in2_loc_q0;
+
+assign mul_ln38_43_fu_3373_p2 = ($signed(mul_ln38_43_fu_3373_p0) * $signed(in1_loc_load_43_reg_4393));
+
+assign mul_ln38_44_fu_3408_p0 = in2_loc_q1;
+
+assign mul_ln38_44_fu_3408_p2 = ($signed(mul_ln38_44_fu_3408_p0) * $signed(in1_loc_load_44_reg_4408));
+
+assign mul_ln38_45_fu_3413_p0 = in2_loc_q0;
+
+assign mul_ln38_45_fu_3413_p2 = ($signed(mul_ln38_45_fu_3413_p0) * $signed(in1_loc_load_45_reg_4413));
+
+assign mul_ln38_46_fu_3443_p0 = in2_loc_q1;
+
+assign mul_ln38_46_fu_3443_p2 = ($signed(mul_ln38_46_fu_3443_p0) * $signed(in1_loc_load_46_reg_4428));
+
+assign mul_ln38_47_fu_3448_p0 = in2_loc_q0;
+
+assign mul_ln38_47_fu_3448_p2 = ($signed(mul_ln38_47_fu_3448_p0) * $signed(in1_loc_load_47_reg_4433));
+
+assign mul_ln38_48_fu_3493_p0 = in2_loc_q1;
+
+assign mul_ln38_48_fu_3493_p2 = ($signed(mul_ln38_48_fu_3493_p0) * $signed(in1_loc_load_48_reg_4448));
+
+assign mul_ln38_49_fu_3498_p0 = in2_loc_q0;
+
+assign mul_ln38_49_fu_3498_p2 = ($signed(mul_ln38_49_fu_3498_p0) * $signed(in1_loc_load_49_reg_4453));
+
+assign mul_ln38_4_fu_2618_p0 = in2_loc_q1;
+
+assign mul_ln38_4_fu_2618_p2 = ($signed(mul_ln38_4_fu_2618_p0) * $signed(in1_loc_load_4_reg_4008));
+
+assign mul_ln38_50_fu_3528_p0 = in2_loc_q1;
+
+assign mul_ln38_50_fu_3528_p2 = ($signed(mul_ln38_50_fu_3528_p0) * $signed(in1_loc_load_50_reg_4468));
+
+assign mul_ln38_51_fu_3533_p0 = in2_loc_q0;
+
+assign mul_ln38_51_fu_3533_p2 = ($signed(mul_ln38_51_fu_3533_p0) * $signed(in1_loc_load_51_reg_4473));
+
+assign mul_ln38_52_fu_3568_p0 = in2_loc_q1;
+
+assign mul_ln38_52_fu_3568_p2 = ($signed(mul_ln38_52_fu_3568_p0) * $signed(in1_loc_load_52_reg_4488));
+
+assign mul_ln38_53_fu_3573_p0 = in2_loc_q0;
+
+assign mul_ln38_53_fu_3573_p2 = ($signed(mul_ln38_53_fu_3573_p0) * $signed(in1_loc_load_53_reg_4493));
+
+assign mul_ln38_54_fu_3603_p0 = in2_loc_q1;
+
+assign mul_ln38_54_fu_3603_p2 = ($signed(mul_ln38_54_fu_3603_p0) * $signed(in1_loc_load_54_reg_4508));
+
+assign mul_ln38_55_fu_3608_p0 = in2_loc_q0;
+
+assign mul_ln38_55_fu_3608_p2 = ($signed(mul_ln38_55_fu_3608_p0) * $signed(in1_loc_load_55_reg_4513));
+
+assign mul_ln38_56_fu_3648_p0 = in2_loc_q1;
+
+assign mul_ln38_56_fu_3648_p2 = ($signed(mul_ln38_56_fu_3648_p0) * $signed(in1_loc_load_56_reg_4528));
+
+assign mul_ln38_57_fu_3653_p0 = in2_loc_q0;
+
+assign mul_ln38_57_fu_3653_p2 = ($signed(mul_ln38_57_fu_3653_p0) * $signed(in1_loc_load_57_reg_4533));
+
+assign mul_ln38_58_fu_3683_p0 = in2_loc_q1;
+
+assign mul_ln38_58_fu_3683_p2 = ($signed(mul_ln38_58_fu_3683_p0) * $signed(in1_loc_load_58_reg_4548));
+
+assign mul_ln38_59_fu_3688_p0 = in2_loc_q0;
+
+assign mul_ln38_59_fu_3688_p2 = ($signed(mul_ln38_59_fu_3688_p0) * $signed(in1_loc_load_59_reg_4553));
+
+assign mul_ln38_5_fu_2623_p0 = in2_loc_q0;
+
+assign mul_ln38_5_fu_2623_p2 = ($signed(mul_ln38_5_fu_2623_p0) * $signed(in1_loc_load_5_reg_4013));
+
+assign mul_ln38_60_fu_3723_p0 = in2_loc_q1;
+
+assign mul_ln38_60_fu_3723_p2 = ($signed(mul_ln38_60_fu_3723_p0) * $signed(in1_loc_load_60_reg_4568));
+
+assign mul_ln38_61_fu_3728_p0 = in2_loc_q0;
+
+assign mul_ln38_61_fu_3728_p2 = ($signed(mul_ln38_61_fu_3728_p0) * $signed(in1_loc_load_61_reg_4573));
+
+assign mul_ln38_62_fu_3738_p0 = in2_loc_q1;
+
+assign mul_ln38_62_fu_3738_p2 = ($signed(mul_ln38_62_fu_3738_p0) * $signed(in1_loc_load_62_reg_4583));
+
+assign mul_ln38_63_fu_3743_p0 = in2_loc_q0;
+
+assign mul_ln38_63_fu_3743_p2 = ($signed(mul_ln38_63_fu_3743_p0) * $signed(in1_loc_load_63_reg_4588));
+
+assign mul_ln38_6_fu_2653_p0 = in2_loc_q1;
+
+assign mul_ln38_6_fu_2653_p2 = ($signed(mul_ln38_6_fu_2653_p0) * $signed(in1_loc_load_6_reg_4028));
+
+assign mul_ln38_7_fu_2658_p0 = in2_loc_q0;
+
+assign mul_ln38_7_fu_2658_p2 = ($signed(mul_ln38_7_fu_2658_p0) * $signed(in1_loc_load_7_reg_4033));
+
+assign mul_ln38_8_fu_2698_p0 = in2_loc_q1;
+
+assign mul_ln38_8_fu_2698_p2 = ($signed(mul_ln38_8_fu_2698_p0) * $signed(in1_loc_load_8_reg_4048));
+
+assign mul_ln38_9_fu_2703_p0 = in2_loc_q0;
+
+assign mul_ln38_9_fu_2703_p2 = ($signed(mul_ln38_9_fu_2703_p0) * $signed(in1_loc_load_9_reg_4053));
+
+assign mul_ln38_fu_2542_p0 = in2_loc_q0;
+
+assign mul_ln38_fu_2542_p2 = ($signed(mul_ln38_fu_2542_p0) * $signed(in1_loc_load_reg_3968));
+
+assign or_ln38_10_fu_1732_p2 = (tmp_2_reg_3877 | 37'd11);
+
+assign or_ln38_11_fu_1746_p2 = (tmp_2_reg_3877 | 37'd12);
+
+assign or_ln38_12_fu_1760_p2 = (tmp_2_reg_3877 | 37'd13);
+
+assign or_ln38_13_fu_1774_p2 = (tmp_2_reg_3877 | 37'd14);
+
+assign or_ln38_14_fu_1788_p2 = (tmp_2_reg_3877 | 37'd15);
+
+assign or_ln38_15_fu_1802_p2 = (tmp_2_reg_3877 | 37'd16);
+
+assign or_ln38_16_fu_1816_p2 = (tmp_2_reg_3877 | 37'd17);
+
+assign or_ln38_17_fu_1830_p2 = (tmp_2_reg_3877 | 37'd18);
+
+assign or_ln38_18_fu_1844_p2 = (tmp_2_reg_3877 | 37'd19);
+
+assign or_ln38_19_fu_1858_p2 = (tmp_2_reg_3877 | 37'd20);
+
+assign or_ln38_1_fu_1606_p2 = (tmp_2_reg_3877 | 37'd2);
+
+assign or_ln38_20_fu_1872_p2 = (tmp_2_reg_3877 | 37'd21);
+
+assign or_ln38_21_fu_1886_p2 = (tmp_2_reg_3877 | 37'd22);
+
+assign or_ln38_22_fu_1900_p2 = (tmp_2_reg_3877 | 37'd23);
+
+assign or_ln38_23_fu_1914_p2 = (tmp_2_reg_3877 | 37'd24);
+
+assign or_ln38_24_fu_1928_p2 = (tmp_2_reg_3877 | 37'd25);
+
+assign or_ln38_25_fu_1942_p2 = (tmp_2_reg_3877 | 37'd26);
+
+assign or_ln38_26_fu_1956_p2 = (tmp_2_reg_3877 | 37'd27);
+
+assign or_ln38_27_fu_1970_p2 = (tmp_2_reg_3877 | 37'd28);
+
+assign or_ln38_28_fu_1984_p2 = (tmp_2_reg_3877 | 37'd29);
+
+assign or_ln38_29_fu_1998_p2 = (tmp_2_reg_3877 | 37'd30);
+
+assign or_ln38_2_fu_1620_p2 = (tmp_2_reg_3877 | 37'd3);
+
+assign or_ln38_30_fu_2012_p2 = (tmp_2_reg_3877 | 37'd31);
+
+assign or_ln38_31_fu_2026_p2 = (tmp_2_reg_3877 | 37'd32);
+
+assign or_ln38_32_fu_2040_p2 = (tmp_2_reg_3877 | 37'd33);
+
+assign or_ln38_33_fu_2054_p2 = (tmp_2_reg_3877 | 37'd34);
+
+assign or_ln38_34_fu_2068_p2 = (tmp_2_reg_3877 | 37'd35);
+
+assign or_ln38_35_fu_2082_p2 = (tmp_2_reg_3877 | 37'd36);
+
+assign or_ln38_36_fu_2096_p2 = (tmp_2_reg_3877 | 37'd37);
+
+assign or_ln38_37_fu_2110_p2 = (tmp_2_reg_3877 | 37'd38);
+
+assign or_ln38_38_fu_2124_p2 = (tmp_2_reg_3877 | 37'd39);
+
+assign or_ln38_39_fu_2138_p2 = (tmp_2_reg_3877 | 37'd40);
+
+assign or_ln38_3_fu_1634_p2 = (tmp_2_reg_3877 | 37'd4);
+
+assign or_ln38_40_fu_2152_p2 = (tmp_2_reg_3877 | 37'd41);
+
+assign or_ln38_41_fu_2166_p2 = (tmp_2_reg_3877 | 37'd42);
+
+assign or_ln38_42_fu_2180_p2 = (tmp_2_reg_3877 | 37'd43);
+
+assign or_ln38_43_fu_2194_p2 = (tmp_2_reg_3877 | 37'd44);
+
+assign or_ln38_44_fu_2208_p2 = (tmp_2_reg_3877 | 37'd45);
+
+assign or_ln38_45_fu_2222_p2 = (tmp_2_reg_3877 | 37'd46);
+
+assign or_ln38_46_fu_2236_p2 = (tmp_2_reg_3877 | 37'd47);
+
+assign or_ln38_47_fu_2250_p2 = (tmp_2_reg_3877 | 37'd48);
+
+assign or_ln38_48_fu_2264_p2 = (tmp_2_reg_3877 | 37'd49);
+
+assign or_ln38_49_fu_2278_p2 = (tmp_2_reg_3877 | 37'd50);
+
+assign or_ln38_4_fu_1648_p2 = (tmp_2_reg_3877 | 37'd5);
+
+assign or_ln38_50_fu_2292_p2 = (tmp_2_reg_3877 | 37'd51);
+
+assign or_ln38_51_fu_2306_p2 = (tmp_2_reg_3877 | 37'd52);
+
+assign or_ln38_52_fu_2320_p2 = (tmp_2_reg_3877 | 37'd53);
+
+assign or_ln38_53_fu_2334_p2 = (tmp_2_reg_3877 | 37'd54);
+
+assign or_ln38_54_fu_2348_p2 = (tmp_2_reg_3877 | 37'd55);
+
+assign or_ln38_55_fu_2362_p2 = (tmp_2_reg_3877 | 37'd56);
+
+assign or_ln38_56_fu_2376_p2 = (tmp_2_reg_3877 | 37'd57);
+
+assign or_ln38_57_fu_2390_p2 = (tmp_2_reg_3877 | 37'd58);
+
+assign or_ln38_58_fu_2404_p2 = (tmp_2_reg_3877 | 37'd59);
+
+assign or_ln38_59_fu_2418_p2 = (tmp_2_reg_3877 | 37'd60);
+
+assign or_ln38_5_fu_1662_p2 = (tmp_2_reg_3877 | 37'd6);
+
+assign or_ln38_60_fu_2432_p2 = (tmp_2_reg_3877 | 37'd61);
+
+assign or_ln38_61_fu_2446_p2 = (tmp_2_reg_3877 | 37'd62);
+
+assign or_ln38_62_fu_2460_p2 = (tmp_2_reg_3877 | 37'd63);
+
+assign or_ln38_6_fu_1676_p2 = (tmp_2_reg_3877 | 37'd7);
+
+assign or_ln38_7_fu_1690_p2 = (tmp_2_reg_3877 | 37'd8);
+
+assign or_ln38_8_fu_1704_p2 = (tmp_2_reg_3877 | 37'd9);
+
+assign or_ln38_9_fu_1718_p2 = (tmp_2_reg_3877 | 37'd10);
+
+assign or_ln38_fu_1591_p2 = (tmp_2_fu_1574_p3 | 37'd1);
+
+assign out_loc_d0 = (add_ln38_30_reg_4997 + add_ln38_62_fu_3774_p2);
+
+assign sext_ln38_10_fu_2683_p1 = $signed(add_ln38_73_fu_2678_p2);
+
+assign sext_ln38_11_fu_2693_p1 = $signed(add_ln38_74_fu_2688_p2);
+
+assign sext_ln38_12_fu_2718_p1 = $signed(add_ln38_75_fu_2713_p2);
+
+assign sext_ln38_13_fu_2728_p1 = $signed(add_ln38_76_fu_2723_p2);
+
+assign sext_ln38_14_fu_2758_p1 = $signed(add_ln38_77_fu_2753_p2);
+
+assign sext_ln38_15_fu_2768_p1 = $signed(add_ln38_78_fu_2763_p2);
+
+assign sext_ln38_16_fu_2793_p1 = $signed(add_ln38_79_fu_2788_p2);
+
+assign sext_ln38_17_fu_2803_p1 = $signed(add_ln38_80_fu_2798_p2);
+
+assign sext_ln38_18_fu_2843_p1 = $signed(add_ln38_81_fu_2838_p2);
+
+assign sext_ln38_19_fu_2853_p1 = $signed(add_ln38_82_fu_2848_p2);
+
+assign sext_ln38_1_fu_2507_p1 = $signed(add_ln38_64_fu_2501_p2);
+
+assign sext_ln38_20_fu_2878_p1 = $signed(add_ln38_83_fu_2873_p2);
+
+assign sext_ln38_21_fu_2888_p1 = $signed(add_ln38_84_fu_2883_p2);
+
+assign sext_ln38_22_fu_2918_p1 = $signed(add_ln38_85_fu_2913_p2);
+
+assign sext_ln38_23_fu_2928_p1 = $signed(add_ln38_86_fu_2923_p2);
+
+assign sext_ln38_24_fu_2953_p1 = $signed(add_ln38_87_fu_2948_p2);
+
+assign sext_ln38_25_fu_2963_p1 = $signed(add_ln38_88_fu_2958_p2);
+
+assign sext_ln38_26_fu_2998_p1 = $signed(add_ln38_89_fu_2993_p2);
+
+assign sext_ln38_27_fu_3008_p1 = $signed(add_ln38_90_fu_3003_p2);
+
+assign sext_ln38_28_fu_3033_p1 = $signed(add_ln38_91_fu_3028_p2);
+
+assign sext_ln38_29_fu_3043_p1 = $signed(add_ln38_92_fu_3038_p2);
+
+assign sext_ln38_2_fu_2527_p1 = $signed(add_ln38_65_fu_2522_p2);
+
+assign sext_ln38_30_fu_3073_p1 = $signed(add_ln38_93_fu_3068_p2);
+
+assign sext_ln38_31_fu_3083_p1 = $signed(add_ln38_94_fu_3078_p2);
+
+assign sext_ln38_32_fu_3108_p1 = $signed(add_ln38_95_fu_3103_p2);
+
+assign sext_ln38_33_fu_3118_p1 = $signed(add_ln38_96_fu_3113_p2);
+
+assign sext_ln38_34_fu_3163_p1 = $signed(add_ln38_97_fu_3158_p2);
+
+assign sext_ln38_35_fu_3173_p1 = $signed(add_ln38_98_fu_3168_p2);
+
+assign sext_ln38_36_fu_3198_p1 = $signed(add_ln38_99_fu_3193_p2);
+
+assign sext_ln38_37_fu_3208_p1 = $signed(add_ln38_100_fu_3203_p2);
+
+assign sext_ln38_38_fu_3238_p1 = $signed(add_ln38_101_fu_3233_p2);
+
+assign sext_ln38_39_fu_3248_p1 = $signed(add_ln38_102_fu_3243_p2);
+
+assign sext_ln38_3_fu_2537_p1 = $signed(add_ln38_66_fu_2532_p2);
+
+assign sext_ln38_40_fu_3273_p1 = $signed(add_ln38_103_fu_3268_p2);
+
+assign sext_ln38_41_fu_3283_p1 = $signed(add_ln38_104_fu_3278_p2);
+
+assign sext_ln38_42_fu_3318_p1 = $signed(add_ln38_105_fu_3313_p2);
+
+assign sext_ln38_43_fu_3328_p1 = $signed(add_ln38_106_fu_3323_p2);
+
+assign sext_ln38_44_fu_3353_p1 = $signed(add_ln38_107_fu_3348_p2);
+
+assign sext_ln38_45_fu_3363_p1 = $signed(add_ln38_108_fu_3358_p2);
+
+assign sext_ln38_46_fu_3393_p1 = $signed(add_ln38_109_fu_3388_p2);
+
+assign sext_ln38_47_fu_3403_p1 = $signed(add_ln38_110_fu_3398_p2);
+
+assign sext_ln38_48_fu_3428_p1 = $signed(add_ln38_111_fu_3423_p2);
+
+assign sext_ln38_49_fu_3438_p1 = $signed(add_ln38_112_fu_3433_p2);
+
+assign sext_ln38_4_fu_2557_p1 = $signed(add_ln38_67_fu_2552_p2);
+
+assign sext_ln38_50_fu_3478_p1 = $signed(add_ln38_113_fu_3473_p2);
+
+assign sext_ln38_51_fu_3488_p1 = $signed(add_ln38_114_fu_3483_p2);
+
+assign sext_ln38_52_fu_3513_p1 = $signed(add_ln38_115_fu_3508_p2);
+
+assign sext_ln38_53_fu_3523_p1 = $signed(add_ln38_116_fu_3518_p2);
+
+assign sext_ln38_54_fu_3553_p1 = $signed(add_ln38_117_fu_3548_p2);
+
+assign sext_ln38_55_fu_3563_p1 = $signed(add_ln38_118_fu_3558_p2);
+
+assign sext_ln38_56_fu_3588_p1 = $signed(add_ln38_119_fu_3583_p2);
+
+assign sext_ln38_57_fu_3598_p1 = $signed(add_ln38_120_fu_3593_p2);
+
+assign sext_ln38_58_fu_3633_p1 = $signed(add_ln38_121_fu_3628_p2);
+
+assign sext_ln38_59_fu_3643_p1 = $signed(add_ln38_122_fu_3638_p2);
+
+assign sext_ln38_5_fu_2567_p1 = $signed(add_ln38_68_fu_2562_p2);
+
+assign sext_ln38_60_fu_3668_p1 = $signed(add_ln38_123_fu_3663_p2);
+
+assign sext_ln38_61_fu_3678_p1 = $signed(add_ln38_124_fu_3673_p2);
+
+assign sext_ln38_62_fu_3708_p1 = $signed(add_ln38_125_fu_3703_p2);
+
+assign sext_ln38_63_fu_3718_p1 = $signed(add_ln38_126_fu_3713_p2);
+
+assign sext_ln38_64_fu_2517_p1 = $signed(add_ln38_127_fu_2512_p2);
+
+assign sext_ln38_6_fu_2603_p1 = $signed(add_ln38_69_fu_2598_p2);
+
+assign sext_ln38_7_fu_2613_p1 = $signed(add_ln38_70_fu_2608_p2);
+
+assign sext_ln38_8_fu_2638_p1 = $signed(add_ln38_71_fu_2633_p2);
+
+assign sext_ln38_9_fu_2648_p1 = $signed(add_ln38_72_fu_2643_p2);
+
+assign sext_ln38_fu_2492_p1 = j_0_reg_1445;
+
+assign tmp_10_fu_1709_p3 = {{27'd0}, {or_ln38_8_fu_1704_p2}};
+
+assign tmp_11_fu_1723_p3 = {{27'd0}, {or_ln38_9_fu_1718_p2}};
+
+assign tmp_12_fu_1737_p3 = {{27'd0}, {or_ln38_10_fu_1732_p2}};
+
+assign tmp_13_fu_1751_p3 = {{27'd0}, {or_ln38_11_fu_1746_p2}};
+
+assign tmp_14_fu_1765_p3 = {{27'd0}, {or_ln38_12_fu_1760_p2}};
+
+assign tmp_15_fu_1779_p3 = {{27'd0}, {or_ln38_13_fu_1774_p2}};
+
+assign tmp_16_fu_1793_p3 = {{27'd0}, {or_ln38_14_fu_1788_p2}};
+
+assign tmp_17_fu_1807_p3 = {{27'd0}, {or_ln38_15_fu_1802_p2}};
+
+assign tmp_18_fu_1821_p3 = {{27'd0}, {or_ln38_16_fu_1816_p2}};
+
+assign tmp_19_fu_1835_p3 = {{27'd0}, {or_ln38_17_fu_1830_p2}};
+
+assign tmp_20_fu_1849_p3 = {{27'd0}, {or_ln38_18_fu_1844_p2}};
+
+assign tmp_21_fu_1863_p3 = {{27'd0}, {or_ln38_19_fu_1858_p2}};
+
+assign tmp_22_fu_1877_p3 = {{27'd0}, {or_ln38_20_fu_1872_p2}};
+
+assign tmp_23_fu_1891_p3 = {{27'd0}, {or_ln38_21_fu_1886_p2}};
+
+assign tmp_24_fu_1905_p3 = {{27'd0}, {or_ln38_22_fu_1900_p2}};
+
+assign tmp_25_fu_1919_p3 = {{27'd0}, {or_ln38_23_fu_1914_p2}};
+
+assign tmp_26_fu_1933_p3 = {{27'd0}, {or_ln38_24_fu_1928_p2}};
+
+assign tmp_27_fu_1947_p3 = {{27'd0}, {or_ln38_25_fu_1942_p2}};
+
+assign tmp_28_fu_1961_p3 = {{27'd0}, {or_ln38_26_fu_1956_p2}};
+
+assign tmp_29_fu_1975_p3 = {{27'd0}, {or_ln38_27_fu_1970_p2}};
+
+assign tmp_2_fu_1574_p3 = {{i_0_reg_1434}, {6'd0}};
+
+assign tmp_30_fu_1989_p3 = {{27'd0}, {or_ln38_28_fu_1984_p2}};
+
+assign tmp_31_fu_2003_p3 = {{27'd0}, {or_ln38_29_fu_1998_p2}};
+
+assign tmp_32_fu_2017_p3 = {{27'd0}, {or_ln38_30_fu_2012_p2}};
+
+assign tmp_33_fu_2031_p3 = {{27'd0}, {or_ln38_31_fu_2026_p2}};
+
+assign tmp_34_fu_2045_p3 = {{27'd0}, {or_ln38_32_fu_2040_p2}};
+
+assign tmp_35_fu_2059_p3 = {{27'd0}, {or_ln38_33_fu_2054_p2}};
+
+assign tmp_36_fu_2073_p3 = {{27'd0}, {or_ln38_34_fu_2068_p2}};
+
+assign tmp_37_fu_2087_p3 = {{27'd0}, {or_ln38_35_fu_2082_p2}};
+
+assign tmp_38_fu_2101_p3 = {{27'd0}, {or_ln38_36_fu_2096_p2}};
+
+assign tmp_39_fu_2115_p3 = {{27'd0}, {or_ln38_37_fu_2110_p2}};
+
+assign tmp_3_fu_1597_p3 = {{27'd0}, {or_ln38_fu_1591_p2}};
+
+assign tmp_40_fu_2129_p3 = {{27'd0}, {or_ln38_38_fu_2124_p2}};
+
+assign tmp_41_fu_2143_p3 = {{27'd0}, {or_ln38_39_fu_2138_p2}};
+
+assign tmp_42_fu_2157_p3 = {{27'd0}, {or_ln38_40_fu_2152_p2}};
+
+assign tmp_43_fu_2171_p3 = {{27'd0}, {or_ln38_41_fu_2166_p2}};
+
+assign tmp_44_fu_2185_p3 = {{27'd0}, {or_ln38_42_fu_2180_p2}};
+
+assign tmp_45_fu_2199_p3 = {{27'd0}, {or_ln38_43_fu_2194_p2}};
+
+assign tmp_46_fu_2213_p3 = {{27'd0}, {or_ln38_44_fu_2208_p2}};
+
+assign tmp_47_fu_2227_p3 = {{27'd0}, {or_ln38_45_fu_2222_p2}};
+
+assign tmp_48_fu_2241_p3 = {{27'd0}, {or_ln38_46_fu_2236_p2}};
+
+assign tmp_49_fu_2255_p3 = {{27'd0}, {or_ln38_47_fu_2250_p2}};
+
+assign tmp_4_fu_1611_p3 = {{27'd0}, {or_ln38_1_fu_1606_p2}};
+
+assign tmp_50_fu_2269_p3 = {{27'd0}, {or_ln38_48_fu_2264_p2}};
+
+assign tmp_51_fu_2283_p3 = {{27'd0}, {or_ln38_49_fu_2278_p2}};
+
+assign tmp_52_fu_2297_p3 = {{27'd0}, {or_ln38_50_fu_2292_p2}};
+
+assign tmp_53_fu_2311_p3 = {{27'd0}, {or_ln38_51_fu_2306_p2}};
+
+assign tmp_54_fu_2325_p3 = {{27'd0}, {or_ln38_52_fu_2320_p2}};
+
+assign tmp_55_fu_2339_p3 = {{27'd0}, {or_ln38_53_fu_2334_p2}};
+
+assign tmp_56_fu_2353_p3 = {{27'd0}, {or_ln38_54_fu_2348_p2}};
+
+assign tmp_57_fu_2367_p3 = {{27'd0}, {or_ln38_55_fu_2362_p2}};
+
+assign tmp_58_fu_2381_p3 = {{27'd0}, {or_ln38_56_fu_2376_p2}};
+
+assign tmp_59_fu_2395_p3 = {{27'd0}, {or_ln38_57_fu_2390_p2}};
+
+assign tmp_5_fu_1625_p3 = {{27'd0}, {or_ln38_2_fu_1620_p2}};
+
+assign tmp_60_fu_2409_p3 = {{27'd0}, {or_ln38_58_fu_2404_p2}};
+
+assign tmp_61_fu_2423_p3 = {{27'd0}, {or_ln38_59_fu_2418_p2}};
+
+assign tmp_62_fu_2437_p3 = {{27'd0}, {or_ln38_60_fu_2432_p2}};
+
+assign tmp_63_fu_2451_p3 = {{27'd0}, {or_ln38_61_fu_2446_p2}};
+
+assign tmp_64_fu_2465_p3 = {{27'd0}, {or_ln38_62_fu_2460_p2}};
+
+assign tmp_6_fu_1639_p3 = {{27'd0}, {or_ln38_3_fu_1634_p2}};
+
+assign tmp_7_fu_1653_p3 = {{27'd0}, {or_ln38_4_fu_1648_p2}};
+
+assign tmp_8_fu_1667_p3 = {{27'd0}, {or_ln38_5_fu_1662_p2}};
+
+assign tmp_9_fu_1681_p3 = {{27'd0}, {or_ln38_6_fu_1676_p2}};
+
+assign tmp_s_fu_1695_p3 = {{27'd0}, {or_ln38_7_fu_1690_p2}};
+
+assign trunc_ln38_1_fu_2497_p1 = j_0_reg_1445[13:0];
+
+assign trunc_ln38_fu_1587_p1 = i_0_reg_1434[7:0];
+
+assign zext_ln27_fu_1537_p1 = phi_ln27_reg_1410_pp0_iter1_reg;
+
+assign zext_ln28_fu_1554_p1 = phi_ln28_reg_1422_pp1_iter1_reg;
+
+assign zext_ln31_fu_1559_p1 = i_0_reg_1434;
+
+assign zext_ln38_cast_fu_2474_p3 = {{trunc_ln38_reg_3943}, {6'd0}};
+
+assign zext_ln38_fu_1582_p1 = tmp_2_fu_1574_p3;
+
+assign zext_ln42_fu_3796_p1 = phi_ln42_reg_1456;
+
+always @ (posedge ap_clk) begin
+    out_mem_addr_reg_3828[31:30] <= 2'b00;
+    in2_mem_addr_reg_3834[31:30] <= 2'b00;
+    tmp_2_reg_3877[5:0] <= 6'b000000;
+    zext_ln38_cast_reg_4578[5:0] <= 6'b000000;
+end
+
+endmodule //mmult
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in1_loc.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in1_loc.v
new file mode 100755
index 0000000..d6b9c3d
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in1_loc.v
@@ -0,0 +1,88 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input[AWIDTH-1:0] addr1;
+input ce1;
+output reg[DWIDTH-1:0] q1;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+always @(posedge clk)  
+begin 
+    if (ce1) begin
+        q1 <= ram[addr1];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_in1_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0,
+    address1,
+    ce1,
+    q1);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+input[AddressWidth - 1:0] address1;
+input ce1;
+output[DataWidth - 1:0] q1;
+
+
+
+mmult_in1_loc_ram mmult_in1_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ),
+    .addr1( address1 ),
+    .ce1( ce1 ),
+    .q1( q1 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in1_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in1_mem_m_axi.v
new file mode 100755
index 0000000..81f7248
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in1_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in1_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in1_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in1_mem_m_axi_write
+mmult_in1_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in1_mem_m_axi_read
+mmult_in1_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in1_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in1_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in1_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in1_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in1_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in2_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in2_mem_m_axi.v
new file mode 100755
index 0000000..a2eab07
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in2_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in2_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in2_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in2_mem_m_axi_write
+mmult_in2_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in2_mem_m_axi_read
+mmult_in2_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in2_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in2_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in2_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in2_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in2_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_out_loc.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_out_loc.v
new file mode 100755
index 0000000..dedfa23
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_out_loc.v
@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_out_loc_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_out_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_out_loc_ram mmult_out_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_out_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_out_mem_m_axi.v
new file mode 100755
index 0000000..cc472db
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_out_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_out_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_out_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_out_mem_m_axi_write
+mmult_out_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_out_mem_m_axi_read
+mmult_out_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_out_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_out_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_out_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_out_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_out_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_params_s_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_params_s_axi.v
new file mode 100755
index 0000000..d470352
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_params_s_axi.v
@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult.vhd
new file mode 100755
index 0000000..991a8c2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult.vhd
@@ -0,0 +1,4778 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+-- Version: 2020.1
+-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult is
+generic (
+    C_M_AXI_IN1_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_S_AXI_PARAMS_ADDR_WIDTH : INTEGER := 6;
+    C_S_AXI_PARAMS_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_IN2_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_OUT_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_CACHE_VALUE : INTEGER := 3 );
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    m_axi_in1_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in1_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_WREADY : IN STD_LOGIC;
+    m_axi_in1_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in1_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in1_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in1_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RVALID : IN STD_LOGIC;
+    m_axi_in1_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_RLAST : IN STD_LOGIC;
+    m_axi_in1_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BVALID : IN STD_LOGIC;
+    m_axi_in1_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in2_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_WREADY : IN STD_LOGIC;
+    m_axi_in2_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in2_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in2_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in2_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RVALID : IN STD_LOGIC;
+    m_axi_in2_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_RLAST : IN STD_LOGIC;
+    m_axi_in2_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BVALID : IN STD_LOGIC;
+    m_axi_in2_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_out_mem_AWREADY : IN STD_LOGIC;
+    m_axi_out_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_WVALID : OUT STD_LOGIC;
+    m_axi_out_mem_WREADY : IN STD_LOGIC;
+    m_axi_out_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_out_mem_WLAST : OUT STD_LOGIC;
+    m_axi_out_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_out_mem_ARREADY : IN STD_LOGIC;
+    m_axi_out_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RVALID : IN STD_LOGIC;
+    m_axi_out_mem_RREADY : OUT STD_LOGIC;
+    m_axi_out_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_RLAST : IN STD_LOGIC;
+    m_axi_out_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BVALID : IN STD_LOGIC;
+    m_axi_out_mem_BREADY : OUT STD_LOGIC;
+    m_axi_out_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_BUSER_WIDTH-1 downto 0);
+    s_axi_params_AWVALID : IN STD_LOGIC;
+    s_axi_params_AWREADY : OUT STD_LOGIC;
+    s_axi_params_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_WVALID : IN STD_LOGIC;
+    s_axi_params_WREADY : OUT STD_LOGIC;
+    s_axi_params_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH/8-1 downto 0);
+    s_axi_params_ARVALID : IN STD_LOGIC;
+    s_axi_params_ARREADY : OUT STD_LOGIC;
+    s_axi_params_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_RVALID : OUT STD_LOGIC;
+    s_axi_params_RREADY : IN STD_LOGIC;
+    s_axi_params_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    s_axi_params_BVALID : OUT STD_LOGIC;
+    s_axi_params_BREADY : IN STD_LOGIC;
+    s_axi_params_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    interrupt : OUT STD_LOGIC );
+end;
+
+
+architecture behav of mmult is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=153755,HLS_SYN_TPT=none,HLS_SYN_MEM=30,HLS_SYN_DSP=192,HLS_SYN_FF=6462,HLS_SYN_LUT=10635,HLS_VERSION=2020_1}";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
+    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
+    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
+    constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
+    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
+    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
+    constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
+    constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
+    constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
+    constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
+    constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
+    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
+    constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
+    constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
+    constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
+    constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
+    constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
+    constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
+    constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
+    constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
+    constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
+    constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
+    constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
+    constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
+    constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
+    constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
+    constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
+    constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
+    constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
+    constant ap_ST_fsm_state39 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
+    constant ap_ST_fsm_state40 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
+    constant ap_ST_fsm_state41 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
+    constant ap_ST_fsm_state42 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
+    constant ap_ST_fsm_state43 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
+    constant ap_ST_fsm_state44 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state45 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state46 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state47 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state48 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state49 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state50 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state51 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state52 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state53 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state54 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state55 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state56 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state57 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state58 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state59 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state60 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state61 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state62 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state63 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state64 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state65 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state66 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state67 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state68 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state69 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state70 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state71 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state72 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state73 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state74 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state75 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state76 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state77 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state78 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state79 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state80 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state81 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state82 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state83 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state84 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state85 : STD_LOGIC_VECTOR (90 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state86 : STD_LOGIC_VECTOR (90 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state87 : STD_LOGIC_VECTOR (90 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state88 : STD_LOGIC_VECTOR (90 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state89 : STD_LOGIC_VECTOR (90 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (90 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state93 : STD_LOGIC_VECTOR (90 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state94 : STD_LOGIC_VECTOR (90 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state95 : STD_LOGIC_VECTOR (90 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state96 : STD_LOGIC_VECTOR (90 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_ST_fsm_state97 : STD_LOGIC_VECTOR (90 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
+    constant ap_const_lv32_5A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011010";
+    constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
+    constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
+    constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
+    constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
+    constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
+    constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
+    constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
+    constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
+    constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
+    constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
+    constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
+    constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
+    constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
+    constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
+    constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
+    constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
+    constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
+    constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
+    constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
+    constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
+    constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
+    constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
+    constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
+    constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
+    constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
+    constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
+    constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
+    constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
+    constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
+    constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
+    constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
+    constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
+    constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
+    constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
+    constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
+    constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
+    constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
+    constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010";
+    constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011";
+    constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
+    constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
+    constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
+    constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
+    constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
+    constant ap_const_lv32_41 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000001";
+    constant ap_const_lv32_42 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000010";
+    constant ap_const_lv32_43 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000011";
+    constant ap_const_lv32_44 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000100";
+    constant ap_const_lv32_45 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000101";
+    constant ap_const_lv32_46 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000110";
+    constant ap_const_lv32_47 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000111";
+    constant ap_const_lv32_48 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001000";
+    constant ap_const_lv32_49 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001001";
+    constant ap_const_lv32_4A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001010";
+    constant ap_const_lv32_4B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001011";
+    constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
+    constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
+    constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
+    constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
+    constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
+    constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
+    constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
+    constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
+    constant ap_const_lv32_55 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010101";
+    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
+    constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
+    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
+    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
+    constant ap_const_lv32_54 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010100";
+    constant ap_const_lv32_1000 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000001000000000000";
+    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
+    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv13_1000 : STD_LOGIC_VECTOR (12 downto 0) := "1000000000000";
+    constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
+    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
+    constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
+    constant ap_const_lv37_1 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000001";
+    constant ap_const_lv27_0 : STD_LOGIC_VECTOR (26 downto 0) := "000000000000000000000000000";
+    constant ap_const_lv37_2 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000010";
+    constant ap_const_lv37_3 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000011";
+    constant ap_const_lv37_4 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000100";
+    constant ap_const_lv37_5 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000101";
+    constant ap_const_lv37_6 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000110";
+    constant ap_const_lv37_7 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000111";
+    constant ap_const_lv37_8 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000001000";
+    constant ap_const_lv37_9 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000001001";
+    constant ap_const_lv37_A : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000001010";
+    constant ap_const_lv37_B : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000001011";
+    constant ap_const_lv37_C : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000001100";
+    constant ap_const_lv37_D : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000001101";
+    constant ap_const_lv37_E : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000001110";
+    constant ap_const_lv37_F : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000001111";
+    constant ap_const_lv37_10 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000010000";
+    constant ap_const_lv37_11 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000010001";
+    constant ap_const_lv37_12 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000010010";
+    constant ap_const_lv37_13 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000010011";
+    constant ap_const_lv37_14 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000010100";
+    constant ap_const_lv37_15 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000010101";
+    constant ap_const_lv37_16 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000010110";
+    constant ap_const_lv37_17 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000010111";
+    constant ap_const_lv37_18 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000011000";
+    constant ap_const_lv37_19 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000011001";
+    constant ap_const_lv37_1A : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000011010";
+    constant ap_const_lv37_1B : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000011011";
+    constant ap_const_lv37_1C : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000011100";
+    constant ap_const_lv37_1D : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000011101";
+    constant ap_const_lv37_1E : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000011110";
+    constant ap_const_lv37_1F : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000011111";
+    constant ap_const_lv37_20 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100000";
+    constant ap_const_lv37_21 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100001";
+    constant ap_const_lv37_22 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100010";
+    constant ap_const_lv37_23 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100011";
+    constant ap_const_lv37_24 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100100";
+    constant ap_const_lv37_25 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100101";
+    constant ap_const_lv37_26 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100110";
+    constant ap_const_lv37_27 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100111";
+    constant ap_const_lv37_28 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000101000";
+    constant ap_const_lv37_29 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000101001";
+    constant ap_const_lv37_2A : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000101010";
+    constant ap_const_lv37_2B : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000101011";
+    constant ap_const_lv37_2C : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000101100";
+    constant ap_const_lv37_2D : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000101101";
+    constant ap_const_lv37_2E : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000101110";
+    constant ap_const_lv37_2F : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000101111";
+    constant ap_const_lv37_30 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000110000";
+    constant ap_const_lv37_31 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000110001";
+    constant ap_const_lv37_32 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000110010";
+    constant ap_const_lv37_33 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000110011";
+    constant ap_const_lv37_34 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000110100";
+    constant ap_const_lv37_35 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000110101";
+    constant ap_const_lv37_36 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000110110";
+    constant ap_const_lv37_37 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000110111";
+    constant ap_const_lv37_38 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000111000";
+    constant ap_const_lv37_39 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000111001";
+    constant ap_const_lv37_3A : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000111010";
+    constant ap_const_lv37_3B : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000111011";
+    constant ap_const_lv37_3C : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000111100";
+    constant ap_const_lv37_3D : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000111101";
+    constant ap_const_lv37_3E : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000111110";
+    constant ap_const_lv37_3F : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000111111";
+    constant ap_const_lv14_40 : STD_LOGIC_VECTOR (13 downto 0) := "00000001000000";
+    constant ap_const_lv14_80 : STD_LOGIC_VECTOR (13 downto 0) := "00000010000000";
+    constant ap_const_lv14_C0 : STD_LOGIC_VECTOR (13 downto 0) := "00000011000000";
+    constant ap_const_lv14_100 : STD_LOGIC_VECTOR (13 downto 0) := "00000100000000";
+    constant ap_const_lv14_140 : STD_LOGIC_VECTOR (13 downto 0) := "00000101000000";
+    constant ap_const_lv14_180 : STD_LOGIC_VECTOR (13 downto 0) := "00000110000000";
+    constant ap_const_lv14_1C0 : STD_LOGIC_VECTOR (13 downto 0) := "00000111000000";
+    constant ap_const_lv14_200 : STD_LOGIC_VECTOR (13 downto 0) := "00001000000000";
+    constant ap_const_lv14_240 : STD_LOGIC_VECTOR (13 downto 0) := "00001001000000";
+    constant ap_const_lv14_280 : STD_LOGIC_VECTOR (13 downto 0) := "00001010000000";
+    constant ap_const_lv14_2C0 : STD_LOGIC_VECTOR (13 downto 0) := "00001011000000";
+    constant ap_const_lv14_300 : STD_LOGIC_VECTOR (13 downto 0) := "00001100000000";
+    constant ap_const_lv14_340 : STD_LOGIC_VECTOR (13 downto 0) := "00001101000000";
+    constant ap_const_lv14_380 : STD_LOGIC_VECTOR (13 downto 0) := "00001110000000";
+    constant ap_const_lv14_3C0 : STD_LOGIC_VECTOR (13 downto 0) := "00001111000000";
+    constant ap_const_lv14_400 : STD_LOGIC_VECTOR (13 downto 0) := "00010000000000";
+    constant ap_const_lv14_440 : STD_LOGIC_VECTOR (13 downto 0) := "00010001000000";
+    constant ap_const_lv14_480 : STD_LOGIC_VECTOR (13 downto 0) := "00010010000000";
+    constant ap_const_lv14_4C0 : STD_LOGIC_VECTOR (13 downto 0) := "00010011000000";
+    constant ap_const_lv14_500 : STD_LOGIC_VECTOR (13 downto 0) := "00010100000000";
+    constant ap_const_lv14_540 : STD_LOGIC_VECTOR (13 downto 0) := "00010101000000";
+    constant ap_const_lv14_580 : STD_LOGIC_VECTOR (13 downto 0) := "00010110000000";
+    constant ap_const_lv14_5C0 : STD_LOGIC_VECTOR (13 downto 0) := "00010111000000";
+    constant ap_const_lv14_600 : STD_LOGIC_VECTOR (13 downto 0) := "00011000000000";
+    constant ap_const_lv14_640 : STD_LOGIC_VECTOR (13 downto 0) := "00011001000000";
+    constant ap_const_lv14_680 : STD_LOGIC_VECTOR (13 downto 0) := "00011010000000";
+    constant ap_const_lv14_6C0 : STD_LOGIC_VECTOR (13 downto 0) := "00011011000000";
+    constant ap_const_lv14_700 : STD_LOGIC_VECTOR (13 downto 0) := "00011100000000";
+    constant ap_const_lv14_740 : STD_LOGIC_VECTOR (13 downto 0) := "00011101000000";
+    constant ap_const_lv14_780 : STD_LOGIC_VECTOR (13 downto 0) := "00011110000000";
+    constant ap_const_lv14_7C0 : STD_LOGIC_VECTOR (13 downto 0) := "00011111000000";
+    constant ap_const_lv14_800 : STD_LOGIC_VECTOR (13 downto 0) := "00100000000000";
+    constant ap_const_lv14_840 : STD_LOGIC_VECTOR (13 downto 0) := "00100001000000";
+    constant ap_const_lv14_880 : STD_LOGIC_VECTOR (13 downto 0) := "00100010000000";
+    constant ap_const_lv14_8C0 : STD_LOGIC_VECTOR (13 downto 0) := "00100011000000";
+    constant ap_const_lv14_900 : STD_LOGIC_VECTOR (13 downto 0) := "00100100000000";
+    constant ap_const_lv14_940 : STD_LOGIC_VECTOR (13 downto 0) := "00100101000000";
+    constant ap_const_lv14_980 : STD_LOGIC_VECTOR (13 downto 0) := "00100110000000";
+    constant ap_const_lv14_9C0 : STD_LOGIC_VECTOR (13 downto 0) := "00100111000000";
+    constant ap_const_lv14_A00 : STD_LOGIC_VECTOR (13 downto 0) := "00101000000000";
+    constant ap_const_lv14_A40 : STD_LOGIC_VECTOR (13 downto 0) := "00101001000000";
+    constant ap_const_lv14_A80 : STD_LOGIC_VECTOR (13 downto 0) := "00101010000000";
+    constant ap_const_lv14_AC0 : STD_LOGIC_VECTOR (13 downto 0) := "00101011000000";
+    constant ap_const_lv14_B00 : STD_LOGIC_VECTOR (13 downto 0) := "00101100000000";
+    constant ap_const_lv14_B40 : STD_LOGIC_VECTOR (13 downto 0) := "00101101000000";
+    constant ap_const_lv14_B80 : STD_LOGIC_VECTOR (13 downto 0) := "00101110000000";
+    constant ap_const_lv14_BC0 : STD_LOGIC_VECTOR (13 downto 0) := "00101111000000";
+    constant ap_const_lv14_C00 : STD_LOGIC_VECTOR (13 downto 0) := "00110000000000";
+    constant ap_const_lv14_C40 : STD_LOGIC_VECTOR (13 downto 0) := "00110001000000";
+    constant ap_const_lv14_C80 : STD_LOGIC_VECTOR (13 downto 0) := "00110010000000";
+    constant ap_const_lv14_CC0 : STD_LOGIC_VECTOR (13 downto 0) := "00110011000000";
+    constant ap_const_lv14_D00 : STD_LOGIC_VECTOR (13 downto 0) := "00110100000000";
+    constant ap_const_lv14_D40 : STD_LOGIC_VECTOR (13 downto 0) := "00110101000000";
+    constant ap_const_lv14_D80 : STD_LOGIC_VECTOR (13 downto 0) := "00110110000000";
+    constant ap_const_lv14_DC0 : STD_LOGIC_VECTOR (13 downto 0) := "00110111000000";
+    constant ap_const_lv14_E00 : STD_LOGIC_VECTOR (13 downto 0) := "00111000000000";
+    constant ap_const_lv14_E40 : STD_LOGIC_VECTOR (13 downto 0) := "00111001000000";
+    constant ap_const_lv14_E80 : STD_LOGIC_VECTOR (13 downto 0) := "00111010000000";
+    constant ap_const_lv14_EC0 : STD_LOGIC_VECTOR (13 downto 0) := "00111011000000";
+    constant ap_const_lv14_F00 : STD_LOGIC_VECTOR (13 downto 0) := "00111100000000";
+    constant ap_const_lv14_F40 : STD_LOGIC_VECTOR (13 downto 0) := "00111101000000";
+    constant ap_const_lv14_F80 : STD_LOGIC_VECTOR (13 downto 0) := "00111110000000";
+    constant ap_const_lv14_FC0 : STD_LOGIC_VECTOR (13 downto 0) := "00111111000000";
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal ap_start : STD_LOGIC;
+    signal ap_done : STD_LOGIC;
+    signal ap_idle : STD_LOGIC;
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (90 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal ap_ready : STD_LOGIC;
+    signal in1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_r : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal in1_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal icmp_ln27_reg_3840 : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state12 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
+    signal in2_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
+    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp1_stage0 : BOOLEAN;
+    signal icmp_ln28_reg_3854 : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_AW : STD_LOGIC;
+    signal ap_CS_fsm_state23 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state23 : signal is "none";
+    signal icmp_ln31_fu_1563_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_W : STD_LOGIC;
+    signal ap_enable_reg_pp2_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp2_stage0 : BOOLEAN;
+    signal icmp_ln42_reg_5307 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln42_reg_5307_pp2_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_B : STD_LOGIC;
+    signal ap_CS_fsm_state97 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state97 : signal is "none";
+    signal in1_mem_AWREADY : STD_LOGIC;
+    signal in1_mem_WREADY : STD_LOGIC;
+    signal in1_mem_ARVALID : STD_LOGIC;
+    signal in1_mem_ARREADY : STD_LOGIC;
+    signal in1_mem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RVALID : STD_LOGIC;
+    signal in1_mem_RREADY : STD_LOGIC;
+    signal in1_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RLAST : STD_LOGIC;
+    signal in1_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BVALID : STD_LOGIC;
+    signal in1_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_AWREADY : STD_LOGIC;
+    signal in2_mem_WREADY : STD_LOGIC;
+    signal in2_mem_ARVALID : STD_LOGIC;
+    signal in2_mem_ARREADY : STD_LOGIC;
+    signal in2_mem_RVALID : STD_LOGIC;
+    signal in2_mem_RREADY : STD_LOGIC;
+    signal in2_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_RLAST : STD_LOGIC;
+    signal in2_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BVALID : STD_LOGIC;
+    signal in2_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_AWVALID : STD_LOGIC;
+    signal out_mem_AWREADY : STD_LOGIC;
+    signal out_mem_WVALID : STD_LOGIC;
+    signal out_mem_WREADY : STD_LOGIC;
+    signal out_mem_ARREADY : STD_LOGIC;
+    signal out_mem_RVALID : STD_LOGIC;
+    signal out_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_RLAST : STD_LOGIC;
+    signal out_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BVALID : STD_LOGIC;
+    signal out_mem_BREADY : STD_LOGIC;
+    signal out_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal phi_ln27_reg_1410 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln27_reg_1410_pp0_iter1_reg : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_block_state9_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state11_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal phi_ln28_reg_1422 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln28_reg_1422_pp1_iter1_reg : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_block_state19_pp1_stage0_iter0 : BOOLEAN;
+    signal ap_block_state20_pp1_stage0_iter1 : BOOLEAN;
+    signal ap_block_state21_pp1_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp1_stage0_11001 : BOOLEAN;
+    signal phi_ln42_reg_1456 : STD_LOGIC_VECTOR (12 downto 0);
+    signal dim_read_reg_3801 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out5_reg_3807 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in_reg_3812 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in3_reg_3817 : STD_LOGIC_VECTOR (29 downto 0);
+    signal out_mem_addr_reg_3828 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
+    signal in2_mem_addr_reg_3834 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln27_fu_1525_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln27_reg_3840_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln27_fu_1531_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal add_ln27_reg_3844 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal in1_mem_addr_read_reg_3849 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln28_fu_1542_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln28_reg_3854_pp1_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln28_fu_1548_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal add_ln28_reg_3858 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
+    signal in2_mem_addr_read_reg_3863 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state23_io : BOOLEAN;
+    signal i_fu_1568_p2 : STD_LOGIC_VECTOR (30 downto 0);
+    signal i_reg_3872 : STD_LOGIC_VECTOR (30 downto 0);
+    signal tmp_2_fu_1574_p3 : STD_LOGIC_VECTOR (36 downto 0);
+    signal tmp_2_reg_3877 : STD_LOGIC_VECTOR (36 downto 0);
+    signal trunc_ln38_fu_1587_p1 : STD_LOGIC_VECTOR (7 downto 0);
+    signal trunc_ln38_reg_3943 : STD_LOGIC_VECTOR (7 downto 0);
+    signal ap_CS_fsm_state24 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state24 : signal is "none";
+    signal in1_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_reg_3968 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_q1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_1_reg_3973 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state25 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
+    signal in1_loc_load_2_reg_3988 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_3_reg_3993 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state26 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
+    signal in1_loc_load_4_reg_4008 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_5_reg_4013 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state27 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
+    signal in1_loc_load_6_reg_4028 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_7_reg_4033 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state28 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state28 : signal is "none";
+    signal in1_loc_load_8_reg_4048 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_9_reg_4053 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state29 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state29 : signal is "none";
+    signal in1_loc_load_10_reg_4068 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_11_reg_4073 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state30 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state30 : signal is "none";
+    signal in1_loc_load_12_reg_4088 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_13_reg_4093 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state31 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state31 : signal is "none";
+    signal in1_loc_load_14_reg_4108 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_15_reg_4113 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state32 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state32 : signal is "none";
+    signal in1_loc_load_16_reg_4128 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_17_reg_4133 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state33 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state33 : signal is "none";
+    signal in1_loc_load_18_reg_4148 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_19_reg_4153 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state34 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state34 : signal is "none";
+    signal in1_loc_load_20_reg_4168 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_21_reg_4173 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state35 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state35 : signal is "none";
+    signal in1_loc_load_22_reg_4188 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_23_reg_4193 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state36 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state36 : signal is "none";
+    signal in1_loc_load_24_reg_4208 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_25_reg_4213 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state37 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state37 : signal is "none";
+    signal in1_loc_load_26_reg_4228 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_27_reg_4233 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state38 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state38 : signal is "none";
+    signal in1_loc_load_28_reg_4248 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_29_reg_4253 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state39 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state39 : signal is "none";
+    signal in1_loc_load_30_reg_4268 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_31_reg_4273 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state40 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state40 : signal is "none";
+    signal in1_loc_load_32_reg_4288 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_33_reg_4293 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state41 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state41 : signal is "none";
+    signal in1_loc_load_34_reg_4308 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_35_reg_4313 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state42 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state42 : signal is "none";
+    signal in1_loc_load_36_reg_4328 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_37_reg_4333 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state43 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state43 : signal is "none";
+    signal in1_loc_load_38_reg_4348 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_39_reg_4353 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state44 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state44 : signal is "none";
+    signal in1_loc_load_40_reg_4368 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_41_reg_4373 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state45 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state45 : signal is "none";
+    signal in1_loc_load_42_reg_4388 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_43_reg_4393 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state46 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state46 : signal is "none";
+    signal in1_loc_load_44_reg_4408 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_45_reg_4413 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state47 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state47 : signal is "none";
+    signal in1_loc_load_46_reg_4428 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_47_reg_4433 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state48 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state48 : signal is "none";
+    signal in1_loc_load_48_reg_4448 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_49_reg_4453 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state49 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state49 : signal is "none";
+    signal in1_loc_load_50_reg_4468 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_51_reg_4473 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state50 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state50 : signal is "none";
+    signal in1_loc_load_52_reg_4488 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_53_reg_4493 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state51 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state51 : signal is "none";
+    signal in1_loc_load_54_reg_4508 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_55_reg_4513 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state52 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state52 : signal is "none";
+    signal in1_loc_load_56_reg_4528 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_57_reg_4533 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state53 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state53 : signal is "none";
+    signal in1_loc_load_58_reg_4548 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_59_reg_4553 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state54 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state54 : signal is "none";
+    signal in1_loc_load_60_reg_4568 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_61_reg_4573 : STD_LOGIC_VECTOR (31 downto 0);
+    signal zext_ln38_cast_fu_2474_p3 : STD_LOGIC_VECTOR (13 downto 0);
+    signal zext_ln38_cast_reg_4578 : STD_LOGIC_VECTOR (13 downto 0);
+    signal ap_CS_fsm_state55 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state55 : signal is "none";
+    signal in1_loc_load_62_reg_4583 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_load_63_reg_4588 : STD_LOGIC_VECTOR (31 downto 0);
+    signal j_fu_2486_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal j_reg_4596 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state56 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state56 : signal is "none";
+    signal trunc_ln38_1_fu_2497_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal trunc_ln38_1_reg_4601 : STD_LOGIC_VECTOR (13 downto 0);
+    signal icmp_ln33_fu_2481_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_loc_addr_reg_4677 : STD_LOGIC_VECTOR (11 downto 0);
+    signal ap_CS_fsm_state57 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state57 : signal is "none";
+    signal mul_ln38_fu_2542_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_reg_4692 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_fu_2547_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_reg_4697 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state58 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state58 : signal is "none";
+    signal mul_ln38_3_fu_2577_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_reg_4712 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_2_fu_2592_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_2_reg_4717 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state59 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state59 : signal is "none";
+    signal mul_ln38_5_fu_2623_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_reg_4732 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_3_fu_2628_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_3_reg_4737 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state60 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state60 : signal is "none";
+    signal mul_ln38_7_fu_2658_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_reg_4752 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_6_fu_2673_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_6_reg_4757 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state61 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state61 : signal is "none";
+    signal mul_ln38_9_fu_2703_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_reg_4772 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_7_fu_2708_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_7_reg_4777 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state62 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state62 : signal is "none";
+    signal mul_ln38_11_fu_2738_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_reg_4792 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_9_fu_2748_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_9_reg_4797 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state63 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state63 : signal is "none";
+    signal mul_ln38_13_fu_2778_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_reg_4812 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_10_fu_2783_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_10_reg_4817 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state64 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state64 : signal is "none";
+    signal mul_ln38_15_fu_2813_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_reg_4832 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_14_fu_2833_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_14_reg_4837 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state65 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state65 : signal is "none";
+    signal mul_ln38_17_fu_2863_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_reg_4852 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_15_fu_2868_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_15_reg_4857 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state66 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state66 : signal is "none";
+    signal mul_ln38_19_fu_2898_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_reg_4872 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_17_fu_2908_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_17_reg_4877 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state67 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state67 : signal is "none";
+    signal mul_ln38_21_fu_2938_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_reg_4892 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_18_fu_2943_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_18_reg_4897 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state68 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state68 : signal is "none";
+    signal mul_ln38_23_fu_2973_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_reg_4912 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_fu_2988_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_reg_4917 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state69 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state69 : signal is "none";
+    signal mul_ln38_25_fu_3018_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_reg_4932 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_22_fu_3023_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_22_reg_4937 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state70 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state70 : signal is "none";
+    signal mul_ln38_27_fu_3053_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_reg_4952 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_24_fu_3063_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_24_reg_4957 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state71 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state71 : signal is "none";
+    signal mul_ln38_29_fu_3093_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_reg_4972 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_25_fu_3098_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_25_reg_4977 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state72 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state72 : signal is "none";
+    signal mul_ln38_31_fu_3128_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_reg_4992 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_30_fu_3153_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_30_reg_4997 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state73 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state73 : signal is "none";
+    signal mul_ln38_33_fu_3183_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_reg_5012 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_31_fu_3188_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_31_reg_5017 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state74 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state74 : signal is "none";
+    signal mul_ln38_35_fu_3218_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_reg_5032 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_33_fu_3228_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_33_reg_5037 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state75 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state75 : signal is "none";
+    signal mul_ln38_37_fu_3258_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_reg_5052 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_34_fu_3263_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_34_reg_5057 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state76 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state76 : signal is "none";
+    signal mul_ln38_39_fu_3293_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_reg_5072 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_fu_3308_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_reg_5077 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state77 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state77 : signal is "none";
+    signal mul_ln38_41_fu_3338_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_reg_5092 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_38_fu_3343_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_38_reg_5097 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state78 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state78 : signal is "none";
+    signal mul_ln38_43_fu_3373_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_reg_5112 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_40_fu_3383_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_40_reg_5117 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state79 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state79 : signal is "none";
+    signal mul_ln38_45_fu_3413_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_reg_5132 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_41_fu_3418_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_41_reg_5137 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state80 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state80 : signal is "none";
+    signal mul_ln38_47_fu_3448_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_reg_5152 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_45_fu_3468_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_45_reg_5157 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state81 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state81 : signal is "none";
+    signal mul_ln38_49_fu_3498_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_reg_5172 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_46_fu_3503_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_46_reg_5177 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state82 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state82 : signal is "none";
+    signal mul_ln38_51_fu_3533_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_reg_5192 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_48_fu_3543_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_48_reg_5197 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state83 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state83 : signal is "none";
+    signal mul_ln38_53_fu_3573_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_reg_5212 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_49_fu_3578_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_49_reg_5217 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state84 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state84 : signal is "none";
+    signal mul_ln38_55_fu_3608_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_reg_5232 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_fu_3623_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_reg_5237 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state85 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state85 : signal is "none";
+    signal mul_ln38_57_fu_3653_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_reg_5252 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_53_fu_3658_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_53_reg_5257 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state86 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state86 : signal is "none";
+    signal mul_ln38_59_fu_3688_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_reg_5272 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_55_fu_3698_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_55_reg_5277 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state87 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state87 : signal is "none";
+    signal mul_ln38_61_fu_3728_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_reg_5292 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_56_fu_3733_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_56_reg_5297 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_61_fu_3769_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_61_reg_5302 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state88 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state88 : signal is "none";
+    signal icmp_ln42_fu_3784_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
+    signal ap_block_state90_pp2_stage0_iter0 : BOOLEAN;
+    signal ap_block_state91_pp2_stage0_iter1 : BOOLEAN;
+    signal ap_block_state92_pp2_stage0_iter2 : BOOLEAN;
+    signal ap_block_state92_io : BOOLEAN;
+    signal ap_block_pp2_stage0_11001 : BOOLEAN;
+    signal add_ln42_fu_3790_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
+    signal out_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_load_reg_5321 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state9 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_CS_fsm_state18 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
+    signal ap_block_pp1_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp1_exit_iter0_state19 : STD_LOGIC;
+    signal ap_enable_reg_pp1_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp2_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp2_exit_iter0_state90 : STD_LOGIC;
+    signal in1_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal in1_loc_ce0 : STD_LOGIC;
+    signal in1_loc_we0 : STD_LOGIC;
+    signal in1_loc_address1 : STD_LOGIC_VECTOR (11 downto 0);
+    signal in1_loc_ce1 : STD_LOGIC;
+    signal in2_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal in2_loc_ce0 : STD_LOGIC;
+    signal in2_loc_we0 : STD_LOGIC;
+    signal in2_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_address1 : STD_LOGIC_VECTOR (11 downto 0);
+    signal in2_loc_ce1 : STD_LOGIC;
+    signal in2_loc_q1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_ce0 : STD_LOGIC;
+    signal out_loc_we0 : STD_LOGIC;
+    signal out_loc_d0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_phi_mux_phi_ln27_phi_fu_1414_p4 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_phi_mux_phi_ln28_phi_fu_1426_p4 : STD_LOGIC_VECTOR (12 downto 0);
+    signal i_0_reg_1434 : STD_LOGIC_VECTOR (30 downto 0);
+    signal ap_CS_fsm_state22 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
+    signal j_0_reg_1445 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state89 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state89 : signal is "none";
+    signal zext_ln27_fu_1537_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln28_fu_1554_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln38_fu_1582_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_3_fu_1597_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_4_fu_1611_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_5_fu_1625_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_6_fu_1639_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_7_fu_1653_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_8_fu_1667_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_9_fu_1681_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_s_fu_1695_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_10_fu_1709_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_11_fu_1723_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_12_fu_1737_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_13_fu_1751_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_14_fu_1765_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_15_fu_1779_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_16_fu_1793_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_17_fu_1807_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_18_fu_1821_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_19_fu_1835_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_20_fu_1849_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_21_fu_1863_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_22_fu_1877_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_23_fu_1891_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_24_fu_1905_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_25_fu_1919_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_26_fu_1933_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_27_fu_1947_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_28_fu_1961_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_29_fu_1975_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_30_fu_1989_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_31_fu_2003_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_32_fu_2017_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_33_fu_2031_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_34_fu_2045_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_35_fu_2059_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_36_fu_2073_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_37_fu_2087_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_38_fu_2101_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_39_fu_2115_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_40_fu_2129_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_41_fu_2143_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_42_fu_2157_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_43_fu_2171_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_44_fu_2185_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_45_fu_2199_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_46_fu_2213_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_47_fu_2227_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_48_fu_2241_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_49_fu_2255_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_50_fu_2269_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_51_fu_2283_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_52_fu_2297_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_53_fu_2311_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_54_fu_2325_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_55_fu_2339_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_56_fu_2353_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_57_fu_2367_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_58_fu_2381_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_59_fu_2395_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_60_fu_2409_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_61_fu_2423_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_62_fu_2437_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_63_fu_2451_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_64_fu_2465_p3 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_fu_2492_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_1_fu_2507_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_64_fu_2517_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_2_fu_2527_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_3_fu_2537_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_4_fu_2557_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_5_fu_2567_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_6_fu_2603_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_7_fu_2613_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_8_fu_2638_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_9_fu_2648_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_10_fu_2683_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_11_fu_2693_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_12_fu_2718_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_13_fu_2728_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_14_fu_2758_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_15_fu_2768_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_16_fu_2793_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_17_fu_2803_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_18_fu_2843_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_19_fu_2853_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_20_fu_2878_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_21_fu_2888_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_22_fu_2918_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_23_fu_2928_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_24_fu_2953_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_25_fu_2963_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_26_fu_2998_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_27_fu_3008_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_28_fu_3033_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_29_fu_3043_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_30_fu_3073_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_31_fu_3083_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_32_fu_3108_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_33_fu_3118_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_34_fu_3163_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_35_fu_3173_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_36_fu_3198_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_37_fu_3208_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_38_fu_3238_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_39_fu_3248_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_40_fu_3273_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_41_fu_3283_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_42_fu_3318_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_43_fu_3328_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_44_fu_3353_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_45_fu_3363_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_46_fu_3393_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_47_fu_3403_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_48_fu_3428_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_49_fu_3438_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_50_fu_3478_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_51_fu_3488_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_52_fu_3513_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_53_fu_3523_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_54_fu_3553_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_55_fu_3563_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_56_fu_3588_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_57_fu_3598_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_58_fu_3633_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_59_fu_3643_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_60_fu_3668_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_61_fu_3678_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_62_fu_3708_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_63_fu_3718_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln42_fu_3796_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_6_fu_1497_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_fu_1507_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_5_fu_1516_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp2_stage0_01001 : BOOLEAN;
+    signal zext_ln31_fu_1559_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal or_ln38_fu_1591_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_1_fu_1606_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_2_fu_1620_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_3_fu_1634_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_4_fu_1648_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_5_fu_1662_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_6_fu_1676_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_7_fu_1690_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_8_fu_1704_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_9_fu_1718_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_10_fu_1732_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_11_fu_1746_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_12_fu_1760_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_13_fu_1774_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_14_fu_1788_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_15_fu_1802_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_16_fu_1816_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_17_fu_1830_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_18_fu_1844_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_19_fu_1858_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_20_fu_1872_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_21_fu_1886_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_22_fu_1900_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_23_fu_1914_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_24_fu_1928_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_25_fu_1942_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_26_fu_1956_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_27_fu_1970_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_28_fu_1984_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_29_fu_1998_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_30_fu_2012_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_31_fu_2026_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_32_fu_2040_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_33_fu_2054_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_34_fu_2068_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_35_fu_2082_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_36_fu_2096_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_37_fu_2110_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_38_fu_2124_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_39_fu_2138_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_40_fu_2152_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_41_fu_2166_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_42_fu_2180_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_43_fu_2194_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_44_fu_2208_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_45_fu_2222_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_46_fu_2236_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_47_fu_2250_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_48_fu_2264_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_49_fu_2278_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_50_fu_2292_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_51_fu_2306_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_52_fu_2320_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_53_fu_2334_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_54_fu_2348_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_55_fu_2362_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_56_fu_2376_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_57_fu_2390_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_58_fu_2404_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_59_fu_2418_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_60_fu_2432_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_61_fu_2446_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal or_ln38_62_fu_2460_p2 : STD_LOGIC_VECTOR (36 downto 0);
+    signal add_ln38_64_fu_2501_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_127_fu_2512_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_65_fu_2522_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_66_fu_2532_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_fu_2542_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_fu_2547_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_67_fu_2552_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_68_fu_2562_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_2_fu_2572_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_fu_2577_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_fu_2572_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_fu_2582_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_1_fu_2587_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_69_fu_2598_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_70_fu_2608_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_4_fu_2618_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_fu_2623_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_fu_2618_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_71_fu_2633_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_72_fu_2643_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_6_fu_2653_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_fu_2658_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_fu_2653_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_4_fu_2663_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_5_fu_2668_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_73_fu_2678_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_74_fu_2688_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_8_fu_2698_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_fu_2703_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_fu_2698_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_75_fu_2713_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_76_fu_2723_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_10_fu_2733_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_fu_2738_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_fu_2733_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_8_fu_2743_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_77_fu_2753_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_78_fu_2763_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_12_fu_2773_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_fu_2778_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_fu_2773_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_79_fu_2788_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_80_fu_2798_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_14_fu_2808_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_fu_2813_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_fu_2808_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_11_fu_2818_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_12_fu_2823_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_13_fu_2828_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_81_fu_2838_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_82_fu_2848_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_16_fu_2858_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_fu_2863_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_fu_2858_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_83_fu_2873_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_84_fu_2883_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_18_fu_2893_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_fu_2898_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_fu_2893_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_16_fu_2903_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_85_fu_2913_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_86_fu_2923_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_20_fu_2933_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_fu_2938_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_fu_2933_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_87_fu_2948_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_88_fu_2958_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_22_fu_2968_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_fu_2973_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_fu_2968_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_19_fu_2978_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_20_fu_2983_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_89_fu_2993_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_90_fu_3003_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_24_fu_3013_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_fu_3018_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_fu_3013_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_91_fu_3028_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_92_fu_3038_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_26_fu_3048_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_fu_3053_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_fu_3048_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_23_fu_3058_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_93_fu_3068_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_94_fu_3078_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_28_fu_3088_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_fu_3093_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_fu_3088_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_95_fu_3103_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_96_fu_3113_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_30_fu_3123_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_fu_3128_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_fu_3123_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_26_fu_3133_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_27_fu_3138_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_28_fu_3143_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_29_fu_3148_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_97_fu_3158_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_98_fu_3168_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_32_fu_3178_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_fu_3183_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_fu_3178_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_99_fu_3193_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_100_fu_3203_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_34_fu_3213_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_fu_3218_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_fu_3213_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_32_fu_3223_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_101_fu_3233_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_102_fu_3243_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_36_fu_3253_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_fu_3258_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_fu_3253_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_103_fu_3268_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_104_fu_3278_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_38_fu_3288_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_fu_3293_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_fu_3288_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_35_fu_3298_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_36_fu_3303_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_105_fu_3313_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_106_fu_3323_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_40_fu_3333_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_fu_3338_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_fu_3333_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_107_fu_3348_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_108_fu_3358_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_42_fu_3368_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_fu_3373_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_fu_3368_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_39_fu_3378_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_109_fu_3388_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_110_fu_3398_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_44_fu_3408_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_fu_3413_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_fu_3408_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_111_fu_3423_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_112_fu_3433_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_46_fu_3443_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_fu_3448_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_fu_3443_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_42_fu_3453_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_43_fu_3458_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_44_fu_3463_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_113_fu_3473_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_114_fu_3483_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_48_fu_3493_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_fu_3498_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_fu_3493_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_115_fu_3508_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_116_fu_3518_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_50_fu_3528_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_fu_3533_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_fu_3528_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_47_fu_3538_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_117_fu_3548_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_118_fu_3558_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_52_fu_3568_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_fu_3573_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_fu_3568_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_119_fu_3583_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_120_fu_3593_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_54_fu_3603_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_fu_3608_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_fu_3603_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_50_fu_3613_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_51_fu_3618_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_121_fu_3628_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_122_fu_3638_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_56_fu_3648_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_fu_3653_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_fu_3648_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_123_fu_3663_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_124_fu_3673_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_58_fu_3683_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_fu_3688_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_fu_3683_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_54_fu_3693_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_125_fu_3703_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_126_fu_3713_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_60_fu_3723_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_fu_3728_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_fu_3723_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_fu_3738_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_fu_3743_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_fu_3743_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_fu_3738_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_57_fu_3748_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_58_fu_3754_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_59_fu_3759_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_60_fu_3764_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_62_fu_3774_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (90 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal ap_idle_pp1 : STD_LOGIC;
+    signal ap_enable_pp1 : STD_LOGIC;
+    signal ap_idle_pp2 : STD_LOGIC;
+    signal ap_enable_pp2 : STD_LOGIC;
+
+    component mmult_in1_loc IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        address1 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce1 : IN STD_LOGIC;
+        q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_out_loc IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_params_s_axi IS
+    generic (
+        C_S_AXI_ADDR_WIDTH : INTEGER;
+        C_S_AXI_DATA_WIDTH : INTEGER );
+    port (
+        AWVALID : IN STD_LOGIC;
+        AWREADY : OUT STD_LOGIC;
+        AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        WVALID : IN STD_LOGIC;
+        WREADY : OUT STD_LOGIC;
+        WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
+        ARVALID : IN STD_LOGIC;
+        ARREADY : OUT STD_LOGIC;
+        ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        RVALID : OUT STD_LOGIC;
+        RREADY : IN STD_LOGIC;
+        RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : OUT STD_LOGIC;
+        BREADY : IN STD_LOGIC;
+        BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        ap_start : OUT STD_LOGIC;
+        interrupt : OUT STD_LOGIC;
+        ap_ready : IN STD_LOGIC;
+        ap_done : IN STD_LOGIC;
+        ap_idle : IN STD_LOGIC;
+        in1 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        in2 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        out_r : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dim : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_in2_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_out_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+
+begin
+    mmult_params_s_axi_U : component mmult_params_s_axi
+    generic map (
+        C_S_AXI_ADDR_WIDTH => C_S_AXI_PARAMS_ADDR_WIDTH,
+        C_S_AXI_DATA_WIDTH => C_S_AXI_PARAMS_DATA_WIDTH)
+    port map (
+        AWVALID => s_axi_params_AWVALID,
+        AWREADY => s_axi_params_AWREADY,
+        AWADDR => s_axi_params_AWADDR,
+        WVALID => s_axi_params_WVALID,
+        WREADY => s_axi_params_WREADY,
+        WDATA => s_axi_params_WDATA,
+        WSTRB => s_axi_params_WSTRB,
+        ARVALID => s_axi_params_ARVALID,
+        ARREADY => s_axi_params_ARREADY,
+        ARADDR => s_axi_params_ARADDR,
+        RVALID => s_axi_params_RVALID,
+        RREADY => s_axi_params_RREADY,
+        RDATA => s_axi_params_RDATA,
+        RRESP => s_axi_params_RRESP,
+        BVALID => s_axi_params_BVALID,
+        BREADY => s_axi_params_BREADY,
+        BRESP => s_axi_params_BRESP,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        ap_start => ap_start,
+        interrupt => interrupt,
+        ap_ready => ap_ready,
+        ap_done => ap_done,
+        ap_idle => ap_idle,
+        in1 => in1,
+        in2 => in2,
+        out_r => out_r,
+        dim => dim);
+
+    mmult_in1_mem_m_axi_U : component mmult_in1_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN1_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN1_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN1_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN1_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN1_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN1_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN1_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN1_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN1_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN1_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN1_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in1_mem_AWVALID,
+        AWREADY => m_axi_in1_mem_AWREADY,
+        AWADDR => m_axi_in1_mem_AWADDR,
+        AWID => m_axi_in1_mem_AWID,
+        AWLEN => m_axi_in1_mem_AWLEN,
+        AWSIZE => m_axi_in1_mem_AWSIZE,
+        AWBURST => m_axi_in1_mem_AWBURST,
+        AWLOCK => m_axi_in1_mem_AWLOCK,
+        AWCACHE => m_axi_in1_mem_AWCACHE,
+        AWPROT => m_axi_in1_mem_AWPROT,
+        AWQOS => m_axi_in1_mem_AWQOS,
+        AWREGION => m_axi_in1_mem_AWREGION,
+        AWUSER => m_axi_in1_mem_AWUSER,
+        WVALID => m_axi_in1_mem_WVALID,
+        WREADY => m_axi_in1_mem_WREADY,
+        WDATA => m_axi_in1_mem_WDATA,
+        WSTRB => m_axi_in1_mem_WSTRB,
+        WLAST => m_axi_in1_mem_WLAST,
+        WID => m_axi_in1_mem_WID,
+        WUSER => m_axi_in1_mem_WUSER,
+        ARVALID => m_axi_in1_mem_ARVALID,
+        ARREADY => m_axi_in1_mem_ARREADY,
+        ARADDR => m_axi_in1_mem_ARADDR,
+        ARID => m_axi_in1_mem_ARID,
+        ARLEN => m_axi_in1_mem_ARLEN,
+        ARSIZE => m_axi_in1_mem_ARSIZE,
+        ARBURST => m_axi_in1_mem_ARBURST,
+        ARLOCK => m_axi_in1_mem_ARLOCK,
+        ARCACHE => m_axi_in1_mem_ARCACHE,
+        ARPROT => m_axi_in1_mem_ARPROT,
+        ARQOS => m_axi_in1_mem_ARQOS,
+        ARREGION => m_axi_in1_mem_ARREGION,
+        ARUSER => m_axi_in1_mem_ARUSER,
+        RVALID => m_axi_in1_mem_RVALID,
+        RREADY => m_axi_in1_mem_RREADY,
+        RDATA => m_axi_in1_mem_RDATA,
+        RLAST => m_axi_in1_mem_RLAST,
+        RID => m_axi_in1_mem_RID,
+        RUSER => m_axi_in1_mem_RUSER,
+        RRESP => m_axi_in1_mem_RRESP,
+        BVALID => m_axi_in1_mem_BVALID,
+        BREADY => m_axi_in1_mem_BREADY,
+        BRESP => m_axi_in1_mem_BRESP,
+        BID => m_axi_in1_mem_BID,
+        BUSER => m_axi_in1_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in1_mem_ARVALID,
+        I_ARREADY => in1_mem_ARREADY,
+        I_ARADDR => in1_mem_ARADDR,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in1_mem_RVALID,
+        I_RREADY => in1_mem_RREADY,
+        I_RDATA => in1_mem_RDATA,
+        I_RID => in1_mem_RID,
+        I_RUSER => in1_mem_RUSER,
+        I_RRESP => in1_mem_RRESP,
+        I_RLAST => in1_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in1_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in1_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in1_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in1_mem_BRESP,
+        I_BID => in1_mem_BID,
+        I_BUSER => in1_mem_BUSER);
+
+    mmult_in2_mem_m_axi_U : component mmult_in2_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN2_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN2_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN2_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN2_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN2_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN2_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN2_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN2_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN2_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN2_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN2_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in2_mem_AWVALID,
+        AWREADY => m_axi_in2_mem_AWREADY,
+        AWADDR => m_axi_in2_mem_AWADDR,
+        AWID => m_axi_in2_mem_AWID,
+        AWLEN => m_axi_in2_mem_AWLEN,
+        AWSIZE => m_axi_in2_mem_AWSIZE,
+        AWBURST => m_axi_in2_mem_AWBURST,
+        AWLOCK => m_axi_in2_mem_AWLOCK,
+        AWCACHE => m_axi_in2_mem_AWCACHE,
+        AWPROT => m_axi_in2_mem_AWPROT,
+        AWQOS => m_axi_in2_mem_AWQOS,
+        AWREGION => m_axi_in2_mem_AWREGION,
+        AWUSER => m_axi_in2_mem_AWUSER,
+        WVALID => m_axi_in2_mem_WVALID,
+        WREADY => m_axi_in2_mem_WREADY,
+        WDATA => m_axi_in2_mem_WDATA,
+        WSTRB => m_axi_in2_mem_WSTRB,
+        WLAST => m_axi_in2_mem_WLAST,
+        WID => m_axi_in2_mem_WID,
+        WUSER => m_axi_in2_mem_WUSER,
+        ARVALID => m_axi_in2_mem_ARVALID,
+        ARREADY => m_axi_in2_mem_ARREADY,
+        ARADDR => m_axi_in2_mem_ARADDR,
+        ARID => m_axi_in2_mem_ARID,
+        ARLEN => m_axi_in2_mem_ARLEN,
+        ARSIZE => m_axi_in2_mem_ARSIZE,
+        ARBURST => m_axi_in2_mem_ARBURST,
+        ARLOCK => m_axi_in2_mem_ARLOCK,
+        ARCACHE => m_axi_in2_mem_ARCACHE,
+        ARPROT => m_axi_in2_mem_ARPROT,
+        ARQOS => m_axi_in2_mem_ARQOS,
+        ARREGION => m_axi_in2_mem_ARREGION,
+        ARUSER => m_axi_in2_mem_ARUSER,
+        RVALID => m_axi_in2_mem_RVALID,
+        RREADY => m_axi_in2_mem_RREADY,
+        RDATA => m_axi_in2_mem_RDATA,
+        RLAST => m_axi_in2_mem_RLAST,
+        RID => m_axi_in2_mem_RID,
+        RUSER => m_axi_in2_mem_RUSER,
+        RRESP => m_axi_in2_mem_RRESP,
+        BVALID => m_axi_in2_mem_BVALID,
+        BREADY => m_axi_in2_mem_BREADY,
+        BRESP => m_axi_in2_mem_BRESP,
+        BID => m_axi_in2_mem_BID,
+        BUSER => m_axi_in2_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in2_mem_ARVALID,
+        I_ARREADY => in2_mem_ARREADY,
+        I_ARADDR => in2_mem_addr_reg_3834,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in2_mem_RVALID,
+        I_RREADY => in2_mem_RREADY,
+        I_RDATA => in2_mem_RDATA,
+        I_RID => in2_mem_RID,
+        I_RUSER => in2_mem_RUSER,
+        I_RRESP => in2_mem_RRESP,
+        I_RLAST => in2_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in2_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in2_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in2_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in2_mem_BRESP,
+        I_BID => in2_mem_BID,
+        I_BUSER => in2_mem_BUSER);
+
+    mmult_out_mem_m_axi_U : component mmult_out_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_OUT_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_OUT_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_OUT_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_OUT_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_OUT_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_OUT_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_OUT_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_OUT_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_OUT_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_OUT_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_OUT_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_out_mem_AWVALID,
+        AWREADY => m_axi_out_mem_AWREADY,
+        AWADDR => m_axi_out_mem_AWADDR,
+        AWID => m_axi_out_mem_AWID,
+        AWLEN => m_axi_out_mem_AWLEN,
+        AWSIZE => m_axi_out_mem_AWSIZE,
+        AWBURST => m_axi_out_mem_AWBURST,
+        AWLOCK => m_axi_out_mem_AWLOCK,
+        AWCACHE => m_axi_out_mem_AWCACHE,
+        AWPROT => m_axi_out_mem_AWPROT,
+        AWQOS => m_axi_out_mem_AWQOS,
+        AWREGION => m_axi_out_mem_AWREGION,
+        AWUSER => m_axi_out_mem_AWUSER,
+        WVALID => m_axi_out_mem_WVALID,
+        WREADY => m_axi_out_mem_WREADY,
+        WDATA => m_axi_out_mem_WDATA,
+        WSTRB => m_axi_out_mem_WSTRB,
+        WLAST => m_axi_out_mem_WLAST,
+        WID => m_axi_out_mem_WID,
+        WUSER => m_axi_out_mem_WUSER,
+        ARVALID => m_axi_out_mem_ARVALID,
+        ARREADY => m_axi_out_mem_ARREADY,
+        ARADDR => m_axi_out_mem_ARADDR,
+        ARID => m_axi_out_mem_ARID,
+        ARLEN => m_axi_out_mem_ARLEN,
+        ARSIZE => m_axi_out_mem_ARSIZE,
+        ARBURST => m_axi_out_mem_ARBURST,
+        ARLOCK => m_axi_out_mem_ARLOCK,
+        ARCACHE => m_axi_out_mem_ARCACHE,
+        ARPROT => m_axi_out_mem_ARPROT,
+        ARQOS => m_axi_out_mem_ARQOS,
+        ARREGION => m_axi_out_mem_ARREGION,
+        ARUSER => m_axi_out_mem_ARUSER,
+        RVALID => m_axi_out_mem_RVALID,
+        RREADY => m_axi_out_mem_RREADY,
+        RDATA => m_axi_out_mem_RDATA,
+        RLAST => m_axi_out_mem_RLAST,
+        RID => m_axi_out_mem_RID,
+        RUSER => m_axi_out_mem_RUSER,
+        RRESP => m_axi_out_mem_RRESP,
+        BVALID => m_axi_out_mem_BVALID,
+        BREADY => m_axi_out_mem_BREADY,
+        BRESP => m_axi_out_mem_BRESP,
+        BID => m_axi_out_mem_BID,
+        BUSER => m_axi_out_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => ap_const_logic_0,
+        I_ARREADY => out_mem_ARREADY,
+        I_ARADDR => ap_const_lv32_0,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_0,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => out_mem_RVALID,
+        I_RREADY => ap_const_logic_0,
+        I_RDATA => out_mem_RDATA,
+        I_RID => out_mem_RID,
+        I_RUSER => out_mem_RUSER,
+        I_RRESP => out_mem_RRESP,
+        I_RLAST => out_mem_RLAST,
+        I_AWVALID => out_mem_AWVALID,
+        I_AWREADY => out_mem_AWREADY,
+        I_AWADDR => out_mem_addr_reg_3828,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_1000,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => out_mem_WVALID,
+        I_WREADY => out_mem_WREADY,
+        I_WDATA => out_loc_load_reg_5321,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_F,
+        I_BVALID => out_mem_BVALID,
+        I_BREADY => out_mem_BREADY,
+        I_BRESP => out_mem_BRESP,
+        I_BID => out_mem_BID,
+        I_BUSER => out_mem_BUSER);
+
+    in1_loc_U : component mmult_in1_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_address0,
+        ce0 => in1_loc_ce0,
+        we0 => in1_loc_we0,
+        d0 => in1_mem_addr_read_reg_3849,
+        q0 => in1_loc_q0,
+        address1 => in1_loc_address1,
+        ce1 => in1_loc_ce1,
+        q1 => in1_loc_q1);
+
+    in2_loc_U : component mmult_in1_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_address0,
+        ce0 => in2_loc_ce0,
+        we0 => in2_loc_we0,
+        d0 => in2_mem_addr_read_reg_3863,
+        q0 => in2_loc_q0,
+        address1 => in2_loc_address1,
+        ce1 => in2_loc_ce1,
+        q1 => in2_loc_q1);
+
+    out_loc_U : component mmult_out_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => out_loc_address0,
+        ce0 => out_loc_ce0,
+        we0 => out_loc_we0,
+        d0 => out_loc_d0,
+        q0 => out_loc_q0);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state9);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19)) then 
+                        ap_enable_reg_pp1_iter1 <= (ap_const_logic_1 xor ap_condition_pp1_exit_iter0_state19);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_condition_pp2_exit_iter0_state90) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+                elsif (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_1563_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp2_exit_iter0_state90)) then 
+                        ap_enable_reg_pp2_iter1 <= (ap_const_logic_1 xor ap_condition_pp2_exit_iter0_state90);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+                elsif (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_1563_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+                    ap_enable_reg_pp2_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0_reg_1434_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                i_0_reg_1434 <= ap_const_lv31_0;
+            elsif (((icmp_ln33_fu_2481_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state56))) then 
+                i_0_reg_1434 <= i_reg_3872;
+            end if; 
+        end if;
+    end process;
+
+    j_0_reg_1445_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state89)) then 
+                j_0_reg_1445 <= j_reg_4596;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state55)) then 
+                j_0_reg_1445 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln27_reg_1410_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_reg_3840 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                phi_ln27_reg_1410 <= add_ln27_reg_3844;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                phi_ln27_reg_1410 <= ap_const_lv13_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln28_reg_1422_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                phi_ln28_reg_1422 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_reg_3854 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+                phi_ln28_reg_1422 <= add_ln28_reg_3858;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln42_reg_1456_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_1563_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+                phi_ln42_reg_1456 <= ap_const_lv13_0;
+            elsif (((icmp_ln42_fu_3784_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001))) then 
+                phi_ln42_reg_1456 <= add_ln42_fu_3790_p2;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                add_ln27_reg_3844 <= add_ln27_fu_1531_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                add_ln28_reg_3858 <= add_ln28_fu_1548_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state63)) then
+                add_ln38_10_reg_4817 <= add_ln38_10_fu_2783_p2;
+                mul_ln38_13_reg_4812 <= mul_ln38_13_fu_2778_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state64)) then
+                add_ln38_14_reg_4837 <= add_ln38_14_fu_2833_p2;
+                mul_ln38_15_reg_4832 <= mul_ln38_15_fu_2813_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state65)) then
+                add_ln38_15_reg_4857 <= add_ln38_15_fu_2868_p2;
+                mul_ln38_17_reg_4852 <= mul_ln38_17_fu_2863_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state66)) then
+                add_ln38_17_reg_4877 <= add_ln38_17_fu_2908_p2;
+                mul_ln38_19_reg_4872 <= mul_ln38_19_fu_2898_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state67)) then
+                add_ln38_18_reg_4897 <= add_ln38_18_fu_2943_p2;
+                mul_ln38_21_reg_4892 <= mul_ln38_21_fu_2938_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state68)) then
+                add_ln38_21_reg_4917 <= add_ln38_21_fu_2988_p2;
+                mul_ln38_23_reg_4912 <= mul_ln38_23_fu_2973_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state69)) then
+                add_ln38_22_reg_4937 <= add_ln38_22_fu_3023_p2;
+                mul_ln38_25_reg_4932 <= mul_ln38_25_fu_3018_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state70)) then
+                add_ln38_24_reg_4957 <= add_ln38_24_fu_3063_p2;
+                mul_ln38_27_reg_4952 <= mul_ln38_27_fu_3053_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state71)) then
+                add_ln38_25_reg_4977 <= add_ln38_25_fu_3098_p2;
+                mul_ln38_29_reg_4972 <= mul_ln38_29_fu_3093_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state58)) then
+                add_ln38_2_reg_4717 <= add_ln38_2_fu_2592_p2;
+                mul_ln38_3_reg_4712 <= mul_ln38_3_fu_2577_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state72)) then
+                add_ln38_30_reg_4997 <= add_ln38_30_fu_3153_p2;
+                mul_ln38_31_reg_4992 <= mul_ln38_31_fu_3128_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state73)) then
+                add_ln38_31_reg_5017 <= add_ln38_31_fu_3188_p2;
+                mul_ln38_33_reg_5012 <= mul_ln38_33_fu_3183_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state74)) then
+                add_ln38_33_reg_5037 <= add_ln38_33_fu_3228_p2;
+                mul_ln38_35_reg_5032 <= mul_ln38_35_fu_3218_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state75)) then
+                add_ln38_34_reg_5057 <= add_ln38_34_fu_3263_p2;
+                mul_ln38_37_reg_5052 <= mul_ln38_37_fu_3258_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state76)) then
+                add_ln38_37_reg_5077 <= add_ln38_37_fu_3308_p2;
+                mul_ln38_39_reg_5072 <= mul_ln38_39_fu_3293_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state77)) then
+                add_ln38_38_reg_5097 <= add_ln38_38_fu_3343_p2;
+                mul_ln38_41_reg_5092 <= mul_ln38_41_fu_3338_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state59)) then
+                add_ln38_3_reg_4737 <= add_ln38_3_fu_2628_p2;
+                mul_ln38_5_reg_4732 <= mul_ln38_5_fu_2623_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state78)) then
+                add_ln38_40_reg_5117 <= add_ln38_40_fu_3383_p2;
+                mul_ln38_43_reg_5112 <= mul_ln38_43_fu_3373_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state79)) then
+                add_ln38_41_reg_5137 <= add_ln38_41_fu_3418_p2;
+                mul_ln38_45_reg_5132 <= mul_ln38_45_fu_3413_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state80)) then
+                add_ln38_45_reg_5157 <= add_ln38_45_fu_3468_p2;
+                mul_ln38_47_reg_5152 <= mul_ln38_47_fu_3448_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state81)) then
+                add_ln38_46_reg_5177 <= add_ln38_46_fu_3503_p2;
+                mul_ln38_49_reg_5172 <= mul_ln38_49_fu_3498_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state82)) then
+                add_ln38_48_reg_5197 <= add_ln38_48_fu_3543_p2;
+                mul_ln38_51_reg_5192 <= mul_ln38_51_fu_3533_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state83)) then
+                add_ln38_49_reg_5217 <= add_ln38_49_fu_3578_p2;
+                mul_ln38_53_reg_5212 <= mul_ln38_53_fu_3573_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state84)) then
+                add_ln38_52_reg_5237 <= add_ln38_52_fu_3623_p2;
+                mul_ln38_55_reg_5232 <= mul_ln38_55_fu_3608_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state85)) then
+                add_ln38_53_reg_5257 <= add_ln38_53_fu_3658_p2;
+                mul_ln38_57_reg_5252 <= mul_ln38_57_fu_3653_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state86)) then
+                add_ln38_55_reg_5277 <= add_ln38_55_fu_3698_p2;
+                mul_ln38_59_reg_5272 <= mul_ln38_59_fu_3688_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state87)) then
+                add_ln38_56_reg_5297 <= add_ln38_56_fu_3733_p2;
+                mul_ln38_61_reg_5292 <= mul_ln38_61_fu_3728_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state88)) then
+                add_ln38_61_reg_5302 <= add_ln38_61_fu_3769_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state60)) then
+                add_ln38_6_reg_4757 <= add_ln38_6_fu_2673_p2;
+                mul_ln38_7_reg_4752 <= mul_ln38_7_fu_2658_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state61)) then
+                add_ln38_7_reg_4777 <= add_ln38_7_fu_2708_p2;
+                mul_ln38_9_reg_4772 <= mul_ln38_9_fu_2703_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state62)) then
+                add_ln38_9_reg_4797 <= add_ln38_9_fu_2748_p2;
+                mul_ln38_11_reg_4792 <= mul_ln38_11_fu_2738_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                dim_read_reg_3801 <= dim;
+                in3_reg_3817 <= in1(31 downto 2);
+                in_reg_3812 <= in2(31 downto 2);
+                out5_reg_3807 <= out_r(31 downto 2);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                i_reg_3872 <= i_fu_1568_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                icmp_ln27_reg_3840 <= icmp_ln27_fu_1525_p2;
+                icmp_ln27_reg_3840_pp0_iter1_reg <= icmp_ln27_reg_3840;
+                phi_ln27_reg_1410_pp0_iter1_reg <= phi_ln27_reg_1410;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                icmp_ln28_reg_3854 <= icmp_ln28_fu_1542_p2;
+                icmp_ln28_reg_3854_pp1_iter1_reg <= icmp_ln28_reg_3854;
+                phi_ln28_reg_1422_pp1_iter1_reg <= phi_ln28_reg_1422;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001))) then
+                icmp_ln42_reg_5307 <= icmp_ln42_fu_3784_p2;
+                icmp_ln42_reg_5307_pp2_iter1_reg <= icmp_ln42_reg_5307;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state29)) then
+                in1_loc_load_10_reg_4068 <= in1_loc_q1;
+                in1_loc_load_11_reg_4073 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state30)) then
+                in1_loc_load_12_reg_4088 <= in1_loc_q1;
+                in1_loc_load_13_reg_4093 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state31)) then
+                in1_loc_load_14_reg_4108 <= in1_loc_q1;
+                in1_loc_load_15_reg_4113 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state32)) then
+                in1_loc_load_16_reg_4128 <= in1_loc_q1;
+                in1_loc_load_17_reg_4133 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state33)) then
+                in1_loc_load_18_reg_4148 <= in1_loc_q1;
+                in1_loc_load_19_reg_4153 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state24)) then
+                in1_loc_load_1_reg_3973 <= in1_loc_q1;
+                in1_loc_load_reg_3968 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state34)) then
+                in1_loc_load_20_reg_4168 <= in1_loc_q1;
+                in1_loc_load_21_reg_4173 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state35)) then
+                in1_loc_load_22_reg_4188 <= in1_loc_q1;
+                in1_loc_load_23_reg_4193 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state36)) then
+                in1_loc_load_24_reg_4208 <= in1_loc_q1;
+                in1_loc_load_25_reg_4213 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state37)) then
+                in1_loc_load_26_reg_4228 <= in1_loc_q1;
+                in1_loc_load_27_reg_4233 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state38)) then
+                in1_loc_load_28_reg_4248 <= in1_loc_q1;
+                in1_loc_load_29_reg_4253 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state25)) then
+                in1_loc_load_2_reg_3988 <= in1_loc_q1;
+                in1_loc_load_3_reg_3993 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state39)) then
+                in1_loc_load_30_reg_4268 <= in1_loc_q1;
+                in1_loc_load_31_reg_4273 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state40)) then
+                in1_loc_load_32_reg_4288 <= in1_loc_q1;
+                in1_loc_load_33_reg_4293 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state41)) then
+                in1_loc_load_34_reg_4308 <= in1_loc_q1;
+                in1_loc_load_35_reg_4313 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state42)) then
+                in1_loc_load_36_reg_4328 <= in1_loc_q1;
+                in1_loc_load_37_reg_4333 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state43)) then
+                in1_loc_load_38_reg_4348 <= in1_loc_q1;
+                in1_loc_load_39_reg_4353 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state44)) then
+                in1_loc_load_40_reg_4368 <= in1_loc_q1;
+                in1_loc_load_41_reg_4373 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state45)) then
+                in1_loc_load_42_reg_4388 <= in1_loc_q1;
+                in1_loc_load_43_reg_4393 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state46)) then
+                in1_loc_load_44_reg_4408 <= in1_loc_q1;
+                in1_loc_load_45_reg_4413 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state47)) then
+                in1_loc_load_46_reg_4428 <= in1_loc_q1;
+                in1_loc_load_47_reg_4433 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state48)) then
+                in1_loc_load_48_reg_4448 <= in1_loc_q1;
+                in1_loc_load_49_reg_4453 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state26)) then
+                in1_loc_load_4_reg_4008 <= in1_loc_q1;
+                in1_loc_load_5_reg_4013 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state49)) then
+                in1_loc_load_50_reg_4468 <= in1_loc_q1;
+                in1_loc_load_51_reg_4473 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state50)) then
+                in1_loc_load_52_reg_4488 <= in1_loc_q1;
+                in1_loc_load_53_reg_4493 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state51)) then
+                in1_loc_load_54_reg_4508 <= in1_loc_q1;
+                in1_loc_load_55_reg_4513 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state52)) then
+                in1_loc_load_56_reg_4528 <= in1_loc_q1;
+                in1_loc_load_57_reg_4533 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state53)) then
+                in1_loc_load_58_reg_4548 <= in1_loc_q1;
+                in1_loc_load_59_reg_4553 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state54)) then
+                in1_loc_load_60_reg_4568 <= in1_loc_q1;
+                in1_loc_load_61_reg_4573 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state55)) then
+                in1_loc_load_62_reg_4583 <= in1_loc_q1;
+                in1_loc_load_63_reg_4588 <= in1_loc_q0;
+                    zext_ln38_cast_reg_4578(13 downto 6) <= zext_ln38_cast_fu_2474_p3(13 downto 6);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state27)) then
+                in1_loc_load_6_reg_4028 <= in1_loc_q1;
+                in1_loc_load_7_reg_4033 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state28)) then
+                in1_loc_load_8_reg_4048 <= in1_loc_q1;
+                in1_loc_load_9_reg_4053 <= in1_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_reg_3840 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                in1_mem_addr_read_reg_3849 <= in1_mem_RDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_reg_3854 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                in2_mem_addr_read_reg_3863 <= in2_mem_RDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
+                    in2_mem_addr_reg_3834(29 downto 0) <= empty_5_fu_1516_p1(32 - 1 downto 0)(29 downto 0);
+                    out_mem_addr_reg_3828(29 downto 0) <= empty_fu_1507_p1(32 - 1 downto 0)(29 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state56)) then
+                j_reg_4596 <= j_fu_2486_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state57)) then
+                mul_ln38_1_reg_4697 <= mul_ln38_1_fu_2547_p2;
+                mul_ln38_reg_4692 <= mul_ln38_fu_2542_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln33_fu_2481_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
+                out_loc_addr_reg_4677 <= sext_ln38_64_fu_2517_p1(12 - 1 downto 0);
+                trunc_ln38_1_reg_4601 <= trunc_ln38_1_fu_2497_p1;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln42_reg_5307 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001))) then
+                out_loc_load_reg_5321 <= out_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_1563_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                    tmp_2_reg_3877(36 downto 6) <= tmp_2_fu_1574_p3(36 downto 6);
+                trunc_ln38_reg_3943 <= trunc_ln38_fu_1587_p1;
+            end if;
+        end if;
+    end process;
+    out_mem_addr_reg_3828(31 downto 30) <= "00";
+    in2_mem_addr_reg_3834(31 downto 30) <= "00";
+    tmp_2_reg_3877(5 downto 0) <= "000000";
+    zext_ln38_cast_reg_4578(5 downto 0) <= "000000";
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_enable_reg_pp0_iter1, ap_CS_fsm_state12, ap_enable_reg_pp1_iter1, ap_CS_fsm_state23, icmp_ln31_fu_1563_p2, ap_enable_reg_pp2_iter2, ap_CS_fsm_state97, in1_mem_ARREADY, in2_mem_ARREADY, out_mem_BVALID, icmp_ln27_fu_1525_p2, ap_enable_reg_pp0_iter0, icmp_ln28_fu_1542_p2, ap_enable_reg_pp1_iter0, ap_block_state23_io, ap_CS_fsm_state56, icmp_ln33_fu_2481_p2, icmp_ln42_fu_3784_p2, ap_enable_reg_pp2_iter0, ap_enable_reg_pp2_iter1, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter2, ap_block_pp1_stage0_subdone, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0_subdone)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when ap_ST_fsm_state3 => 
+                ap_NS_fsm <= ap_ST_fsm_state4;
+            when ap_ST_fsm_state4 => 
+                ap_NS_fsm <= ap_ST_fsm_state5;
+            when ap_ST_fsm_state5 => 
+                ap_NS_fsm <= ap_ST_fsm_state6;
+            when ap_ST_fsm_state6 => 
+                ap_NS_fsm <= ap_ST_fsm_state7;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state8;
+            when ap_ST_fsm_state8 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((icmp_ln27_fu_1525_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) and not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((icmp_ln27_fu_1525_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state12 => 
+                if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then
+                    ap_NS_fsm <= ap_ST_fsm_state13;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                end if;
+            when ap_ST_fsm_state13 => 
+                ap_NS_fsm <= ap_ST_fsm_state14;
+            when ap_ST_fsm_state14 => 
+                ap_NS_fsm <= ap_ST_fsm_state15;
+            when ap_ST_fsm_state15 => 
+                ap_NS_fsm <= ap_ST_fsm_state16;
+            when ap_ST_fsm_state16 => 
+                ap_NS_fsm <= ap_ST_fsm_state17;
+            when ap_ST_fsm_state17 => 
+                ap_NS_fsm <= ap_ST_fsm_state18;
+            when ap_ST_fsm_state18 => 
+                ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+            when ap_ST_fsm_pp1_stage0 => 
+                if ((not(((icmp_ln28_fu_1542_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) and not(((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                elsif ((((icmp_ln28_fu_1542_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) or ((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state22;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                end if;
+            when ap_ST_fsm_state22 => 
+                ap_NS_fsm <= ap_ST_fsm_state23;
+            when ap_ST_fsm_state23 => 
+                if (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_1563_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                elsif (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_1563_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                    ap_NS_fsm <= ap_ST_fsm_state24;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state23;
+                end if;
+            when ap_ST_fsm_state24 => 
+                ap_NS_fsm <= ap_ST_fsm_state25;
+            when ap_ST_fsm_state25 => 
+                ap_NS_fsm <= ap_ST_fsm_state26;
+            when ap_ST_fsm_state26 => 
+                ap_NS_fsm <= ap_ST_fsm_state27;
+            when ap_ST_fsm_state27 => 
+                ap_NS_fsm <= ap_ST_fsm_state28;
+            when ap_ST_fsm_state28 => 
+                ap_NS_fsm <= ap_ST_fsm_state29;
+            when ap_ST_fsm_state29 => 
+                ap_NS_fsm <= ap_ST_fsm_state30;
+            when ap_ST_fsm_state30 => 
+                ap_NS_fsm <= ap_ST_fsm_state31;
+            when ap_ST_fsm_state31 => 
+                ap_NS_fsm <= ap_ST_fsm_state32;
+            when ap_ST_fsm_state32 => 
+                ap_NS_fsm <= ap_ST_fsm_state33;
+            when ap_ST_fsm_state33 => 
+                ap_NS_fsm <= ap_ST_fsm_state34;
+            when ap_ST_fsm_state34 => 
+                ap_NS_fsm <= ap_ST_fsm_state35;
+            when ap_ST_fsm_state35 => 
+                ap_NS_fsm <= ap_ST_fsm_state36;
+            when ap_ST_fsm_state36 => 
+                ap_NS_fsm <= ap_ST_fsm_state37;
+            when ap_ST_fsm_state37 => 
+                ap_NS_fsm <= ap_ST_fsm_state38;
+            when ap_ST_fsm_state38 => 
+                ap_NS_fsm <= ap_ST_fsm_state39;
+            when ap_ST_fsm_state39 => 
+                ap_NS_fsm <= ap_ST_fsm_state40;
+            when ap_ST_fsm_state40 => 
+                ap_NS_fsm <= ap_ST_fsm_state41;
+            when ap_ST_fsm_state41 => 
+                ap_NS_fsm <= ap_ST_fsm_state42;
+            when ap_ST_fsm_state42 => 
+                ap_NS_fsm <= ap_ST_fsm_state43;
+            when ap_ST_fsm_state43 => 
+                ap_NS_fsm <= ap_ST_fsm_state44;
+            when ap_ST_fsm_state44 => 
+                ap_NS_fsm <= ap_ST_fsm_state45;
+            when ap_ST_fsm_state45 => 
+                ap_NS_fsm <= ap_ST_fsm_state46;
+            when ap_ST_fsm_state46 => 
+                ap_NS_fsm <= ap_ST_fsm_state47;
+            when ap_ST_fsm_state47 => 
+                ap_NS_fsm <= ap_ST_fsm_state48;
+            when ap_ST_fsm_state48 => 
+                ap_NS_fsm <= ap_ST_fsm_state49;
+            when ap_ST_fsm_state49 => 
+                ap_NS_fsm <= ap_ST_fsm_state50;
+            when ap_ST_fsm_state50 => 
+                ap_NS_fsm <= ap_ST_fsm_state51;
+            when ap_ST_fsm_state51 => 
+                ap_NS_fsm <= ap_ST_fsm_state52;
+            when ap_ST_fsm_state52 => 
+                ap_NS_fsm <= ap_ST_fsm_state53;
+            when ap_ST_fsm_state53 => 
+                ap_NS_fsm <= ap_ST_fsm_state54;
+            when ap_ST_fsm_state54 => 
+                ap_NS_fsm <= ap_ST_fsm_state55;
+            when ap_ST_fsm_state55 => 
+                ap_NS_fsm <= ap_ST_fsm_state56;
+            when ap_ST_fsm_state56 => 
+                if (((icmp_ln33_fu_2481_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state56))) then
+                    ap_NS_fsm <= ap_ST_fsm_state23;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state57;
+                end if;
+            when ap_ST_fsm_state57 => 
+                ap_NS_fsm <= ap_ST_fsm_state58;
+            when ap_ST_fsm_state58 => 
+                ap_NS_fsm <= ap_ST_fsm_state59;
+            when ap_ST_fsm_state59 => 
+                ap_NS_fsm <= ap_ST_fsm_state60;
+            when ap_ST_fsm_state60 => 
+                ap_NS_fsm <= ap_ST_fsm_state61;
+            when ap_ST_fsm_state61 => 
+                ap_NS_fsm <= ap_ST_fsm_state62;
+            when ap_ST_fsm_state62 => 
+                ap_NS_fsm <= ap_ST_fsm_state63;
+            when ap_ST_fsm_state63 => 
+                ap_NS_fsm <= ap_ST_fsm_state64;
+            when ap_ST_fsm_state64 => 
+                ap_NS_fsm <= ap_ST_fsm_state65;
+            when ap_ST_fsm_state65 => 
+                ap_NS_fsm <= ap_ST_fsm_state66;
+            when ap_ST_fsm_state66 => 
+                ap_NS_fsm <= ap_ST_fsm_state67;
+            when ap_ST_fsm_state67 => 
+                ap_NS_fsm <= ap_ST_fsm_state68;
+            when ap_ST_fsm_state68 => 
+                ap_NS_fsm <= ap_ST_fsm_state69;
+            when ap_ST_fsm_state69 => 
+                ap_NS_fsm <= ap_ST_fsm_state70;
+            when ap_ST_fsm_state70 => 
+                ap_NS_fsm <= ap_ST_fsm_state71;
+            when ap_ST_fsm_state71 => 
+                ap_NS_fsm <= ap_ST_fsm_state72;
+            when ap_ST_fsm_state72 => 
+                ap_NS_fsm <= ap_ST_fsm_state73;
+            when ap_ST_fsm_state73 => 
+                ap_NS_fsm <= ap_ST_fsm_state74;
+            when ap_ST_fsm_state74 => 
+                ap_NS_fsm <= ap_ST_fsm_state75;
+            when ap_ST_fsm_state75 => 
+                ap_NS_fsm <= ap_ST_fsm_state76;
+            when ap_ST_fsm_state76 => 
+                ap_NS_fsm <= ap_ST_fsm_state77;
+            when ap_ST_fsm_state77 => 
+                ap_NS_fsm <= ap_ST_fsm_state78;
+            when ap_ST_fsm_state78 => 
+                ap_NS_fsm <= ap_ST_fsm_state79;
+            when ap_ST_fsm_state79 => 
+                ap_NS_fsm <= ap_ST_fsm_state80;
+            when ap_ST_fsm_state80 => 
+                ap_NS_fsm <= ap_ST_fsm_state81;
+            when ap_ST_fsm_state81 => 
+                ap_NS_fsm <= ap_ST_fsm_state82;
+            when ap_ST_fsm_state82 => 
+                ap_NS_fsm <= ap_ST_fsm_state83;
+            when ap_ST_fsm_state83 => 
+                ap_NS_fsm <= ap_ST_fsm_state84;
+            when ap_ST_fsm_state84 => 
+                ap_NS_fsm <= ap_ST_fsm_state85;
+            when ap_ST_fsm_state85 => 
+                ap_NS_fsm <= ap_ST_fsm_state86;
+            when ap_ST_fsm_state86 => 
+                ap_NS_fsm <= ap_ST_fsm_state87;
+            when ap_ST_fsm_state87 => 
+                ap_NS_fsm <= ap_ST_fsm_state88;
+            when ap_ST_fsm_state88 => 
+                ap_NS_fsm <= ap_ST_fsm_state89;
+            when ap_ST_fsm_state89 => 
+                ap_NS_fsm <= ap_ST_fsm_state56;
+            when ap_ST_fsm_pp2_stage0 => 
+                if ((not(((icmp_ln42_fu_3784_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))) and not(((ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                elsif ((((ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0)) or ((icmp_ln42_fu_3784_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state93;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                end if;
+            when ap_ST_fsm_state93 => 
+                ap_NS_fsm <= ap_ST_fsm_state94;
+            when ap_ST_fsm_state94 => 
+                ap_NS_fsm <= ap_ST_fsm_state95;
+            when ap_ST_fsm_state95 => 
+                ap_NS_fsm <= ap_ST_fsm_state96;
+            when ap_ST_fsm_state96 => 
+                ap_NS_fsm <= ap_ST_fsm_state97;
+            when ap_ST_fsm_state97 => 
+                if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state97))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state97;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+        end case;
+    end process;
+    add_ln27_fu_1531_p2 <= std_logic_vector(unsigned(ap_phi_mux_phi_ln27_phi_fu_1414_p4) + unsigned(ap_const_lv13_1));
+    add_ln28_fu_1548_p2 <= std_logic_vector(unsigned(ap_phi_mux_phi_ln28_phi_fu_1426_p4) + unsigned(ap_const_lv13_1));
+    add_ln38_100_fu_3203_p2 <= std_logic_vector(unsigned(ap_const_lv14_940) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_101_fu_3233_p2 <= std_logic_vector(unsigned(ap_const_lv14_980) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_102_fu_3243_p2 <= std_logic_vector(unsigned(ap_const_lv14_9C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_103_fu_3268_p2 <= std_logic_vector(unsigned(ap_const_lv14_A00) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_104_fu_3278_p2 <= std_logic_vector(unsigned(ap_const_lv14_A40) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_105_fu_3313_p2 <= std_logic_vector(unsigned(ap_const_lv14_A80) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_106_fu_3323_p2 <= std_logic_vector(unsigned(ap_const_lv14_AC0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_107_fu_3348_p2 <= std_logic_vector(unsigned(ap_const_lv14_B00) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_108_fu_3358_p2 <= std_logic_vector(unsigned(ap_const_lv14_B40) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_109_fu_3388_p2 <= std_logic_vector(unsigned(ap_const_lv14_B80) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_10_fu_2783_p2 <= std_logic_vector(unsigned(mul_ln38_12_fu_2773_p2) + unsigned(mul_ln38_11_reg_4792));
+    add_ln38_110_fu_3398_p2 <= std_logic_vector(unsigned(ap_const_lv14_BC0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_111_fu_3423_p2 <= std_logic_vector(unsigned(ap_const_lv14_C00) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_112_fu_3433_p2 <= std_logic_vector(unsigned(ap_const_lv14_C40) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_113_fu_3473_p2 <= std_logic_vector(unsigned(ap_const_lv14_C80) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_114_fu_3483_p2 <= std_logic_vector(unsigned(ap_const_lv14_CC0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_115_fu_3508_p2 <= std_logic_vector(unsigned(ap_const_lv14_D00) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_116_fu_3518_p2 <= std_logic_vector(unsigned(ap_const_lv14_D40) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_117_fu_3548_p2 <= std_logic_vector(unsigned(ap_const_lv14_D80) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_118_fu_3558_p2 <= std_logic_vector(unsigned(ap_const_lv14_DC0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_119_fu_3583_p2 <= std_logic_vector(unsigned(ap_const_lv14_E00) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_11_fu_2818_p2 <= std_logic_vector(unsigned(mul_ln38_14_fu_2808_p2) + unsigned(mul_ln38_13_reg_4812));
+    add_ln38_120_fu_3593_p2 <= std_logic_vector(unsigned(ap_const_lv14_E40) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_121_fu_3628_p2 <= std_logic_vector(unsigned(ap_const_lv14_E80) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_122_fu_3638_p2 <= std_logic_vector(unsigned(ap_const_lv14_EC0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_123_fu_3663_p2 <= std_logic_vector(unsigned(ap_const_lv14_F00) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_124_fu_3673_p2 <= std_logic_vector(unsigned(ap_const_lv14_F40) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_125_fu_3703_p2 <= std_logic_vector(unsigned(ap_const_lv14_F80) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_126_fu_3713_p2 <= std_logic_vector(unsigned(ap_const_lv14_FC0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_127_fu_2512_p2 <= std_logic_vector(unsigned(zext_ln38_cast_reg_4578) + unsigned(trunc_ln38_1_fu_2497_p1));
+    add_ln38_12_fu_2823_p2 <= std_logic_vector(unsigned(add_ln38_10_reg_4817) + unsigned(add_ln38_11_fu_2818_p2));
+    add_ln38_13_fu_2828_p2 <= std_logic_vector(unsigned(add_ln38_9_reg_4797) + unsigned(add_ln38_12_fu_2823_p2));
+    add_ln38_14_fu_2833_p2 <= std_logic_vector(unsigned(add_ln38_6_reg_4757) + unsigned(add_ln38_13_fu_2828_p2));
+    add_ln38_15_fu_2868_p2 <= std_logic_vector(unsigned(mul_ln38_16_fu_2858_p2) + unsigned(mul_ln38_15_reg_4832));
+    add_ln38_16_fu_2903_p2 <= std_logic_vector(unsigned(mul_ln38_18_fu_2893_p2) + unsigned(mul_ln38_17_reg_4852));
+    add_ln38_17_fu_2908_p2 <= std_logic_vector(unsigned(add_ln38_15_reg_4857) + unsigned(add_ln38_16_fu_2903_p2));
+    add_ln38_18_fu_2943_p2 <= std_logic_vector(unsigned(mul_ln38_20_fu_2933_p2) + unsigned(mul_ln38_19_reg_4872));
+    add_ln38_19_fu_2978_p2 <= std_logic_vector(unsigned(mul_ln38_22_fu_2968_p2) + unsigned(mul_ln38_21_reg_4892));
+    add_ln38_1_fu_2587_p2 <= std_logic_vector(unsigned(mul_ln38_2_fu_2572_p2) + unsigned(mul_ln38_1_reg_4697));
+    add_ln38_20_fu_2983_p2 <= std_logic_vector(unsigned(add_ln38_18_reg_4897) + unsigned(add_ln38_19_fu_2978_p2));
+    add_ln38_21_fu_2988_p2 <= std_logic_vector(unsigned(add_ln38_17_reg_4877) + unsigned(add_ln38_20_fu_2983_p2));
+    add_ln38_22_fu_3023_p2 <= std_logic_vector(unsigned(mul_ln38_24_fu_3013_p2) + unsigned(mul_ln38_23_reg_4912));
+    add_ln38_23_fu_3058_p2 <= std_logic_vector(unsigned(mul_ln38_26_fu_3048_p2) + unsigned(mul_ln38_25_reg_4932));
+    add_ln38_24_fu_3063_p2 <= std_logic_vector(unsigned(add_ln38_22_reg_4937) + unsigned(add_ln38_23_fu_3058_p2));
+    add_ln38_25_fu_3098_p2 <= std_logic_vector(unsigned(mul_ln38_28_fu_3088_p2) + unsigned(mul_ln38_27_reg_4952));
+    add_ln38_26_fu_3133_p2 <= std_logic_vector(unsigned(mul_ln38_30_fu_3123_p2) + unsigned(mul_ln38_29_reg_4972));
+    add_ln38_27_fu_3138_p2 <= std_logic_vector(unsigned(add_ln38_25_reg_4977) + unsigned(add_ln38_26_fu_3133_p2));
+    add_ln38_28_fu_3143_p2 <= std_logic_vector(unsigned(add_ln38_24_reg_4957) + unsigned(add_ln38_27_fu_3138_p2));
+    add_ln38_29_fu_3148_p2 <= std_logic_vector(unsigned(add_ln38_21_reg_4917) + unsigned(add_ln38_28_fu_3143_p2));
+    add_ln38_2_fu_2592_p2 <= std_logic_vector(unsigned(add_ln38_fu_2582_p2) + unsigned(add_ln38_1_fu_2587_p2));
+    add_ln38_30_fu_3153_p2 <= std_logic_vector(unsigned(add_ln38_14_reg_4837) + unsigned(add_ln38_29_fu_3148_p2));
+    add_ln38_31_fu_3188_p2 <= std_logic_vector(unsigned(mul_ln38_32_fu_3178_p2) + unsigned(mul_ln38_31_reg_4992));
+    add_ln38_32_fu_3223_p2 <= std_logic_vector(unsigned(mul_ln38_34_fu_3213_p2) + unsigned(mul_ln38_33_reg_5012));
+    add_ln38_33_fu_3228_p2 <= std_logic_vector(unsigned(add_ln38_31_reg_5017) + unsigned(add_ln38_32_fu_3223_p2));
+    add_ln38_34_fu_3263_p2 <= std_logic_vector(unsigned(mul_ln38_36_fu_3253_p2) + unsigned(mul_ln38_35_reg_5032));
+    add_ln38_35_fu_3298_p2 <= std_logic_vector(unsigned(mul_ln38_38_fu_3288_p2) + unsigned(mul_ln38_37_reg_5052));
+    add_ln38_36_fu_3303_p2 <= std_logic_vector(unsigned(add_ln38_34_reg_5057) + unsigned(add_ln38_35_fu_3298_p2));
+    add_ln38_37_fu_3308_p2 <= std_logic_vector(unsigned(add_ln38_33_reg_5037) + unsigned(add_ln38_36_fu_3303_p2));
+    add_ln38_38_fu_3343_p2 <= std_logic_vector(unsigned(mul_ln38_40_fu_3333_p2) + unsigned(mul_ln38_39_reg_5072));
+    add_ln38_39_fu_3378_p2 <= std_logic_vector(unsigned(mul_ln38_42_fu_3368_p2) + unsigned(mul_ln38_41_reg_5092));
+    add_ln38_3_fu_2628_p2 <= std_logic_vector(unsigned(mul_ln38_4_fu_2618_p2) + unsigned(mul_ln38_3_reg_4712));
+    add_ln38_40_fu_3383_p2 <= std_logic_vector(unsigned(add_ln38_38_reg_5097) + unsigned(add_ln38_39_fu_3378_p2));
+    add_ln38_41_fu_3418_p2 <= std_logic_vector(unsigned(mul_ln38_44_fu_3408_p2) + unsigned(mul_ln38_43_reg_5112));
+    add_ln38_42_fu_3453_p2 <= std_logic_vector(unsigned(mul_ln38_46_fu_3443_p2) + unsigned(mul_ln38_45_reg_5132));
+    add_ln38_43_fu_3458_p2 <= std_logic_vector(unsigned(add_ln38_41_reg_5137) + unsigned(add_ln38_42_fu_3453_p2));
+    add_ln38_44_fu_3463_p2 <= std_logic_vector(unsigned(add_ln38_40_reg_5117) + unsigned(add_ln38_43_fu_3458_p2));
+    add_ln38_45_fu_3468_p2 <= std_logic_vector(unsigned(add_ln38_37_reg_5077) + unsigned(add_ln38_44_fu_3463_p2));
+    add_ln38_46_fu_3503_p2 <= std_logic_vector(unsigned(mul_ln38_48_fu_3493_p2) + unsigned(mul_ln38_47_reg_5152));
+    add_ln38_47_fu_3538_p2 <= std_logic_vector(unsigned(mul_ln38_50_fu_3528_p2) + unsigned(mul_ln38_49_reg_5172));
+    add_ln38_48_fu_3543_p2 <= std_logic_vector(unsigned(add_ln38_46_reg_5177) + unsigned(add_ln38_47_fu_3538_p2));
+    add_ln38_49_fu_3578_p2 <= std_logic_vector(unsigned(mul_ln38_52_fu_3568_p2) + unsigned(mul_ln38_51_reg_5192));
+    add_ln38_4_fu_2663_p2 <= std_logic_vector(unsigned(mul_ln38_6_fu_2653_p2) + unsigned(mul_ln38_5_reg_4732));
+    add_ln38_50_fu_3613_p2 <= std_logic_vector(unsigned(mul_ln38_54_fu_3603_p2) + unsigned(mul_ln38_53_reg_5212));
+    add_ln38_51_fu_3618_p2 <= std_logic_vector(unsigned(add_ln38_49_reg_5217) + unsigned(add_ln38_50_fu_3613_p2));
+    add_ln38_52_fu_3623_p2 <= std_logic_vector(unsigned(add_ln38_48_reg_5197) + unsigned(add_ln38_51_fu_3618_p2));
+    add_ln38_53_fu_3658_p2 <= std_logic_vector(unsigned(mul_ln38_56_fu_3648_p2) + unsigned(mul_ln38_55_reg_5232));
+    add_ln38_54_fu_3693_p2 <= std_logic_vector(unsigned(mul_ln38_58_fu_3683_p2) + unsigned(mul_ln38_57_reg_5252));
+    add_ln38_55_fu_3698_p2 <= std_logic_vector(unsigned(add_ln38_53_reg_5257) + unsigned(add_ln38_54_fu_3693_p2));
+    add_ln38_56_fu_3733_p2 <= std_logic_vector(unsigned(mul_ln38_60_fu_3723_p2) + unsigned(mul_ln38_59_reg_5272));
+    add_ln38_57_fu_3748_p2 <= std_logic_vector(unsigned(mul_ln38_63_fu_3743_p2) + unsigned(mul_ln38_62_fu_3738_p2));
+    add_ln38_58_fu_3754_p2 <= std_logic_vector(unsigned(mul_ln38_61_reg_5292) + unsigned(add_ln38_57_fu_3748_p2));
+    add_ln38_59_fu_3759_p2 <= std_logic_vector(unsigned(add_ln38_56_reg_5297) + unsigned(add_ln38_58_fu_3754_p2));
+    add_ln38_5_fu_2668_p2 <= std_logic_vector(unsigned(add_ln38_3_reg_4737) + unsigned(add_ln38_4_fu_2663_p2));
+    add_ln38_60_fu_3764_p2 <= std_logic_vector(unsigned(add_ln38_55_reg_5277) + unsigned(add_ln38_59_fu_3759_p2));
+    add_ln38_61_fu_3769_p2 <= std_logic_vector(unsigned(add_ln38_52_reg_5237) + unsigned(add_ln38_60_fu_3764_p2));
+    add_ln38_62_fu_3774_p2 <= std_logic_vector(unsigned(add_ln38_45_reg_5157) + unsigned(add_ln38_61_reg_5302));
+    add_ln38_64_fu_2501_p2 <= std_logic_vector(unsigned(ap_const_lv14_40) + unsigned(trunc_ln38_1_fu_2497_p1));
+    add_ln38_65_fu_2522_p2 <= std_logic_vector(unsigned(ap_const_lv14_80) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_66_fu_2532_p2 <= std_logic_vector(unsigned(ap_const_lv14_C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_67_fu_2552_p2 <= std_logic_vector(unsigned(ap_const_lv14_100) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_68_fu_2562_p2 <= std_logic_vector(unsigned(ap_const_lv14_140) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_69_fu_2598_p2 <= std_logic_vector(unsigned(ap_const_lv14_180) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_6_fu_2673_p2 <= std_logic_vector(unsigned(add_ln38_2_reg_4717) + unsigned(add_ln38_5_fu_2668_p2));
+    add_ln38_70_fu_2608_p2 <= std_logic_vector(unsigned(ap_const_lv14_1C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_71_fu_2633_p2 <= std_logic_vector(unsigned(ap_const_lv14_200) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_72_fu_2643_p2 <= std_logic_vector(unsigned(ap_const_lv14_240) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_73_fu_2678_p2 <= std_logic_vector(unsigned(ap_const_lv14_280) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_74_fu_2688_p2 <= std_logic_vector(unsigned(ap_const_lv14_2C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_75_fu_2713_p2 <= std_logic_vector(unsigned(ap_const_lv14_300) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_76_fu_2723_p2 <= std_logic_vector(unsigned(ap_const_lv14_340) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_77_fu_2753_p2 <= std_logic_vector(unsigned(ap_const_lv14_380) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_78_fu_2763_p2 <= std_logic_vector(unsigned(ap_const_lv14_3C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_79_fu_2788_p2 <= std_logic_vector(unsigned(ap_const_lv14_400) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_7_fu_2708_p2 <= std_logic_vector(unsigned(mul_ln38_8_fu_2698_p2) + unsigned(mul_ln38_7_reg_4752));
+    add_ln38_80_fu_2798_p2 <= std_logic_vector(unsigned(ap_const_lv14_440) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_81_fu_2838_p2 <= std_logic_vector(unsigned(ap_const_lv14_480) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_82_fu_2848_p2 <= std_logic_vector(unsigned(ap_const_lv14_4C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_83_fu_2873_p2 <= std_logic_vector(unsigned(ap_const_lv14_500) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_84_fu_2883_p2 <= std_logic_vector(unsigned(ap_const_lv14_540) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_85_fu_2913_p2 <= std_logic_vector(unsigned(ap_const_lv14_580) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_86_fu_2923_p2 <= std_logic_vector(unsigned(ap_const_lv14_5C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_87_fu_2948_p2 <= std_logic_vector(unsigned(ap_const_lv14_600) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_88_fu_2958_p2 <= std_logic_vector(unsigned(ap_const_lv14_640) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_89_fu_2993_p2 <= std_logic_vector(unsigned(ap_const_lv14_680) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_8_fu_2743_p2 <= std_logic_vector(unsigned(mul_ln38_10_fu_2733_p2) + unsigned(mul_ln38_9_reg_4772));
+    add_ln38_90_fu_3003_p2 <= std_logic_vector(unsigned(ap_const_lv14_6C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_91_fu_3028_p2 <= std_logic_vector(unsigned(ap_const_lv14_700) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_92_fu_3038_p2 <= std_logic_vector(unsigned(ap_const_lv14_740) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_93_fu_3068_p2 <= std_logic_vector(unsigned(ap_const_lv14_780) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_94_fu_3078_p2 <= std_logic_vector(unsigned(ap_const_lv14_7C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_95_fu_3103_p2 <= std_logic_vector(unsigned(ap_const_lv14_800) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_96_fu_3113_p2 <= std_logic_vector(unsigned(ap_const_lv14_840) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_97_fu_3158_p2 <= std_logic_vector(unsigned(ap_const_lv14_880) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_98_fu_3168_p2 <= std_logic_vector(unsigned(ap_const_lv14_8C0) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_99_fu_3193_p2 <= std_logic_vector(unsigned(ap_const_lv14_900) + unsigned(trunc_ln38_1_reg_4601));
+    add_ln38_9_fu_2748_p2 <= std_logic_vector(unsigned(add_ln38_7_reg_4777) + unsigned(add_ln38_8_fu_2743_p2));
+    add_ln38_fu_2582_p2 <= std_logic_vector(unsigned(mul_ln38_reg_4692) + unsigned(out_loc_q0));
+    add_ln42_fu_3790_p2 <= std_logic_vector(unsigned(phi_ln42_reg_1456) + unsigned(ap_const_lv13_1));
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(8);
+    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(16);
+    ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(85);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state12 <= ap_CS_fsm(9);
+    ap_CS_fsm_state18 <= ap_CS_fsm(15);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state22 <= ap_CS_fsm(17);
+    ap_CS_fsm_state23 <= ap_CS_fsm(18);
+    ap_CS_fsm_state24 <= ap_CS_fsm(19);
+    ap_CS_fsm_state25 <= ap_CS_fsm(20);
+    ap_CS_fsm_state26 <= ap_CS_fsm(21);
+    ap_CS_fsm_state27 <= ap_CS_fsm(22);
+    ap_CS_fsm_state28 <= ap_CS_fsm(23);
+    ap_CS_fsm_state29 <= ap_CS_fsm(24);
+    ap_CS_fsm_state30 <= ap_CS_fsm(25);
+    ap_CS_fsm_state31 <= ap_CS_fsm(26);
+    ap_CS_fsm_state32 <= ap_CS_fsm(27);
+    ap_CS_fsm_state33 <= ap_CS_fsm(28);
+    ap_CS_fsm_state34 <= ap_CS_fsm(29);
+    ap_CS_fsm_state35 <= ap_CS_fsm(30);
+    ap_CS_fsm_state36 <= ap_CS_fsm(31);
+    ap_CS_fsm_state37 <= ap_CS_fsm(32);
+    ap_CS_fsm_state38 <= ap_CS_fsm(33);
+    ap_CS_fsm_state39 <= ap_CS_fsm(34);
+    ap_CS_fsm_state40 <= ap_CS_fsm(35);
+    ap_CS_fsm_state41 <= ap_CS_fsm(36);
+    ap_CS_fsm_state42 <= ap_CS_fsm(37);
+    ap_CS_fsm_state43 <= ap_CS_fsm(38);
+    ap_CS_fsm_state44 <= ap_CS_fsm(39);
+    ap_CS_fsm_state45 <= ap_CS_fsm(40);
+    ap_CS_fsm_state46 <= ap_CS_fsm(41);
+    ap_CS_fsm_state47 <= ap_CS_fsm(42);
+    ap_CS_fsm_state48 <= ap_CS_fsm(43);
+    ap_CS_fsm_state49 <= ap_CS_fsm(44);
+    ap_CS_fsm_state50 <= ap_CS_fsm(45);
+    ap_CS_fsm_state51 <= ap_CS_fsm(46);
+    ap_CS_fsm_state52 <= ap_CS_fsm(47);
+    ap_CS_fsm_state53 <= ap_CS_fsm(48);
+    ap_CS_fsm_state54 <= ap_CS_fsm(49);
+    ap_CS_fsm_state55 <= ap_CS_fsm(50);
+    ap_CS_fsm_state56 <= ap_CS_fsm(51);
+    ap_CS_fsm_state57 <= ap_CS_fsm(52);
+    ap_CS_fsm_state58 <= ap_CS_fsm(53);
+    ap_CS_fsm_state59 <= ap_CS_fsm(54);
+    ap_CS_fsm_state60 <= ap_CS_fsm(55);
+    ap_CS_fsm_state61 <= ap_CS_fsm(56);
+    ap_CS_fsm_state62 <= ap_CS_fsm(57);
+    ap_CS_fsm_state63 <= ap_CS_fsm(58);
+    ap_CS_fsm_state64 <= ap_CS_fsm(59);
+    ap_CS_fsm_state65 <= ap_CS_fsm(60);
+    ap_CS_fsm_state66 <= ap_CS_fsm(61);
+    ap_CS_fsm_state67 <= ap_CS_fsm(62);
+    ap_CS_fsm_state68 <= ap_CS_fsm(63);
+    ap_CS_fsm_state69 <= ap_CS_fsm(64);
+    ap_CS_fsm_state70 <= ap_CS_fsm(65);
+    ap_CS_fsm_state71 <= ap_CS_fsm(66);
+    ap_CS_fsm_state72 <= ap_CS_fsm(67);
+    ap_CS_fsm_state73 <= ap_CS_fsm(68);
+    ap_CS_fsm_state74 <= ap_CS_fsm(69);
+    ap_CS_fsm_state75 <= ap_CS_fsm(70);
+    ap_CS_fsm_state76 <= ap_CS_fsm(71);
+    ap_CS_fsm_state77 <= ap_CS_fsm(72);
+    ap_CS_fsm_state78 <= ap_CS_fsm(73);
+    ap_CS_fsm_state79 <= ap_CS_fsm(74);
+    ap_CS_fsm_state8 <= ap_CS_fsm(7);
+    ap_CS_fsm_state80 <= ap_CS_fsm(75);
+    ap_CS_fsm_state81 <= ap_CS_fsm(76);
+    ap_CS_fsm_state82 <= ap_CS_fsm(77);
+    ap_CS_fsm_state83 <= ap_CS_fsm(78);
+    ap_CS_fsm_state84 <= ap_CS_fsm(79);
+    ap_CS_fsm_state85 <= ap_CS_fsm(80);
+    ap_CS_fsm_state86 <= ap_CS_fsm(81);
+    ap_CS_fsm_state87 <= ap_CS_fsm(82);
+    ap_CS_fsm_state88 <= ap_CS_fsm(83);
+    ap_CS_fsm_state89 <= ap_CS_fsm(84);
+    ap_CS_fsm_state97 <= ap_CS_fsm(90);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_11001_assign_proc : process(ap_enable_reg_pp0_iter1, icmp_ln27_reg_3840, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_11001 <= ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln27_reg_3840 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(ap_enable_reg_pp0_iter1, icmp_ln27_reg_3840, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_subdone <= ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln27_reg_3840 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp1_stage0_11001_assign_proc : process(ap_enable_reg_pp1_iter1, icmp_ln28_reg_3854, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_11001 <= ((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln28_reg_3854 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp1_stage0_subdone_assign_proc : process(ap_enable_reg_pp1_iter1, icmp_ln28_reg_3854, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_subdone <= ((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln28_reg_3854 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp2_stage0_01001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp2_stage0_11001_assign_proc : process(ap_enable_reg_pp2_iter2, ap_block_state92_io)
+    begin
+                ap_block_pp2_stage0_11001 <= ((ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_const_boolean_1 = ap_block_state92_io));
+    end process;
+
+
+    ap_block_pp2_stage0_subdone_assign_proc : process(ap_enable_reg_pp2_iter2, ap_block_state92_io)
+    begin
+                ap_block_pp2_stage0_subdone <= ((ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_const_boolean_1 = ap_block_state92_io));
+    end process;
+
+
+    ap_block_state10_pp0_stage0_iter1_assign_proc : process(icmp_ln27_reg_3840, in1_mem_RVALID)
+    begin
+                ap_block_state10_pp0_stage0_iter1 <= ((in1_mem_RVALID = ap_const_logic_0) and (icmp_ln27_reg_3840 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state11_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state19_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state20_pp1_stage0_iter1_assign_proc : process(icmp_ln28_reg_3854, in2_mem_RVALID)
+    begin
+                ap_block_state20_pp1_stage0_iter1 <= ((in2_mem_RVALID = ap_const_logic_0) and (icmp_ln28_reg_3854 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state21_pp1_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state23_io_assign_proc : process(icmp_ln31_fu_1563_p2, out_mem_AWREADY)
+    begin
+                ap_block_state23_io <= ((out_mem_AWREADY = ap_const_logic_0) and (icmp_ln31_fu_1563_p2 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state90_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state91_pp2_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state92_io_assign_proc : process(icmp_ln42_reg_5307_pp2_iter1_reg, out_mem_WREADY)
+    begin
+                ap_block_state92_io <= ((out_mem_WREADY = ap_const_logic_0) and (icmp_ln42_reg_5307_pp2_iter1_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state92_pp2_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state9_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state9_assign_proc : process(icmp_ln27_fu_1525_p2)
+    begin
+        if ((icmp_ln27_fu_1525_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp1_exit_iter0_state19_assign_proc : process(icmp_ln28_fu_1542_p2)
+    begin
+        if ((icmp_ln28_fu_1542_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_1;
+        else 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp2_exit_iter0_state90_assign_proc : process(icmp_ln42_fu_3784_p2)
+    begin
+        if ((icmp_ln42_fu_3784_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp2_exit_iter0_state90 <= ap_const_logic_1;
+        else 
+            ap_condition_pp2_exit_iter0_state90 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_CS_fsm_state97, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state97))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
+    ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp1 <= ap_const_logic_1;
+        else 
+            ap_idle_pp1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter2, ap_enable_reg_pp2_iter0, ap_enable_reg_pp2_iter1)
+    begin
+        if (((ap_enable_reg_pp2_iter2 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0))) then 
+            ap_idle_pp2 <= ap_const_logic_1;
+        else 
+            ap_idle_pp2 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_phi_ln27_phi_fu_1414_p4_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, icmp_ln27_reg_3840, phi_ln27_reg_1410, add_ln27_reg_3844)
+    begin
+        if (((icmp_ln27_reg_3840 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            ap_phi_mux_phi_ln27_phi_fu_1414_p4 <= add_ln27_reg_3844;
+        else 
+            ap_phi_mux_phi_ln27_phi_fu_1414_p4 <= phi_ln27_reg_1410;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_phi_ln28_phi_fu_1426_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, icmp_ln28_reg_3854, phi_ln28_reg_1422, add_ln28_reg_3858)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (icmp_ln28_reg_3854 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            ap_phi_mux_phi_ln28_phi_fu_1426_p4 <= add_ln28_reg_3858;
+        else 
+            ap_phi_mux_phi_ln28_phi_fu_1426_p4 <= phi_ln28_reg_1422;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state97, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state97))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    empty_5_fu_1516_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in_reg_3812),64));
+    empty_6_fu_1497_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in3_reg_3817),64));
+    empty_fu_1507_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(out5_reg_3807),64));
+    i_fu_1568_p2 <= std_logic_vector(unsigned(i_0_reg_1434) + unsigned(ap_const_lv31_1));
+    icmp_ln27_fu_1525_p2 <= "1" when (ap_phi_mux_phi_ln27_phi_fu_1414_p4 = ap_const_lv13_1000) else "0";
+    icmp_ln28_fu_1542_p2 <= "1" when (ap_phi_mux_phi_ln28_phi_fu_1426_p4 = ap_const_lv13_1000) else "0";
+    icmp_ln31_fu_1563_p2 <= "1" when (signed(zext_ln31_fu_1559_p1) < signed(dim_read_reg_3801)) else "0";
+    icmp_ln33_fu_2481_p2 <= "1" when (j_0_reg_1445 = dim_read_reg_3801) else "0";
+    icmp_ln42_fu_3784_p2 <= "1" when (phi_ln42_reg_1456 = ap_const_lv13_1000) else "0";
+
+    in1_loc_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34, ap_CS_fsm_state35, ap_CS_fsm_state36, ap_CS_fsm_state37, ap_CS_fsm_state38, ap_CS_fsm_state39, ap_CS_fsm_state40, ap_CS_fsm_state41, ap_CS_fsm_state42, ap_CS_fsm_state43, ap_CS_fsm_state44, ap_CS_fsm_state45, ap_CS_fsm_state46, ap_CS_fsm_state47, ap_CS_fsm_state48, ap_CS_fsm_state49, ap_CS_fsm_state50, ap_CS_fsm_state51, ap_CS_fsm_state52, ap_CS_fsm_state53, ap_CS_fsm_state54, ap_enable_reg_pp0_iter2, zext_ln27_fu_1537_p1, zext_ln38_fu_1582_p1, tmp_5_fu_1625_p3, tmp_7_fu_1653_p3, tmp_9_fu_1681_p3, tmp_10_fu_1709_p3, tmp_12_fu_1737_p3, tmp_14_fu_1765_p3, tmp_16_fu_1793_p3, tmp_18_fu_1821_p3, tmp_20_fu_1849_p3, tmp_22_fu_1877_p3, tmp_24_fu_1905_p3, tmp_26_fu_1933_p3, tmp_28_fu_1961_p3, tmp_30_fu_1989_p3, tmp_32_fu_2017_p3, tmp_34_fu_2045_p3, tmp_36_fu_2073_p3, tmp_38_fu_2101_p3, tmp_40_fu_2129_p3, tmp_42_fu_2157_p3, tmp_44_fu_2185_p3, tmp_46_fu_2213_p3, tmp_48_fu_2241_p3, tmp_50_fu_2269_p3, tmp_52_fu_2297_p3, tmp_54_fu_2325_p3, tmp_56_fu_2353_p3, tmp_58_fu_2381_p3, tmp_60_fu_2409_p3, tmp_62_fu_2437_p3, tmp_64_fu_2465_p3)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state54)) then 
+            in1_loc_address0 <= tmp_64_fu_2465_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state53)) then 
+            in1_loc_address0 <= tmp_62_fu_2437_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state52)) then 
+            in1_loc_address0 <= tmp_60_fu_2409_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state51)) then 
+            in1_loc_address0 <= tmp_58_fu_2381_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state50)) then 
+            in1_loc_address0 <= tmp_56_fu_2353_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state49)) then 
+            in1_loc_address0 <= tmp_54_fu_2325_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state48)) then 
+            in1_loc_address0 <= tmp_52_fu_2297_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state47)) then 
+            in1_loc_address0 <= tmp_50_fu_2269_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state46)) then 
+            in1_loc_address0 <= tmp_48_fu_2241_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state45)) then 
+            in1_loc_address0 <= tmp_46_fu_2213_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state44)) then 
+            in1_loc_address0 <= tmp_44_fu_2185_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state43)) then 
+            in1_loc_address0 <= tmp_42_fu_2157_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state42)) then 
+            in1_loc_address0 <= tmp_40_fu_2129_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state41)) then 
+            in1_loc_address0 <= tmp_38_fu_2101_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state40)) then 
+            in1_loc_address0 <= tmp_36_fu_2073_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state39)) then 
+            in1_loc_address0 <= tmp_34_fu_2045_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state38)) then 
+            in1_loc_address0 <= tmp_32_fu_2017_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state37)) then 
+            in1_loc_address0 <= tmp_30_fu_1989_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state36)) then 
+            in1_loc_address0 <= tmp_28_fu_1961_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state35)) then 
+            in1_loc_address0 <= tmp_26_fu_1933_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state34)) then 
+            in1_loc_address0 <= tmp_24_fu_1905_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state33)) then 
+            in1_loc_address0 <= tmp_22_fu_1877_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state32)) then 
+            in1_loc_address0 <= tmp_20_fu_1849_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then 
+            in1_loc_address0 <= tmp_18_fu_1821_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state30)) then 
+            in1_loc_address0 <= tmp_16_fu_1793_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state29)) then 
+            in1_loc_address0 <= tmp_14_fu_1765_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state28)) then 
+            in1_loc_address0 <= tmp_12_fu_1737_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then 
+            in1_loc_address0 <= tmp_10_fu_1709_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then 
+            in1_loc_address0 <= tmp_9_fu_1681_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in1_loc_address0 <= tmp_7_fu_1653_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+            in1_loc_address0 <= tmp_5_fu_1625_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_address0 <= zext_ln38_fu_1582_p1(12 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_address0 <= zext_ln27_fu_1537_p1(12 - 1 downto 0);
+        else 
+            in1_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_address1_assign_proc : process(ap_CS_fsm_state23, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34, ap_CS_fsm_state35, ap_CS_fsm_state36, ap_CS_fsm_state37, ap_CS_fsm_state38, ap_CS_fsm_state39, ap_CS_fsm_state40, ap_CS_fsm_state41, ap_CS_fsm_state42, ap_CS_fsm_state43, ap_CS_fsm_state44, ap_CS_fsm_state45, ap_CS_fsm_state46, ap_CS_fsm_state47, ap_CS_fsm_state48, ap_CS_fsm_state49, ap_CS_fsm_state50, ap_CS_fsm_state51, ap_CS_fsm_state52, ap_CS_fsm_state53, ap_CS_fsm_state54, tmp_3_fu_1597_p3, tmp_4_fu_1611_p3, tmp_6_fu_1639_p3, tmp_8_fu_1667_p3, tmp_s_fu_1695_p3, tmp_11_fu_1723_p3, tmp_13_fu_1751_p3, tmp_15_fu_1779_p3, tmp_17_fu_1807_p3, tmp_19_fu_1835_p3, tmp_21_fu_1863_p3, tmp_23_fu_1891_p3, tmp_25_fu_1919_p3, tmp_27_fu_1947_p3, tmp_29_fu_1975_p3, tmp_31_fu_2003_p3, tmp_33_fu_2031_p3, tmp_35_fu_2059_p3, tmp_37_fu_2087_p3, tmp_39_fu_2115_p3, tmp_41_fu_2143_p3, tmp_43_fu_2171_p3, tmp_45_fu_2199_p3, tmp_47_fu_2227_p3, tmp_49_fu_2255_p3, tmp_51_fu_2283_p3, tmp_53_fu_2311_p3, tmp_55_fu_2339_p3, tmp_57_fu_2367_p3, tmp_59_fu_2395_p3, tmp_61_fu_2423_p3, tmp_63_fu_2451_p3)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state54)) then 
+            in1_loc_address1 <= tmp_63_fu_2451_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state53)) then 
+            in1_loc_address1 <= tmp_61_fu_2423_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state52)) then 
+            in1_loc_address1 <= tmp_59_fu_2395_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state51)) then 
+            in1_loc_address1 <= tmp_57_fu_2367_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state50)) then 
+            in1_loc_address1 <= tmp_55_fu_2339_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state49)) then 
+            in1_loc_address1 <= tmp_53_fu_2311_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state48)) then 
+            in1_loc_address1 <= tmp_51_fu_2283_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state47)) then 
+            in1_loc_address1 <= tmp_49_fu_2255_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state46)) then 
+            in1_loc_address1 <= tmp_47_fu_2227_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state45)) then 
+            in1_loc_address1 <= tmp_45_fu_2199_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state44)) then 
+            in1_loc_address1 <= tmp_43_fu_2171_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state43)) then 
+            in1_loc_address1 <= tmp_41_fu_2143_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state42)) then 
+            in1_loc_address1 <= tmp_39_fu_2115_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state41)) then 
+            in1_loc_address1 <= tmp_37_fu_2087_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state40)) then 
+            in1_loc_address1 <= tmp_35_fu_2059_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state39)) then 
+            in1_loc_address1 <= tmp_33_fu_2031_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state38)) then 
+            in1_loc_address1 <= tmp_31_fu_2003_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state37)) then 
+            in1_loc_address1 <= tmp_29_fu_1975_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state36)) then 
+            in1_loc_address1 <= tmp_27_fu_1947_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state35)) then 
+            in1_loc_address1 <= tmp_25_fu_1919_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state34)) then 
+            in1_loc_address1 <= tmp_23_fu_1891_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state33)) then 
+            in1_loc_address1 <= tmp_21_fu_1863_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state32)) then 
+            in1_loc_address1 <= tmp_19_fu_1835_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state31)) then 
+            in1_loc_address1 <= tmp_17_fu_1807_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state30)) then 
+            in1_loc_address1 <= tmp_15_fu_1779_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state29)) then 
+            in1_loc_address1 <= tmp_13_fu_1751_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state28)) then 
+            in1_loc_address1 <= tmp_11_fu_1723_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then 
+            in1_loc_address1 <= tmp_s_fu_1695_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then 
+            in1_loc_address1 <= tmp_8_fu_1667_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in1_loc_address1 <= tmp_6_fu_1639_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+            in1_loc_address1 <= tmp_4_fu_1611_p3(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_address1 <= tmp_3_fu_1597_p3(12 - 1 downto 0);
+        else 
+            in1_loc_address1 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34, ap_CS_fsm_state35, ap_CS_fsm_state36, ap_CS_fsm_state37, ap_CS_fsm_state38, ap_CS_fsm_state39, ap_CS_fsm_state40, ap_CS_fsm_state41, ap_CS_fsm_state42, ap_CS_fsm_state43, ap_CS_fsm_state44, ap_CS_fsm_state45, ap_CS_fsm_state46, ap_CS_fsm_state47, ap_CS_fsm_state48, ap_CS_fsm_state49, ap_CS_fsm_state50, ap_CS_fsm_state51, ap_CS_fsm_state52, ap_CS_fsm_state53, ap_CS_fsm_state54, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state51) or (ap_const_logic_1 = ap_CS_fsm_state50) or (ap_const_logic_1 = ap_CS_fsm_state49) or (ap_const_logic_1 = ap_CS_fsm_state48) or (ap_const_logic_1 = ap_CS_fsm_state47) or (ap_const_logic_1 = ap_CS_fsm_state46) or (ap_const_logic_1 = ap_CS_fsm_state45) or (ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state43) or (ap_const_logic_1 = ap_CS_fsm_state42) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state40) or (ap_const_logic_1 = ap_CS_fsm_state39) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state37) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state35) or (ap_const_logic_1 = ap_CS_fsm_state34) or (ap_const_logic_1 = ap_CS_fsm_state33) or (ap_const_logic_1 = ap_CS_fsm_state32) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state30) or (ap_const_logic_1 = ap_CS_fsm_state29) or (ap_const_logic_1 = ap_CS_fsm_state28) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state54) or (ap_const_logic_1 = ap_CS_fsm_state53) or (ap_const_logic_1 = ap_CS_fsm_state52) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_ce1_assign_proc : process(ap_CS_fsm_state23, ap_block_state23_io, ap_CS_fsm_state24, ap_CS_fsm_state25, ap_CS_fsm_state26, ap_CS_fsm_state27, ap_CS_fsm_state28, ap_CS_fsm_state29, ap_CS_fsm_state30, ap_CS_fsm_state31, ap_CS_fsm_state32, ap_CS_fsm_state33, ap_CS_fsm_state34, ap_CS_fsm_state35, ap_CS_fsm_state36, ap_CS_fsm_state37, ap_CS_fsm_state38, ap_CS_fsm_state39, ap_CS_fsm_state40, ap_CS_fsm_state41, ap_CS_fsm_state42, ap_CS_fsm_state43, ap_CS_fsm_state44, ap_CS_fsm_state45, ap_CS_fsm_state46, ap_CS_fsm_state47, ap_CS_fsm_state48, ap_CS_fsm_state49, ap_CS_fsm_state50, ap_CS_fsm_state51, ap_CS_fsm_state52, ap_CS_fsm_state53, ap_CS_fsm_state54)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state51) or (ap_const_logic_1 = ap_CS_fsm_state50) or (ap_const_logic_1 = ap_CS_fsm_state49) or (ap_const_logic_1 = ap_CS_fsm_state48) or (ap_const_logic_1 = ap_CS_fsm_state47) or (ap_const_logic_1 = ap_CS_fsm_state46) or (ap_const_logic_1 = ap_CS_fsm_state45) or (ap_const_logic_1 = ap_CS_fsm_state44) or (ap_const_logic_1 = ap_CS_fsm_state43) or (ap_const_logic_1 = ap_CS_fsm_state42) or (ap_const_logic_1 = ap_CS_fsm_state41) or (ap_const_logic_1 = ap_CS_fsm_state40) or (ap_const_logic_1 = ap_CS_fsm_state39) or (ap_const_logic_1 = ap_CS_fsm_state38) or (ap_const_logic_1 = ap_CS_fsm_state37) or (ap_const_logic_1 = ap_CS_fsm_state36) or (ap_const_logic_1 = ap_CS_fsm_state35) or (ap_const_logic_1 = ap_CS_fsm_state34) or (ap_const_logic_1 = ap_CS_fsm_state33) or (ap_const_logic_1 = ap_CS_fsm_state32) or (ap_const_logic_1 = ap_CS_fsm_state31) or (ap_const_logic_1 = ap_CS_fsm_state30) or (ap_const_logic_1 = ap_CS_fsm_state29) or (ap_const_logic_1 = ap_CS_fsm_state28) or (ap_const_logic_1 = ap_CS_fsm_state27) or (ap_const_logic_1 = ap_CS_fsm_state26) or (ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state24) or (ap_const_logic_1 = ap_CS_fsm_state54) or (ap_const_logic_1 = ap_CS_fsm_state53) or (ap_const_logic_1 = ap_CS_fsm_state52) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_ce1 <= ap_const_logic_1;
+        else 
+            in1_loc_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_we0_assign_proc : process(ap_block_pp0_stage0_11001, icmp_ln27_reg_3840_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_reg_3840_pp0_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    in1_mem_ARADDR <= empty_6_fu_1497_p1(32 - 1 downto 0);
+
+    in1_mem_ARVALID_assign_proc : process(ap_CS_fsm_state2, in1_mem_ARREADY)
+    begin
+        if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            in1_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in1_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, icmp_ln27_reg_3840, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_reg_3840 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_RREADY <= ap_const_logic_1;
+        else 
+            in1_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_AR_assign_proc : process(m_axi_in1_mem_ARREADY, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            in1_mem_blk_n_AR <= m_axi_in1_mem_ARREADY;
+        else 
+            in1_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_R_assign_proc : process(m_axi_in1_mem_RVALID, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, icmp_ln27_reg_3840)
+    begin
+        if (((icmp_ln27_reg_3840 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_blk_n_R <= m_axi_in1_mem_RVALID;
+        else 
+            in1_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_loc_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state56, ap_CS_fsm_state57, ap_CS_fsm_state58, ap_CS_fsm_state59, ap_CS_fsm_state60, ap_CS_fsm_state61, ap_CS_fsm_state62, ap_CS_fsm_state63, ap_CS_fsm_state64, ap_CS_fsm_state65, ap_CS_fsm_state66, ap_CS_fsm_state67, ap_CS_fsm_state68, ap_CS_fsm_state69, ap_CS_fsm_state70, ap_CS_fsm_state71, ap_CS_fsm_state72, ap_CS_fsm_state73, ap_CS_fsm_state74, ap_CS_fsm_state75, ap_CS_fsm_state76, ap_CS_fsm_state77, ap_CS_fsm_state78, ap_CS_fsm_state79, ap_CS_fsm_state80, ap_CS_fsm_state81, ap_CS_fsm_state82, ap_CS_fsm_state83, ap_CS_fsm_state84, ap_CS_fsm_state85, ap_CS_fsm_state86, ap_CS_fsm_state87, ap_enable_reg_pp1_iter2, zext_ln28_fu_1554_p1, sext_ln38_fu_2492_p1, sext_ln38_3_fu_2537_p1, sext_ln38_5_fu_2567_p1, sext_ln38_7_fu_2613_p1, sext_ln38_9_fu_2648_p1, sext_ln38_11_fu_2693_p1, sext_ln38_13_fu_2728_p1, sext_ln38_15_fu_2768_p1, sext_ln38_17_fu_2803_p1, sext_ln38_19_fu_2853_p1, sext_ln38_21_fu_2888_p1, sext_ln38_23_fu_2928_p1, sext_ln38_25_fu_2963_p1, sext_ln38_27_fu_3008_p1, sext_ln38_29_fu_3043_p1, sext_ln38_31_fu_3083_p1, sext_ln38_33_fu_3118_p1, sext_ln38_35_fu_3173_p1, sext_ln38_37_fu_3208_p1, sext_ln38_39_fu_3248_p1, sext_ln38_41_fu_3283_p1, sext_ln38_43_fu_3328_p1, sext_ln38_45_fu_3363_p1, sext_ln38_47_fu_3403_p1, sext_ln38_49_fu_3438_p1, sext_ln38_51_fu_3488_p1, sext_ln38_53_fu_3523_p1, sext_ln38_55_fu_3563_p1, sext_ln38_57_fu_3598_p1, sext_ln38_59_fu_3643_p1, sext_ln38_61_fu_3678_p1, sext_ln38_63_fu_3718_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state87)) then 
+            in2_loc_address0 <= sext_ln38_63_fu_3718_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state86)) then 
+            in2_loc_address0 <= sext_ln38_61_fu_3678_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state85)) then 
+            in2_loc_address0 <= sext_ln38_59_fu_3643_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state84)) then 
+            in2_loc_address0 <= sext_ln38_57_fu_3598_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state83)) then 
+            in2_loc_address0 <= sext_ln38_55_fu_3563_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state82)) then 
+            in2_loc_address0 <= sext_ln38_53_fu_3523_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state81)) then 
+            in2_loc_address0 <= sext_ln38_51_fu_3488_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state80)) then 
+            in2_loc_address0 <= sext_ln38_49_fu_3438_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state79)) then 
+            in2_loc_address0 <= sext_ln38_47_fu_3403_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state78)) then 
+            in2_loc_address0 <= sext_ln38_45_fu_3363_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state77)) then 
+            in2_loc_address0 <= sext_ln38_43_fu_3328_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state76)) then 
+            in2_loc_address0 <= sext_ln38_41_fu_3283_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state75)) then 
+            in2_loc_address0 <= sext_ln38_39_fu_3248_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state74)) then 
+            in2_loc_address0 <= sext_ln38_37_fu_3208_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state73)) then 
+            in2_loc_address0 <= sext_ln38_35_fu_3173_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state72)) then 
+            in2_loc_address0 <= sext_ln38_33_fu_3118_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state71)) then 
+            in2_loc_address0 <= sext_ln38_31_fu_3083_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state70)) then 
+            in2_loc_address0 <= sext_ln38_29_fu_3043_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state69)) then 
+            in2_loc_address0 <= sext_ln38_27_fu_3008_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state68)) then 
+            in2_loc_address0 <= sext_ln38_25_fu_2963_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state67)) then 
+            in2_loc_address0 <= sext_ln38_23_fu_2928_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state66)) then 
+            in2_loc_address0 <= sext_ln38_21_fu_2888_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state65)) then 
+            in2_loc_address0 <= sext_ln38_19_fu_2853_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state64)) then 
+            in2_loc_address0 <= sext_ln38_17_fu_2803_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state63)) then 
+            in2_loc_address0 <= sext_ln38_15_fu_2768_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state62)) then 
+            in2_loc_address0 <= sext_ln38_13_fu_2728_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state61)) then 
+            in2_loc_address0 <= sext_ln38_11_fu_2693_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state60)) then 
+            in2_loc_address0 <= sext_ln38_9_fu_2648_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state59)) then 
+            in2_loc_address0 <= sext_ln38_7_fu_2613_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state58)) then 
+            in2_loc_address0 <= sext_ln38_5_fu_2567_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state57)) then 
+            in2_loc_address0 <= sext_ln38_3_fu_2537_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state56)) then 
+            in2_loc_address0 <= sext_ln38_fu_2492_p1(12 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_address0 <= zext_ln28_fu_1554_p1(12 - 1 downto 0);
+        else 
+            in2_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_address1_assign_proc : process(ap_CS_fsm_state56, ap_CS_fsm_state57, ap_CS_fsm_state58, ap_CS_fsm_state59, ap_CS_fsm_state60, ap_CS_fsm_state61, ap_CS_fsm_state62, ap_CS_fsm_state63, ap_CS_fsm_state64, ap_CS_fsm_state65, ap_CS_fsm_state66, ap_CS_fsm_state67, ap_CS_fsm_state68, ap_CS_fsm_state69, ap_CS_fsm_state70, ap_CS_fsm_state71, ap_CS_fsm_state72, ap_CS_fsm_state73, ap_CS_fsm_state74, ap_CS_fsm_state75, ap_CS_fsm_state76, ap_CS_fsm_state77, ap_CS_fsm_state78, ap_CS_fsm_state79, ap_CS_fsm_state80, ap_CS_fsm_state81, ap_CS_fsm_state82, ap_CS_fsm_state83, ap_CS_fsm_state84, ap_CS_fsm_state85, ap_CS_fsm_state86, ap_CS_fsm_state87, sext_ln38_1_fu_2507_p1, sext_ln38_2_fu_2527_p1, sext_ln38_4_fu_2557_p1, sext_ln38_6_fu_2603_p1, sext_ln38_8_fu_2638_p1, sext_ln38_10_fu_2683_p1, sext_ln38_12_fu_2718_p1, sext_ln38_14_fu_2758_p1, sext_ln38_16_fu_2793_p1, sext_ln38_18_fu_2843_p1, sext_ln38_20_fu_2878_p1, sext_ln38_22_fu_2918_p1, sext_ln38_24_fu_2953_p1, sext_ln38_26_fu_2998_p1, sext_ln38_28_fu_3033_p1, sext_ln38_30_fu_3073_p1, sext_ln38_32_fu_3108_p1, sext_ln38_34_fu_3163_p1, sext_ln38_36_fu_3198_p1, sext_ln38_38_fu_3238_p1, sext_ln38_40_fu_3273_p1, sext_ln38_42_fu_3318_p1, sext_ln38_44_fu_3353_p1, sext_ln38_46_fu_3393_p1, sext_ln38_48_fu_3428_p1, sext_ln38_50_fu_3478_p1, sext_ln38_52_fu_3513_p1, sext_ln38_54_fu_3553_p1, sext_ln38_56_fu_3588_p1, sext_ln38_58_fu_3633_p1, sext_ln38_60_fu_3668_p1, sext_ln38_62_fu_3708_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state87)) then 
+            in2_loc_address1 <= sext_ln38_62_fu_3708_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state86)) then 
+            in2_loc_address1 <= sext_ln38_60_fu_3668_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state85)) then 
+            in2_loc_address1 <= sext_ln38_58_fu_3633_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state84)) then 
+            in2_loc_address1 <= sext_ln38_56_fu_3588_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state83)) then 
+            in2_loc_address1 <= sext_ln38_54_fu_3553_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state82)) then 
+            in2_loc_address1 <= sext_ln38_52_fu_3513_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state81)) then 
+            in2_loc_address1 <= sext_ln38_50_fu_3478_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state80)) then 
+            in2_loc_address1 <= sext_ln38_48_fu_3428_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state79)) then 
+            in2_loc_address1 <= sext_ln38_46_fu_3393_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state78)) then 
+            in2_loc_address1 <= sext_ln38_44_fu_3353_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state77)) then 
+            in2_loc_address1 <= sext_ln38_42_fu_3318_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state76)) then 
+            in2_loc_address1 <= sext_ln38_40_fu_3273_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state75)) then 
+            in2_loc_address1 <= sext_ln38_38_fu_3238_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state74)) then 
+            in2_loc_address1 <= sext_ln38_36_fu_3198_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state73)) then 
+            in2_loc_address1 <= sext_ln38_34_fu_3163_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state72)) then 
+            in2_loc_address1 <= sext_ln38_32_fu_3108_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state71)) then 
+            in2_loc_address1 <= sext_ln38_30_fu_3073_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state70)) then 
+            in2_loc_address1 <= sext_ln38_28_fu_3033_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state69)) then 
+            in2_loc_address1 <= sext_ln38_26_fu_2998_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state68)) then 
+            in2_loc_address1 <= sext_ln38_24_fu_2953_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state67)) then 
+            in2_loc_address1 <= sext_ln38_22_fu_2918_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state66)) then 
+            in2_loc_address1 <= sext_ln38_20_fu_2878_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state65)) then 
+            in2_loc_address1 <= sext_ln38_18_fu_2843_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state64)) then 
+            in2_loc_address1 <= sext_ln38_16_fu_2793_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state63)) then 
+            in2_loc_address1 <= sext_ln38_14_fu_2758_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state62)) then 
+            in2_loc_address1 <= sext_ln38_12_fu_2718_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state61)) then 
+            in2_loc_address1 <= sext_ln38_10_fu_2683_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state60)) then 
+            in2_loc_address1 <= sext_ln38_8_fu_2638_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state59)) then 
+            in2_loc_address1 <= sext_ln38_6_fu_2603_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state58)) then 
+            in2_loc_address1 <= sext_ln38_4_fu_2557_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state57)) then 
+            in2_loc_address1 <= sext_ln38_2_fu_2527_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state56)) then 
+            in2_loc_address1 <= sext_ln38_1_fu_2507_p1(12 - 1 downto 0);
+        else 
+            in2_loc_address1 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state56, ap_CS_fsm_state57, ap_CS_fsm_state58, ap_CS_fsm_state59, ap_CS_fsm_state60, ap_CS_fsm_state61, ap_CS_fsm_state62, ap_CS_fsm_state63, ap_CS_fsm_state64, ap_CS_fsm_state65, ap_CS_fsm_state66, ap_CS_fsm_state67, ap_CS_fsm_state68, ap_CS_fsm_state69, ap_CS_fsm_state70, ap_CS_fsm_state71, ap_CS_fsm_state72, ap_CS_fsm_state73, ap_CS_fsm_state74, ap_CS_fsm_state75, ap_CS_fsm_state76, ap_CS_fsm_state77, ap_CS_fsm_state78, ap_CS_fsm_state79, ap_CS_fsm_state80, ap_CS_fsm_state81, ap_CS_fsm_state82, ap_CS_fsm_state83, ap_CS_fsm_state84, ap_CS_fsm_state85, ap_CS_fsm_state86, ap_CS_fsm_state87, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state87) or (ap_const_logic_1 = ap_CS_fsm_state86) or (ap_const_logic_1 = ap_CS_fsm_state85) or (ap_const_logic_1 = ap_CS_fsm_state84) or (ap_const_logic_1 = ap_CS_fsm_state83) or (ap_const_logic_1 = ap_CS_fsm_state82) or (ap_const_logic_1 = ap_CS_fsm_state81) or (ap_const_logic_1 = ap_CS_fsm_state80) or (ap_const_logic_1 = ap_CS_fsm_state79) or (ap_const_logic_1 = ap_CS_fsm_state78) or (ap_const_logic_1 = ap_CS_fsm_state77) or (ap_const_logic_1 = ap_CS_fsm_state76) or (ap_const_logic_1 = ap_CS_fsm_state75) or (ap_const_logic_1 = ap_CS_fsm_state74) or (ap_const_logic_1 = ap_CS_fsm_state73) or (ap_const_logic_1 = ap_CS_fsm_state72) or (ap_const_logic_1 = ap_CS_fsm_state71) or (ap_const_logic_1 = ap_CS_fsm_state70) or (ap_const_logic_1 = ap_CS_fsm_state69) or (ap_const_logic_1 = ap_CS_fsm_state68) or (ap_const_logic_1 = ap_CS_fsm_state67) or (ap_const_logic_1 = ap_CS_fsm_state66) or (ap_const_logic_1 = ap_CS_fsm_state65) or (ap_const_logic_1 = ap_CS_fsm_state64) or (ap_const_logic_1 = ap_CS_fsm_state63) or (ap_const_logic_1 = ap_CS_fsm_state62) or (ap_const_logic_1 = ap_CS_fsm_state61) or (ap_const_logic_1 = ap_CS_fsm_state60) or (ap_const_logic_1 = ap_CS_fsm_state59) or (ap_const_logic_1 = ap_CS_fsm_state58) or (ap_const_logic_1 = ap_CS_fsm_state57) or (ap_const_logic_1 = ap_CS_fsm_state56) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_ce1_assign_proc : process(ap_CS_fsm_state56, ap_CS_fsm_state57, ap_CS_fsm_state58, ap_CS_fsm_state59, ap_CS_fsm_state60, ap_CS_fsm_state61, ap_CS_fsm_state62, ap_CS_fsm_state63, ap_CS_fsm_state64, ap_CS_fsm_state65, ap_CS_fsm_state66, ap_CS_fsm_state67, ap_CS_fsm_state68, ap_CS_fsm_state69, ap_CS_fsm_state70, ap_CS_fsm_state71, ap_CS_fsm_state72, ap_CS_fsm_state73, ap_CS_fsm_state74, ap_CS_fsm_state75, ap_CS_fsm_state76, ap_CS_fsm_state77, ap_CS_fsm_state78, ap_CS_fsm_state79, ap_CS_fsm_state80, ap_CS_fsm_state81, ap_CS_fsm_state82, ap_CS_fsm_state83, ap_CS_fsm_state84, ap_CS_fsm_state85, ap_CS_fsm_state86, ap_CS_fsm_state87)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state87) or (ap_const_logic_1 = ap_CS_fsm_state86) or (ap_const_logic_1 = ap_CS_fsm_state85) or (ap_const_logic_1 = ap_CS_fsm_state84) or (ap_const_logic_1 = ap_CS_fsm_state83) or (ap_const_logic_1 = ap_CS_fsm_state82) or (ap_const_logic_1 = ap_CS_fsm_state81) or (ap_const_logic_1 = ap_CS_fsm_state80) or (ap_const_logic_1 = ap_CS_fsm_state79) or (ap_const_logic_1 = ap_CS_fsm_state78) or (ap_const_logic_1 = ap_CS_fsm_state77) or (ap_const_logic_1 = ap_CS_fsm_state76) or (ap_const_logic_1 = ap_CS_fsm_state75) or (ap_const_logic_1 = ap_CS_fsm_state74) or (ap_const_logic_1 = ap_CS_fsm_state73) or (ap_const_logic_1 = ap_CS_fsm_state72) or (ap_const_logic_1 = ap_CS_fsm_state71) or (ap_const_logic_1 = ap_CS_fsm_state70) or (ap_const_logic_1 = ap_CS_fsm_state69) or (ap_const_logic_1 = ap_CS_fsm_state68) or (ap_const_logic_1 = ap_CS_fsm_state67) or (ap_const_logic_1 = ap_CS_fsm_state66) or (ap_const_logic_1 = ap_CS_fsm_state65) or (ap_const_logic_1 = ap_CS_fsm_state64) or (ap_const_logic_1 = ap_CS_fsm_state63) or (ap_const_logic_1 = ap_CS_fsm_state62) or (ap_const_logic_1 = ap_CS_fsm_state61) or (ap_const_logic_1 = ap_CS_fsm_state60) or (ap_const_logic_1 = ap_CS_fsm_state59) or (ap_const_logic_1 = ap_CS_fsm_state58) or (ap_const_logic_1 = ap_CS_fsm_state57) or (ap_const_logic_1 = ap_CS_fsm_state56))) then 
+            in2_loc_ce1 <= ap_const_logic_1;
+        else 
+            in2_loc_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_we0_assign_proc : process(ap_block_pp1_stage0_11001, icmp_ln28_reg_3854_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_reg_3854_pp1_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_ARVALID_assign_proc : process(ap_CS_fsm_state12, in2_mem_ARREADY)
+    begin
+        if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then 
+            in2_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in2_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_RREADY_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, icmp_ln28_reg_3854, ap_block_pp1_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_reg_3854 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_RREADY <= ap_const_logic_1;
+        else 
+            in2_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_AR_assign_proc : process(m_axi_in2_mem_ARREADY, ap_CS_fsm_state12)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state12)) then 
+            in2_mem_blk_n_AR <= m_axi_in2_mem_ARREADY;
+        else 
+            in2_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_R_assign_proc : process(m_axi_in2_mem_RVALID, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, icmp_ln28_reg_3854)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (icmp_ln28_reg_3854 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_blk_n_R <= m_axi_in2_mem_RVALID;
+        else 
+            in2_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    j_fu_2486_p2 <= std_logic_vector(signed(j_0_reg_1445) + signed(ap_const_lv32_1));
+    mul_ln38_10_fu_2733_p0 <= in2_loc_q1;
+    mul_ln38_10_fu_2733_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_10_fu_2733_p0) * signed(in1_loc_load_10_reg_4068))), 32));
+    mul_ln38_11_fu_2738_p0 <= in2_loc_q0;
+    mul_ln38_11_fu_2738_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_11_fu_2738_p0) * signed(in1_loc_load_11_reg_4073))), 32));
+    mul_ln38_12_fu_2773_p0 <= in2_loc_q1;
+    mul_ln38_12_fu_2773_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_12_fu_2773_p0) * signed(in1_loc_load_12_reg_4088))), 32));
+    mul_ln38_13_fu_2778_p0 <= in2_loc_q0;
+    mul_ln38_13_fu_2778_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_13_fu_2778_p0) * signed(in1_loc_load_13_reg_4093))), 32));
+    mul_ln38_14_fu_2808_p0 <= in2_loc_q1;
+    mul_ln38_14_fu_2808_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_14_fu_2808_p0) * signed(in1_loc_load_14_reg_4108))), 32));
+    mul_ln38_15_fu_2813_p0 <= in2_loc_q0;
+    mul_ln38_15_fu_2813_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_15_fu_2813_p0) * signed(in1_loc_load_15_reg_4113))), 32));
+    mul_ln38_16_fu_2858_p0 <= in2_loc_q1;
+    mul_ln38_16_fu_2858_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_16_fu_2858_p0) * signed(in1_loc_load_16_reg_4128))), 32));
+    mul_ln38_17_fu_2863_p0 <= in2_loc_q0;
+    mul_ln38_17_fu_2863_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_17_fu_2863_p0) * signed(in1_loc_load_17_reg_4133))), 32));
+    mul_ln38_18_fu_2893_p0 <= in2_loc_q1;
+    mul_ln38_18_fu_2893_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_18_fu_2893_p0) * signed(in1_loc_load_18_reg_4148))), 32));
+    mul_ln38_19_fu_2898_p0 <= in2_loc_q0;
+    mul_ln38_19_fu_2898_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_19_fu_2898_p0) * signed(in1_loc_load_19_reg_4153))), 32));
+    mul_ln38_1_fu_2547_p0 <= in2_loc_q1;
+    mul_ln38_1_fu_2547_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_1_fu_2547_p0) * signed(in1_loc_load_1_reg_3973))), 32));
+    mul_ln38_20_fu_2933_p0 <= in2_loc_q1;
+    mul_ln38_20_fu_2933_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_20_fu_2933_p0) * signed(in1_loc_load_20_reg_4168))), 32));
+    mul_ln38_21_fu_2938_p0 <= in2_loc_q0;
+    mul_ln38_21_fu_2938_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_21_fu_2938_p0) * signed(in1_loc_load_21_reg_4173))), 32));
+    mul_ln38_22_fu_2968_p0 <= in2_loc_q1;
+    mul_ln38_22_fu_2968_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_22_fu_2968_p0) * signed(in1_loc_load_22_reg_4188))), 32));
+    mul_ln38_23_fu_2973_p0 <= in2_loc_q0;
+    mul_ln38_23_fu_2973_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_23_fu_2973_p0) * signed(in1_loc_load_23_reg_4193))), 32));
+    mul_ln38_24_fu_3013_p0 <= in2_loc_q1;
+    mul_ln38_24_fu_3013_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_24_fu_3013_p0) * signed(in1_loc_load_24_reg_4208))), 32));
+    mul_ln38_25_fu_3018_p0 <= in2_loc_q0;
+    mul_ln38_25_fu_3018_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_25_fu_3018_p0) * signed(in1_loc_load_25_reg_4213))), 32));
+    mul_ln38_26_fu_3048_p0 <= in2_loc_q1;
+    mul_ln38_26_fu_3048_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_26_fu_3048_p0) * signed(in1_loc_load_26_reg_4228))), 32));
+    mul_ln38_27_fu_3053_p0 <= in2_loc_q0;
+    mul_ln38_27_fu_3053_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_27_fu_3053_p0) * signed(in1_loc_load_27_reg_4233))), 32));
+    mul_ln38_28_fu_3088_p0 <= in2_loc_q1;
+    mul_ln38_28_fu_3088_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_28_fu_3088_p0) * signed(in1_loc_load_28_reg_4248))), 32));
+    mul_ln38_29_fu_3093_p0 <= in2_loc_q0;
+    mul_ln38_29_fu_3093_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_29_fu_3093_p0) * signed(in1_loc_load_29_reg_4253))), 32));
+    mul_ln38_2_fu_2572_p0 <= in2_loc_q1;
+    mul_ln38_2_fu_2572_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_2_fu_2572_p0) * signed(in1_loc_load_2_reg_3988))), 32));
+    mul_ln38_30_fu_3123_p0 <= in2_loc_q1;
+    mul_ln38_30_fu_3123_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_30_fu_3123_p0) * signed(in1_loc_load_30_reg_4268))), 32));
+    mul_ln38_31_fu_3128_p0 <= in2_loc_q0;
+    mul_ln38_31_fu_3128_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_31_fu_3128_p0) * signed(in1_loc_load_31_reg_4273))), 32));
+    mul_ln38_32_fu_3178_p0 <= in2_loc_q1;
+    mul_ln38_32_fu_3178_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_32_fu_3178_p0) * signed(in1_loc_load_32_reg_4288))), 32));
+    mul_ln38_33_fu_3183_p0 <= in2_loc_q0;
+    mul_ln38_33_fu_3183_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_33_fu_3183_p0) * signed(in1_loc_load_33_reg_4293))), 32));
+    mul_ln38_34_fu_3213_p0 <= in2_loc_q1;
+    mul_ln38_34_fu_3213_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_34_fu_3213_p0) * signed(in1_loc_load_34_reg_4308))), 32));
+    mul_ln38_35_fu_3218_p0 <= in2_loc_q0;
+    mul_ln38_35_fu_3218_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_35_fu_3218_p0) * signed(in1_loc_load_35_reg_4313))), 32));
+    mul_ln38_36_fu_3253_p0 <= in2_loc_q1;
+    mul_ln38_36_fu_3253_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_36_fu_3253_p0) * signed(in1_loc_load_36_reg_4328))), 32));
+    mul_ln38_37_fu_3258_p0 <= in2_loc_q0;
+    mul_ln38_37_fu_3258_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_37_fu_3258_p0) * signed(in1_loc_load_37_reg_4333))), 32));
+    mul_ln38_38_fu_3288_p0 <= in2_loc_q1;
+    mul_ln38_38_fu_3288_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_38_fu_3288_p0) * signed(in1_loc_load_38_reg_4348))), 32));
+    mul_ln38_39_fu_3293_p0 <= in2_loc_q0;
+    mul_ln38_39_fu_3293_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_39_fu_3293_p0) * signed(in1_loc_load_39_reg_4353))), 32));
+    mul_ln38_3_fu_2577_p0 <= in2_loc_q0;
+    mul_ln38_3_fu_2577_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_3_fu_2577_p0) * signed(in1_loc_load_3_reg_3993))), 32));
+    mul_ln38_40_fu_3333_p0 <= in2_loc_q1;
+    mul_ln38_40_fu_3333_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_40_fu_3333_p0) * signed(in1_loc_load_40_reg_4368))), 32));
+    mul_ln38_41_fu_3338_p0 <= in2_loc_q0;
+    mul_ln38_41_fu_3338_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_41_fu_3338_p0) * signed(in1_loc_load_41_reg_4373))), 32));
+    mul_ln38_42_fu_3368_p0 <= in2_loc_q1;
+    mul_ln38_42_fu_3368_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_42_fu_3368_p0) * signed(in1_loc_load_42_reg_4388))), 32));
+    mul_ln38_43_fu_3373_p0 <= in2_loc_q0;
+    mul_ln38_43_fu_3373_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_43_fu_3373_p0) * signed(in1_loc_load_43_reg_4393))), 32));
+    mul_ln38_44_fu_3408_p0 <= in2_loc_q1;
+    mul_ln38_44_fu_3408_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_44_fu_3408_p0) * signed(in1_loc_load_44_reg_4408))), 32));
+    mul_ln38_45_fu_3413_p0 <= in2_loc_q0;
+    mul_ln38_45_fu_3413_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_45_fu_3413_p0) * signed(in1_loc_load_45_reg_4413))), 32));
+    mul_ln38_46_fu_3443_p0 <= in2_loc_q1;
+    mul_ln38_46_fu_3443_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_46_fu_3443_p0) * signed(in1_loc_load_46_reg_4428))), 32));
+    mul_ln38_47_fu_3448_p0 <= in2_loc_q0;
+    mul_ln38_47_fu_3448_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_47_fu_3448_p0) * signed(in1_loc_load_47_reg_4433))), 32));
+    mul_ln38_48_fu_3493_p0 <= in2_loc_q1;
+    mul_ln38_48_fu_3493_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_48_fu_3493_p0) * signed(in1_loc_load_48_reg_4448))), 32));
+    mul_ln38_49_fu_3498_p0 <= in2_loc_q0;
+    mul_ln38_49_fu_3498_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_49_fu_3498_p0) * signed(in1_loc_load_49_reg_4453))), 32));
+    mul_ln38_4_fu_2618_p0 <= in2_loc_q1;
+    mul_ln38_4_fu_2618_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_4_fu_2618_p0) * signed(in1_loc_load_4_reg_4008))), 32));
+    mul_ln38_50_fu_3528_p0 <= in2_loc_q1;
+    mul_ln38_50_fu_3528_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_50_fu_3528_p0) * signed(in1_loc_load_50_reg_4468))), 32));
+    mul_ln38_51_fu_3533_p0 <= in2_loc_q0;
+    mul_ln38_51_fu_3533_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_51_fu_3533_p0) * signed(in1_loc_load_51_reg_4473))), 32));
+    mul_ln38_52_fu_3568_p0 <= in2_loc_q1;
+    mul_ln38_52_fu_3568_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_52_fu_3568_p0) * signed(in1_loc_load_52_reg_4488))), 32));
+    mul_ln38_53_fu_3573_p0 <= in2_loc_q0;
+    mul_ln38_53_fu_3573_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_53_fu_3573_p0) * signed(in1_loc_load_53_reg_4493))), 32));
+    mul_ln38_54_fu_3603_p0 <= in2_loc_q1;
+    mul_ln38_54_fu_3603_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_54_fu_3603_p0) * signed(in1_loc_load_54_reg_4508))), 32));
+    mul_ln38_55_fu_3608_p0 <= in2_loc_q0;
+    mul_ln38_55_fu_3608_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_55_fu_3608_p0) * signed(in1_loc_load_55_reg_4513))), 32));
+    mul_ln38_56_fu_3648_p0 <= in2_loc_q1;
+    mul_ln38_56_fu_3648_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_56_fu_3648_p0) * signed(in1_loc_load_56_reg_4528))), 32));
+    mul_ln38_57_fu_3653_p0 <= in2_loc_q0;
+    mul_ln38_57_fu_3653_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_57_fu_3653_p0) * signed(in1_loc_load_57_reg_4533))), 32));
+    mul_ln38_58_fu_3683_p0 <= in2_loc_q1;
+    mul_ln38_58_fu_3683_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_58_fu_3683_p0) * signed(in1_loc_load_58_reg_4548))), 32));
+    mul_ln38_59_fu_3688_p0 <= in2_loc_q0;
+    mul_ln38_59_fu_3688_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_59_fu_3688_p0) * signed(in1_loc_load_59_reg_4553))), 32));
+    mul_ln38_5_fu_2623_p0 <= in2_loc_q0;
+    mul_ln38_5_fu_2623_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_5_fu_2623_p0) * signed(in1_loc_load_5_reg_4013))), 32));
+    mul_ln38_60_fu_3723_p0 <= in2_loc_q1;
+    mul_ln38_60_fu_3723_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_60_fu_3723_p0) * signed(in1_loc_load_60_reg_4568))), 32));
+    mul_ln38_61_fu_3728_p0 <= in2_loc_q0;
+    mul_ln38_61_fu_3728_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_61_fu_3728_p0) * signed(in1_loc_load_61_reg_4573))), 32));
+    mul_ln38_62_fu_3738_p0 <= in2_loc_q1;
+    mul_ln38_62_fu_3738_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_62_fu_3738_p0) * signed(in1_loc_load_62_reg_4583))), 32));
+    mul_ln38_63_fu_3743_p0 <= in2_loc_q0;
+    mul_ln38_63_fu_3743_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_63_fu_3743_p0) * signed(in1_loc_load_63_reg_4588))), 32));
+    mul_ln38_6_fu_2653_p0 <= in2_loc_q1;
+    mul_ln38_6_fu_2653_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_6_fu_2653_p0) * signed(in1_loc_load_6_reg_4028))), 32));
+    mul_ln38_7_fu_2658_p0 <= in2_loc_q0;
+    mul_ln38_7_fu_2658_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_7_fu_2658_p0) * signed(in1_loc_load_7_reg_4033))), 32));
+    mul_ln38_8_fu_2698_p0 <= in2_loc_q1;
+    mul_ln38_8_fu_2698_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_8_fu_2698_p0) * signed(in1_loc_load_8_reg_4048))), 32));
+    mul_ln38_9_fu_2703_p0 <= in2_loc_q0;
+    mul_ln38_9_fu_2703_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_9_fu_2703_p0) * signed(in1_loc_load_9_reg_4053))), 32));
+    mul_ln38_fu_2542_p0 <= in2_loc_q0;
+    mul_ln38_fu_2542_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_fu_2542_p0) * signed(in1_loc_load_reg_3968))), 32));
+    or_ln38_10_fu_1732_p2 <= (tmp_2_reg_3877 or ap_const_lv37_B);
+    or_ln38_11_fu_1746_p2 <= (tmp_2_reg_3877 or ap_const_lv37_C);
+    or_ln38_12_fu_1760_p2 <= (tmp_2_reg_3877 or ap_const_lv37_D);
+    or_ln38_13_fu_1774_p2 <= (tmp_2_reg_3877 or ap_const_lv37_E);
+    or_ln38_14_fu_1788_p2 <= (tmp_2_reg_3877 or ap_const_lv37_F);
+    or_ln38_15_fu_1802_p2 <= (tmp_2_reg_3877 or ap_const_lv37_10);
+    or_ln38_16_fu_1816_p2 <= (tmp_2_reg_3877 or ap_const_lv37_11);
+    or_ln38_17_fu_1830_p2 <= (tmp_2_reg_3877 or ap_const_lv37_12);
+    or_ln38_18_fu_1844_p2 <= (tmp_2_reg_3877 or ap_const_lv37_13);
+    or_ln38_19_fu_1858_p2 <= (tmp_2_reg_3877 or ap_const_lv37_14);
+    or_ln38_1_fu_1606_p2 <= (tmp_2_reg_3877 or ap_const_lv37_2);
+    or_ln38_20_fu_1872_p2 <= (tmp_2_reg_3877 or ap_const_lv37_15);
+    or_ln38_21_fu_1886_p2 <= (tmp_2_reg_3877 or ap_const_lv37_16);
+    or_ln38_22_fu_1900_p2 <= (tmp_2_reg_3877 or ap_const_lv37_17);
+    or_ln38_23_fu_1914_p2 <= (tmp_2_reg_3877 or ap_const_lv37_18);
+    or_ln38_24_fu_1928_p2 <= (tmp_2_reg_3877 or ap_const_lv37_19);
+    or_ln38_25_fu_1942_p2 <= (tmp_2_reg_3877 or ap_const_lv37_1A);
+    or_ln38_26_fu_1956_p2 <= (tmp_2_reg_3877 or ap_const_lv37_1B);
+    or_ln38_27_fu_1970_p2 <= (tmp_2_reg_3877 or ap_const_lv37_1C);
+    or_ln38_28_fu_1984_p2 <= (tmp_2_reg_3877 or ap_const_lv37_1D);
+    or_ln38_29_fu_1998_p2 <= (tmp_2_reg_3877 or ap_const_lv37_1E);
+    or_ln38_2_fu_1620_p2 <= (tmp_2_reg_3877 or ap_const_lv37_3);
+    or_ln38_30_fu_2012_p2 <= (tmp_2_reg_3877 or ap_const_lv37_1F);
+    or_ln38_31_fu_2026_p2 <= (tmp_2_reg_3877 or ap_const_lv37_20);
+    or_ln38_32_fu_2040_p2 <= (tmp_2_reg_3877 or ap_const_lv37_21);
+    or_ln38_33_fu_2054_p2 <= (tmp_2_reg_3877 or ap_const_lv37_22);
+    or_ln38_34_fu_2068_p2 <= (tmp_2_reg_3877 or ap_const_lv37_23);
+    or_ln38_35_fu_2082_p2 <= (tmp_2_reg_3877 or ap_const_lv37_24);
+    or_ln38_36_fu_2096_p2 <= (tmp_2_reg_3877 or ap_const_lv37_25);
+    or_ln38_37_fu_2110_p2 <= (tmp_2_reg_3877 or ap_const_lv37_26);
+    or_ln38_38_fu_2124_p2 <= (tmp_2_reg_3877 or ap_const_lv37_27);
+    or_ln38_39_fu_2138_p2 <= (tmp_2_reg_3877 or ap_const_lv37_28);
+    or_ln38_3_fu_1634_p2 <= (tmp_2_reg_3877 or ap_const_lv37_4);
+    or_ln38_40_fu_2152_p2 <= (tmp_2_reg_3877 or ap_const_lv37_29);
+    or_ln38_41_fu_2166_p2 <= (tmp_2_reg_3877 or ap_const_lv37_2A);
+    or_ln38_42_fu_2180_p2 <= (tmp_2_reg_3877 or ap_const_lv37_2B);
+    or_ln38_43_fu_2194_p2 <= (tmp_2_reg_3877 or ap_const_lv37_2C);
+    or_ln38_44_fu_2208_p2 <= (tmp_2_reg_3877 or ap_const_lv37_2D);
+    or_ln38_45_fu_2222_p2 <= (tmp_2_reg_3877 or ap_const_lv37_2E);
+    or_ln38_46_fu_2236_p2 <= (tmp_2_reg_3877 or ap_const_lv37_2F);
+    or_ln38_47_fu_2250_p2 <= (tmp_2_reg_3877 or ap_const_lv37_30);
+    or_ln38_48_fu_2264_p2 <= (tmp_2_reg_3877 or ap_const_lv37_31);
+    or_ln38_49_fu_2278_p2 <= (tmp_2_reg_3877 or ap_const_lv37_32);
+    or_ln38_4_fu_1648_p2 <= (tmp_2_reg_3877 or ap_const_lv37_5);
+    or_ln38_50_fu_2292_p2 <= (tmp_2_reg_3877 or ap_const_lv37_33);
+    or_ln38_51_fu_2306_p2 <= (tmp_2_reg_3877 or ap_const_lv37_34);
+    or_ln38_52_fu_2320_p2 <= (tmp_2_reg_3877 or ap_const_lv37_35);
+    or_ln38_53_fu_2334_p2 <= (tmp_2_reg_3877 or ap_const_lv37_36);
+    or_ln38_54_fu_2348_p2 <= (tmp_2_reg_3877 or ap_const_lv37_37);
+    or_ln38_55_fu_2362_p2 <= (tmp_2_reg_3877 or ap_const_lv37_38);
+    or_ln38_56_fu_2376_p2 <= (tmp_2_reg_3877 or ap_const_lv37_39);
+    or_ln38_57_fu_2390_p2 <= (tmp_2_reg_3877 or ap_const_lv37_3A);
+    or_ln38_58_fu_2404_p2 <= (tmp_2_reg_3877 or ap_const_lv37_3B);
+    or_ln38_59_fu_2418_p2 <= (tmp_2_reg_3877 or ap_const_lv37_3C);
+    or_ln38_5_fu_1662_p2 <= (tmp_2_reg_3877 or ap_const_lv37_6);
+    or_ln38_60_fu_2432_p2 <= (tmp_2_reg_3877 or ap_const_lv37_3D);
+    or_ln38_61_fu_2446_p2 <= (tmp_2_reg_3877 or ap_const_lv37_3E);
+    or_ln38_62_fu_2460_p2 <= (tmp_2_reg_3877 or ap_const_lv37_3F);
+    or_ln38_6_fu_1676_p2 <= (tmp_2_reg_3877 or ap_const_lv37_7);
+    or_ln38_7_fu_1690_p2 <= (tmp_2_reg_3877 or ap_const_lv37_8);
+    or_ln38_8_fu_1704_p2 <= (tmp_2_reg_3877 or ap_const_lv37_9);
+    or_ln38_9_fu_1718_p2 <= (tmp_2_reg_3877 or ap_const_lv37_A);
+    or_ln38_fu_1591_p2 <= (tmp_2_fu_1574_p3 or ap_const_lv37_1);
+
+    out_loc_address0_assign_proc : process(ap_block_pp2_stage0, out_loc_addr_reg_4677, ap_CS_fsm_state57, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_CS_fsm_state89, zext_ln42_fu_3796_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            out_loc_address0 <= zext_ln42_fu_3796_p1(12 - 1 downto 0);
+        elsif (((ap_const_logic_1 = ap_CS_fsm_state89) or (ap_const_logic_1 = ap_CS_fsm_state57))) then 
+            out_loc_address0 <= out_loc_addr_reg_4677;
+        else 
+            out_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    out_loc_ce0_assign_proc : process(ap_CS_fsm_state57, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_CS_fsm_state89)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state89) or (ap_const_logic_1 = ap_CS_fsm_state57) or ((ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001)))) then 
+            out_loc_ce0 <= ap_const_logic_1;
+        else 
+            out_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    out_loc_d0 <= std_logic_vector(unsigned(add_ln38_30_reg_4997) + unsigned(add_ln38_62_fu_3774_p2));
+
+    out_loc_we0_assign_proc : process(ap_CS_fsm_state89)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state89)) then 
+            out_loc_we0 <= ap_const_logic_1;
+        else 
+            out_loc_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_AWVALID_assign_proc : process(ap_CS_fsm_state23, icmp_ln31_fu_1563_p2, ap_block_state23_io)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_1563_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+            out_mem_AWVALID <= ap_const_logic_1;
+        else 
+            out_mem_AWVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_BREADY_assign_proc : process(ap_CS_fsm_state97, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state97))) then 
+            out_mem_BREADY <= ap_const_logic_1;
+        else 
+            out_mem_BREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_WVALID_assign_proc : process(ap_enable_reg_pp2_iter2, icmp_ln42_reg_5307_pp2_iter1_reg, ap_block_pp2_stage0_11001)
+    begin
+        if (((icmp_ln42_reg_5307_pp2_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001))) then 
+            out_mem_WVALID <= ap_const_logic_1;
+        else 
+            out_mem_WVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AW_assign_proc : process(m_axi_out_mem_AWREADY, ap_CS_fsm_state23, icmp_ln31_fu_1563_p2)
+    begin
+        if (((icmp_ln31_fu_1563_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+            out_mem_blk_n_AW <= m_axi_out_mem_AWREADY;
+        else 
+            out_mem_blk_n_AW <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_B_assign_proc : process(m_axi_out_mem_BVALID, ap_CS_fsm_state97)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state97)) then 
+            out_mem_blk_n_B <= m_axi_out_mem_BVALID;
+        else 
+            out_mem_blk_n_B <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_W_assign_proc : process(m_axi_out_mem_WREADY, ap_enable_reg_pp2_iter2, ap_block_pp2_stage0, icmp_ln42_reg_5307_pp2_iter1_reg)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (icmp_ln42_reg_5307_pp2_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            out_mem_blk_n_W <= m_axi_out_mem_WREADY;
+        else 
+            out_mem_blk_n_W <= ap_const_logic_1;
+        end if; 
+    end process;
+
+        sext_ln38_10_fu_2683_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_73_fu_2678_p2),64));
+
+        sext_ln38_11_fu_2693_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_74_fu_2688_p2),64));
+
+        sext_ln38_12_fu_2718_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_75_fu_2713_p2),64));
+
+        sext_ln38_13_fu_2728_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_76_fu_2723_p2),64));
+
+        sext_ln38_14_fu_2758_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_77_fu_2753_p2),64));
+
+        sext_ln38_15_fu_2768_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_78_fu_2763_p2),64));
+
+        sext_ln38_16_fu_2793_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_79_fu_2788_p2),64));
+
+        sext_ln38_17_fu_2803_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_80_fu_2798_p2),64));
+
+        sext_ln38_18_fu_2843_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_81_fu_2838_p2),64));
+
+        sext_ln38_19_fu_2853_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_82_fu_2848_p2),64));
+
+        sext_ln38_1_fu_2507_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_64_fu_2501_p2),64));
+
+        sext_ln38_20_fu_2878_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_83_fu_2873_p2),64));
+
+        sext_ln38_21_fu_2888_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_84_fu_2883_p2),64));
+
+        sext_ln38_22_fu_2918_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_85_fu_2913_p2),64));
+
+        sext_ln38_23_fu_2928_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_86_fu_2923_p2),64));
+
+        sext_ln38_24_fu_2953_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_87_fu_2948_p2),64));
+
+        sext_ln38_25_fu_2963_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_88_fu_2958_p2),64));
+
+        sext_ln38_26_fu_2998_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_89_fu_2993_p2),64));
+
+        sext_ln38_27_fu_3008_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_90_fu_3003_p2),64));
+
+        sext_ln38_28_fu_3033_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_91_fu_3028_p2),64));
+
+        sext_ln38_29_fu_3043_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_92_fu_3038_p2),64));
+
+        sext_ln38_2_fu_2527_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_65_fu_2522_p2),64));
+
+        sext_ln38_30_fu_3073_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_93_fu_3068_p2),64));
+
+        sext_ln38_31_fu_3083_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_94_fu_3078_p2),64));
+
+        sext_ln38_32_fu_3108_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_95_fu_3103_p2),64));
+
+        sext_ln38_33_fu_3118_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_96_fu_3113_p2),64));
+
+        sext_ln38_34_fu_3163_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_97_fu_3158_p2),64));
+
+        sext_ln38_35_fu_3173_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_98_fu_3168_p2),64));
+
+        sext_ln38_36_fu_3198_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_99_fu_3193_p2),64));
+
+        sext_ln38_37_fu_3208_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_100_fu_3203_p2),64));
+
+        sext_ln38_38_fu_3238_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_101_fu_3233_p2),64));
+
+        sext_ln38_39_fu_3248_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_102_fu_3243_p2),64));
+
+        sext_ln38_3_fu_2537_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_66_fu_2532_p2),64));
+
+        sext_ln38_40_fu_3273_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_103_fu_3268_p2),64));
+
+        sext_ln38_41_fu_3283_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_104_fu_3278_p2),64));
+
+        sext_ln38_42_fu_3318_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_105_fu_3313_p2),64));
+
+        sext_ln38_43_fu_3328_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_106_fu_3323_p2),64));
+
+        sext_ln38_44_fu_3353_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_107_fu_3348_p2),64));
+
+        sext_ln38_45_fu_3363_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_108_fu_3358_p2),64));
+
+        sext_ln38_46_fu_3393_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_109_fu_3388_p2),64));
+
+        sext_ln38_47_fu_3403_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_110_fu_3398_p2),64));
+
+        sext_ln38_48_fu_3428_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_111_fu_3423_p2),64));
+
+        sext_ln38_49_fu_3438_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_112_fu_3433_p2),64));
+
+        sext_ln38_4_fu_2557_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_67_fu_2552_p2),64));
+
+        sext_ln38_50_fu_3478_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_113_fu_3473_p2),64));
+
+        sext_ln38_51_fu_3488_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_114_fu_3483_p2),64));
+
+        sext_ln38_52_fu_3513_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_115_fu_3508_p2),64));
+
+        sext_ln38_53_fu_3523_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_116_fu_3518_p2),64));
+
+        sext_ln38_54_fu_3553_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_117_fu_3548_p2),64));
+
+        sext_ln38_55_fu_3563_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_118_fu_3558_p2),64));
+
+        sext_ln38_56_fu_3588_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_119_fu_3583_p2),64));
+
+        sext_ln38_57_fu_3598_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_120_fu_3593_p2),64));
+
+        sext_ln38_58_fu_3633_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_121_fu_3628_p2),64));
+
+        sext_ln38_59_fu_3643_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_122_fu_3638_p2),64));
+
+        sext_ln38_5_fu_2567_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_68_fu_2562_p2),64));
+
+        sext_ln38_60_fu_3668_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_123_fu_3663_p2),64));
+
+        sext_ln38_61_fu_3678_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_124_fu_3673_p2),64));
+
+        sext_ln38_62_fu_3708_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_125_fu_3703_p2),64));
+
+        sext_ln38_63_fu_3718_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_126_fu_3713_p2),64));
+
+        sext_ln38_64_fu_2517_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_127_fu_2512_p2),64));
+
+        sext_ln38_6_fu_2603_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_69_fu_2598_p2),64));
+
+        sext_ln38_7_fu_2613_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_70_fu_2608_p2),64));
+
+        sext_ln38_8_fu_2638_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_71_fu_2633_p2),64));
+
+        sext_ln38_9_fu_2648_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_72_fu_2643_p2),64));
+
+        sext_ln38_fu_2492_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(j_0_reg_1445),64));
+
+    tmp_10_fu_1709_p3 <= (ap_const_lv27_0 & or_ln38_8_fu_1704_p2);
+    tmp_11_fu_1723_p3 <= (ap_const_lv27_0 & or_ln38_9_fu_1718_p2);
+    tmp_12_fu_1737_p3 <= (ap_const_lv27_0 & or_ln38_10_fu_1732_p2);
+    tmp_13_fu_1751_p3 <= (ap_const_lv27_0 & or_ln38_11_fu_1746_p2);
+    tmp_14_fu_1765_p3 <= (ap_const_lv27_0 & or_ln38_12_fu_1760_p2);
+    tmp_15_fu_1779_p3 <= (ap_const_lv27_0 & or_ln38_13_fu_1774_p2);
+    tmp_16_fu_1793_p3 <= (ap_const_lv27_0 & or_ln38_14_fu_1788_p2);
+    tmp_17_fu_1807_p3 <= (ap_const_lv27_0 & or_ln38_15_fu_1802_p2);
+    tmp_18_fu_1821_p3 <= (ap_const_lv27_0 & or_ln38_16_fu_1816_p2);
+    tmp_19_fu_1835_p3 <= (ap_const_lv27_0 & or_ln38_17_fu_1830_p2);
+    tmp_20_fu_1849_p3 <= (ap_const_lv27_0 & or_ln38_18_fu_1844_p2);
+    tmp_21_fu_1863_p3 <= (ap_const_lv27_0 & or_ln38_19_fu_1858_p2);
+    tmp_22_fu_1877_p3 <= (ap_const_lv27_0 & or_ln38_20_fu_1872_p2);
+    tmp_23_fu_1891_p3 <= (ap_const_lv27_0 & or_ln38_21_fu_1886_p2);
+    tmp_24_fu_1905_p3 <= (ap_const_lv27_0 & or_ln38_22_fu_1900_p2);
+    tmp_25_fu_1919_p3 <= (ap_const_lv27_0 & or_ln38_23_fu_1914_p2);
+    tmp_26_fu_1933_p3 <= (ap_const_lv27_0 & or_ln38_24_fu_1928_p2);
+    tmp_27_fu_1947_p3 <= (ap_const_lv27_0 & or_ln38_25_fu_1942_p2);
+    tmp_28_fu_1961_p3 <= (ap_const_lv27_0 & or_ln38_26_fu_1956_p2);
+    tmp_29_fu_1975_p3 <= (ap_const_lv27_0 & or_ln38_27_fu_1970_p2);
+    tmp_2_fu_1574_p3 <= (i_0_reg_1434 & ap_const_lv6_0);
+    tmp_30_fu_1989_p3 <= (ap_const_lv27_0 & or_ln38_28_fu_1984_p2);
+    tmp_31_fu_2003_p3 <= (ap_const_lv27_0 & or_ln38_29_fu_1998_p2);
+    tmp_32_fu_2017_p3 <= (ap_const_lv27_0 & or_ln38_30_fu_2012_p2);
+    tmp_33_fu_2031_p3 <= (ap_const_lv27_0 & or_ln38_31_fu_2026_p2);
+    tmp_34_fu_2045_p3 <= (ap_const_lv27_0 & or_ln38_32_fu_2040_p2);
+    tmp_35_fu_2059_p3 <= (ap_const_lv27_0 & or_ln38_33_fu_2054_p2);
+    tmp_36_fu_2073_p3 <= (ap_const_lv27_0 & or_ln38_34_fu_2068_p2);
+    tmp_37_fu_2087_p3 <= (ap_const_lv27_0 & or_ln38_35_fu_2082_p2);
+    tmp_38_fu_2101_p3 <= (ap_const_lv27_0 & or_ln38_36_fu_2096_p2);
+    tmp_39_fu_2115_p3 <= (ap_const_lv27_0 & or_ln38_37_fu_2110_p2);
+    tmp_3_fu_1597_p3 <= (ap_const_lv27_0 & or_ln38_fu_1591_p2);
+    tmp_40_fu_2129_p3 <= (ap_const_lv27_0 & or_ln38_38_fu_2124_p2);
+    tmp_41_fu_2143_p3 <= (ap_const_lv27_0 & or_ln38_39_fu_2138_p2);
+    tmp_42_fu_2157_p3 <= (ap_const_lv27_0 & or_ln38_40_fu_2152_p2);
+    tmp_43_fu_2171_p3 <= (ap_const_lv27_0 & or_ln38_41_fu_2166_p2);
+    tmp_44_fu_2185_p3 <= (ap_const_lv27_0 & or_ln38_42_fu_2180_p2);
+    tmp_45_fu_2199_p3 <= (ap_const_lv27_0 & or_ln38_43_fu_2194_p2);
+    tmp_46_fu_2213_p3 <= (ap_const_lv27_0 & or_ln38_44_fu_2208_p2);
+    tmp_47_fu_2227_p3 <= (ap_const_lv27_0 & or_ln38_45_fu_2222_p2);
+    tmp_48_fu_2241_p3 <= (ap_const_lv27_0 & or_ln38_46_fu_2236_p2);
+    tmp_49_fu_2255_p3 <= (ap_const_lv27_0 & or_ln38_47_fu_2250_p2);
+    tmp_4_fu_1611_p3 <= (ap_const_lv27_0 & or_ln38_1_fu_1606_p2);
+    tmp_50_fu_2269_p3 <= (ap_const_lv27_0 & or_ln38_48_fu_2264_p2);
+    tmp_51_fu_2283_p3 <= (ap_const_lv27_0 & or_ln38_49_fu_2278_p2);
+    tmp_52_fu_2297_p3 <= (ap_const_lv27_0 & or_ln38_50_fu_2292_p2);
+    tmp_53_fu_2311_p3 <= (ap_const_lv27_0 & or_ln38_51_fu_2306_p2);
+    tmp_54_fu_2325_p3 <= (ap_const_lv27_0 & or_ln38_52_fu_2320_p2);
+    tmp_55_fu_2339_p3 <= (ap_const_lv27_0 & or_ln38_53_fu_2334_p2);
+    tmp_56_fu_2353_p3 <= (ap_const_lv27_0 & or_ln38_54_fu_2348_p2);
+    tmp_57_fu_2367_p3 <= (ap_const_lv27_0 & or_ln38_55_fu_2362_p2);
+    tmp_58_fu_2381_p3 <= (ap_const_lv27_0 & or_ln38_56_fu_2376_p2);
+    tmp_59_fu_2395_p3 <= (ap_const_lv27_0 & or_ln38_57_fu_2390_p2);
+    tmp_5_fu_1625_p3 <= (ap_const_lv27_0 & or_ln38_2_fu_1620_p2);
+    tmp_60_fu_2409_p3 <= (ap_const_lv27_0 & or_ln38_58_fu_2404_p2);
+    tmp_61_fu_2423_p3 <= (ap_const_lv27_0 & or_ln38_59_fu_2418_p2);
+    tmp_62_fu_2437_p3 <= (ap_const_lv27_0 & or_ln38_60_fu_2432_p2);
+    tmp_63_fu_2451_p3 <= (ap_const_lv27_0 & or_ln38_61_fu_2446_p2);
+    tmp_64_fu_2465_p3 <= (ap_const_lv27_0 & or_ln38_62_fu_2460_p2);
+    tmp_6_fu_1639_p3 <= (ap_const_lv27_0 & or_ln38_3_fu_1634_p2);
+    tmp_7_fu_1653_p3 <= (ap_const_lv27_0 & or_ln38_4_fu_1648_p2);
+    tmp_8_fu_1667_p3 <= (ap_const_lv27_0 & or_ln38_5_fu_1662_p2);
+    tmp_9_fu_1681_p3 <= (ap_const_lv27_0 & or_ln38_6_fu_1676_p2);
+    tmp_s_fu_1695_p3 <= (ap_const_lv27_0 & or_ln38_7_fu_1690_p2);
+    trunc_ln38_1_fu_2497_p1 <= j_0_reg_1445(14 - 1 downto 0);
+    trunc_ln38_fu_1587_p1 <= i_0_reg_1434(8 - 1 downto 0);
+    zext_ln27_fu_1537_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln27_reg_1410_pp0_iter1_reg),64));
+    zext_ln28_fu_1554_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln28_reg_1422_pp1_iter1_reg),64));
+    zext_ln31_fu_1559_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_0_reg_1434),32));
+    zext_ln38_cast_fu_2474_p3 <= (trunc_ln38_reg_3943 & ap_const_lv6_0);
+    zext_ln38_fu_1582_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_fu_1574_p3),64));
+    zext_ln42_fu_3796_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln42_reg_1456),64));
+end behav;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in1_loc.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in1_loc.vhd
new file mode 100755
index 0000000..5825c9a
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in1_loc.vhd
@@ -0,0 +1,146 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_in1_loc_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 12; 
+            MEM_SIZE    : integer := 4096
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce1       : in std_logic; 
+          q1        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_in1_loc_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+signal addr1_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+memory_access_guard_1: process (addr1) 
+begin
+      addr1_tmp <= addr1;
+--synthesis translate_off
+      if (CONV_INTEGER(addr1) > mem_size-1) then
+           addr1_tmp <= (others => '0');
+      else 
+           addr1_tmp <= addr1;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_1: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce1 = '1') then 
+            q1 <= ram(CONV_INTEGER(addr1_tmp));
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_in1_loc is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 4096;
+        AddressWidth : INTEGER := 12);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce1 : IN STD_LOGIC;
+        q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_in1_loc is
+    component mmult_in1_loc_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR;
+            addr1 : IN STD_LOGIC_VECTOR;
+            ce1 : IN STD_LOGIC;
+            q1 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_in1_loc_ram_U :  component mmult_in1_loc_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0,
+        addr1 => address1,
+        ce1 => ce1,
+        q1 => q1);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in1_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in1_mem_m_axi.vhd
new file mode 100755
index 0000000..5d4f5b4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in1_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi;
+
+architecture behave of mmult_in1_mem_m_axi is
+    component mmult_in1_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_write;
+
+    component mmult_in1_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_read;
+
+    component mmult_in1_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in1_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in1_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in1_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in1_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in1_mem_m_axi_fifo;
+
+architecture behave of mmult_in1_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in1_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in1_mem_m_axi_decoder;
+
+architecture behav of mmult_in1_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in1_mem_m_axi_throttl;
+
+architecture behav of mmult_in1_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in1_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in1_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_read;
+
+architecture behave of mmult_in1_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_write;
+
+architecture behave of mmult_in1_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in1_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in1_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in2_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in2_mem_m_axi.vhd
new file mode 100755
index 0000000..84687e2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_in2_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi;
+
+architecture behave of mmult_in2_mem_m_axi is
+    component mmult_in2_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_write;
+
+    component mmult_in2_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_read;
+
+    component mmult_in2_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in2_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in2_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in2_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in2_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in2_mem_m_axi_fifo;
+
+architecture behave of mmult_in2_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in2_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in2_mem_m_axi_decoder;
+
+architecture behav of mmult_in2_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in2_mem_m_axi_throttl;
+
+architecture behav of mmult_in2_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in2_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in2_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_read;
+
+architecture behave of mmult_in2_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_write;
+
+architecture behave of mmult_in2_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in2_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in2_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_out_loc.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_out_loc.vhd
new file mode 100755
index 0000000..ec49d88
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_out_loc.vhd
@@ -0,0 +1,112 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_out_loc_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 12; 
+            MEM_SIZE    : integer := 4096
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_out_loc_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_out_loc is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 4096;
+        AddressWidth : INTEGER := 12);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_out_loc is
+    component mmult_out_loc_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_out_loc_ram_U :  component mmult_out_loc_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_out_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_out_mem_m_axi.vhd
new file mode 100755
index 0000000..f2bd717
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_out_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi;
+
+architecture behave of mmult_out_mem_m_axi is
+    component mmult_out_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_write;
+
+    component mmult_out_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_read;
+
+    component mmult_out_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_out_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_out_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_out_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi_reg_slice;
+
+architecture behave of mmult_out_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_out_mem_m_axi_fifo;
+
+architecture behave of mmult_out_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_out_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_out_mem_m_axi_decoder;
+
+architecture behav of mmult_out_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_out_mem_m_axi_throttl;
+
+architecture behav of mmult_out_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_out_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_out_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_read;
+
+architecture behave of mmult_out_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_write;
+
+architecture behave of mmult_out_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_out_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_out_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_params_s_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_params_s_axi.vhd
new file mode 100755
index 0000000..1f9adde
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/vhdl/mmult_params_s_axi.vhd
@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/misc/logo.png b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/misc/logo.png
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diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/xgui/mmult_v4_0.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/xgui/mmult_v4_0.tcl
new file mode 100755
index 0000000..0276fbf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_5/xgui/mmult_v4_0.tcl
@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/component.xml b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/component.xml
new file mode 100755
index 0000000..1769670
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/component.xml
@@ -0,0 +1,5578 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>hls</spirit:library>
+  <spirit:name>mmult</spirit:name>
+  <spirit:version>6.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_params"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.ADDR_WIDTH">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi_params:m_axi_in1_mem:m_axi_in2_mem:m_axi_out_mem</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interrupt</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in1_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in1_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in2_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in2_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_out_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_out_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in1_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in2_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_out_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_BASE_PARAM">C_S_AXI_PARAMS_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_HIGH_PARAM">C_S_AXI_PARAMS_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>CTRL</spirit:name>
+          <spirit:displayName>CTRL</spirit:displayName>
+          <spirit:description>Control signals</spirit:description>
+          <spirit:addressOffset>0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>AP_START</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_start&apos;.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_DONE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_done&apos;.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_IDLE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_idle&apos;.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_READY</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_ready&apos;.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_1</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">3</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AUTO_RESTART</spirit:name>
+            <spirit:description>Control signal Register for &apos;auto_restart&apos;.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_2</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">24</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+        <spirit:register>
+          <spirit:name>GIER</spirit:name>
+          <spirit:displayName>GIER</spirit:displayName>
+          <spirit:description>Global Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>4</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Enable</spirit:name>
+            <spirit:description>Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">31</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
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+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+        <spirit:register>
+          <spirit:name>IP_IER</spirit:name>
+          <spirit:displayName>IP_IER</spirit:displayName>
+          <spirit:description>IP Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>8</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+          <spirit:field>
+            <spirit:name>CHAN0_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 0 (ap_done) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
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+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:field>
+            <spirit:name>CHAN1_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 1 (ap_ready) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
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+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
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+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
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+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+        <spirit:register>
+          <spirit:name>IP_ISR</spirit:name>
+          <spirit:displayName>IP_ISR</spirit:displayName>
+          <spirit:description>IP Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>12</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
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+          <spirit:field>
+            <spirit:name>CHAN0_INT_ST</spirit:name>
+            <spirit:description>Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 input interrupt, 1 = Channel 0 input interrup</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
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+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
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+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
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+            <spirit:name>CHAN1_INT_ST</spirit:name>
+            <spirit:description>Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 input interrupt, 1 = Channel 1 input interrup</spirit:description>
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+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
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+            <spirit:readAction>modify</spirit:readAction>
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+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
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+            <spirit:description>Bit 31 to 0 Data signal of in1</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
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+        <spirit:name>hdl/verilog/mmult.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
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+        <spirit:userFileType>driver_mdd</spirit:userFileType>
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+      <spirit:file>
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+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="16" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" spirit:order="17" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH" spirit:order="18" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH" spirit:order="19" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH" spirit:order="20" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH" spirit:order="21" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH" spirit:order="22" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE" spirit:order="23" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE" spirit:order="24" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE" spirit:order="25" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" spirit:order="26" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH" spirit:order="27" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="28" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" spirit:order="29" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH" spirit:order="30" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH" spirit:order="31" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH" spirit:order="32" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH" spirit:order="33" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH" spirit:order="34" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE" spirit:order="35" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE" spirit:order="36" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE" spirit:order="37" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mmult_v6_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>clk_period</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.clk_period" spirit:order="38">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>machine</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.machine" spirit:order="39">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>combinational</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.combinational" spirit:order="40">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>latency</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.latency" spirit:order="41">24795</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>II</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.II" spirit:order="42">x</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/VIVADO_HLS_IP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>Mmult</xilinx:displayName>
+      <xilinx:definitionSource>HLS</xilinx:definitionSource>
+      <xilinx:coreRevision>2105141710</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2021-05-14T15:10:43Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b5dd57e8"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="c6fd4807"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5ce530f0"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0a6a9917"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="7681d788"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c9a673dd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="37a14001"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/constraints/mmult_ooc.xdc b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/constraints/mmult_ooc.xdc
new file mode 100755
index 0000000..2ed5eee
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/constraints/mmult_ooc.xdc
@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/doc/ReleaseNotes.txt b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/doc/ReleaseNotes.txt
new file mode 100755
index 0000000..48cc01b
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/doc/ReleaseNotes.txt
@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/data/mmult.mdd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/data/mmult.mdd
new file mode 100755
index 0000000..a8aa677
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/data/mmult.mdd
@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v6_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 6.0;
+
+END driver
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/data/mmult.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/data/mmult.tcl
new file mode 100755
index 0000000..0de7a9c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/data/mmult.tcl
@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/Makefile b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/Makefile
new file mode 100755
index 0000000..7f76086
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/Makefile
@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult.c
new file mode 100755
index 0000000..fb9a1fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult.c
@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult.h
new file mode 100755
index 0000000..4983669
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult.h
@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_hw.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_hw.h
new file mode 100755
index 0000000..3a0a2a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_hw.h
@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_linux.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_linux.c
new file mode 100755
index 0000000..c8dbb33
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_linux.c
@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_sinit.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_sinit.c
new file mode 100755
index 0000000..f099590
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/drivers/mmult_v6_0/src/xmmult_sinit.c
@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult.v
new file mode 100755
index 0000000..228e881
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult.v
@@ -0,0 +1,8117 @@
+// ==============================================================
+// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+// Version: 2020.1
+// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+// 
+// ===========================================================
+
+`timescale 1 ns / 1 ps 
+
+(* CORE_GENERATION_INFO="mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=24795,HLS_SYN_TPT=none,HLS_SYN_MEM=142,HLS_SYN_DSP=192,HLS_SYN_FF=4685,HLS_SYN_LUT=8017,HLS_VERSION=2020_1}" *)
+
+module mmult (
+        ap_clk,
+        ap_rst_n,
+        m_axi_in1_mem_AWVALID,
+        m_axi_in1_mem_AWREADY,
+        m_axi_in1_mem_AWADDR,
+        m_axi_in1_mem_AWID,
+        m_axi_in1_mem_AWLEN,
+        m_axi_in1_mem_AWSIZE,
+        m_axi_in1_mem_AWBURST,
+        m_axi_in1_mem_AWLOCK,
+        m_axi_in1_mem_AWCACHE,
+        m_axi_in1_mem_AWPROT,
+        m_axi_in1_mem_AWQOS,
+        m_axi_in1_mem_AWREGION,
+        m_axi_in1_mem_AWUSER,
+        m_axi_in1_mem_WVALID,
+        m_axi_in1_mem_WREADY,
+        m_axi_in1_mem_WDATA,
+        m_axi_in1_mem_WSTRB,
+        m_axi_in1_mem_WLAST,
+        m_axi_in1_mem_WID,
+        m_axi_in1_mem_WUSER,
+        m_axi_in1_mem_ARVALID,
+        m_axi_in1_mem_ARREADY,
+        m_axi_in1_mem_ARADDR,
+        m_axi_in1_mem_ARID,
+        m_axi_in1_mem_ARLEN,
+        m_axi_in1_mem_ARSIZE,
+        m_axi_in1_mem_ARBURST,
+        m_axi_in1_mem_ARLOCK,
+        m_axi_in1_mem_ARCACHE,
+        m_axi_in1_mem_ARPROT,
+        m_axi_in1_mem_ARQOS,
+        m_axi_in1_mem_ARREGION,
+        m_axi_in1_mem_ARUSER,
+        m_axi_in1_mem_RVALID,
+        m_axi_in1_mem_RREADY,
+        m_axi_in1_mem_RDATA,
+        m_axi_in1_mem_RLAST,
+        m_axi_in1_mem_RID,
+        m_axi_in1_mem_RUSER,
+        m_axi_in1_mem_RRESP,
+        m_axi_in1_mem_BVALID,
+        m_axi_in1_mem_BREADY,
+        m_axi_in1_mem_BRESP,
+        m_axi_in1_mem_BID,
+        m_axi_in1_mem_BUSER,
+        m_axi_in2_mem_AWVALID,
+        m_axi_in2_mem_AWREADY,
+        m_axi_in2_mem_AWADDR,
+        m_axi_in2_mem_AWID,
+        m_axi_in2_mem_AWLEN,
+        m_axi_in2_mem_AWSIZE,
+        m_axi_in2_mem_AWBURST,
+        m_axi_in2_mem_AWLOCK,
+        m_axi_in2_mem_AWCACHE,
+        m_axi_in2_mem_AWPROT,
+        m_axi_in2_mem_AWQOS,
+        m_axi_in2_mem_AWREGION,
+        m_axi_in2_mem_AWUSER,
+        m_axi_in2_mem_WVALID,
+        m_axi_in2_mem_WREADY,
+        m_axi_in2_mem_WDATA,
+        m_axi_in2_mem_WSTRB,
+        m_axi_in2_mem_WLAST,
+        m_axi_in2_mem_WID,
+        m_axi_in2_mem_WUSER,
+        m_axi_in2_mem_ARVALID,
+        m_axi_in2_mem_ARREADY,
+        m_axi_in2_mem_ARADDR,
+        m_axi_in2_mem_ARID,
+        m_axi_in2_mem_ARLEN,
+        m_axi_in2_mem_ARSIZE,
+        m_axi_in2_mem_ARBURST,
+        m_axi_in2_mem_ARLOCK,
+        m_axi_in2_mem_ARCACHE,
+        m_axi_in2_mem_ARPROT,
+        m_axi_in2_mem_ARQOS,
+        m_axi_in2_mem_ARREGION,
+        m_axi_in2_mem_ARUSER,
+        m_axi_in2_mem_RVALID,
+        m_axi_in2_mem_RREADY,
+        m_axi_in2_mem_RDATA,
+        m_axi_in2_mem_RLAST,
+        m_axi_in2_mem_RID,
+        m_axi_in2_mem_RUSER,
+        m_axi_in2_mem_RRESP,
+        m_axi_in2_mem_BVALID,
+        m_axi_in2_mem_BREADY,
+        m_axi_in2_mem_BRESP,
+        m_axi_in2_mem_BID,
+        m_axi_in2_mem_BUSER,
+        m_axi_out_mem_AWVALID,
+        m_axi_out_mem_AWREADY,
+        m_axi_out_mem_AWADDR,
+        m_axi_out_mem_AWID,
+        m_axi_out_mem_AWLEN,
+        m_axi_out_mem_AWSIZE,
+        m_axi_out_mem_AWBURST,
+        m_axi_out_mem_AWLOCK,
+        m_axi_out_mem_AWCACHE,
+        m_axi_out_mem_AWPROT,
+        m_axi_out_mem_AWQOS,
+        m_axi_out_mem_AWREGION,
+        m_axi_out_mem_AWUSER,
+        m_axi_out_mem_WVALID,
+        m_axi_out_mem_WREADY,
+        m_axi_out_mem_WDATA,
+        m_axi_out_mem_WSTRB,
+        m_axi_out_mem_WLAST,
+        m_axi_out_mem_WID,
+        m_axi_out_mem_WUSER,
+        m_axi_out_mem_ARVALID,
+        m_axi_out_mem_ARREADY,
+        m_axi_out_mem_ARADDR,
+        m_axi_out_mem_ARID,
+        m_axi_out_mem_ARLEN,
+        m_axi_out_mem_ARSIZE,
+        m_axi_out_mem_ARBURST,
+        m_axi_out_mem_ARLOCK,
+        m_axi_out_mem_ARCACHE,
+        m_axi_out_mem_ARPROT,
+        m_axi_out_mem_ARQOS,
+        m_axi_out_mem_ARREGION,
+        m_axi_out_mem_ARUSER,
+        m_axi_out_mem_RVALID,
+        m_axi_out_mem_RREADY,
+        m_axi_out_mem_RDATA,
+        m_axi_out_mem_RLAST,
+        m_axi_out_mem_RID,
+        m_axi_out_mem_RUSER,
+        m_axi_out_mem_RRESP,
+        m_axi_out_mem_BVALID,
+        m_axi_out_mem_BREADY,
+        m_axi_out_mem_BRESP,
+        m_axi_out_mem_BID,
+        m_axi_out_mem_BUSER,
+        s_axi_params_AWVALID,
+        s_axi_params_AWREADY,
+        s_axi_params_AWADDR,
+        s_axi_params_WVALID,
+        s_axi_params_WREADY,
+        s_axi_params_WDATA,
+        s_axi_params_WSTRB,
+        s_axi_params_ARVALID,
+        s_axi_params_ARREADY,
+        s_axi_params_ARADDR,
+        s_axi_params_RVALID,
+        s_axi_params_RREADY,
+        s_axi_params_RDATA,
+        s_axi_params_RRESP,
+        s_axi_params_BVALID,
+        s_axi_params_BREADY,
+        s_axi_params_BRESP,
+        interrupt
+);
+
+parameter    ap_ST_fsm_state1 = 29'd1;
+parameter    ap_ST_fsm_state2 = 29'd2;
+parameter    ap_ST_fsm_state3 = 29'd4;
+parameter    ap_ST_fsm_state4 = 29'd8;
+parameter    ap_ST_fsm_state5 = 29'd16;
+parameter    ap_ST_fsm_state6 = 29'd32;
+parameter    ap_ST_fsm_state7 = 29'd64;
+parameter    ap_ST_fsm_state8 = 29'd128;
+parameter    ap_ST_fsm_pp0_stage0 = 29'd256;
+parameter    ap_ST_fsm_state12 = 29'd512;
+parameter    ap_ST_fsm_state13 = 29'd1024;
+parameter    ap_ST_fsm_state14 = 29'd2048;
+parameter    ap_ST_fsm_state15 = 29'd4096;
+parameter    ap_ST_fsm_state16 = 29'd8192;
+parameter    ap_ST_fsm_state17 = 29'd16384;
+parameter    ap_ST_fsm_state18 = 29'd32768;
+parameter    ap_ST_fsm_pp1_stage0 = 29'd65536;
+parameter    ap_ST_fsm_state22 = 29'd131072;
+parameter    ap_ST_fsm_state23 = 29'd262144;
+parameter    ap_ST_fsm_state24 = 29'd524288;
+parameter    ap_ST_fsm_state25 = 29'd1048576;
+parameter    ap_ST_fsm_state26 = 29'd2097152;
+parameter    ap_ST_fsm_state27 = 29'd4194304;
+parameter    ap_ST_fsm_pp2_stage0 = 29'd8388608;
+parameter    ap_ST_fsm_state31 = 29'd16777216;
+parameter    ap_ST_fsm_state32 = 29'd33554432;
+parameter    ap_ST_fsm_state33 = 29'd67108864;
+parameter    ap_ST_fsm_state34 = 29'd134217728;
+parameter    ap_ST_fsm_state35 = 29'd268435456;
+parameter    C_S_AXI_PARAMS_DATA_WIDTH = 32;
+parameter    C_S_AXI_PARAMS_ADDR_WIDTH = 6;
+parameter    C_S_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_OUT_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_CACHE_VALUE = 3;
+
+parameter C_S_AXI_PARAMS_WSTRB_WIDTH = (32 / 8);
+parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN1_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN2_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_OUT_MEM_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+output   m_axi_in1_mem_AWVALID;
+input   m_axi_in1_mem_AWREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_AWADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_AWID;
+output  [7:0] m_axi_in1_mem_AWLEN;
+output  [2:0] m_axi_in1_mem_AWSIZE;
+output  [1:0] m_axi_in1_mem_AWBURST;
+output  [1:0] m_axi_in1_mem_AWLOCK;
+output  [3:0] m_axi_in1_mem_AWCACHE;
+output  [2:0] m_axi_in1_mem_AWPROT;
+output  [3:0] m_axi_in1_mem_AWQOS;
+output  [3:0] m_axi_in1_mem_AWREGION;
+output  [C_M_AXI_IN1_MEM_AWUSER_WIDTH - 1:0] m_axi_in1_mem_AWUSER;
+output   m_axi_in1_mem_WVALID;
+input   m_axi_in1_mem_WREADY;
+output  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_WDATA;
+output  [C_M_AXI_IN1_MEM_WSTRB_WIDTH - 1:0] m_axi_in1_mem_WSTRB;
+output   m_axi_in1_mem_WLAST;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_WID;
+output  [C_M_AXI_IN1_MEM_WUSER_WIDTH - 1:0] m_axi_in1_mem_WUSER;
+output   m_axi_in1_mem_ARVALID;
+input   m_axi_in1_mem_ARREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_ARADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_ARID;
+output  [7:0] m_axi_in1_mem_ARLEN;
+output  [2:0] m_axi_in1_mem_ARSIZE;
+output  [1:0] m_axi_in1_mem_ARBURST;
+output  [1:0] m_axi_in1_mem_ARLOCK;
+output  [3:0] m_axi_in1_mem_ARCACHE;
+output  [2:0] m_axi_in1_mem_ARPROT;
+output  [3:0] m_axi_in1_mem_ARQOS;
+output  [3:0] m_axi_in1_mem_ARREGION;
+output  [C_M_AXI_IN1_MEM_ARUSER_WIDTH - 1:0] m_axi_in1_mem_ARUSER;
+input   m_axi_in1_mem_RVALID;
+output   m_axi_in1_mem_RREADY;
+input  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_RDATA;
+input   m_axi_in1_mem_RLAST;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_RID;
+input  [C_M_AXI_IN1_MEM_RUSER_WIDTH - 1:0] m_axi_in1_mem_RUSER;
+input  [1:0] m_axi_in1_mem_RRESP;
+input   m_axi_in1_mem_BVALID;
+output   m_axi_in1_mem_BREADY;
+input  [1:0] m_axi_in1_mem_BRESP;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_BID;
+input  [C_M_AXI_IN1_MEM_BUSER_WIDTH - 1:0] m_axi_in1_mem_BUSER;
+output   m_axi_in2_mem_AWVALID;
+input   m_axi_in2_mem_AWREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_AWADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_AWID;
+output  [7:0] m_axi_in2_mem_AWLEN;
+output  [2:0] m_axi_in2_mem_AWSIZE;
+output  [1:0] m_axi_in2_mem_AWBURST;
+output  [1:0] m_axi_in2_mem_AWLOCK;
+output  [3:0] m_axi_in2_mem_AWCACHE;
+output  [2:0] m_axi_in2_mem_AWPROT;
+output  [3:0] m_axi_in2_mem_AWQOS;
+output  [3:0] m_axi_in2_mem_AWREGION;
+output  [C_M_AXI_IN2_MEM_AWUSER_WIDTH - 1:0] m_axi_in2_mem_AWUSER;
+output   m_axi_in2_mem_WVALID;
+input   m_axi_in2_mem_WREADY;
+output  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_WDATA;
+output  [C_M_AXI_IN2_MEM_WSTRB_WIDTH - 1:0] m_axi_in2_mem_WSTRB;
+output   m_axi_in2_mem_WLAST;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_WID;
+output  [C_M_AXI_IN2_MEM_WUSER_WIDTH - 1:0] m_axi_in2_mem_WUSER;
+output   m_axi_in2_mem_ARVALID;
+input   m_axi_in2_mem_ARREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_ARADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_ARID;
+output  [7:0] m_axi_in2_mem_ARLEN;
+output  [2:0] m_axi_in2_mem_ARSIZE;
+output  [1:0] m_axi_in2_mem_ARBURST;
+output  [1:0] m_axi_in2_mem_ARLOCK;
+output  [3:0] m_axi_in2_mem_ARCACHE;
+output  [2:0] m_axi_in2_mem_ARPROT;
+output  [3:0] m_axi_in2_mem_ARQOS;
+output  [3:0] m_axi_in2_mem_ARREGION;
+output  [C_M_AXI_IN2_MEM_ARUSER_WIDTH - 1:0] m_axi_in2_mem_ARUSER;
+input   m_axi_in2_mem_RVALID;
+output   m_axi_in2_mem_RREADY;
+input  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_RDATA;
+input   m_axi_in2_mem_RLAST;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_RID;
+input  [C_M_AXI_IN2_MEM_RUSER_WIDTH - 1:0] m_axi_in2_mem_RUSER;
+input  [1:0] m_axi_in2_mem_RRESP;
+input   m_axi_in2_mem_BVALID;
+output   m_axi_in2_mem_BREADY;
+input  [1:0] m_axi_in2_mem_BRESP;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_BID;
+input  [C_M_AXI_IN2_MEM_BUSER_WIDTH - 1:0] m_axi_in2_mem_BUSER;
+output   m_axi_out_mem_AWVALID;
+input   m_axi_out_mem_AWREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_AWADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_AWID;
+output  [7:0] m_axi_out_mem_AWLEN;
+output  [2:0] m_axi_out_mem_AWSIZE;
+output  [1:0] m_axi_out_mem_AWBURST;
+output  [1:0] m_axi_out_mem_AWLOCK;
+output  [3:0] m_axi_out_mem_AWCACHE;
+output  [2:0] m_axi_out_mem_AWPROT;
+output  [3:0] m_axi_out_mem_AWQOS;
+output  [3:0] m_axi_out_mem_AWREGION;
+output  [C_M_AXI_OUT_MEM_AWUSER_WIDTH - 1:0] m_axi_out_mem_AWUSER;
+output   m_axi_out_mem_WVALID;
+input   m_axi_out_mem_WREADY;
+output  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_WDATA;
+output  [C_M_AXI_OUT_MEM_WSTRB_WIDTH - 1:0] m_axi_out_mem_WSTRB;
+output   m_axi_out_mem_WLAST;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_WID;
+output  [C_M_AXI_OUT_MEM_WUSER_WIDTH - 1:0] m_axi_out_mem_WUSER;
+output   m_axi_out_mem_ARVALID;
+input   m_axi_out_mem_ARREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_ARADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_ARID;
+output  [7:0] m_axi_out_mem_ARLEN;
+output  [2:0] m_axi_out_mem_ARSIZE;
+output  [1:0] m_axi_out_mem_ARBURST;
+output  [1:0] m_axi_out_mem_ARLOCK;
+output  [3:0] m_axi_out_mem_ARCACHE;
+output  [2:0] m_axi_out_mem_ARPROT;
+output  [3:0] m_axi_out_mem_ARQOS;
+output  [3:0] m_axi_out_mem_ARREGION;
+output  [C_M_AXI_OUT_MEM_ARUSER_WIDTH - 1:0] m_axi_out_mem_ARUSER;
+input   m_axi_out_mem_RVALID;
+output   m_axi_out_mem_RREADY;
+input  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_RDATA;
+input   m_axi_out_mem_RLAST;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_RID;
+input  [C_M_AXI_OUT_MEM_RUSER_WIDTH - 1:0] m_axi_out_mem_RUSER;
+input  [1:0] m_axi_out_mem_RRESP;
+input   m_axi_out_mem_BVALID;
+output   m_axi_out_mem_BREADY;
+input  [1:0] m_axi_out_mem_BRESP;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_BID;
+input  [C_M_AXI_OUT_MEM_BUSER_WIDTH - 1:0] m_axi_out_mem_BUSER;
+input   s_axi_params_AWVALID;
+output   s_axi_params_AWREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_AWADDR;
+input   s_axi_params_WVALID;
+output   s_axi_params_WREADY;
+input  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_WDATA;
+input  [C_S_AXI_PARAMS_WSTRB_WIDTH - 1:0] s_axi_params_WSTRB;
+input   s_axi_params_ARVALID;
+output   s_axi_params_ARREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_ARADDR;
+output   s_axi_params_RVALID;
+input   s_axi_params_RREADY;
+output  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_RDATA;
+output  [1:0] s_axi_params_RRESP;
+output   s_axi_params_BVALID;
+input   s_axi_params_BREADY;
+output  [1:0] s_axi_params_BRESP;
+output   interrupt;
+
+ reg    ap_rst_n_inv;
+wire    ap_start;
+reg    ap_done;
+reg    ap_idle;
+(* fsm_encoding = "none" *) reg   [28:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    ap_ready;
+wire   [31:0] in1;
+wire   [31:0] in2;
+wire   [31:0] out_r;
+wire   [31:0] dim;
+reg    in1_mem_blk_n_AR;
+wire    ap_CS_fsm_state2;
+reg    in1_mem_blk_n_R;
+wire    ap_CS_fsm_pp0_stage0;
+reg    ap_enable_reg_pp0_iter1;
+wire    ap_block_pp0_stage0;
+reg    in2_mem_blk_n_AR;
+wire    ap_CS_fsm_state12;
+reg    in2_mem_blk_n_R;
+wire    ap_CS_fsm_pp1_stage0;
+reg    ap_enable_reg_pp1_iter1;
+wire    ap_block_pp1_stage0;
+reg    out_mem_blk_n_AW;
+wire    ap_CS_fsm_state23;
+wire   [0:0] icmp_ln31_fu_3598_p2;
+reg    out_mem_blk_n_W;
+reg    ap_enable_reg_pp2_iter2;
+wire    ap_block_pp2_stage0;
+reg   [0:0] icmp_ln42_reg_5750;
+reg   [0:0] icmp_ln42_reg_5750_pp2_iter1_reg;
+reg    out_mem_blk_n_B;
+wire    ap_CS_fsm_state35;
+wire    in1_mem_AWREADY;
+wire    in1_mem_WREADY;
+reg    in1_mem_ARVALID;
+wire    in1_mem_ARREADY;
+wire   [31:0] in1_mem_ARADDR;
+wire    in1_mem_RVALID;
+reg    in1_mem_RREADY;
+wire   [31:0] in1_mem_RDATA;
+wire    in1_mem_RLAST;
+wire   [0:0] in1_mem_RID;
+wire   [0:0] in1_mem_RUSER;
+wire   [1:0] in1_mem_RRESP;
+wire    in1_mem_BVALID;
+wire   [1:0] in1_mem_BRESP;
+wire   [0:0] in1_mem_BID;
+wire   [0:0] in1_mem_BUSER;
+wire    in2_mem_AWREADY;
+wire    in2_mem_WREADY;
+reg    in2_mem_ARVALID;
+wire    in2_mem_ARREADY;
+wire    in2_mem_RVALID;
+reg    in2_mem_RREADY;
+wire   [31:0] in2_mem_RDATA;
+wire    in2_mem_RLAST;
+wire   [0:0] in2_mem_RID;
+wire   [0:0] in2_mem_RUSER;
+wire   [1:0] in2_mem_RRESP;
+wire    in2_mem_BVALID;
+wire   [1:0] in2_mem_BRESP;
+wire   [0:0] in2_mem_BID;
+wire   [0:0] in2_mem_BUSER;
+reg    out_mem_AWVALID;
+wire    out_mem_AWREADY;
+reg    out_mem_WVALID;
+wire    out_mem_WREADY;
+wire    out_mem_ARREADY;
+wire    out_mem_RVALID;
+wire   [31:0] out_mem_RDATA;
+wire    out_mem_RLAST;
+wire   [0:0] out_mem_RID;
+wire   [0:0] out_mem_RUSER;
+wire   [1:0] out_mem_RRESP;
+wire    out_mem_BVALID;
+reg    out_mem_BREADY;
+wire   [1:0] out_mem_BRESP;
+wire   [0:0] out_mem_BID;
+wire   [0:0] out_mem_BUSER;
+reg   [12:0] phi_ln27_reg_3295;
+reg   [12:0] phi_ln28_reg_3306;
+reg   [12:0] phi_ln42_reg_3339;
+reg   [31:0] dim_read_reg_4492;
+reg   [29:0] out5_reg_4498;
+reg   [29:0] in_reg_4503;
+reg   [29:0] in3_reg_4508;
+reg   [31:0] out_mem_addr_reg_4519;
+wire    ap_CS_fsm_state8;
+reg   [31:0] in2_mem_addr_reg_4525;
+wire   [0:0] icmp_ln27_fu_3408_p2;
+wire    ap_block_state9_pp0_stage0_iter0;
+reg    ap_block_state10_pp0_stage0_iter1;
+wire    ap_block_state11_pp0_stage0_iter2;
+reg    ap_block_pp0_stage0_11001;
+wire   [12:0] add_ln27_fu_3414_p2;
+reg    ap_enable_reg_pp0_iter0;
+reg   [6:0] lshr_ln_reg_4540;
+reg   [6:0] lshr_ln_reg_4540_pp0_iter1_reg;
+wire   [5:0] trunc_ln27_fu_3430_p1;
+reg   [5:0] trunc_ln27_reg_4545;
+reg   [5:0] trunc_ln27_reg_4545_pp0_iter1_reg;
+reg   [31:0] in1_mem_addr_read_reg_4549;
+wire   [0:0] icmp_ln28_fu_3501_p2;
+wire    ap_block_state19_pp1_stage0_iter0;
+reg    ap_block_state20_pp1_stage0_iter1;
+wire    ap_block_state21_pp1_stage0_iter2;
+reg    ap_block_pp1_stage0_11001;
+wire   [12:0] add_ln28_fu_3507_p2;
+reg    ap_enable_reg_pp1_iter0;
+wire   [5:0] trunc_ln28_fu_3513_p1;
+reg   [5:0] trunc_ln28_reg_4626;
+reg   [5:0] trunc_ln28_reg_4626_pp1_iter1_reg;
+reg   [5:0] trunc_ln1_reg_4631;
+reg   [5:0] trunc_ln1_reg_4631_pp1_iter1_reg;
+reg   [31:0] in2_mem_addr_read_reg_4635;
+reg    ap_block_state23_io;
+wire   [30:0] i_fu_3603_p2;
+reg   [30:0] i_reg_4707;
+wire   [7:0] trunc_ln38_fu_3677_p1;
+reg   [7:0] trunc_ln38_reg_4712;
+wire   [13:0] zext_ln38_1_cast_fu_3681_p3;
+reg   [13:0] zext_ln38_1_cast_reg_5037;
+wire    ap_CS_fsm_state24;
+wire   [31:0] in1_loc_0_q0;
+reg  signed [31:0] in1_loc_0_load_reg_5042;
+wire   [31:0] in1_loc_1_q0;
+reg  signed [31:0] in1_loc_1_load_reg_5047;
+wire   [31:0] in1_loc_2_q0;
+reg  signed [31:0] in1_loc_2_load_reg_5052;
+wire   [31:0] in1_loc_3_q0;
+reg  signed [31:0] in1_loc_3_load_reg_5057;
+wire   [31:0] in1_loc_4_q0;
+reg  signed [31:0] in1_loc_4_load_reg_5062;
+wire   [31:0] in1_loc_5_q0;
+reg  signed [31:0] in1_loc_5_load_reg_5067;
+wire   [31:0] in1_loc_6_q0;
+reg  signed [31:0] in1_loc_6_load_reg_5072;
+wire   [31:0] in1_loc_7_q0;
+reg  signed [31:0] in1_loc_7_load_reg_5077;
+wire   [31:0] in1_loc_8_q0;
+reg  signed [31:0] in1_loc_8_load_reg_5082;
+wire   [31:0] in1_loc_9_q0;
+reg  signed [31:0] in1_loc_9_load_reg_5087;
+wire   [31:0] in1_loc_10_q0;
+reg  signed [31:0] in1_loc_10_load_reg_5092;
+wire   [31:0] in1_loc_11_q0;
+reg  signed [31:0] in1_loc_11_load_reg_5097;
+wire   [31:0] in1_loc_12_q0;
+reg  signed [31:0] in1_loc_12_load_reg_5102;
+wire   [31:0] in1_loc_13_q0;
+reg  signed [31:0] in1_loc_13_load_reg_5107;
+wire   [31:0] in1_loc_14_q0;
+reg  signed [31:0] in1_loc_14_load_reg_5112;
+wire   [31:0] in1_loc_15_q0;
+reg  signed [31:0] in1_loc_15_load_reg_5117;
+wire   [31:0] in1_loc_16_q0;
+reg  signed [31:0] in1_loc_16_load_reg_5122;
+wire   [31:0] in1_loc_17_q0;
+reg  signed [31:0] in1_loc_17_load_reg_5127;
+wire   [31:0] in1_loc_18_q0;
+reg  signed [31:0] in1_loc_18_load_reg_5132;
+wire   [31:0] in1_loc_19_q0;
+reg  signed [31:0] in1_loc_19_load_reg_5137;
+wire   [31:0] in1_loc_20_q0;
+reg  signed [31:0] in1_loc_20_load_reg_5142;
+wire   [31:0] in1_loc_21_q0;
+reg  signed [31:0] in1_loc_21_load_reg_5147;
+wire   [31:0] in1_loc_22_q0;
+reg  signed [31:0] in1_loc_22_load_reg_5152;
+wire   [31:0] in1_loc_23_q0;
+reg  signed [31:0] in1_loc_23_load_reg_5157;
+wire   [31:0] in1_loc_24_q0;
+reg  signed [31:0] in1_loc_24_load_reg_5162;
+wire   [31:0] in1_loc_25_q0;
+reg  signed [31:0] in1_loc_25_load_reg_5167;
+wire   [31:0] in1_loc_26_q0;
+reg  signed [31:0] in1_loc_26_load_reg_5172;
+wire   [31:0] in1_loc_27_q0;
+reg  signed [31:0] in1_loc_27_load_reg_5177;
+wire   [31:0] in1_loc_28_q0;
+reg  signed [31:0] in1_loc_28_load_reg_5182;
+wire   [31:0] in1_loc_29_q0;
+reg  signed [31:0] in1_loc_29_load_reg_5187;
+wire   [31:0] in1_loc_30_q0;
+reg  signed [31:0] in1_loc_30_load_reg_5192;
+wire   [31:0] in1_loc_31_q0;
+reg  signed [31:0] in1_loc_31_load_reg_5197;
+wire   [31:0] in1_loc_32_q0;
+reg  signed [31:0] in1_loc_32_load_reg_5202;
+wire   [31:0] in1_loc_33_q0;
+reg  signed [31:0] in1_loc_33_load_reg_5207;
+wire   [31:0] in1_loc_34_q0;
+reg  signed [31:0] in1_loc_34_load_reg_5212;
+wire   [31:0] in1_loc_35_q0;
+reg  signed [31:0] in1_loc_35_load_reg_5217;
+wire   [31:0] in1_loc_36_q0;
+reg  signed [31:0] in1_loc_36_load_reg_5222;
+wire   [31:0] in1_loc_37_q0;
+reg  signed [31:0] in1_loc_37_load_reg_5227;
+wire   [31:0] in1_loc_38_q0;
+reg  signed [31:0] in1_loc_38_load_reg_5232;
+wire   [31:0] in1_loc_39_q0;
+reg  signed [31:0] in1_loc_39_load_reg_5237;
+wire   [31:0] in1_loc_40_q0;
+reg  signed [31:0] in1_loc_40_load_reg_5242;
+wire   [31:0] in1_loc_41_q0;
+reg  signed [31:0] in1_loc_41_load_reg_5247;
+wire   [31:0] in1_loc_42_q0;
+reg  signed [31:0] in1_loc_42_load_reg_5252;
+wire   [31:0] in1_loc_43_q0;
+reg  signed [31:0] in1_loc_43_load_reg_5257;
+wire   [31:0] in1_loc_44_q0;
+reg  signed [31:0] in1_loc_44_load_reg_5262;
+wire   [31:0] in1_loc_45_q0;
+reg  signed [31:0] in1_loc_45_load_reg_5267;
+wire   [31:0] in1_loc_46_q0;
+reg  signed [31:0] in1_loc_46_load_reg_5272;
+wire   [31:0] in1_loc_47_q0;
+reg  signed [31:0] in1_loc_47_load_reg_5277;
+wire   [31:0] in1_loc_48_q0;
+reg  signed [31:0] in1_loc_48_load_reg_5282;
+wire   [31:0] in1_loc_49_q0;
+reg  signed [31:0] in1_loc_49_load_reg_5287;
+wire   [31:0] in1_loc_50_q0;
+reg  signed [31:0] in1_loc_50_load_reg_5292;
+wire   [31:0] in1_loc_51_q0;
+reg  signed [31:0] in1_loc_51_load_reg_5297;
+wire   [31:0] in1_loc_52_q0;
+reg  signed [31:0] in1_loc_52_load_reg_5302;
+wire   [31:0] in1_loc_53_q0;
+reg  signed [31:0] in1_loc_53_load_reg_5307;
+wire   [31:0] in1_loc_54_q0;
+reg  signed [31:0] in1_loc_54_load_reg_5312;
+wire   [31:0] in1_loc_55_q0;
+reg  signed [31:0] in1_loc_55_load_reg_5317;
+wire   [31:0] in1_loc_56_q0;
+reg  signed [31:0] in1_loc_56_load_reg_5322;
+wire   [31:0] in1_loc_57_q0;
+reg  signed [31:0] in1_loc_57_load_reg_5327;
+wire   [31:0] in1_loc_58_q0;
+reg  signed [31:0] in1_loc_58_load_reg_5332;
+wire   [31:0] in1_loc_59_q0;
+reg  signed [31:0] in1_loc_59_load_reg_5337;
+wire   [31:0] in1_loc_60_q0;
+reg  signed [31:0] in1_loc_60_load_reg_5342;
+wire   [31:0] in1_loc_61_q0;
+reg  signed [31:0] in1_loc_61_load_reg_5347;
+wire   [31:0] in1_loc_62_q0;
+reg  signed [31:0] in1_loc_62_load_reg_5352;
+wire   [31:0] in1_loc_63_q0;
+reg  signed [31:0] in1_loc_63_load_reg_5357;
+wire   [31:0] j_fu_3693_p2;
+reg   [31:0] j_reg_5365;
+wire    ap_CS_fsm_state25;
+reg   [11:0] out_loc_addr_reg_5370;
+wire   [0:0] icmp_ln33_fu_3688_p2;
+wire   [31:0] add_ln38_6_fu_4137_p2;
+reg   [31:0] add_ln38_6_reg_5695;
+wire    ap_CS_fsm_state26;
+wire   [31:0] add_ln38_9_fu_4155_p2;
+reg   [31:0] add_ln38_9_reg_5700;
+wire   [31:0] add_ln38_12_fu_4173_p2;
+reg   [31:0] add_ln38_12_reg_5705;
+wire   [31:0] add_ln38_21_fu_4215_p2;
+reg   [31:0] add_ln38_21_reg_5710;
+wire   [31:0] add_ln38_28_fu_4257_p2;
+reg   [31:0] add_ln38_28_reg_5715;
+wire   [31:0] add_ln38_37_fu_4299_p2;
+reg   [31:0] add_ln38_37_reg_5720;
+wire   [31:0] add_ln38_40_fu_4317_p2;
+reg   [31:0] add_ln38_40_reg_5725;
+wire   [31:0] add_ln38_43_fu_4335_p2;
+reg   [31:0] add_ln38_43_reg_5730;
+wire   [31:0] add_ln38_52_fu_4377_p2;
+reg   [31:0] add_ln38_52_reg_5735;
+wire   [31:0] add_ln38_55_fu_4395_p2;
+reg   [31:0] add_ln38_55_reg_5740;
+wire   [31:0] add_ln38_59_fu_4419_p2;
+reg   [31:0] add_ln38_59_reg_5745;
+wire   [0:0] icmp_ln42_fu_4475_p2;
+wire    ap_CS_fsm_pp2_stage0;
+wire    ap_block_state28_pp2_stage0_iter0;
+wire    ap_block_state29_pp2_stage0_iter1;
+wire    ap_block_state30_pp2_stage0_iter2;
+reg    ap_block_state30_io;
+reg    ap_block_pp2_stage0_11001;
+wire   [12:0] add_ln42_fu_4481_p2;
+reg    ap_enable_reg_pp2_iter0;
+wire   [31:0] out_loc_q0;
+reg   [31:0] out_loc_load_reg_5764;
+reg    ap_enable_reg_pp2_iter1;
+reg    ap_block_pp0_stage0_subdone;
+reg    ap_condition_pp0_exit_iter0_state9;
+reg    ap_enable_reg_pp0_iter2;
+wire    ap_CS_fsm_state18;
+reg    ap_block_pp1_stage0_subdone;
+reg    ap_condition_pp1_exit_iter0_state19;
+reg    ap_enable_reg_pp1_iter2;
+reg    ap_block_pp2_stage0_subdone;
+reg    ap_condition_pp2_exit_iter0_state28;
+reg   [5:0] in1_loc_0_address0;
+reg    in1_loc_0_ce0;
+reg    in1_loc_0_we0;
+reg   [5:0] in1_loc_1_address0;
+reg    in1_loc_1_ce0;
+reg    in1_loc_1_we0;
+reg   [5:0] in1_loc_2_address0;
+reg    in1_loc_2_ce0;
+reg    in1_loc_2_we0;
+reg   [5:0] in1_loc_3_address0;
+reg    in1_loc_3_ce0;
+reg    in1_loc_3_we0;
+reg   [5:0] in1_loc_4_address0;
+reg    in1_loc_4_ce0;
+reg    in1_loc_4_we0;
+reg   [5:0] in1_loc_5_address0;
+reg    in1_loc_5_ce0;
+reg    in1_loc_5_we0;
+reg   [5:0] in1_loc_6_address0;
+reg    in1_loc_6_ce0;
+reg    in1_loc_6_we0;
+reg   [5:0] in1_loc_7_address0;
+reg    in1_loc_7_ce0;
+reg    in1_loc_7_we0;
+reg   [5:0] in1_loc_8_address0;
+reg    in1_loc_8_ce0;
+reg    in1_loc_8_we0;
+reg   [5:0] in1_loc_9_address0;
+reg    in1_loc_9_ce0;
+reg    in1_loc_9_we0;
+reg   [5:0] in1_loc_10_address0;
+reg    in1_loc_10_ce0;
+reg    in1_loc_10_we0;
+reg   [5:0] in1_loc_11_address0;
+reg    in1_loc_11_ce0;
+reg    in1_loc_11_we0;
+reg   [5:0] in1_loc_12_address0;
+reg    in1_loc_12_ce0;
+reg    in1_loc_12_we0;
+reg   [5:0] in1_loc_13_address0;
+reg    in1_loc_13_ce0;
+reg    in1_loc_13_we0;
+reg   [5:0] in1_loc_14_address0;
+reg    in1_loc_14_ce0;
+reg    in1_loc_14_we0;
+reg   [5:0] in1_loc_15_address0;
+reg    in1_loc_15_ce0;
+reg    in1_loc_15_we0;
+reg   [5:0] in1_loc_16_address0;
+reg    in1_loc_16_ce0;
+reg    in1_loc_16_we0;
+reg   [5:0] in1_loc_17_address0;
+reg    in1_loc_17_ce0;
+reg    in1_loc_17_we0;
+reg   [5:0] in1_loc_18_address0;
+reg    in1_loc_18_ce0;
+reg    in1_loc_18_we0;
+reg   [5:0] in1_loc_19_address0;
+reg    in1_loc_19_ce0;
+reg    in1_loc_19_we0;
+reg   [5:0] in1_loc_20_address0;
+reg    in1_loc_20_ce0;
+reg    in1_loc_20_we0;
+reg   [5:0] in1_loc_21_address0;
+reg    in1_loc_21_ce0;
+reg    in1_loc_21_we0;
+reg   [5:0] in1_loc_22_address0;
+reg    in1_loc_22_ce0;
+reg    in1_loc_22_we0;
+reg   [5:0] in1_loc_23_address0;
+reg    in1_loc_23_ce0;
+reg    in1_loc_23_we0;
+reg   [5:0] in1_loc_24_address0;
+reg    in1_loc_24_ce0;
+reg    in1_loc_24_we0;
+reg   [5:0] in1_loc_25_address0;
+reg    in1_loc_25_ce0;
+reg    in1_loc_25_we0;
+reg   [5:0] in1_loc_26_address0;
+reg    in1_loc_26_ce0;
+reg    in1_loc_26_we0;
+reg   [5:0] in1_loc_27_address0;
+reg    in1_loc_27_ce0;
+reg    in1_loc_27_we0;
+reg   [5:0] in1_loc_28_address0;
+reg    in1_loc_28_ce0;
+reg    in1_loc_28_we0;
+reg   [5:0] in1_loc_29_address0;
+reg    in1_loc_29_ce0;
+reg    in1_loc_29_we0;
+reg   [5:0] in1_loc_30_address0;
+reg    in1_loc_30_ce0;
+reg    in1_loc_30_we0;
+reg   [5:0] in1_loc_31_address0;
+reg    in1_loc_31_ce0;
+reg    in1_loc_31_we0;
+reg   [5:0] in1_loc_32_address0;
+reg    in1_loc_32_ce0;
+reg    in1_loc_32_we0;
+reg   [5:0] in1_loc_33_address0;
+reg    in1_loc_33_ce0;
+reg    in1_loc_33_we0;
+reg   [5:0] in1_loc_34_address0;
+reg    in1_loc_34_ce0;
+reg    in1_loc_34_we0;
+reg   [5:0] in1_loc_35_address0;
+reg    in1_loc_35_ce0;
+reg    in1_loc_35_we0;
+reg   [5:0] in1_loc_36_address0;
+reg    in1_loc_36_ce0;
+reg    in1_loc_36_we0;
+reg   [5:0] in1_loc_37_address0;
+reg    in1_loc_37_ce0;
+reg    in1_loc_37_we0;
+reg   [5:0] in1_loc_38_address0;
+reg    in1_loc_38_ce0;
+reg    in1_loc_38_we0;
+reg   [5:0] in1_loc_39_address0;
+reg    in1_loc_39_ce0;
+reg    in1_loc_39_we0;
+reg   [5:0] in1_loc_40_address0;
+reg    in1_loc_40_ce0;
+reg    in1_loc_40_we0;
+reg   [5:0] in1_loc_41_address0;
+reg    in1_loc_41_ce0;
+reg    in1_loc_41_we0;
+reg   [5:0] in1_loc_42_address0;
+reg    in1_loc_42_ce0;
+reg    in1_loc_42_we0;
+reg   [5:0] in1_loc_43_address0;
+reg    in1_loc_43_ce0;
+reg    in1_loc_43_we0;
+reg   [5:0] in1_loc_44_address0;
+reg    in1_loc_44_ce0;
+reg    in1_loc_44_we0;
+reg   [5:0] in1_loc_45_address0;
+reg    in1_loc_45_ce0;
+reg    in1_loc_45_we0;
+reg   [5:0] in1_loc_46_address0;
+reg    in1_loc_46_ce0;
+reg    in1_loc_46_we0;
+reg   [5:0] in1_loc_47_address0;
+reg    in1_loc_47_ce0;
+reg    in1_loc_47_we0;
+reg   [5:0] in1_loc_48_address0;
+reg    in1_loc_48_ce0;
+reg    in1_loc_48_we0;
+reg   [5:0] in1_loc_49_address0;
+reg    in1_loc_49_ce0;
+reg    in1_loc_49_we0;
+reg   [5:0] in1_loc_50_address0;
+reg    in1_loc_50_ce0;
+reg    in1_loc_50_we0;
+reg   [5:0] in1_loc_51_address0;
+reg    in1_loc_51_ce0;
+reg    in1_loc_51_we0;
+reg   [5:0] in1_loc_52_address0;
+reg    in1_loc_52_ce0;
+reg    in1_loc_52_we0;
+reg   [5:0] in1_loc_53_address0;
+reg    in1_loc_53_ce0;
+reg    in1_loc_53_we0;
+reg   [5:0] in1_loc_54_address0;
+reg    in1_loc_54_ce0;
+reg    in1_loc_54_we0;
+reg   [5:0] in1_loc_55_address0;
+reg    in1_loc_55_ce0;
+reg    in1_loc_55_we0;
+reg   [5:0] in1_loc_56_address0;
+reg    in1_loc_56_ce0;
+reg    in1_loc_56_we0;
+reg   [5:0] in1_loc_57_address0;
+reg    in1_loc_57_ce0;
+reg    in1_loc_57_we0;
+reg   [5:0] in1_loc_58_address0;
+reg    in1_loc_58_ce0;
+reg    in1_loc_58_we0;
+reg   [5:0] in1_loc_59_address0;
+reg    in1_loc_59_ce0;
+reg    in1_loc_59_we0;
+reg   [5:0] in1_loc_60_address0;
+reg    in1_loc_60_ce0;
+reg    in1_loc_60_we0;
+reg   [5:0] in1_loc_61_address0;
+reg    in1_loc_61_ce0;
+reg    in1_loc_61_we0;
+reg   [5:0] in1_loc_62_address0;
+reg    in1_loc_62_ce0;
+reg    in1_loc_62_we0;
+reg   [5:0] in1_loc_63_address0;
+reg    in1_loc_63_ce0;
+reg    in1_loc_63_we0;
+reg   [5:0] in2_loc_0_address0;
+reg    in2_loc_0_ce0;
+reg    in2_loc_0_we0;
+wire   [31:0] in2_loc_0_q0;
+reg   [5:0] in2_loc_1_address0;
+reg    in2_loc_1_ce0;
+reg    in2_loc_1_we0;
+wire   [31:0] in2_loc_1_q0;
+reg   [5:0] in2_loc_2_address0;
+reg    in2_loc_2_ce0;
+reg    in2_loc_2_we0;
+wire   [31:0] in2_loc_2_q0;
+reg   [5:0] in2_loc_3_address0;
+reg    in2_loc_3_ce0;
+reg    in2_loc_3_we0;
+wire   [31:0] in2_loc_3_q0;
+reg   [5:0] in2_loc_4_address0;
+reg    in2_loc_4_ce0;
+reg    in2_loc_4_we0;
+wire   [31:0] in2_loc_4_q0;
+reg   [5:0] in2_loc_5_address0;
+reg    in2_loc_5_ce0;
+reg    in2_loc_5_we0;
+wire   [31:0] in2_loc_5_q0;
+reg   [5:0] in2_loc_6_address0;
+reg    in2_loc_6_ce0;
+reg    in2_loc_6_we0;
+wire   [31:0] in2_loc_6_q0;
+reg   [5:0] in2_loc_7_address0;
+reg    in2_loc_7_ce0;
+reg    in2_loc_7_we0;
+wire   [31:0] in2_loc_7_q0;
+reg   [5:0] in2_loc_8_address0;
+reg    in2_loc_8_ce0;
+reg    in2_loc_8_we0;
+wire   [31:0] in2_loc_8_q0;
+reg   [5:0] in2_loc_9_address0;
+reg    in2_loc_9_ce0;
+reg    in2_loc_9_we0;
+wire   [31:0] in2_loc_9_q0;
+reg   [5:0] in2_loc_10_address0;
+reg    in2_loc_10_ce0;
+reg    in2_loc_10_we0;
+wire   [31:0] in2_loc_10_q0;
+reg   [5:0] in2_loc_11_address0;
+reg    in2_loc_11_ce0;
+reg    in2_loc_11_we0;
+wire   [31:0] in2_loc_11_q0;
+reg   [5:0] in2_loc_12_address0;
+reg    in2_loc_12_ce0;
+reg    in2_loc_12_we0;
+wire   [31:0] in2_loc_12_q0;
+reg   [5:0] in2_loc_13_address0;
+reg    in2_loc_13_ce0;
+reg    in2_loc_13_we0;
+wire   [31:0] in2_loc_13_q0;
+reg   [5:0] in2_loc_14_address0;
+reg    in2_loc_14_ce0;
+reg    in2_loc_14_we0;
+wire   [31:0] in2_loc_14_q0;
+reg   [5:0] in2_loc_15_address0;
+reg    in2_loc_15_ce0;
+reg    in2_loc_15_we0;
+wire   [31:0] in2_loc_15_q0;
+reg   [5:0] in2_loc_16_address0;
+reg    in2_loc_16_ce0;
+reg    in2_loc_16_we0;
+wire   [31:0] in2_loc_16_q0;
+reg   [5:0] in2_loc_17_address0;
+reg    in2_loc_17_ce0;
+reg    in2_loc_17_we0;
+wire   [31:0] in2_loc_17_q0;
+reg   [5:0] in2_loc_18_address0;
+reg    in2_loc_18_ce0;
+reg    in2_loc_18_we0;
+wire   [31:0] in2_loc_18_q0;
+reg   [5:0] in2_loc_19_address0;
+reg    in2_loc_19_ce0;
+reg    in2_loc_19_we0;
+wire   [31:0] in2_loc_19_q0;
+reg   [5:0] in2_loc_20_address0;
+reg    in2_loc_20_ce0;
+reg    in2_loc_20_we0;
+wire   [31:0] in2_loc_20_q0;
+reg   [5:0] in2_loc_21_address0;
+reg    in2_loc_21_ce0;
+reg    in2_loc_21_we0;
+wire   [31:0] in2_loc_21_q0;
+reg   [5:0] in2_loc_22_address0;
+reg    in2_loc_22_ce0;
+reg    in2_loc_22_we0;
+wire   [31:0] in2_loc_22_q0;
+reg   [5:0] in2_loc_23_address0;
+reg    in2_loc_23_ce0;
+reg    in2_loc_23_we0;
+wire   [31:0] in2_loc_23_q0;
+reg   [5:0] in2_loc_24_address0;
+reg    in2_loc_24_ce0;
+reg    in2_loc_24_we0;
+wire   [31:0] in2_loc_24_q0;
+reg   [5:0] in2_loc_25_address0;
+reg    in2_loc_25_ce0;
+reg    in2_loc_25_we0;
+wire   [31:0] in2_loc_25_q0;
+reg   [5:0] in2_loc_26_address0;
+reg    in2_loc_26_ce0;
+reg    in2_loc_26_we0;
+wire   [31:0] in2_loc_26_q0;
+reg   [5:0] in2_loc_27_address0;
+reg    in2_loc_27_ce0;
+reg    in2_loc_27_we0;
+wire   [31:0] in2_loc_27_q0;
+reg   [5:0] in2_loc_28_address0;
+reg    in2_loc_28_ce0;
+reg    in2_loc_28_we0;
+wire   [31:0] in2_loc_28_q0;
+reg   [5:0] in2_loc_29_address0;
+reg    in2_loc_29_ce0;
+reg    in2_loc_29_we0;
+wire   [31:0] in2_loc_29_q0;
+reg   [5:0] in2_loc_30_address0;
+reg    in2_loc_30_ce0;
+reg    in2_loc_30_we0;
+wire   [31:0] in2_loc_30_q0;
+reg   [5:0] in2_loc_31_address0;
+reg    in2_loc_31_ce0;
+reg    in2_loc_31_we0;
+wire   [31:0] in2_loc_31_q0;
+reg   [5:0] in2_loc_32_address0;
+reg    in2_loc_32_ce0;
+reg    in2_loc_32_we0;
+wire   [31:0] in2_loc_32_q0;
+reg   [5:0] in2_loc_33_address0;
+reg    in2_loc_33_ce0;
+reg    in2_loc_33_we0;
+wire   [31:0] in2_loc_33_q0;
+reg   [5:0] in2_loc_34_address0;
+reg    in2_loc_34_ce0;
+reg    in2_loc_34_we0;
+wire   [31:0] in2_loc_34_q0;
+reg   [5:0] in2_loc_35_address0;
+reg    in2_loc_35_ce0;
+reg    in2_loc_35_we0;
+wire   [31:0] in2_loc_35_q0;
+reg   [5:0] in2_loc_36_address0;
+reg    in2_loc_36_ce0;
+reg    in2_loc_36_we0;
+wire   [31:0] in2_loc_36_q0;
+reg   [5:0] in2_loc_37_address0;
+reg    in2_loc_37_ce0;
+reg    in2_loc_37_we0;
+wire   [31:0] in2_loc_37_q0;
+reg   [5:0] in2_loc_38_address0;
+reg    in2_loc_38_ce0;
+reg    in2_loc_38_we0;
+wire   [31:0] in2_loc_38_q0;
+reg   [5:0] in2_loc_39_address0;
+reg    in2_loc_39_ce0;
+reg    in2_loc_39_we0;
+wire   [31:0] in2_loc_39_q0;
+reg   [5:0] in2_loc_40_address0;
+reg    in2_loc_40_ce0;
+reg    in2_loc_40_we0;
+wire   [31:0] in2_loc_40_q0;
+reg   [5:0] in2_loc_41_address0;
+reg    in2_loc_41_ce0;
+reg    in2_loc_41_we0;
+wire   [31:0] in2_loc_41_q0;
+reg   [5:0] in2_loc_42_address0;
+reg    in2_loc_42_ce0;
+reg    in2_loc_42_we0;
+wire   [31:0] in2_loc_42_q0;
+reg   [5:0] in2_loc_43_address0;
+reg    in2_loc_43_ce0;
+reg    in2_loc_43_we0;
+wire   [31:0] in2_loc_43_q0;
+reg   [5:0] in2_loc_44_address0;
+reg    in2_loc_44_ce0;
+reg    in2_loc_44_we0;
+wire   [31:0] in2_loc_44_q0;
+reg   [5:0] in2_loc_45_address0;
+reg    in2_loc_45_ce0;
+reg    in2_loc_45_we0;
+wire   [31:0] in2_loc_45_q0;
+reg   [5:0] in2_loc_46_address0;
+reg    in2_loc_46_ce0;
+reg    in2_loc_46_we0;
+wire   [31:0] in2_loc_46_q0;
+reg   [5:0] in2_loc_47_address0;
+reg    in2_loc_47_ce0;
+reg    in2_loc_47_we0;
+wire   [31:0] in2_loc_47_q0;
+reg   [5:0] in2_loc_48_address0;
+reg    in2_loc_48_ce0;
+reg    in2_loc_48_we0;
+wire   [31:0] in2_loc_48_q0;
+reg   [5:0] in2_loc_49_address0;
+reg    in2_loc_49_ce0;
+reg    in2_loc_49_we0;
+wire   [31:0] in2_loc_49_q0;
+reg   [5:0] in2_loc_50_address0;
+reg    in2_loc_50_ce0;
+reg    in2_loc_50_we0;
+wire   [31:0] in2_loc_50_q0;
+reg   [5:0] in2_loc_51_address0;
+reg    in2_loc_51_ce0;
+reg    in2_loc_51_we0;
+wire   [31:0] in2_loc_51_q0;
+reg   [5:0] in2_loc_52_address0;
+reg    in2_loc_52_ce0;
+reg    in2_loc_52_we0;
+wire   [31:0] in2_loc_52_q0;
+reg   [5:0] in2_loc_53_address0;
+reg    in2_loc_53_ce0;
+reg    in2_loc_53_we0;
+wire   [31:0] in2_loc_53_q0;
+reg   [5:0] in2_loc_54_address0;
+reg    in2_loc_54_ce0;
+reg    in2_loc_54_we0;
+wire   [31:0] in2_loc_54_q0;
+reg   [5:0] in2_loc_55_address0;
+reg    in2_loc_55_ce0;
+reg    in2_loc_55_we0;
+wire   [31:0] in2_loc_55_q0;
+reg   [5:0] in2_loc_56_address0;
+reg    in2_loc_56_ce0;
+reg    in2_loc_56_we0;
+wire   [31:0] in2_loc_56_q0;
+reg   [5:0] in2_loc_57_address0;
+reg    in2_loc_57_ce0;
+reg    in2_loc_57_we0;
+wire   [31:0] in2_loc_57_q0;
+reg   [5:0] in2_loc_58_address0;
+reg    in2_loc_58_ce0;
+reg    in2_loc_58_we0;
+wire   [31:0] in2_loc_58_q0;
+reg   [5:0] in2_loc_59_address0;
+reg    in2_loc_59_ce0;
+reg    in2_loc_59_we0;
+wire   [31:0] in2_loc_59_q0;
+reg   [5:0] in2_loc_60_address0;
+reg    in2_loc_60_ce0;
+reg    in2_loc_60_we0;
+wire   [31:0] in2_loc_60_q0;
+reg   [5:0] in2_loc_61_address0;
+reg    in2_loc_61_ce0;
+reg    in2_loc_61_we0;
+wire   [31:0] in2_loc_61_q0;
+reg   [5:0] in2_loc_62_address0;
+reg    in2_loc_62_ce0;
+reg    in2_loc_62_we0;
+wire   [31:0] in2_loc_62_q0;
+reg   [5:0] in2_loc_63_address0;
+reg    in2_loc_63_ce0;
+reg    in2_loc_63_we0;
+wire   [31:0] in2_loc_63_q0;
+reg   [11:0] out_loc_address0;
+reg    out_loc_ce0;
+reg    out_loc_we0;
+wire   [31:0] out_loc_d0;
+reg   [30:0] i_0_reg_3317;
+wire    ap_CS_fsm_state22;
+reg  signed [31:0] j_0_reg_3328;
+wire    ap_CS_fsm_state27;
+wire   [63:0] zext_ln27_fu_3434_p1;
+wire   [63:0] zext_ln28_fu_3527_p1;
+wire   [63:0] zext_ln38_fu_3609_p1;
+wire  signed [63:0] sext_ln38_1_fu_3776_p1;
+wire  signed [63:0] sext_ln38_fu_3699_p1;
+wire   [63:0] zext_ln42_fu_4487_p1;
+wire   [63:0] empty_8_fu_3380_p1;
+wire   [63:0] empty_fu_3390_p1;
+wire   [63:0] empty_7_fu_3399_p1;
+wire    ap_block_pp2_stage0_01001;
+wire   [31:0] zext_ln31_fu_3594_p1;
+wire   [13:0] trunc_ln38_1_fu_3767_p1;
+wire   [13:0] add_ln38_64_fu_3771_p2;
+wire  signed [31:0] mul_ln38_fu_3781_p0;
+wire  signed [31:0] mul_ln38_1_fu_3786_p0;
+wire  signed [31:0] mul_ln38_2_fu_3791_p0;
+wire  signed [31:0] mul_ln38_3_fu_3796_p0;
+wire  signed [31:0] mul_ln38_4_fu_3801_p0;
+wire  signed [31:0] mul_ln38_5_fu_3806_p0;
+wire  signed [31:0] mul_ln38_6_fu_3811_p0;
+wire  signed [31:0] mul_ln38_7_fu_3816_p0;
+wire  signed [31:0] mul_ln38_8_fu_3821_p0;
+wire  signed [31:0] mul_ln38_9_fu_3826_p0;
+wire  signed [31:0] mul_ln38_10_fu_3831_p0;
+wire  signed [31:0] mul_ln38_11_fu_3836_p0;
+wire  signed [31:0] mul_ln38_12_fu_3841_p0;
+wire  signed [31:0] mul_ln38_13_fu_3846_p0;
+wire  signed [31:0] mul_ln38_14_fu_3851_p0;
+wire  signed [31:0] mul_ln38_15_fu_3856_p0;
+wire  signed [31:0] mul_ln38_16_fu_3861_p0;
+wire  signed [31:0] mul_ln38_17_fu_3866_p0;
+wire  signed [31:0] mul_ln38_18_fu_3871_p0;
+wire  signed [31:0] mul_ln38_19_fu_3876_p0;
+wire  signed [31:0] mul_ln38_20_fu_3881_p0;
+wire  signed [31:0] mul_ln38_21_fu_3886_p0;
+wire  signed [31:0] mul_ln38_22_fu_3891_p0;
+wire  signed [31:0] mul_ln38_23_fu_3896_p0;
+wire  signed [31:0] mul_ln38_24_fu_3901_p0;
+wire  signed [31:0] mul_ln38_25_fu_3906_p0;
+wire  signed [31:0] mul_ln38_26_fu_3911_p0;
+wire  signed [31:0] mul_ln38_27_fu_3916_p0;
+wire  signed [31:0] mul_ln38_28_fu_3921_p0;
+wire  signed [31:0] mul_ln38_29_fu_3926_p0;
+wire  signed [31:0] mul_ln38_30_fu_3931_p0;
+wire  signed [31:0] mul_ln38_31_fu_3936_p0;
+wire  signed [31:0] mul_ln38_32_fu_3941_p0;
+wire  signed [31:0] mul_ln38_33_fu_3946_p0;
+wire  signed [31:0] mul_ln38_34_fu_3951_p0;
+wire  signed [31:0] mul_ln38_35_fu_3956_p0;
+wire  signed [31:0] mul_ln38_36_fu_3961_p0;
+wire  signed [31:0] mul_ln38_37_fu_3966_p0;
+wire  signed [31:0] mul_ln38_38_fu_3971_p0;
+wire  signed [31:0] mul_ln38_39_fu_3976_p0;
+wire  signed [31:0] mul_ln38_40_fu_3981_p0;
+wire  signed [31:0] mul_ln38_41_fu_3986_p0;
+wire  signed [31:0] mul_ln38_42_fu_3991_p0;
+wire  signed [31:0] mul_ln38_43_fu_3996_p0;
+wire  signed [31:0] mul_ln38_44_fu_4001_p0;
+wire  signed [31:0] mul_ln38_45_fu_4006_p0;
+wire  signed [31:0] mul_ln38_46_fu_4011_p0;
+wire  signed [31:0] mul_ln38_47_fu_4016_p0;
+wire  signed [31:0] mul_ln38_48_fu_4021_p0;
+wire  signed [31:0] mul_ln38_49_fu_4026_p0;
+wire  signed [31:0] mul_ln38_50_fu_4031_p0;
+wire  signed [31:0] mul_ln38_51_fu_4036_p0;
+wire  signed [31:0] mul_ln38_52_fu_4041_p0;
+wire  signed [31:0] mul_ln38_53_fu_4046_p0;
+wire  signed [31:0] mul_ln38_54_fu_4051_p0;
+wire  signed [31:0] mul_ln38_55_fu_4056_p0;
+wire  signed [31:0] mul_ln38_56_fu_4061_p0;
+wire  signed [31:0] mul_ln38_57_fu_4066_p0;
+wire  signed [31:0] mul_ln38_58_fu_4071_p0;
+wire  signed [31:0] mul_ln38_59_fu_4076_p0;
+wire  signed [31:0] mul_ln38_60_fu_4081_p0;
+wire  signed [31:0] mul_ln38_61_fu_4086_p0;
+wire  signed [31:0] mul_ln38_62_fu_4091_p0;
+wire  signed [31:0] mul_ln38_63_fu_4096_p0;
+wire   [31:0] mul_ln38_fu_3781_p2;
+wire   [31:0] mul_ln38_2_fu_3791_p2;
+wire   [31:0] mul_ln38_1_fu_3786_p2;
+wire   [31:0] add_ln38_fu_4101_p2;
+wire   [31:0] add_ln38_1_fu_4107_p2;
+wire   [31:0] mul_ln38_4_fu_3801_p2;
+wire   [31:0] mul_ln38_3_fu_3796_p2;
+wire   [31:0] mul_ln38_6_fu_3811_p2;
+wire   [31:0] mul_ln38_5_fu_3806_p2;
+wire   [31:0] add_ln38_3_fu_4119_p2;
+wire   [31:0] add_ln38_4_fu_4125_p2;
+wire   [31:0] add_ln38_2_fu_4113_p2;
+wire   [31:0] add_ln38_5_fu_4131_p2;
+wire   [31:0] mul_ln38_8_fu_3821_p2;
+wire   [31:0] mul_ln38_7_fu_3816_p2;
+wire   [31:0] mul_ln38_10_fu_3831_p2;
+wire   [31:0] mul_ln38_9_fu_3826_p2;
+wire   [31:0] add_ln38_7_fu_4143_p2;
+wire   [31:0] add_ln38_8_fu_4149_p2;
+wire   [31:0] mul_ln38_12_fu_3841_p2;
+wire   [31:0] mul_ln38_11_fu_3836_p2;
+wire   [31:0] mul_ln38_14_fu_3851_p2;
+wire   [31:0] mul_ln38_13_fu_3846_p2;
+wire   [31:0] add_ln38_10_fu_4161_p2;
+wire   [31:0] add_ln38_11_fu_4167_p2;
+wire   [31:0] mul_ln38_16_fu_3861_p2;
+wire   [31:0] mul_ln38_15_fu_3856_p2;
+wire   [31:0] mul_ln38_18_fu_3871_p2;
+wire   [31:0] mul_ln38_17_fu_3866_p2;
+wire   [31:0] add_ln38_15_fu_4179_p2;
+wire   [31:0] add_ln38_16_fu_4185_p2;
+wire   [31:0] mul_ln38_20_fu_3881_p2;
+wire   [31:0] mul_ln38_19_fu_3876_p2;
+wire   [31:0] mul_ln38_22_fu_3891_p2;
+wire   [31:0] mul_ln38_21_fu_3886_p2;
+wire   [31:0] add_ln38_18_fu_4197_p2;
+wire   [31:0] add_ln38_19_fu_4203_p2;
+wire   [31:0] add_ln38_17_fu_4191_p2;
+wire   [31:0] add_ln38_20_fu_4209_p2;
+wire   [31:0] mul_ln38_24_fu_3901_p2;
+wire   [31:0] mul_ln38_23_fu_3896_p2;
+wire   [31:0] mul_ln38_26_fu_3911_p2;
+wire   [31:0] mul_ln38_25_fu_3906_p2;
+wire   [31:0] add_ln38_22_fu_4221_p2;
+wire   [31:0] add_ln38_23_fu_4227_p2;
+wire   [31:0] mul_ln38_28_fu_3921_p2;
+wire   [31:0] mul_ln38_27_fu_3916_p2;
+wire   [31:0] mul_ln38_30_fu_3931_p2;
+wire   [31:0] mul_ln38_29_fu_3926_p2;
+wire   [31:0] add_ln38_25_fu_4239_p2;
+wire   [31:0] add_ln38_26_fu_4245_p2;
+wire   [31:0] add_ln38_24_fu_4233_p2;
+wire   [31:0] add_ln38_27_fu_4251_p2;
+wire   [31:0] mul_ln38_32_fu_3941_p2;
+wire   [31:0] mul_ln38_31_fu_3936_p2;
+wire   [31:0] mul_ln38_34_fu_3951_p2;
+wire   [31:0] mul_ln38_33_fu_3946_p2;
+wire   [31:0] add_ln38_31_fu_4263_p2;
+wire   [31:0] add_ln38_32_fu_4269_p2;
+wire   [31:0] mul_ln38_36_fu_3961_p2;
+wire   [31:0] mul_ln38_35_fu_3956_p2;
+wire   [31:0] mul_ln38_38_fu_3971_p2;
+wire   [31:0] mul_ln38_37_fu_3966_p2;
+wire   [31:0] add_ln38_34_fu_4281_p2;
+wire   [31:0] add_ln38_35_fu_4287_p2;
+wire   [31:0] add_ln38_33_fu_4275_p2;
+wire   [31:0] add_ln38_36_fu_4293_p2;
+wire   [31:0] mul_ln38_40_fu_3981_p2;
+wire   [31:0] mul_ln38_39_fu_3976_p2;
+wire   [31:0] mul_ln38_42_fu_3991_p2;
+wire   [31:0] mul_ln38_41_fu_3986_p2;
+wire   [31:0] add_ln38_38_fu_4305_p2;
+wire   [31:0] add_ln38_39_fu_4311_p2;
+wire   [31:0] mul_ln38_44_fu_4001_p2;
+wire   [31:0] mul_ln38_43_fu_3996_p2;
+wire   [31:0] mul_ln38_46_fu_4011_p2;
+wire   [31:0] mul_ln38_45_fu_4006_p2;
+wire   [31:0] add_ln38_41_fu_4323_p2;
+wire   [31:0] add_ln38_42_fu_4329_p2;
+wire   [31:0] mul_ln38_48_fu_4021_p2;
+wire   [31:0] mul_ln38_47_fu_4016_p2;
+wire   [31:0] mul_ln38_50_fu_4031_p2;
+wire   [31:0] mul_ln38_49_fu_4026_p2;
+wire   [31:0] add_ln38_46_fu_4341_p2;
+wire   [31:0] add_ln38_47_fu_4347_p2;
+wire   [31:0] mul_ln38_52_fu_4041_p2;
+wire   [31:0] mul_ln38_51_fu_4036_p2;
+wire   [31:0] mul_ln38_54_fu_4051_p2;
+wire   [31:0] mul_ln38_53_fu_4046_p2;
+wire   [31:0] add_ln38_49_fu_4359_p2;
+wire   [31:0] add_ln38_50_fu_4365_p2;
+wire   [31:0] add_ln38_48_fu_4353_p2;
+wire   [31:0] add_ln38_51_fu_4371_p2;
+wire   [31:0] mul_ln38_56_fu_4061_p2;
+wire   [31:0] mul_ln38_55_fu_4056_p2;
+wire   [31:0] mul_ln38_58_fu_4071_p2;
+wire   [31:0] mul_ln38_57_fu_4066_p2;
+wire   [31:0] add_ln38_53_fu_4383_p2;
+wire   [31:0] add_ln38_54_fu_4389_p2;
+wire   [31:0] mul_ln38_60_fu_4081_p2;
+wire   [31:0] mul_ln38_59_fu_4076_p2;
+wire   [31:0] mul_ln38_63_fu_4096_p2;
+wire   [31:0] mul_ln38_62_fu_4091_p2;
+wire   [31:0] mul_ln38_61_fu_4086_p2;
+wire   [31:0] add_ln38_57_fu_4407_p2;
+wire   [31:0] add_ln38_56_fu_4401_p2;
+wire   [31:0] add_ln38_58_fu_4413_p2;
+wire   [31:0] add_ln38_13_fu_4425_p2;
+wire   [31:0] add_ln38_14_fu_4429_p2;
+wire   [31:0] add_ln38_29_fu_4434_p2;
+wire   [31:0] add_ln38_44_fu_4444_p2;
+wire   [31:0] add_ln38_60_fu_4453_p2;
+wire   [31:0] add_ln38_45_fu_4448_p2;
+wire   [31:0] add_ln38_61_fu_4457_p2;
+wire   [31:0] add_ln38_30_fu_4438_p2;
+wire   [31:0] add_ln38_62_fu_4462_p2;
+reg   [28:0] ap_NS_fsm;
+reg    ap_idle_pp0;
+wire    ap_enable_pp0;
+reg    ap_idle_pp1;
+wire    ap_enable_pp1;
+reg    ap_idle_pp2;
+wire    ap_enable_pp2;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 29'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp1_iter1 = 1'b0;
+#0 ap_enable_reg_pp2_iter2 = 1'b0;
+#0 ap_enable_reg_pp0_iter0 = 1'b0;
+#0 ap_enable_reg_pp1_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp1_iter2 = 1'b0;
+end
+
+mmult_params_s_axi #(
+    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PARAMS_ADDR_WIDTH ),
+    .C_S_AXI_DATA_WIDTH( C_S_AXI_PARAMS_DATA_WIDTH ))
+mmult_params_s_axi_U(
+    .AWVALID(s_axi_params_AWVALID),
+    .AWREADY(s_axi_params_AWREADY),
+    .AWADDR(s_axi_params_AWADDR),
+    .WVALID(s_axi_params_WVALID),
+    .WREADY(s_axi_params_WREADY),
+    .WDATA(s_axi_params_WDATA),
+    .WSTRB(s_axi_params_WSTRB),
+    .ARVALID(s_axi_params_ARVALID),
+    .ARREADY(s_axi_params_ARREADY),
+    .ARADDR(s_axi_params_ARADDR),
+    .RVALID(s_axi_params_RVALID),
+    .RREADY(s_axi_params_RREADY),
+    .RDATA(s_axi_params_RDATA),
+    .RRESP(s_axi_params_RRESP),
+    .BVALID(s_axi_params_BVALID),
+    .BREADY(s_axi_params_BREADY),
+    .BRESP(s_axi_params_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .in1(in1),
+    .in2(in2),
+    .out_r(out_r),
+    .dim(dim)
+);
+
+mmult_in1_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN1_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN1_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN1_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN1_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN1_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN1_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN1_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN1_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN1_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN1_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN1_MEM_CACHE_VALUE ))
+mmult_in1_mem_m_axi_U(
+    .AWVALID(m_axi_in1_mem_AWVALID),
+    .AWREADY(m_axi_in1_mem_AWREADY),
+    .AWADDR(m_axi_in1_mem_AWADDR),
+    .AWID(m_axi_in1_mem_AWID),
+    .AWLEN(m_axi_in1_mem_AWLEN),
+    .AWSIZE(m_axi_in1_mem_AWSIZE),
+    .AWBURST(m_axi_in1_mem_AWBURST),
+    .AWLOCK(m_axi_in1_mem_AWLOCK),
+    .AWCACHE(m_axi_in1_mem_AWCACHE),
+    .AWPROT(m_axi_in1_mem_AWPROT),
+    .AWQOS(m_axi_in1_mem_AWQOS),
+    .AWREGION(m_axi_in1_mem_AWREGION),
+    .AWUSER(m_axi_in1_mem_AWUSER),
+    .WVALID(m_axi_in1_mem_WVALID),
+    .WREADY(m_axi_in1_mem_WREADY),
+    .WDATA(m_axi_in1_mem_WDATA),
+    .WSTRB(m_axi_in1_mem_WSTRB),
+    .WLAST(m_axi_in1_mem_WLAST),
+    .WID(m_axi_in1_mem_WID),
+    .WUSER(m_axi_in1_mem_WUSER),
+    .ARVALID(m_axi_in1_mem_ARVALID),
+    .ARREADY(m_axi_in1_mem_ARREADY),
+    .ARADDR(m_axi_in1_mem_ARADDR),
+    .ARID(m_axi_in1_mem_ARID),
+    .ARLEN(m_axi_in1_mem_ARLEN),
+    .ARSIZE(m_axi_in1_mem_ARSIZE),
+    .ARBURST(m_axi_in1_mem_ARBURST),
+    .ARLOCK(m_axi_in1_mem_ARLOCK),
+    .ARCACHE(m_axi_in1_mem_ARCACHE),
+    .ARPROT(m_axi_in1_mem_ARPROT),
+    .ARQOS(m_axi_in1_mem_ARQOS),
+    .ARREGION(m_axi_in1_mem_ARREGION),
+    .ARUSER(m_axi_in1_mem_ARUSER),
+    .RVALID(m_axi_in1_mem_RVALID),
+    .RREADY(m_axi_in1_mem_RREADY),
+    .RDATA(m_axi_in1_mem_RDATA),
+    .RLAST(m_axi_in1_mem_RLAST),
+    .RID(m_axi_in1_mem_RID),
+    .RUSER(m_axi_in1_mem_RUSER),
+    .RRESP(m_axi_in1_mem_RRESP),
+    .BVALID(m_axi_in1_mem_BVALID),
+    .BREADY(m_axi_in1_mem_BREADY),
+    .BRESP(m_axi_in1_mem_BRESP),
+    .BID(m_axi_in1_mem_BID),
+    .BUSER(m_axi_in1_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in1_mem_ARVALID),
+    .I_ARREADY(in1_mem_ARREADY),
+    .I_ARADDR(in1_mem_ARADDR),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in1_mem_RVALID),
+    .I_RREADY(in1_mem_RREADY),
+    .I_RDATA(in1_mem_RDATA),
+    .I_RID(in1_mem_RID),
+    .I_RUSER(in1_mem_RUSER),
+    .I_RRESP(in1_mem_RRESP),
+    .I_RLAST(in1_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in1_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in1_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in1_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in1_mem_BRESP),
+    .I_BID(in1_mem_BID),
+    .I_BUSER(in1_mem_BUSER)
+);
+
+mmult_in2_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN2_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN2_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN2_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN2_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN2_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN2_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN2_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN2_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN2_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN2_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN2_MEM_CACHE_VALUE ))
+mmult_in2_mem_m_axi_U(
+    .AWVALID(m_axi_in2_mem_AWVALID),
+    .AWREADY(m_axi_in2_mem_AWREADY),
+    .AWADDR(m_axi_in2_mem_AWADDR),
+    .AWID(m_axi_in2_mem_AWID),
+    .AWLEN(m_axi_in2_mem_AWLEN),
+    .AWSIZE(m_axi_in2_mem_AWSIZE),
+    .AWBURST(m_axi_in2_mem_AWBURST),
+    .AWLOCK(m_axi_in2_mem_AWLOCK),
+    .AWCACHE(m_axi_in2_mem_AWCACHE),
+    .AWPROT(m_axi_in2_mem_AWPROT),
+    .AWQOS(m_axi_in2_mem_AWQOS),
+    .AWREGION(m_axi_in2_mem_AWREGION),
+    .AWUSER(m_axi_in2_mem_AWUSER),
+    .WVALID(m_axi_in2_mem_WVALID),
+    .WREADY(m_axi_in2_mem_WREADY),
+    .WDATA(m_axi_in2_mem_WDATA),
+    .WSTRB(m_axi_in2_mem_WSTRB),
+    .WLAST(m_axi_in2_mem_WLAST),
+    .WID(m_axi_in2_mem_WID),
+    .WUSER(m_axi_in2_mem_WUSER),
+    .ARVALID(m_axi_in2_mem_ARVALID),
+    .ARREADY(m_axi_in2_mem_ARREADY),
+    .ARADDR(m_axi_in2_mem_ARADDR),
+    .ARID(m_axi_in2_mem_ARID),
+    .ARLEN(m_axi_in2_mem_ARLEN),
+    .ARSIZE(m_axi_in2_mem_ARSIZE),
+    .ARBURST(m_axi_in2_mem_ARBURST),
+    .ARLOCK(m_axi_in2_mem_ARLOCK),
+    .ARCACHE(m_axi_in2_mem_ARCACHE),
+    .ARPROT(m_axi_in2_mem_ARPROT),
+    .ARQOS(m_axi_in2_mem_ARQOS),
+    .ARREGION(m_axi_in2_mem_ARREGION),
+    .ARUSER(m_axi_in2_mem_ARUSER),
+    .RVALID(m_axi_in2_mem_RVALID),
+    .RREADY(m_axi_in2_mem_RREADY),
+    .RDATA(m_axi_in2_mem_RDATA),
+    .RLAST(m_axi_in2_mem_RLAST),
+    .RID(m_axi_in2_mem_RID),
+    .RUSER(m_axi_in2_mem_RUSER),
+    .RRESP(m_axi_in2_mem_RRESP),
+    .BVALID(m_axi_in2_mem_BVALID),
+    .BREADY(m_axi_in2_mem_BREADY),
+    .BRESP(m_axi_in2_mem_BRESP),
+    .BID(m_axi_in2_mem_BID),
+    .BUSER(m_axi_in2_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in2_mem_ARVALID),
+    .I_ARREADY(in2_mem_ARREADY),
+    .I_ARADDR(in2_mem_addr_reg_4525),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in2_mem_RVALID),
+    .I_RREADY(in2_mem_RREADY),
+    .I_RDATA(in2_mem_RDATA),
+    .I_RID(in2_mem_RID),
+    .I_RUSER(in2_mem_RUSER),
+    .I_RRESP(in2_mem_RRESP),
+    .I_RLAST(in2_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in2_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in2_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in2_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in2_mem_BRESP),
+    .I_BID(in2_mem_BID),
+    .I_BUSER(in2_mem_BUSER)
+);
+
+mmult_out_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_OUT_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_OUT_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_OUT_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_OUT_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_OUT_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_OUT_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_OUT_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_OUT_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_OUT_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_OUT_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_OUT_MEM_CACHE_VALUE ))
+mmult_out_mem_m_axi_U(
+    .AWVALID(m_axi_out_mem_AWVALID),
+    .AWREADY(m_axi_out_mem_AWREADY),
+    .AWADDR(m_axi_out_mem_AWADDR),
+    .AWID(m_axi_out_mem_AWID),
+    .AWLEN(m_axi_out_mem_AWLEN),
+    .AWSIZE(m_axi_out_mem_AWSIZE),
+    .AWBURST(m_axi_out_mem_AWBURST),
+    .AWLOCK(m_axi_out_mem_AWLOCK),
+    .AWCACHE(m_axi_out_mem_AWCACHE),
+    .AWPROT(m_axi_out_mem_AWPROT),
+    .AWQOS(m_axi_out_mem_AWQOS),
+    .AWREGION(m_axi_out_mem_AWREGION),
+    .AWUSER(m_axi_out_mem_AWUSER),
+    .WVALID(m_axi_out_mem_WVALID),
+    .WREADY(m_axi_out_mem_WREADY),
+    .WDATA(m_axi_out_mem_WDATA),
+    .WSTRB(m_axi_out_mem_WSTRB),
+    .WLAST(m_axi_out_mem_WLAST),
+    .WID(m_axi_out_mem_WID),
+    .WUSER(m_axi_out_mem_WUSER),
+    .ARVALID(m_axi_out_mem_ARVALID),
+    .ARREADY(m_axi_out_mem_ARREADY),
+    .ARADDR(m_axi_out_mem_ARADDR),
+    .ARID(m_axi_out_mem_ARID),
+    .ARLEN(m_axi_out_mem_ARLEN),
+    .ARSIZE(m_axi_out_mem_ARSIZE),
+    .ARBURST(m_axi_out_mem_ARBURST),
+    .ARLOCK(m_axi_out_mem_ARLOCK),
+    .ARCACHE(m_axi_out_mem_ARCACHE),
+    .ARPROT(m_axi_out_mem_ARPROT),
+    .ARQOS(m_axi_out_mem_ARQOS),
+    .ARREGION(m_axi_out_mem_ARREGION),
+    .ARUSER(m_axi_out_mem_ARUSER),
+    .RVALID(m_axi_out_mem_RVALID),
+    .RREADY(m_axi_out_mem_RREADY),
+    .RDATA(m_axi_out_mem_RDATA),
+    .RLAST(m_axi_out_mem_RLAST),
+    .RID(m_axi_out_mem_RID),
+    .RUSER(m_axi_out_mem_RUSER),
+    .RRESP(m_axi_out_mem_RRESP),
+    .BVALID(m_axi_out_mem_BVALID),
+    .BREADY(m_axi_out_mem_BREADY),
+    .BRESP(m_axi_out_mem_BRESP),
+    .BID(m_axi_out_mem_BID),
+    .BUSER(m_axi_out_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(1'b0),
+    .I_ARREADY(out_mem_ARREADY),
+    .I_ARADDR(32'd0),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd0),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(out_mem_RVALID),
+    .I_RREADY(1'b0),
+    .I_RDATA(out_mem_RDATA),
+    .I_RID(out_mem_RID),
+    .I_RUSER(out_mem_RUSER),
+    .I_RRESP(out_mem_RRESP),
+    .I_RLAST(out_mem_RLAST),
+    .I_AWVALID(out_mem_AWVALID),
+    .I_AWREADY(out_mem_AWREADY),
+    .I_AWADDR(out_mem_addr_reg_4519),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd4096),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(out_mem_WVALID),
+    .I_WREADY(out_mem_WREADY),
+    .I_WDATA(out_loc_load_reg_5764),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd15),
+    .I_BVALID(out_mem_BVALID),
+    .I_BREADY(out_mem_BREADY),
+    .I_BRESP(out_mem_BRESP),
+    .I_BID(out_mem_BID),
+    .I_BUSER(out_mem_BUSER)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_0_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_0_address0),
+    .ce0(in1_loc_0_ce0),
+    .we0(in1_loc_0_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_0_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_1_address0),
+    .ce0(in1_loc_1_ce0),
+    .we0(in1_loc_1_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_1_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_2_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_2_address0),
+    .ce0(in1_loc_2_ce0),
+    .we0(in1_loc_2_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_2_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_3_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_3_address0),
+    .ce0(in1_loc_3_ce0),
+    .we0(in1_loc_3_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_3_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_4_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_4_address0),
+    .ce0(in1_loc_4_ce0),
+    .we0(in1_loc_4_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_4_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_5_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_5_address0),
+    .ce0(in1_loc_5_ce0),
+    .we0(in1_loc_5_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_5_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_6_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_6_address0),
+    .ce0(in1_loc_6_ce0),
+    .we0(in1_loc_6_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_6_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_7_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_7_address0),
+    .ce0(in1_loc_7_ce0),
+    .we0(in1_loc_7_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_7_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_8_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_8_address0),
+    .ce0(in1_loc_8_ce0),
+    .we0(in1_loc_8_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_8_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_9_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_9_address0),
+    .ce0(in1_loc_9_ce0),
+    .we0(in1_loc_9_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_9_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_10_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_10_address0),
+    .ce0(in1_loc_10_ce0),
+    .we0(in1_loc_10_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_10_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_11_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_11_address0),
+    .ce0(in1_loc_11_ce0),
+    .we0(in1_loc_11_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_11_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_12_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_12_address0),
+    .ce0(in1_loc_12_ce0),
+    .we0(in1_loc_12_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_12_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_13_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_13_address0),
+    .ce0(in1_loc_13_ce0),
+    .we0(in1_loc_13_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_13_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_14_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_14_address0),
+    .ce0(in1_loc_14_ce0),
+    .we0(in1_loc_14_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_14_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_15_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_15_address0),
+    .ce0(in1_loc_15_ce0),
+    .we0(in1_loc_15_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_15_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_16_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_16_address0),
+    .ce0(in1_loc_16_ce0),
+    .we0(in1_loc_16_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_16_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_17_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_17_address0),
+    .ce0(in1_loc_17_ce0),
+    .we0(in1_loc_17_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_17_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_18_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_18_address0),
+    .ce0(in1_loc_18_ce0),
+    .we0(in1_loc_18_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_18_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_19_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_19_address0),
+    .ce0(in1_loc_19_ce0),
+    .we0(in1_loc_19_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_19_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_20_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_20_address0),
+    .ce0(in1_loc_20_ce0),
+    .we0(in1_loc_20_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_20_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_21_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_21_address0),
+    .ce0(in1_loc_21_ce0),
+    .we0(in1_loc_21_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_21_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_22_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_22_address0),
+    .ce0(in1_loc_22_ce0),
+    .we0(in1_loc_22_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_22_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_23_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_23_address0),
+    .ce0(in1_loc_23_ce0),
+    .we0(in1_loc_23_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_23_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_24_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_24_address0),
+    .ce0(in1_loc_24_ce0),
+    .we0(in1_loc_24_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_24_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_25_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_25_address0),
+    .ce0(in1_loc_25_ce0),
+    .we0(in1_loc_25_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_25_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_26_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_26_address0),
+    .ce0(in1_loc_26_ce0),
+    .we0(in1_loc_26_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_26_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_27_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_27_address0),
+    .ce0(in1_loc_27_ce0),
+    .we0(in1_loc_27_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_27_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_28_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_28_address0),
+    .ce0(in1_loc_28_ce0),
+    .we0(in1_loc_28_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_28_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_29_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_29_address0),
+    .ce0(in1_loc_29_ce0),
+    .we0(in1_loc_29_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_29_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_30_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_30_address0),
+    .ce0(in1_loc_30_ce0),
+    .we0(in1_loc_30_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_30_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_31_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_31_address0),
+    .ce0(in1_loc_31_ce0),
+    .we0(in1_loc_31_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_31_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_32_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_32_address0),
+    .ce0(in1_loc_32_ce0),
+    .we0(in1_loc_32_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_32_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_33_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_33_address0),
+    .ce0(in1_loc_33_ce0),
+    .we0(in1_loc_33_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_33_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_34_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_34_address0),
+    .ce0(in1_loc_34_ce0),
+    .we0(in1_loc_34_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_34_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_35_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_35_address0),
+    .ce0(in1_loc_35_ce0),
+    .we0(in1_loc_35_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_35_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_36_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_36_address0),
+    .ce0(in1_loc_36_ce0),
+    .we0(in1_loc_36_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_36_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_37_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_37_address0),
+    .ce0(in1_loc_37_ce0),
+    .we0(in1_loc_37_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_37_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_38_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_38_address0),
+    .ce0(in1_loc_38_ce0),
+    .we0(in1_loc_38_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_38_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_39_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_39_address0),
+    .ce0(in1_loc_39_ce0),
+    .we0(in1_loc_39_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_39_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_40_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_40_address0),
+    .ce0(in1_loc_40_ce0),
+    .we0(in1_loc_40_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_40_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_41_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_41_address0),
+    .ce0(in1_loc_41_ce0),
+    .we0(in1_loc_41_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_41_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_42_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_42_address0),
+    .ce0(in1_loc_42_ce0),
+    .we0(in1_loc_42_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_42_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_43_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_43_address0),
+    .ce0(in1_loc_43_ce0),
+    .we0(in1_loc_43_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_43_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_44_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_44_address0),
+    .ce0(in1_loc_44_ce0),
+    .we0(in1_loc_44_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_44_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_45_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_45_address0),
+    .ce0(in1_loc_45_ce0),
+    .we0(in1_loc_45_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_45_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_46_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_46_address0),
+    .ce0(in1_loc_46_ce0),
+    .we0(in1_loc_46_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_46_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_47_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_47_address0),
+    .ce0(in1_loc_47_ce0),
+    .we0(in1_loc_47_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_47_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_48_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_48_address0),
+    .ce0(in1_loc_48_ce0),
+    .we0(in1_loc_48_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_48_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_49_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_49_address0),
+    .ce0(in1_loc_49_ce0),
+    .we0(in1_loc_49_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_49_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_50_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_50_address0),
+    .ce0(in1_loc_50_ce0),
+    .we0(in1_loc_50_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_50_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_51_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_51_address0),
+    .ce0(in1_loc_51_ce0),
+    .we0(in1_loc_51_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_51_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_52_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_52_address0),
+    .ce0(in1_loc_52_ce0),
+    .we0(in1_loc_52_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_52_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_53_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_53_address0),
+    .ce0(in1_loc_53_ce0),
+    .we0(in1_loc_53_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_53_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_54_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_54_address0),
+    .ce0(in1_loc_54_ce0),
+    .we0(in1_loc_54_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_54_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_55_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_55_address0),
+    .ce0(in1_loc_55_ce0),
+    .we0(in1_loc_55_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_55_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_56_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_56_address0),
+    .ce0(in1_loc_56_ce0),
+    .we0(in1_loc_56_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_56_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_57_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_57_address0),
+    .ce0(in1_loc_57_ce0),
+    .we0(in1_loc_57_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_57_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_58_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_58_address0),
+    .ce0(in1_loc_58_ce0),
+    .we0(in1_loc_58_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_58_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_59_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_59_address0),
+    .ce0(in1_loc_59_ce0),
+    .we0(in1_loc_59_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_59_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_60_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_60_address0),
+    .ce0(in1_loc_60_ce0),
+    .we0(in1_loc_60_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_60_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_61_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_61_address0),
+    .ce0(in1_loc_61_ce0),
+    .we0(in1_loc_61_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_61_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_62_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_62_address0),
+    .ce0(in1_loc_62_ce0),
+    .we0(in1_loc_62_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_62_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_63_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_63_address0),
+    .ce0(in1_loc_63_ce0),
+    .we0(in1_loc_63_we0),
+    .d0(in1_mem_addr_read_reg_4549),
+    .q0(in1_loc_63_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_0_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_0_address0),
+    .ce0(in2_loc_0_ce0),
+    .we0(in2_loc_0_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_0_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_1_address0),
+    .ce0(in2_loc_1_ce0),
+    .we0(in2_loc_1_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_1_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_2_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_2_address0),
+    .ce0(in2_loc_2_ce0),
+    .we0(in2_loc_2_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_2_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_3_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_3_address0),
+    .ce0(in2_loc_3_ce0),
+    .we0(in2_loc_3_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_3_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_4_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_4_address0),
+    .ce0(in2_loc_4_ce0),
+    .we0(in2_loc_4_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_4_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_5_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_5_address0),
+    .ce0(in2_loc_5_ce0),
+    .we0(in2_loc_5_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_5_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_6_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_6_address0),
+    .ce0(in2_loc_6_ce0),
+    .we0(in2_loc_6_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_6_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_7_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_7_address0),
+    .ce0(in2_loc_7_ce0),
+    .we0(in2_loc_7_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_7_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_8_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_8_address0),
+    .ce0(in2_loc_8_ce0),
+    .we0(in2_loc_8_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_8_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_9_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_9_address0),
+    .ce0(in2_loc_9_ce0),
+    .we0(in2_loc_9_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_9_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_10_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_10_address0),
+    .ce0(in2_loc_10_ce0),
+    .we0(in2_loc_10_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_10_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_11_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_11_address0),
+    .ce0(in2_loc_11_ce0),
+    .we0(in2_loc_11_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_11_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_12_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_12_address0),
+    .ce0(in2_loc_12_ce0),
+    .we0(in2_loc_12_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_12_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_13_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_13_address0),
+    .ce0(in2_loc_13_ce0),
+    .we0(in2_loc_13_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_13_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_14_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_14_address0),
+    .ce0(in2_loc_14_ce0),
+    .we0(in2_loc_14_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_14_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_15_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_15_address0),
+    .ce0(in2_loc_15_ce0),
+    .we0(in2_loc_15_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_15_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_16_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_16_address0),
+    .ce0(in2_loc_16_ce0),
+    .we0(in2_loc_16_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_16_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_17_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_17_address0),
+    .ce0(in2_loc_17_ce0),
+    .we0(in2_loc_17_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_17_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_18_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_18_address0),
+    .ce0(in2_loc_18_ce0),
+    .we0(in2_loc_18_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_18_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_19_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_19_address0),
+    .ce0(in2_loc_19_ce0),
+    .we0(in2_loc_19_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_19_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_20_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_20_address0),
+    .ce0(in2_loc_20_ce0),
+    .we0(in2_loc_20_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_20_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_21_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_21_address0),
+    .ce0(in2_loc_21_ce0),
+    .we0(in2_loc_21_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_21_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_22_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_22_address0),
+    .ce0(in2_loc_22_ce0),
+    .we0(in2_loc_22_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_22_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_23_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_23_address0),
+    .ce0(in2_loc_23_ce0),
+    .we0(in2_loc_23_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_23_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_24_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_24_address0),
+    .ce0(in2_loc_24_ce0),
+    .we0(in2_loc_24_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_24_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_25_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_25_address0),
+    .ce0(in2_loc_25_ce0),
+    .we0(in2_loc_25_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_25_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_26_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_26_address0),
+    .ce0(in2_loc_26_ce0),
+    .we0(in2_loc_26_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_26_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_27_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_27_address0),
+    .ce0(in2_loc_27_ce0),
+    .we0(in2_loc_27_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_27_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_28_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_28_address0),
+    .ce0(in2_loc_28_ce0),
+    .we0(in2_loc_28_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_28_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_29_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_29_address0),
+    .ce0(in2_loc_29_ce0),
+    .we0(in2_loc_29_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_29_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_30_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_30_address0),
+    .ce0(in2_loc_30_ce0),
+    .we0(in2_loc_30_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_30_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_31_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_31_address0),
+    .ce0(in2_loc_31_ce0),
+    .we0(in2_loc_31_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_31_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_32_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_32_address0),
+    .ce0(in2_loc_32_ce0),
+    .we0(in2_loc_32_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_32_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_33_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_33_address0),
+    .ce0(in2_loc_33_ce0),
+    .we0(in2_loc_33_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_33_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_34_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_34_address0),
+    .ce0(in2_loc_34_ce0),
+    .we0(in2_loc_34_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_34_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_35_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_35_address0),
+    .ce0(in2_loc_35_ce0),
+    .we0(in2_loc_35_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_35_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_36_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_36_address0),
+    .ce0(in2_loc_36_ce0),
+    .we0(in2_loc_36_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_36_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_37_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_37_address0),
+    .ce0(in2_loc_37_ce0),
+    .we0(in2_loc_37_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_37_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_38_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_38_address0),
+    .ce0(in2_loc_38_ce0),
+    .we0(in2_loc_38_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_38_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_39_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_39_address0),
+    .ce0(in2_loc_39_ce0),
+    .we0(in2_loc_39_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_39_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_40_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_40_address0),
+    .ce0(in2_loc_40_ce0),
+    .we0(in2_loc_40_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_40_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_41_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_41_address0),
+    .ce0(in2_loc_41_ce0),
+    .we0(in2_loc_41_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_41_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_42_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_42_address0),
+    .ce0(in2_loc_42_ce0),
+    .we0(in2_loc_42_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_42_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_43_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_43_address0),
+    .ce0(in2_loc_43_ce0),
+    .we0(in2_loc_43_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_43_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_44_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_44_address0),
+    .ce0(in2_loc_44_ce0),
+    .we0(in2_loc_44_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_44_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_45_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_45_address0),
+    .ce0(in2_loc_45_ce0),
+    .we0(in2_loc_45_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_45_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_46_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_46_address0),
+    .ce0(in2_loc_46_ce0),
+    .we0(in2_loc_46_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_46_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_47_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_47_address0),
+    .ce0(in2_loc_47_ce0),
+    .we0(in2_loc_47_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_47_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_48_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_48_address0),
+    .ce0(in2_loc_48_ce0),
+    .we0(in2_loc_48_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_48_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_49_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_49_address0),
+    .ce0(in2_loc_49_ce0),
+    .we0(in2_loc_49_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_49_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_50_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_50_address0),
+    .ce0(in2_loc_50_ce0),
+    .we0(in2_loc_50_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_50_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_51_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_51_address0),
+    .ce0(in2_loc_51_ce0),
+    .we0(in2_loc_51_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_51_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_52_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_52_address0),
+    .ce0(in2_loc_52_ce0),
+    .we0(in2_loc_52_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_52_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_53_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_53_address0),
+    .ce0(in2_loc_53_ce0),
+    .we0(in2_loc_53_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_53_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_54_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_54_address0),
+    .ce0(in2_loc_54_ce0),
+    .we0(in2_loc_54_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_54_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_55_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_55_address0),
+    .ce0(in2_loc_55_ce0),
+    .we0(in2_loc_55_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_55_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_56_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_56_address0),
+    .ce0(in2_loc_56_ce0),
+    .we0(in2_loc_56_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_56_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_57_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_57_address0),
+    .ce0(in2_loc_57_ce0),
+    .we0(in2_loc_57_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_57_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_58_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_58_address0),
+    .ce0(in2_loc_58_ce0),
+    .we0(in2_loc_58_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_58_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_59_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_59_address0),
+    .ce0(in2_loc_59_ce0),
+    .we0(in2_loc_59_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_59_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_60_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_60_address0),
+    .ce0(in2_loc_60_ce0),
+    .we0(in2_loc_60_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_60_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_61_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_61_address0),
+    .ce0(in2_loc_61_ce0),
+    .we0(in2_loc_61_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_61_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_62_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_62_address0),
+    .ce0(in2_loc_62_ce0),
+    .we0(in2_loc_62_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_62_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_63_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_63_address0),
+    .ce0(in2_loc_63_ce0),
+    .we0(in2_loc_63_we0),
+    .d0(in2_mem_addr_read_reg_4635),
+    .q0(in2_loc_63_q0)
+);
+
+mmult_out_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+out_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(out_loc_address0),
+    .ce0(out_loc_ce0),
+    .we0(out_loc_we0),
+    .d0(out_loc_d0),
+    .q0(out_loc_q0)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state9) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_enable_reg_pp0_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp0_exit_iter0_state9)) begin
+                ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state9);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b0 == ap_block_pp1_stage0_subdone))) begin
+            ap_enable_reg_pp1_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp1_exit_iter0_state19)) begin
+                ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_condition_pp2_exit_iter0_state28) & (1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_subdone))) begin
+            ap_enable_reg_pp2_iter0 <= 1'b0;
+        end else if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_3598_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+            ap_enable_reg_pp2_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp2_exit_iter0_state28)) begin
+                ap_enable_reg_pp2_iter1 <= (1'b1 ^ ap_condition_pp2_exit_iter0_state28);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+        end else if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_3598_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+            ap_enable_reg_pp2_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state22)) begin
+        i_0_reg_3317 <= 31'd0;
+    end else if (((icmp_ln33_fu_3688_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state25))) begin
+        i_0_reg_3317 <= i_reg_4707;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state27)) begin
+        j_0_reg_3328 <= j_reg_5365;
+    end else if ((1'b1 == ap_CS_fsm_state24)) begin
+        j_0_reg_3328 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_fu_3408_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        phi_ln27_reg_3295 <= add_ln27_fu_3414_p2;
+    end else if ((1'b1 == ap_CS_fsm_state8)) begin
+        phi_ln27_reg_3295 <= 13'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        phi_ln28_reg_3306 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_fu_3501_p2 == 1'd0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        phi_ln28_reg_3306 <= add_ln28_fu_3507_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_3598_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+        phi_ln42_reg_3339 <= 13'd0;
+    end else if (((icmp_ln42_fu_4475_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_11001))) begin
+        phi_ln42_reg_3339 <= add_ln42_fu_4481_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state26)) begin
+        add_ln38_12_reg_5705 <= add_ln38_12_fu_4173_p2;
+        add_ln38_21_reg_5710 <= add_ln38_21_fu_4215_p2;
+        add_ln38_28_reg_5715 <= add_ln38_28_fu_4257_p2;
+        add_ln38_37_reg_5720 <= add_ln38_37_fu_4299_p2;
+        add_ln38_40_reg_5725 <= add_ln38_40_fu_4317_p2;
+        add_ln38_43_reg_5730 <= add_ln38_43_fu_4335_p2;
+        add_ln38_52_reg_5735 <= add_ln38_52_fu_4377_p2;
+        add_ln38_55_reg_5740 <= add_ln38_55_fu_4395_p2;
+        add_ln38_59_reg_5745 <= add_ln38_59_fu_4419_p2;
+        add_ln38_6_reg_5695 <= add_ln38_6_fu_4137_p2;
+        add_ln38_9_reg_5700 <= add_ln38_9_fu_4155_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        dim_read_reg_4492 <= dim;
+        in3_reg_4508 <= {{in1[31:2]}};
+        in_reg_4503 <= {{in2[31:2]}};
+        out5_reg_4498 <= {{out_r[31:2]}};
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23))) begin
+        i_reg_4707 <= i_fu_3603_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_11001))) begin
+        icmp_ln42_reg_5750 <= icmp_ln42_fu_4475_p2;
+        icmp_ln42_reg_5750_pp2_iter1_reg <= icmp_ln42_reg_5750;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        in1_loc_0_load_reg_5042 <= in1_loc_0_q0;
+        in1_loc_10_load_reg_5092 <= in1_loc_10_q0;
+        in1_loc_11_load_reg_5097 <= in1_loc_11_q0;
+        in1_loc_12_load_reg_5102 <= in1_loc_12_q0;
+        in1_loc_13_load_reg_5107 <= in1_loc_13_q0;
+        in1_loc_14_load_reg_5112 <= in1_loc_14_q0;
+        in1_loc_15_load_reg_5117 <= in1_loc_15_q0;
+        in1_loc_16_load_reg_5122 <= in1_loc_16_q0;
+        in1_loc_17_load_reg_5127 <= in1_loc_17_q0;
+        in1_loc_18_load_reg_5132 <= in1_loc_18_q0;
+        in1_loc_19_load_reg_5137 <= in1_loc_19_q0;
+        in1_loc_1_load_reg_5047 <= in1_loc_1_q0;
+        in1_loc_20_load_reg_5142 <= in1_loc_20_q0;
+        in1_loc_21_load_reg_5147 <= in1_loc_21_q0;
+        in1_loc_22_load_reg_5152 <= in1_loc_22_q0;
+        in1_loc_23_load_reg_5157 <= in1_loc_23_q0;
+        in1_loc_24_load_reg_5162 <= in1_loc_24_q0;
+        in1_loc_25_load_reg_5167 <= in1_loc_25_q0;
+        in1_loc_26_load_reg_5172 <= in1_loc_26_q0;
+        in1_loc_27_load_reg_5177 <= in1_loc_27_q0;
+        in1_loc_28_load_reg_5182 <= in1_loc_28_q0;
+        in1_loc_29_load_reg_5187 <= in1_loc_29_q0;
+        in1_loc_2_load_reg_5052 <= in1_loc_2_q0;
+        in1_loc_30_load_reg_5192 <= in1_loc_30_q0;
+        in1_loc_31_load_reg_5197 <= in1_loc_31_q0;
+        in1_loc_32_load_reg_5202 <= in1_loc_32_q0;
+        in1_loc_33_load_reg_5207 <= in1_loc_33_q0;
+        in1_loc_34_load_reg_5212 <= in1_loc_34_q0;
+        in1_loc_35_load_reg_5217 <= in1_loc_35_q0;
+        in1_loc_36_load_reg_5222 <= in1_loc_36_q0;
+        in1_loc_37_load_reg_5227 <= in1_loc_37_q0;
+        in1_loc_38_load_reg_5232 <= in1_loc_38_q0;
+        in1_loc_39_load_reg_5237 <= in1_loc_39_q0;
+        in1_loc_3_load_reg_5057 <= in1_loc_3_q0;
+        in1_loc_40_load_reg_5242 <= in1_loc_40_q0;
+        in1_loc_41_load_reg_5247 <= in1_loc_41_q0;
+        in1_loc_42_load_reg_5252 <= in1_loc_42_q0;
+        in1_loc_43_load_reg_5257 <= in1_loc_43_q0;
+        in1_loc_44_load_reg_5262 <= in1_loc_44_q0;
+        in1_loc_45_load_reg_5267 <= in1_loc_45_q0;
+        in1_loc_46_load_reg_5272 <= in1_loc_46_q0;
+        in1_loc_47_load_reg_5277 <= in1_loc_47_q0;
+        in1_loc_48_load_reg_5282 <= in1_loc_48_q0;
+        in1_loc_49_load_reg_5287 <= in1_loc_49_q0;
+        in1_loc_4_load_reg_5062 <= in1_loc_4_q0;
+        in1_loc_50_load_reg_5292 <= in1_loc_50_q0;
+        in1_loc_51_load_reg_5297 <= in1_loc_51_q0;
+        in1_loc_52_load_reg_5302 <= in1_loc_52_q0;
+        in1_loc_53_load_reg_5307 <= in1_loc_53_q0;
+        in1_loc_54_load_reg_5312 <= in1_loc_54_q0;
+        in1_loc_55_load_reg_5317 <= in1_loc_55_q0;
+        in1_loc_56_load_reg_5322 <= in1_loc_56_q0;
+        in1_loc_57_load_reg_5327 <= in1_loc_57_q0;
+        in1_loc_58_load_reg_5332 <= in1_loc_58_q0;
+        in1_loc_59_load_reg_5337 <= in1_loc_59_q0;
+        in1_loc_5_load_reg_5067 <= in1_loc_5_q0;
+        in1_loc_60_load_reg_5342 <= in1_loc_60_q0;
+        in1_loc_61_load_reg_5347 <= in1_loc_61_q0;
+        in1_loc_62_load_reg_5352 <= in1_loc_62_q0;
+        in1_loc_63_load_reg_5357 <= in1_loc_63_q0;
+        in1_loc_6_load_reg_5072 <= in1_loc_6_q0;
+        in1_loc_7_load_reg_5077 <= in1_loc_7_q0;
+        in1_loc_8_load_reg_5082 <= in1_loc_8_q0;
+        in1_loc_9_load_reg_5087 <= in1_loc_9_q0;
+        zext_ln38_1_cast_reg_5037[13 : 6] <= zext_ln38_1_cast_fu_3681_p3[13 : 6];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_addr_read_reg_4549 <= in1_mem_RDATA;
+        lshr_ln_reg_4540_pp0_iter1_reg <= lshr_ln_reg_4540;
+        trunc_ln27_reg_4545_pp0_iter1_reg <= trunc_ln27_reg_4545;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_addr_read_reg_4635 <= in2_mem_RDATA;
+        trunc_ln1_reg_4631_pp1_iter1_reg <= trunc_ln1_reg_4631;
+        trunc_ln28_reg_4626_pp1_iter1_reg <= trunc_ln28_reg_4626;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        in2_mem_addr_reg_4525[29 : 0] <= empty_7_fu_3399_p1[29 : 0];
+        out_mem_addr_reg_4519[29 : 0] <= empty_fu_3390_p1[29 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        j_reg_5365 <= j_fu_3693_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_fu_3408_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        lshr_ln_reg_4540 <= {{phi_ln27_reg_3295[12:6]}};
+        trunc_ln27_reg_4545 <= trunc_ln27_fu_3430_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln33_fu_3688_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state25))) begin
+        out_loc_addr_reg_5370 <= sext_ln38_1_fu_3776_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln42_reg_5750 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_11001))) begin
+        out_loc_load_reg_5764 <= out_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_fu_3501_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        trunc_ln1_reg_4631 <= {{phi_ln28_reg_3306[11:6]}};
+        trunc_ln28_reg_4626 <= trunc_ln28_fu_3513_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_3598_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state23))) begin
+        trunc_ln38_reg_4712 <= trunc_ln38_fu_3677_p1;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln27_fu_3408_p2 == 1'd1)) begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b1;
+    end else begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln28_fu_3501_p2 == 1'd1)) begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b1;
+    end else begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln42_fu_4475_p2 == 1'd1)) begin
+        ap_condition_pp2_exit_iter0_state28 = 1'b1;
+    end else begin
+        ap_condition_pp2_exit_iter0_state28 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state35))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b0))) begin
+        ap_idle_pp1 = 1'b1;
+    end else begin
+        ap_idle_pp1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp2_iter2 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b0) & (ap_enable_reg_pp2_iter0 == 1'b0))) begin
+        ap_idle_pp2 = 1'b1;
+    end else begin
+        ap_idle_pp2 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state35))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_0_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_0_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_0_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_0_ce0 = 1'b1;
+    end else begin
+        in1_loc_0_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_0_we0 = 1'b1;
+    end else begin
+        in1_loc_0_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_10_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_10_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_10_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_10_ce0 = 1'b1;
+    end else begin
+        in1_loc_10_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd10) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_10_we0 = 1'b1;
+    end else begin
+        in1_loc_10_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_11_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_11_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_11_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_11_ce0 = 1'b1;
+    end else begin
+        in1_loc_11_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd11) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_11_we0 = 1'b1;
+    end else begin
+        in1_loc_11_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_12_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_12_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_12_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_12_ce0 = 1'b1;
+    end else begin
+        in1_loc_12_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd12) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_12_we0 = 1'b1;
+    end else begin
+        in1_loc_12_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_13_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_13_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_13_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_13_ce0 = 1'b1;
+    end else begin
+        in1_loc_13_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd13) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_13_we0 = 1'b1;
+    end else begin
+        in1_loc_13_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_14_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_14_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_14_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_14_ce0 = 1'b1;
+    end else begin
+        in1_loc_14_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd14) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_14_we0 = 1'b1;
+    end else begin
+        in1_loc_14_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_15_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_15_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_15_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_15_ce0 = 1'b1;
+    end else begin
+        in1_loc_15_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd15) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_15_we0 = 1'b1;
+    end else begin
+        in1_loc_15_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_16_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_16_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_16_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_16_ce0 = 1'b1;
+    end else begin
+        in1_loc_16_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd16) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_16_we0 = 1'b1;
+    end else begin
+        in1_loc_16_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_17_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_17_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_17_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_17_ce0 = 1'b1;
+    end else begin
+        in1_loc_17_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd17) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_17_we0 = 1'b1;
+    end else begin
+        in1_loc_17_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_18_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_18_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_18_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_18_ce0 = 1'b1;
+    end else begin
+        in1_loc_18_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd18) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_18_we0 = 1'b1;
+    end else begin
+        in1_loc_18_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_19_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_19_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_19_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_19_ce0 = 1'b1;
+    end else begin
+        in1_loc_19_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd19) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_19_we0 = 1'b1;
+    end else begin
+        in1_loc_19_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_1_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_1_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_1_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_1_ce0 = 1'b1;
+    end else begin
+        in1_loc_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_1_we0 = 1'b1;
+    end else begin
+        in1_loc_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_20_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_20_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_20_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_20_ce0 = 1'b1;
+    end else begin
+        in1_loc_20_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd20) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_20_we0 = 1'b1;
+    end else begin
+        in1_loc_20_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_21_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_21_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_21_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_21_ce0 = 1'b1;
+    end else begin
+        in1_loc_21_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd21) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_21_we0 = 1'b1;
+    end else begin
+        in1_loc_21_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_22_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_22_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_22_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_22_ce0 = 1'b1;
+    end else begin
+        in1_loc_22_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd22) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_22_we0 = 1'b1;
+    end else begin
+        in1_loc_22_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_23_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_23_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_23_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_23_ce0 = 1'b1;
+    end else begin
+        in1_loc_23_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd23) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_23_we0 = 1'b1;
+    end else begin
+        in1_loc_23_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_24_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_24_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_24_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_24_ce0 = 1'b1;
+    end else begin
+        in1_loc_24_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd24) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_24_we0 = 1'b1;
+    end else begin
+        in1_loc_24_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_25_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_25_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_25_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_25_ce0 = 1'b1;
+    end else begin
+        in1_loc_25_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd25) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_25_we0 = 1'b1;
+    end else begin
+        in1_loc_25_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_26_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_26_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_26_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_26_ce0 = 1'b1;
+    end else begin
+        in1_loc_26_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd26) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_26_we0 = 1'b1;
+    end else begin
+        in1_loc_26_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_27_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_27_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_27_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_27_ce0 = 1'b1;
+    end else begin
+        in1_loc_27_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd27) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_27_we0 = 1'b1;
+    end else begin
+        in1_loc_27_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_28_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_28_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_28_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_28_ce0 = 1'b1;
+    end else begin
+        in1_loc_28_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd28) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_28_we0 = 1'b1;
+    end else begin
+        in1_loc_28_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_29_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_29_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_29_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_29_ce0 = 1'b1;
+    end else begin
+        in1_loc_29_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd29) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_29_we0 = 1'b1;
+    end else begin
+        in1_loc_29_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_2_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_2_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_2_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_2_ce0 = 1'b1;
+    end else begin
+        in1_loc_2_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd2) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_2_we0 = 1'b1;
+    end else begin
+        in1_loc_2_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_30_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_30_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_30_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_30_ce0 = 1'b1;
+    end else begin
+        in1_loc_30_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd30) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_30_we0 = 1'b1;
+    end else begin
+        in1_loc_30_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_31_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_31_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_31_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_31_ce0 = 1'b1;
+    end else begin
+        in1_loc_31_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd31) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_31_we0 = 1'b1;
+    end else begin
+        in1_loc_31_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_32_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_32_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_32_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_32_ce0 = 1'b1;
+    end else begin
+        in1_loc_32_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd32) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_32_we0 = 1'b1;
+    end else begin
+        in1_loc_32_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_33_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_33_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_33_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_33_ce0 = 1'b1;
+    end else begin
+        in1_loc_33_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd33) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_33_we0 = 1'b1;
+    end else begin
+        in1_loc_33_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_34_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_34_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_34_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_34_ce0 = 1'b1;
+    end else begin
+        in1_loc_34_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd34) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_34_we0 = 1'b1;
+    end else begin
+        in1_loc_34_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_35_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_35_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_35_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_35_ce0 = 1'b1;
+    end else begin
+        in1_loc_35_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd35) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_35_we0 = 1'b1;
+    end else begin
+        in1_loc_35_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_36_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_36_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_36_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_36_ce0 = 1'b1;
+    end else begin
+        in1_loc_36_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd36) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_36_we0 = 1'b1;
+    end else begin
+        in1_loc_36_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_37_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_37_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_37_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_37_ce0 = 1'b1;
+    end else begin
+        in1_loc_37_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd37) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_37_we0 = 1'b1;
+    end else begin
+        in1_loc_37_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_38_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_38_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_38_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_38_ce0 = 1'b1;
+    end else begin
+        in1_loc_38_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd38) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_38_we0 = 1'b1;
+    end else begin
+        in1_loc_38_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_39_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_39_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_39_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_39_ce0 = 1'b1;
+    end else begin
+        in1_loc_39_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd39) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_39_we0 = 1'b1;
+    end else begin
+        in1_loc_39_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_3_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_3_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_3_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_3_ce0 = 1'b1;
+    end else begin
+        in1_loc_3_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd3) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_3_we0 = 1'b1;
+    end else begin
+        in1_loc_3_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_40_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_40_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_40_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_40_ce0 = 1'b1;
+    end else begin
+        in1_loc_40_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd40) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_40_we0 = 1'b1;
+    end else begin
+        in1_loc_40_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_41_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_41_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_41_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_41_ce0 = 1'b1;
+    end else begin
+        in1_loc_41_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd41) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_41_we0 = 1'b1;
+    end else begin
+        in1_loc_41_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_42_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_42_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_42_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_42_ce0 = 1'b1;
+    end else begin
+        in1_loc_42_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd42) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_42_we0 = 1'b1;
+    end else begin
+        in1_loc_42_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_43_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_43_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_43_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_43_ce0 = 1'b1;
+    end else begin
+        in1_loc_43_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd43) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_43_we0 = 1'b1;
+    end else begin
+        in1_loc_43_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_44_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_44_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_44_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_44_ce0 = 1'b1;
+    end else begin
+        in1_loc_44_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd44) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_44_we0 = 1'b1;
+    end else begin
+        in1_loc_44_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_45_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_45_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_45_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_45_ce0 = 1'b1;
+    end else begin
+        in1_loc_45_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd45) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_45_we0 = 1'b1;
+    end else begin
+        in1_loc_45_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_46_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_46_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_46_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_46_ce0 = 1'b1;
+    end else begin
+        in1_loc_46_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd46) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_46_we0 = 1'b1;
+    end else begin
+        in1_loc_46_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_47_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_47_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_47_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_47_ce0 = 1'b1;
+    end else begin
+        in1_loc_47_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd47) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_47_we0 = 1'b1;
+    end else begin
+        in1_loc_47_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_48_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_48_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_48_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_48_ce0 = 1'b1;
+    end else begin
+        in1_loc_48_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd48) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_48_we0 = 1'b1;
+    end else begin
+        in1_loc_48_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_49_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_49_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_49_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_49_ce0 = 1'b1;
+    end else begin
+        in1_loc_49_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd49) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_49_we0 = 1'b1;
+    end else begin
+        in1_loc_49_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_4_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_4_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_4_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_4_ce0 = 1'b1;
+    end else begin
+        in1_loc_4_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd4) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_4_we0 = 1'b1;
+    end else begin
+        in1_loc_4_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_50_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_50_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_50_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_50_ce0 = 1'b1;
+    end else begin
+        in1_loc_50_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd50) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_50_we0 = 1'b1;
+    end else begin
+        in1_loc_50_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_51_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_51_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_51_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_51_ce0 = 1'b1;
+    end else begin
+        in1_loc_51_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd51) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_51_we0 = 1'b1;
+    end else begin
+        in1_loc_51_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_52_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_52_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_52_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_52_ce0 = 1'b1;
+    end else begin
+        in1_loc_52_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd52) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_52_we0 = 1'b1;
+    end else begin
+        in1_loc_52_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_53_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_53_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_53_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_53_ce0 = 1'b1;
+    end else begin
+        in1_loc_53_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd53) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_53_we0 = 1'b1;
+    end else begin
+        in1_loc_53_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_54_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_54_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_54_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_54_ce0 = 1'b1;
+    end else begin
+        in1_loc_54_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd54) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_54_we0 = 1'b1;
+    end else begin
+        in1_loc_54_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_55_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_55_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_55_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_55_ce0 = 1'b1;
+    end else begin
+        in1_loc_55_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd55) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_55_we0 = 1'b1;
+    end else begin
+        in1_loc_55_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_56_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_56_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_56_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_56_ce0 = 1'b1;
+    end else begin
+        in1_loc_56_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd56) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_56_we0 = 1'b1;
+    end else begin
+        in1_loc_56_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_57_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_57_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_57_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_57_ce0 = 1'b1;
+    end else begin
+        in1_loc_57_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd57) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_57_we0 = 1'b1;
+    end else begin
+        in1_loc_57_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_58_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_58_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_58_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_58_ce0 = 1'b1;
+    end else begin
+        in1_loc_58_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd58) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_58_we0 = 1'b1;
+    end else begin
+        in1_loc_58_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_59_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_59_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_59_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_59_ce0 = 1'b1;
+    end else begin
+        in1_loc_59_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd59) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_59_we0 = 1'b1;
+    end else begin
+        in1_loc_59_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_5_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_5_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_5_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_5_ce0 = 1'b1;
+    end else begin
+        in1_loc_5_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd5) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_5_we0 = 1'b1;
+    end else begin
+        in1_loc_5_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_60_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_60_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_60_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_60_ce0 = 1'b1;
+    end else begin
+        in1_loc_60_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd60) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_60_we0 = 1'b1;
+    end else begin
+        in1_loc_60_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_61_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_61_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_61_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_61_ce0 = 1'b1;
+    end else begin
+        in1_loc_61_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd61) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_61_we0 = 1'b1;
+    end else begin
+        in1_loc_61_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_62_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_62_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_62_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_62_ce0 = 1'b1;
+    end else begin
+        in1_loc_62_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd62) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_62_we0 = 1'b1;
+    end else begin
+        in1_loc_62_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_63_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_63_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_63_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_63_ce0 = 1'b1;
+    end else begin
+        in1_loc_63_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd63) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_63_we0 = 1'b1;
+    end else begin
+        in1_loc_63_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_6_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_6_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_6_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_6_ce0 = 1'b1;
+    end else begin
+        in1_loc_6_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd6) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_6_we0 = 1'b1;
+    end else begin
+        in1_loc_6_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_7_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_7_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_7_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_7_ce0 = 1'b1;
+    end else begin
+        in1_loc_7_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd7) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_7_we0 = 1'b1;
+    end else begin
+        in1_loc_7_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_8_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_8_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_8_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_8_ce0 = 1'b1;
+    end else begin
+        in1_loc_8_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd8) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_8_we0 = 1'b1;
+    end else begin
+        in1_loc_8_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state23)) begin
+        in1_loc_9_address0 = zext_ln38_fu_3609_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_9_address0 = zext_ln27_fu_3434_p1;
+    end else begin
+        in1_loc_9_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_state23_io) & (1'b1 == ap_CS_fsm_state23)))) begin
+        in1_loc_9_ce0 = 1'b1;
+    end else begin
+        in1_loc_9_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4545_pp0_iter1_reg == 6'd9) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_9_we0 = 1'b1;
+    end else begin
+        in1_loc_9_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        in1_mem_ARVALID = 1'b1;
+    end else begin
+        in1_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_RREADY = 1'b1;
+    end else begin
+        in1_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        in1_mem_blk_n_AR = m_axi_in1_mem_ARREADY;
+    end else begin
+        in1_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_blk_n_R = m_axi_in1_mem_RVALID;
+    end else begin
+        in1_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_0_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_0_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_0_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_0_ce0 = 1'b1;
+    end else begin
+        in2_loc_0_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_0_we0 = 1'b1;
+    end else begin
+        in2_loc_0_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_10_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_10_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_10_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_10_ce0 = 1'b1;
+    end else begin
+        in2_loc_10_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd10) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_10_we0 = 1'b1;
+    end else begin
+        in2_loc_10_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_11_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_11_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_11_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_11_ce0 = 1'b1;
+    end else begin
+        in2_loc_11_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd11) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_11_we0 = 1'b1;
+    end else begin
+        in2_loc_11_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_12_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_12_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_12_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_12_ce0 = 1'b1;
+    end else begin
+        in2_loc_12_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd12) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_12_we0 = 1'b1;
+    end else begin
+        in2_loc_12_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_13_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_13_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_13_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_13_ce0 = 1'b1;
+    end else begin
+        in2_loc_13_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd13) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_13_we0 = 1'b1;
+    end else begin
+        in2_loc_13_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_14_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_14_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_14_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_14_ce0 = 1'b1;
+    end else begin
+        in2_loc_14_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd14) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_14_we0 = 1'b1;
+    end else begin
+        in2_loc_14_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_15_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_15_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_15_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_15_ce0 = 1'b1;
+    end else begin
+        in2_loc_15_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd15) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_15_we0 = 1'b1;
+    end else begin
+        in2_loc_15_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_16_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_16_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_16_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_16_ce0 = 1'b1;
+    end else begin
+        in2_loc_16_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd16) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_16_we0 = 1'b1;
+    end else begin
+        in2_loc_16_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_17_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_17_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_17_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_17_ce0 = 1'b1;
+    end else begin
+        in2_loc_17_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd17) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_17_we0 = 1'b1;
+    end else begin
+        in2_loc_17_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_18_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_18_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_18_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_18_ce0 = 1'b1;
+    end else begin
+        in2_loc_18_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd18) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_18_we0 = 1'b1;
+    end else begin
+        in2_loc_18_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_19_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_19_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_19_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_19_ce0 = 1'b1;
+    end else begin
+        in2_loc_19_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd19) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_19_we0 = 1'b1;
+    end else begin
+        in2_loc_19_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_1_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_1_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_1_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_1_ce0 = 1'b1;
+    end else begin
+        in2_loc_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd1) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_1_we0 = 1'b1;
+    end else begin
+        in2_loc_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_20_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_20_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_20_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_20_ce0 = 1'b1;
+    end else begin
+        in2_loc_20_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd20) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_20_we0 = 1'b1;
+    end else begin
+        in2_loc_20_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_21_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_21_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_21_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_21_ce0 = 1'b1;
+    end else begin
+        in2_loc_21_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd21) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_21_we0 = 1'b1;
+    end else begin
+        in2_loc_21_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_22_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_22_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_22_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_22_ce0 = 1'b1;
+    end else begin
+        in2_loc_22_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd22) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_22_we0 = 1'b1;
+    end else begin
+        in2_loc_22_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_23_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_23_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_23_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_23_ce0 = 1'b1;
+    end else begin
+        in2_loc_23_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd23) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_23_we0 = 1'b1;
+    end else begin
+        in2_loc_23_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_24_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_24_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_24_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_24_ce0 = 1'b1;
+    end else begin
+        in2_loc_24_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd24) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_24_we0 = 1'b1;
+    end else begin
+        in2_loc_24_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_25_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_25_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_25_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_25_ce0 = 1'b1;
+    end else begin
+        in2_loc_25_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd25) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_25_we0 = 1'b1;
+    end else begin
+        in2_loc_25_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_26_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_26_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_26_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_26_ce0 = 1'b1;
+    end else begin
+        in2_loc_26_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd26) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_26_we0 = 1'b1;
+    end else begin
+        in2_loc_26_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_27_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_27_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_27_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_27_ce0 = 1'b1;
+    end else begin
+        in2_loc_27_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd27) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_27_we0 = 1'b1;
+    end else begin
+        in2_loc_27_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_28_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_28_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_28_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_28_ce0 = 1'b1;
+    end else begin
+        in2_loc_28_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd28) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_28_we0 = 1'b1;
+    end else begin
+        in2_loc_28_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_29_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_29_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_29_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_29_ce0 = 1'b1;
+    end else begin
+        in2_loc_29_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd29) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_29_we0 = 1'b1;
+    end else begin
+        in2_loc_29_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_2_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_2_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_2_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_2_ce0 = 1'b1;
+    end else begin
+        in2_loc_2_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd2) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_2_we0 = 1'b1;
+    end else begin
+        in2_loc_2_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_30_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_30_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_30_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_30_ce0 = 1'b1;
+    end else begin
+        in2_loc_30_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd30) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_30_we0 = 1'b1;
+    end else begin
+        in2_loc_30_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_31_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_31_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_31_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_31_ce0 = 1'b1;
+    end else begin
+        in2_loc_31_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd31) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_31_we0 = 1'b1;
+    end else begin
+        in2_loc_31_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_32_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_32_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_32_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_32_ce0 = 1'b1;
+    end else begin
+        in2_loc_32_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd32) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_32_we0 = 1'b1;
+    end else begin
+        in2_loc_32_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_33_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_33_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_33_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_33_ce0 = 1'b1;
+    end else begin
+        in2_loc_33_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd33) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_33_we0 = 1'b1;
+    end else begin
+        in2_loc_33_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_34_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_34_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_34_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_34_ce0 = 1'b1;
+    end else begin
+        in2_loc_34_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd34) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_34_we0 = 1'b1;
+    end else begin
+        in2_loc_34_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_35_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_35_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_35_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_35_ce0 = 1'b1;
+    end else begin
+        in2_loc_35_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd35) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_35_we0 = 1'b1;
+    end else begin
+        in2_loc_35_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_36_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_36_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_36_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_36_ce0 = 1'b1;
+    end else begin
+        in2_loc_36_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd36) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_36_we0 = 1'b1;
+    end else begin
+        in2_loc_36_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_37_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_37_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_37_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_37_ce0 = 1'b1;
+    end else begin
+        in2_loc_37_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd37) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_37_we0 = 1'b1;
+    end else begin
+        in2_loc_37_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_38_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_38_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_38_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_38_ce0 = 1'b1;
+    end else begin
+        in2_loc_38_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd38) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_38_we0 = 1'b1;
+    end else begin
+        in2_loc_38_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_39_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_39_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_39_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_39_ce0 = 1'b1;
+    end else begin
+        in2_loc_39_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd39) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_39_we0 = 1'b1;
+    end else begin
+        in2_loc_39_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_3_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_3_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_3_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_3_ce0 = 1'b1;
+    end else begin
+        in2_loc_3_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd3) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_3_we0 = 1'b1;
+    end else begin
+        in2_loc_3_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_40_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_40_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_40_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_40_ce0 = 1'b1;
+    end else begin
+        in2_loc_40_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd40) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_40_we0 = 1'b1;
+    end else begin
+        in2_loc_40_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_41_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_41_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_41_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_41_ce0 = 1'b1;
+    end else begin
+        in2_loc_41_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd41) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_41_we0 = 1'b1;
+    end else begin
+        in2_loc_41_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_42_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_42_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_42_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_42_ce0 = 1'b1;
+    end else begin
+        in2_loc_42_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd42) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_42_we0 = 1'b1;
+    end else begin
+        in2_loc_42_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_43_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_43_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_43_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_43_ce0 = 1'b1;
+    end else begin
+        in2_loc_43_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd43) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_43_we0 = 1'b1;
+    end else begin
+        in2_loc_43_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_44_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_44_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_44_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_44_ce0 = 1'b1;
+    end else begin
+        in2_loc_44_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd44) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_44_we0 = 1'b1;
+    end else begin
+        in2_loc_44_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_45_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_45_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_45_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_45_ce0 = 1'b1;
+    end else begin
+        in2_loc_45_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd45) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_45_we0 = 1'b1;
+    end else begin
+        in2_loc_45_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_46_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_46_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_46_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_46_ce0 = 1'b1;
+    end else begin
+        in2_loc_46_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd46) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_46_we0 = 1'b1;
+    end else begin
+        in2_loc_46_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_47_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_47_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_47_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_47_ce0 = 1'b1;
+    end else begin
+        in2_loc_47_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd47) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_47_we0 = 1'b1;
+    end else begin
+        in2_loc_47_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_48_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_48_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_48_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_48_ce0 = 1'b1;
+    end else begin
+        in2_loc_48_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd48) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_48_we0 = 1'b1;
+    end else begin
+        in2_loc_48_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_49_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_49_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_49_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_49_ce0 = 1'b1;
+    end else begin
+        in2_loc_49_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd49) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_49_we0 = 1'b1;
+    end else begin
+        in2_loc_49_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_4_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_4_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_4_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_4_ce0 = 1'b1;
+    end else begin
+        in2_loc_4_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd4) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_4_we0 = 1'b1;
+    end else begin
+        in2_loc_4_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_50_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_50_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_50_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_50_ce0 = 1'b1;
+    end else begin
+        in2_loc_50_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd50) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_50_we0 = 1'b1;
+    end else begin
+        in2_loc_50_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_51_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_51_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_51_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_51_ce0 = 1'b1;
+    end else begin
+        in2_loc_51_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd51) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_51_we0 = 1'b1;
+    end else begin
+        in2_loc_51_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_52_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_52_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_52_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_52_ce0 = 1'b1;
+    end else begin
+        in2_loc_52_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd52) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_52_we0 = 1'b1;
+    end else begin
+        in2_loc_52_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_53_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_53_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_53_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_53_ce0 = 1'b1;
+    end else begin
+        in2_loc_53_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd53) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_53_we0 = 1'b1;
+    end else begin
+        in2_loc_53_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_54_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_54_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_54_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_54_ce0 = 1'b1;
+    end else begin
+        in2_loc_54_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd54) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_54_we0 = 1'b1;
+    end else begin
+        in2_loc_54_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_55_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_55_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_55_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_55_ce0 = 1'b1;
+    end else begin
+        in2_loc_55_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd55) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_55_we0 = 1'b1;
+    end else begin
+        in2_loc_55_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_56_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_56_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_56_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_56_ce0 = 1'b1;
+    end else begin
+        in2_loc_56_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd56) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_56_we0 = 1'b1;
+    end else begin
+        in2_loc_56_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_57_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_57_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_57_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_57_ce0 = 1'b1;
+    end else begin
+        in2_loc_57_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd57) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_57_we0 = 1'b1;
+    end else begin
+        in2_loc_57_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_58_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_58_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_58_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_58_ce0 = 1'b1;
+    end else begin
+        in2_loc_58_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd58) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_58_we0 = 1'b1;
+    end else begin
+        in2_loc_58_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_59_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_59_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_59_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_59_ce0 = 1'b1;
+    end else begin
+        in2_loc_59_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd59) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_59_we0 = 1'b1;
+    end else begin
+        in2_loc_59_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_5_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_5_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_5_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_5_ce0 = 1'b1;
+    end else begin
+        in2_loc_5_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd5) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_5_we0 = 1'b1;
+    end else begin
+        in2_loc_5_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_60_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_60_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_60_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_60_ce0 = 1'b1;
+    end else begin
+        in2_loc_60_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd60) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_60_we0 = 1'b1;
+    end else begin
+        in2_loc_60_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_61_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_61_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_61_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_61_ce0 = 1'b1;
+    end else begin
+        in2_loc_61_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd61) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_61_we0 = 1'b1;
+    end else begin
+        in2_loc_61_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_62_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_62_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_62_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_62_ce0 = 1'b1;
+    end else begin
+        in2_loc_62_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd62) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_62_we0 = 1'b1;
+    end else begin
+        in2_loc_62_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_63_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_63_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_63_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_63_ce0 = 1'b1;
+    end else begin
+        in2_loc_63_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd63) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_63_we0 = 1'b1;
+    end else begin
+        in2_loc_63_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_6_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_6_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_6_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_6_ce0 = 1'b1;
+    end else begin
+        in2_loc_6_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd6) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_6_we0 = 1'b1;
+    end else begin
+        in2_loc_6_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_7_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_7_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_7_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_7_ce0 = 1'b1;
+    end else begin
+        in2_loc_7_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd7) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_7_we0 = 1'b1;
+    end else begin
+        in2_loc_7_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_8_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_8_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_8_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_8_ce0 = 1'b1;
+    end else begin
+        in2_loc_8_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd8) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_8_we0 = 1'b1;
+    end else begin
+        in2_loc_8_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state25)) begin
+        in2_loc_9_address0 = sext_ln38_fu_3699_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_9_address0 = zext_ln28_fu_3527_p1;
+    end else begin
+        in2_loc_9_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_9_ce0 = 1'b1;
+    end else begin
+        in2_loc_9_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4631_pp1_iter1_reg == 6'd9) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_9_we0 = 1'b1;
+    end else begin
+        in2_loc_9_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+        in2_mem_ARVALID = 1'b1;
+    end else begin
+        in2_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_RREADY = 1'b1;
+    end else begin
+        in2_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state12)) begin
+        in2_mem_blk_n_AR = m_axi_in2_mem_ARREADY;
+    end else begin
+        in2_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_blk_n_R = m_axi_in2_mem_RVALID;
+    end else begin
+        in2_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        out_loc_address0 = zext_ln42_fu_4487_p1;
+    end else if ((1'b1 == ap_CS_fsm_state27)) begin
+        out_loc_address0 = out_loc_addr_reg_5370;
+    end else if ((1'b1 == ap_CS_fsm_state25)) begin
+        out_loc_address0 = sext_ln38_1_fu_3776_p1;
+    end else begin
+        out_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state25) | (1'b1 == ap_CS_fsm_state27) | ((ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0) & (1'b0 == ap_block_pp2_stage0_11001)))) begin
+        out_loc_ce0 = 1'b1;
+    end else begin
+        out_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state27)) begin
+        out_loc_we0 = 1'b1;
+    end else begin
+        out_loc_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_3598_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+        out_mem_AWVALID = 1'b1;
+    end else begin
+        out_mem_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state35))) begin
+        out_mem_BREADY = 1'b1;
+    end else begin
+        out_mem_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln42_reg_5750_pp2_iter1_reg == 1'd0) & (ap_enable_reg_pp2_iter2 == 1'b1) & (1'b0 == ap_block_pp2_stage0_11001))) begin
+        out_mem_WVALID = 1'b1;
+    end else begin
+        out_mem_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln31_fu_3598_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+        out_mem_blk_n_AW = m_axi_out_mem_AWREADY;
+    end else begin
+        out_mem_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state35)) begin
+        out_mem_blk_n_B = m_axi_out_mem_BVALID;
+    end else begin
+        out_mem_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (icmp_ln42_reg_5750_pp2_iter1_reg == 1'd0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        out_mem_blk_n_W = m_axi_out_mem_WREADY;
+    end else begin
+        out_mem_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        ap_ST_fsm_pp0_stage0 : begin
+            if ((~((icmp_ln27_fu_3408_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end else if ((((icmp_ln27_fu_3408_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end
+        end
+        ap_ST_fsm_state12 : begin
+            if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+                ap_NS_fsm = ap_ST_fsm_state13;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end
+        end
+        ap_ST_fsm_state13 : begin
+            ap_NS_fsm = ap_ST_fsm_state14;
+        end
+        ap_ST_fsm_state14 : begin
+            ap_NS_fsm = ap_ST_fsm_state15;
+        end
+        ap_ST_fsm_state15 : begin
+            ap_NS_fsm = ap_ST_fsm_state16;
+        end
+        ap_ST_fsm_state16 : begin
+            ap_NS_fsm = ap_ST_fsm_state17;
+        end
+        ap_ST_fsm_state17 : begin
+            ap_NS_fsm = ap_ST_fsm_state18;
+        end
+        ap_ST_fsm_state18 : begin
+            ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+        end
+        ap_ST_fsm_pp1_stage0 : begin
+            if ((~((icmp_ln28_fu_3501_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)) & ~((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end else if ((((icmp_ln28_fu_3501_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)) | ((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state22;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end
+        end
+        ap_ST_fsm_state22 : begin
+            ap_NS_fsm = ap_ST_fsm_state23;
+        end
+        ap_ST_fsm_state23 : begin
+            if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_3598_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state23))) begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end else if (((1'b0 == ap_block_state23_io) & (icmp_ln31_fu_3598_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state23))) begin
+                ap_NS_fsm = ap_ST_fsm_state24;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state23;
+            end
+        end
+        ap_ST_fsm_state24 : begin
+            ap_NS_fsm = ap_ST_fsm_state25;
+        end
+        ap_ST_fsm_state25 : begin
+            if (((icmp_ln33_fu_3688_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state25))) begin
+                ap_NS_fsm = ap_ST_fsm_state23;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state26;
+            end
+        end
+        ap_ST_fsm_state26 : begin
+            ap_NS_fsm = ap_ST_fsm_state27;
+        end
+        ap_ST_fsm_state27 : begin
+            ap_NS_fsm = ap_ST_fsm_state25;
+        end
+        ap_ST_fsm_pp2_stage0 : begin
+            if ((~((icmp_ln42_fu_4475_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter1 == 1'b0)) & ~((ap_enable_reg_pp2_iter2 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter1 == 1'b0)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end else if ((((ap_enable_reg_pp2_iter2 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter1 == 1'b0)) | ((icmp_ln42_fu_4475_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter1 == 1'b0)))) begin
+                ap_NS_fsm = ap_ST_fsm_state31;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end
+        end
+        ap_ST_fsm_state31 : begin
+            ap_NS_fsm = ap_ST_fsm_state32;
+        end
+        ap_ST_fsm_state32 : begin
+            ap_NS_fsm = ap_ST_fsm_state33;
+        end
+        ap_ST_fsm_state33 : begin
+            ap_NS_fsm = ap_ST_fsm_state34;
+        end
+        ap_ST_fsm_state34 : begin
+            ap_NS_fsm = ap_ST_fsm_state35;
+        end
+        ap_ST_fsm_state35 : begin
+            if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state35))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state35;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln27_fu_3414_p2 = (phi_ln27_reg_3295 + 13'd1);
+
+assign add_ln28_fu_3507_p2 = (phi_ln28_reg_3306 + 13'd1);
+
+assign add_ln38_10_fu_4161_p2 = (mul_ln38_12_fu_3841_p2 + mul_ln38_11_fu_3836_p2);
+
+assign add_ln38_11_fu_4167_p2 = (mul_ln38_14_fu_3851_p2 + mul_ln38_13_fu_3846_p2);
+
+assign add_ln38_12_fu_4173_p2 = (add_ln38_10_fu_4161_p2 + add_ln38_11_fu_4167_p2);
+
+assign add_ln38_13_fu_4425_p2 = (add_ln38_9_reg_5700 + add_ln38_12_reg_5705);
+
+assign add_ln38_14_fu_4429_p2 = (add_ln38_6_reg_5695 + add_ln38_13_fu_4425_p2);
+
+assign add_ln38_15_fu_4179_p2 = (mul_ln38_16_fu_3861_p2 + mul_ln38_15_fu_3856_p2);
+
+assign add_ln38_16_fu_4185_p2 = (mul_ln38_18_fu_3871_p2 + mul_ln38_17_fu_3866_p2);
+
+assign add_ln38_17_fu_4191_p2 = (add_ln38_15_fu_4179_p2 + add_ln38_16_fu_4185_p2);
+
+assign add_ln38_18_fu_4197_p2 = (mul_ln38_20_fu_3881_p2 + mul_ln38_19_fu_3876_p2);
+
+assign add_ln38_19_fu_4203_p2 = (mul_ln38_22_fu_3891_p2 + mul_ln38_21_fu_3886_p2);
+
+assign add_ln38_1_fu_4107_p2 = (mul_ln38_2_fu_3791_p2 + mul_ln38_1_fu_3786_p2);
+
+assign add_ln38_20_fu_4209_p2 = (add_ln38_18_fu_4197_p2 + add_ln38_19_fu_4203_p2);
+
+assign add_ln38_21_fu_4215_p2 = (add_ln38_17_fu_4191_p2 + add_ln38_20_fu_4209_p2);
+
+assign add_ln38_22_fu_4221_p2 = (mul_ln38_24_fu_3901_p2 + mul_ln38_23_fu_3896_p2);
+
+assign add_ln38_23_fu_4227_p2 = (mul_ln38_26_fu_3911_p2 + mul_ln38_25_fu_3906_p2);
+
+assign add_ln38_24_fu_4233_p2 = (add_ln38_22_fu_4221_p2 + add_ln38_23_fu_4227_p2);
+
+assign add_ln38_25_fu_4239_p2 = (mul_ln38_28_fu_3921_p2 + mul_ln38_27_fu_3916_p2);
+
+assign add_ln38_26_fu_4245_p2 = (mul_ln38_30_fu_3931_p2 + mul_ln38_29_fu_3926_p2);
+
+assign add_ln38_27_fu_4251_p2 = (add_ln38_25_fu_4239_p2 + add_ln38_26_fu_4245_p2);
+
+assign add_ln38_28_fu_4257_p2 = (add_ln38_24_fu_4233_p2 + add_ln38_27_fu_4251_p2);
+
+assign add_ln38_29_fu_4434_p2 = (add_ln38_21_reg_5710 + add_ln38_28_reg_5715);
+
+assign add_ln38_2_fu_4113_p2 = (add_ln38_fu_4101_p2 + add_ln38_1_fu_4107_p2);
+
+assign add_ln38_30_fu_4438_p2 = (add_ln38_14_fu_4429_p2 + add_ln38_29_fu_4434_p2);
+
+assign add_ln38_31_fu_4263_p2 = (mul_ln38_32_fu_3941_p2 + mul_ln38_31_fu_3936_p2);
+
+assign add_ln38_32_fu_4269_p2 = (mul_ln38_34_fu_3951_p2 + mul_ln38_33_fu_3946_p2);
+
+assign add_ln38_33_fu_4275_p2 = (add_ln38_31_fu_4263_p2 + add_ln38_32_fu_4269_p2);
+
+assign add_ln38_34_fu_4281_p2 = (mul_ln38_36_fu_3961_p2 + mul_ln38_35_fu_3956_p2);
+
+assign add_ln38_35_fu_4287_p2 = (mul_ln38_38_fu_3971_p2 + mul_ln38_37_fu_3966_p2);
+
+assign add_ln38_36_fu_4293_p2 = (add_ln38_34_fu_4281_p2 + add_ln38_35_fu_4287_p2);
+
+assign add_ln38_37_fu_4299_p2 = (add_ln38_33_fu_4275_p2 + add_ln38_36_fu_4293_p2);
+
+assign add_ln38_38_fu_4305_p2 = (mul_ln38_40_fu_3981_p2 + mul_ln38_39_fu_3976_p2);
+
+assign add_ln38_39_fu_4311_p2 = (mul_ln38_42_fu_3991_p2 + mul_ln38_41_fu_3986_p2);
+
+assign add_ln38_3_fu_4119_p2 = (mul_ln38_4_fu_3801_p2 + mul_ln38_3_fu_3796_p2);
+
+assign add_ln38_40_fu_4317_p2 = (add_ln38_38_fu_4305_p2 + add_ln38_39_fu_4311_p2);
+
+assign add_ln38_41_fu_4323_p2 = (mul_ln38_44_fu_4001_p2 + mul_ln38_43_fu_3996_p2);
+
+assign add_ln38_42_fu_4329_p2 = (mul_ln38_46_fu_4011_p2 + mul_ln38_45_fu_4006_p2);
+
+assign add_ln38_43_fu_4335_p2 = (add_ln38_41_fu_4323_p2 + add_ln38_42_fu_4329_p2);
+
+assign add_ln38_44_fu_4444_p2 = (add_ln38_40_reg_5725 + add_ln38_43_reg_5730);
+
+assign add_ln38_45_fu_4448_p2 = (add_ln38_37_reg_5720 + add_ln38_44_fu_4444_p2);
+
+assign add_ln38_46_fu_4341_p2 = (mul_ln38_48_fu_4021_p2 + mul_ln38_47_fu_4016_p2);
+
+assign add_ln38_47_fu_4347_p2 = (mul_ln38_50_fu_4031_p2 + mul_ln38_49_fu_4026_p2);
+
+assign add_ln38_48_fu_4353_p2 = (add_ln38_46_fu_4341_p2 + add_ln38_47_fu_4347_p2);
+
+assign add_ln38_49_fu_4359_p2 = (mul_ln38_52_fu_4041_p2 + mul_ln38_51_fu_4036_p2);
+
+assign add_ln38_4_fu_4125_p2 = (mul_ln38_6_fu_3811_p2 + mul_ln38_5_fu_3806_p2);
+
+assign add_ln38_50_fu_4365_p2 = (mul_ln38_54_fu_4051_p2 + mul_ln38_53_fu_4046_p2);
+
+assign add_ln38_51_fu_4371_p2 = (add_ln38_49_fu_4359_p2 + add_ln38_50_fu_4365_p2);
+
+assign add_ln38_52_fu_4377_p2 = (add_ln38_48_fu_4353_p2 + add_ln38_51_fu_4371_p2);
+
+assign add_ln38_53_fu_4383_p2 = (mul_ln38_56_fu_4061_p2 + mul_ln38_55_fu_4056_p2);
+
+assign add_ln38_54_fu_4389_p2 = (mul_ln38_58_fu_4071_p2 + mul_ln38_57_fu_4066_p2);
+
+assign add_ln38_55_fu_4395_p2 = (add_ln38_53_fu_4383_p2 + add_ln38_54_fu_4389_p2);
+
+assign add_ln38_56_fu_4401_p2 = (mul_ln38_60_fu_4081_p2 + mul_ln38_59_fu_4076_p2);
+
+assign add_ln38_57_fu_4407_p2 = (mul_ln38_63_fu_4096_p2 + mul_ln38_62_fu_4091_p2);
+
+assign add_ln38_58_fu_4413_p2 = (mul_ln38_61_fu_4086_p2 + add_ln38_57_fu_4407_p2);
+
+assign add_ln38_59_fu_4419_p2 = (add_ln38_56_fu_4401_p2 + add_ln38_58_fu_4413_p2);
+
+assign add_ln38_5_fu_4131_p2 = (add_ln38_3_fu_4119_p2 + add_ln38_4_fu_4125_p2);
+
+assign add_ln38_60_fu_4453_p2 = (add_ln38_55_reg_5740 + add_ln38_59_reg_5745);
+
+assign add_ln38_61_fu_4457_p2 = (add_ln38_52_reg_5735 + add_ln38_60_fu_4453_p2);
+
+assign add_ln38_62_fu_4462_p2 = (add_ln38_45_fu_4448_p2 + add_ln38_61_fu_4457_p2);
+
+assign add_ln38_64_fu_3771_p2 = (zext_ln38_1_cast_reg_5037 + trunc_ln38_1_fu_3767_p1);
+
+assign add_ln38_6_fu_4137_p2 = (add_ln38_2_fu_4113_p2 + add_ln38_5_fu_4131_p2);
+
+assign add_ln38_7_fu_4143_p2 = (mul_ln38_8_fu_3821_p2 + mul_ln38_7_fu_3816_p2);
+
+assign add_ln38_8_fu_4149_p2 = (mul_ln38_10_fu_3831_p2 + mul_ln38_9_fu_3826_p2);
+
+assign add_ln38_9_fu_4155_p2 = (add_ln38_7_fu_4143_p2 + add_ln38_8_fu_4149_p2);
+
+assign add_ln38_fu_4101_p2 = (mul_ln38_fu_3781_p2 + out_loc_q0);
+
+assign add_ln42_fu_4481_p2 = (phi_ln42_reg_3339 + 13'd1);
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd8];
+
+assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd16];
+
+assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd23];
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state12 = ap_CS_fsm[32'd9];
+
+assign ap_CS_fsm_state18 = ap_CS_fsm[32'd15];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state22 = ap_CS_fsm[32'd17];
+
+assign ap_CS_fsm_state23 = ap_CS_fsm[32'd18];
+
+assign ap_CS_fsm_state24 = ap_CS_fsm[32'd19];
+
+assign ap_CS_fsm_state25 = ap_CS_fsm[32'd20];
+
+assign ap_CS_fsm_state26 = ap_CS_fsm[32'd21];
+
+assign ap_CS_fsm_state27 = ap_CS_fsm[32'd22];
+
+assign ap_CS_fsm_state35 = ap_CS_fsm[32'd28];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = ((in1_mem_RVALID == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = ((in1_mem_RVALID == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp1_stage0_11001 = ((in2_mem_RVALID == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp1_stage0_subdone = ((in2_mem_RVALID == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+assign ap_block_pp2_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp2_stage0_01001 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp2_stage0_11001 = ((1'b1 == ap_block_state30_io) & (ap_enable_reg_pp2_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp2_stage0_subdone = ((1'b1 == ap_block_state30_io) & (ap_enable_reg_pp2_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state10_pp0_stage0_iter1 = (in1_mem_RVALID == 1'b0);
+end
+
+assign ap_block_state11_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state20_pp1_stage0_iter1 = (in2_mem_RVALID == 1'b0);
+end
+
+assign ap_block_state21_pp1_stage0_iter2 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state23_io = ((out_mem_AWREADY == 1'b0) & (icmp_ln31_fu_3598_p2 == 1'd0));
+end
+
+assign ap_block_state28_pp2_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state29_pp2_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state30_io = ((out_mem_WREADY == 1'b0) & (icmp_ln42_reg_5750_pp2_iter1_reg == 1'd0));
+end
+
+assign ap_block_state30_pp2_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state9_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
+
+assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign empty_7_fu_3399_p1 = in_reg_4503;
+
+assign empty_8_fu_3380_p1 = in3_reg_4508;
+
+assign empty_fu_3390_p1 = out5_reg_4498;
+
+assign i_fu_3603_p2 = (i_0_reg_3317 + 31'd1);
+
+assign icmp_ln27_fu_3408_p2 = ((phi_ln27_reg_3295 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln28_fu_3501_p2 = ((phi_ln28_reg_3306 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln31_fu_3598_p2 = (($signed(zext_ln31_fu_3594_p1) < $signed(dim_read_reg_4492)) ? 1'b1 : 1'b0);
+
+assign icmp_ln33_fu_3688_p2 = ((j_0_reg_3328 == dim_read_reg_4492) ? 1'b1 : 1'b0);
+
+assign icmp_ln42_fu_4475_p2 = ((phi_ln42_reg_3339 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign in1_mem_ARADDR = empty_8_fu_3380_p1;
+
+assign j_fu_3693_p2 = ($signed(j_0_reg_3328) + $signed(32'd1));
+
+assign mul_ln38_10_fu_3831_p0 = in2_loc_10_q0;
+
+assign mul_ln38_10_fu_3831_p2 = ($signed(mul_ln38_10_fu_3831_p0) * $signed(in1_loc_10_load_reg_5092));
+
+assign mul_ln38_11_fu_3836_p0 = in2_loc_11_q0;
+
+assign mul_ln38_11_fu_3836_p2 = ($signed(mul_ln38_11_fu_3836_p0) * $signed(in1_loc_11_load_reg_5097));
+
+assign mul_ln38_12_fu_3841_p0 = in2_loc_12_q0;
+
+assign mul_ln38_12_fu_3841_p2 = ($signed(mul_ln38_12_fu_3841_p0) * $signed(in1_loc_12_load_reg_5102));
+
+assign mul_ln38_13_fu_3846_p0 = in2_loc_13_q0;
+
+assign mul_ln38_13_fu_3846_p2 = ($signed(mul_ln38_13_fu_3846_p0) * $signed(in1_loc_13_load_reg_5107));
+
+assign mul_ln38_14_fu_3851_p0 = in2_loc_14_q0;
+
+assign mul_ln38_14_fu_3851_p2 = ($signed(mul_ln38_14_fu_3851_p0) * $signed(in1_loc_14_load_reg_5112));
+
+assign mul_ln38_15_fu_3856_p0 = in2_loc_15_q0;
+
+assign mul_ln38_15_fu_3856_p2 = ($signed(mul_ln38_15_fu_3856_p0) * $signed(in1_loc_15_load_reg_5117));
+
+assign mul_ln38_16_fu_3861_p0 = in2_loc_16_q0;
+
+assign mul_ln38_16_fu_3861_p2 = ($signed(mul_ln38_16_fu_3861_p0) * $signed(in1_loc_16_load_reg_5122));
+
+assign mul_ln38_17_fu_3866_p0 = in2_loc_17_q0;
+
+assign mul_ln38_17_fu_3866_p2 = ($signed(mul_ln38_17_fu_3866_p0) * $signed(in1_loc_17_load_reg_5127));
+
+assign mul_ln38_18_fu_3871_p0 = in2_loc_18_q0;
+
+assign mul_ln38_18_fu_3871_p2 = ($signed(mul_ln38_18_fu_3871_p0) * $signed(in1_loc_18_load_reg_5132));
+
+assign mul_ln38_19_fu_3876_p0 = in2_loc_19_q0;
+
+assign mul_ln38_19_fu_3876_p2 = ($signed(mul_ln38_19_fu_3876_p0) * $signed(in1_loc_19_load_reg_5137));
+
+assign mul_ln38_1_fu_3786_p0 = in2_loc_1_q0;
+
+assign mul_ln38_1_fu_3786_p2 = ($signed(mul_ln38_1_fu_3786_p0) * $signed(in1_loc_1_load_reg_5047));
+
+assign mul_ln38_20_fu_3881_p0 = in2_loc_20_q0;
+
+assign mul_ln38_20_fu_3881_p2 = ($signed(mul_ln38_20_fu_3881_p0) * $signed(in1_loc_20_load_reg_5142));
+
+assign mul_ln38_21_fu_3886_p0 = in2_loc_21_q0;
+
+assign mul_ln38_21_fu_3886_p2 = ($signed(mul_ln38_21_fu_3886_p0) * $signed(in1_loc_21_load_reg_5147));
+
+assign mul_ln38_22_fu_3891_p0 = in2_loc_22_q0;
+
+assign mul_ln38_22_fu_3891_p2 = ($signed(mul_ln38_22_fu_3891_p0) * $signed(in1_loc_22_load_reg_5152));
+
+assign mul_ln38_23_fu_3896_p0 = in2_loc_23_q0;
+
+assign mul_ln38_23_fu_3896_p2 = ($signed(mul_ln38_23_fu_3896_p0) * $signed(in1_loc_23_load_reg_5157));
+
+assign mul_ln38_24_fu_3901_p0 = in2_loc_24_q0;
+
+assign mul_ln38_24_fu_3901_p2 = ($signed(mul_ln38_24_fu_3901_p0) * $signed(in1_loc_24_load_reg_5162));
+
+assign mul_ln38_25_fu_3906_p0 = in2_loc_25_q0;
+
+assign mul_ln38_25_fu_3906_p2 = ($signed(mul_ln38_25_fu_3906_p0) * $signed(in1_loc_25_load_reg_5167));
+
+assign mul_ln38_26_fu_3911_p0 = in2_loc_26_q0;
+
+assign mul_ln38_26_fu_3911_p2 = ($signed(mul_ln38_26_fu_3911_p0) * $signed(in1_loc_26_load_reg_5172));
+
+assign mul_ln38_27_fu_3916_p0 = in2_loc_27_q0;
+
+assign mul_ln38_27_fu_3916_p2 = ($signed(mul_ln38_27_fu_3916_p0) * $signed(in1_loc_27_load_reg_5177));
+
+assign mul_ln38_28_fu_3921_p0 = in2_loc_28_q0;
+
+assign mul_ln38_28_fu_3921_p2 = ($signed(mul_ln38_28_fu_3921_p0) * $signed(in1_loc_28_load_reg_5182));
+
+assign mul_ln38_29_fu_3926_p0 = in2_loc_29_q0;
+
+assign mul_ln38_29_fu_3926_p2 = ($signed(mul_ln38_29_fu_3926_p0) * $signed(in1_loc_29_load_reg_5187));
+
+assign mul_ln38_2_fu_3791_p0 = in2_loc_2_q0;
+
+assign mul_ln38_2_fu_3791_p2 = ($signed(mul_ln38_2_fu_3791_p0) * $signed(in1_loc_2_load_reg_5052));
+
+assign mul_ln38_30_fu_3931_p0 = in2_loc_30_q0;
+
+assign mul_ln38_30_fu_3931_p2 = ($signed(mul_ln38_30_fu_3931_p0) * $signed(in1_loc_30_load_reg_5192));
+
+assign mul_ln38_31_fu_3936_p0 = in2_loc_31_q0;
+
+assign mul_ln38_31_fu_3936_p2 = ($signed(mul_ln38_31_fu_3936_p0) * $signed(in1_loc_31_load_reg_5197));
+
+assign mul_ln38_32_fu_3941_p0 = in2_loc_32_q0;
+
+assign mul_ln38_32_fu_3941_p2 = ($signed(mul_ln38_32_fu_3941_p0) * $signed(in1_loc_32_load_reg_5202));
+
+assign mul_ln38_33_fu_3946_p0 = in2_loc_33_q0;
+
+assign mul_ln38_33_fu_3946_p2 = ($signed(mul_ln38_33_fu_3946_p0) * $signed(in1_loc_33_load_reg_5207));
+
+assign mul_ln38_34_fu_3951_p0 = in2_loc_34_q0;
+
+assign mul_ln38_34_fu_3951_p2 = ($signed(mul_ln38_34_fu_3951_p0) * $signed(in1_loc_34_load_reg_5212));
+
+assign mul_ln38_35_fu_3956_p0 = in2_loc_35_q0;
+
+assign mul_ln38_35_fu_3956_p2 = ($signed(mul_ln38_35_fu_3956_p0) * $signed(in1_loc_35_load_reg_5217));
+
+assign mul_ln38_36_fu_3961_p0 = in2_loc_36_q0;
+
+assign mul_ln38_36_fu_3961_p2 = ($signed(mul_ln38_36_fu_3961_p0) * $signed(in1_loc_36_load_reg_5222));
+
+assign mul_ln38_37_fu_3966_p0 = in2_loc_37_q0;
+
+assign mul_ln38_37_fu_3966_p2 = ($signed(mul_ln38_37_fu_3966_p0) * $signed(in1_loc_37_load_reg_5227));
+
+assign mul_ln38_38_fu_3971_p0 = in2_loc_38_q0;
+
+assign mul_ln38_38_fu_3971_p2 = ($signed(mul_ln38_38_fu_3971_p0) * $signed(in1_loc_38_load_reg_5232));
+
+assign mul_ln38_39_fu_3976_p0 = in2_loc_39_q0;
+
+assign mul_ln38_39_fu_3976_p2 = ($signed(mul_ln38_39_fu_3976_p0) * $signed(in1_loc_39_load_reg_5237));
+
+assign mul_ln38_3_fu_3796_p0 = in2_loc_3_q0;
+
+assign mul_ln38_3_fu_3796_p2 = ($signed(mul_ln38_3_fu_3796_p0) * $signed(in1_loc_3_load_reg_5057));
+
+assign mul_ln38_40_fu_3981_p0 = in2_loc_40_q0;
+
+assign mul_ln38_40_fu_3981_p2 = ($signed(mul_ln38_40_fu_3981_p0) * $signed(in1_loc_40_load_reg_5242));
+
+assign mul_ln38_41_fu_3986_p0 = in2_loc_41_q0;
+
+assign mul_ln38_41_fu_3986_p2 = ($signed(mul_ln38_41_fu_3986_p0) * $signed(in1_loc_41_load_reg_5247));
+
+assign mul_ln38_42_fu_3991_p0 = in2_loc_42_q0;
+
+assign mul_ln38_42_fu_3991_p2 = ($signed(mul_ln38_42_fu_3991_p0) * $signed(in1_loc_42_load_reg_5252));
+
+assign mul_ln38_43_fu_3996_p0 = in2_loc_43_q0;
+
+assign mul_ln38_43_fu_3996_p2 = ($signed(mul_ln38_43_fu_3996_p0) * $signed(in1_loc_43_load_reg_5257));
+
+assign mul_ln38_44_fu_4001_p0 = in2_loc_44_q0;
+
+assign mul_ln38_44_fu_4001_p2 = ($signed(mul_ln38_44_fu_4001_p0) * $signed(in1_loc_44_load_reg_5262));
+
+assign mul_ln38_45_fu_4006_p0 = in2_loc_45_q0;
+
+assign mul_ln38_45_fu_4006_p2 = ($signed(mul_ln38_45_fu_4006_p0) * $signed(in1_loc_45_load_reg_5267));
+
+assign mul_ln38_46_fu_4011_p0 = in2_loc_46_q0;
+
+assign mul_ln38_46_fu_4011_p2 = ($signed(mul_ln38_46_fu_4011_p0) * $signed(in1_loc_46_load_reg_5272));
+
+assign mul_ln38_47_fu_4016_p0 = in2_loc_47_q0;
+
+assign mul_ln38_47_fu_4016_p2 = ($signed(mul_ln38_47_fu_4016_p0) * $signed(in1_loc_47_load_reg_5277));
+
+assign mul_ln38_48_fu_4021_p0 = in2_loc_48_q0;
+
+assign mul_ln38_48_fu_4021_p2 = ($signed(mul_ln38_48_fu_4021_p0) * $signed(in1_loc_48_load_reg_5282));
+
+assign mul_ln38_49_fu_4026_p0 = in2_loc_49_q0;
+
+assign mul_ln38_49_fu_4026_p2 = ($signed(mul_ln38_49_fu_4026_p0) * $signed(in1_loc_49_load_reg_5287));
+
+assign mul_ln38_4_fu_3801_p0 = in2_loc_4_q0;
+
+assign mul_ln38_4_fu_3801_p2 = ($signed(mul_ln38_4_fu_3801_p0) * $signed(in1_loc_4_load_reg_5062));
+
+assign mul_ln38_50_fu_4031_p0 = in2_loc_50_q0;
+
+assign mul_ln38_50_fu_4031_p2 = ($signed(mul_ln38_50_fu_4031_p0) * $signed(in1_loc_50_load_reg_5292));
+
+assign mul_ln38_51_fu_4036_p0 = in2_loc_51_q0;
+
+assign mul_ln38_51_fu_4036_p2 = ($signed(mul_ln38_51_fu_4036_p0) * $signed(in1_loc_51_load_reg_5297));
+
+assign mul_ln38_52_fu_4041_p0 = in2_loc_52_q0;
+
+assign mul_ln38_52_fu_4041_p2 = ($signed(mul_ln38_52_fu_4041_p0) * $signed(in1_loc_52_load_reg_5302));
+
+assign mul_ln38_53_fu_4046_p0 = in2_loc_53_q0;
+
+assign mul_ln38_53_fu_4046_p2 = ($signed(mul_ln38_53_fu_4046_p0) * $signed(in1_loc_53_load_reg_5307));
+
+assign mul_ln38_54_fu_4051_p0 = in2_loc_54_q0;
+
+assign mul_ln38_54_fu_4051_p2 = ($signed(mul_ln38_54_fu_4051_p0) * $signed(in1_loc_54_load_reg_5312));
+
+assign mul_ln38_55_fu_4056_p0 = in2_loc_55_q0;
+
+assign mul_ln38_55_fu_4056_p2 = ($signed(mul_ln38_55_fu_4056_p0) * $signed(in1_loc_55_load_reg_5317));
+
+assign mul_ln38_56_fu_4061_p0 = in2_loc_56_q0;
+
+assign mul_ln38_56_fu_4061_p2 = ($signed(mul_ln38_56_fu_4061_p0) * $signed(in1_loc_56_load_reg_5322));
+
+assign mul_ln38_57_fu_4066_p0 = in2_loc_57_q0;
+
+assign mul_ln38_57_fu_4066_p2 = ($signed(mul_ln38_57_fu_4066_p0) * $signed(in1_loc_57_load_reg_5327));
+
+assign mul_ln38_58_fu_4071_p0 = in2_loc_58_q0;
+
+assign mul_ln38_58_fu_4071_p2 = ($signed(mul_ln38_58_fu_4071_p0) * $signed(in1_loc_58_load_reg_5332));
+
+assign mul_ln38_59_fu_4076_p0 = in2_loc_59_q0;
+
+assign mul_ln38_59_fu_4076_p2 = ($signed(mul_ln38_59_fu_4076_p0) * $signed(in1_loc_59_load_reg_5337));
+
+assign mul_ln38_5_fu_3806_p0 = in2_loc_5_q0;
+
+assign mul_ln38_5_fu_3806_p2 = ($signed(mul_ln38_5_fu_3806_p0) * $signed(in1_loc_5_load_reg_5067));
+
+assign mul_ln38_60_fu_4081_p0 = in2_loc_60_q0;
+
+assign mul_ln38_60_fu_4081_p2 = ($signed(mul_ln38_60_fu_4081_p0) * $signed(in1_loc_60_load_reg_5342));
+
+assign mul_ln38_61_fu_4086_p0 = in2_loc_61_q0;
+
+assign mul_ln38_61_fu_4086_p2 = ($signed(mul_ln38_61_fu_4086_p0) * $signed(in1_loc_61_load_reg_5347));
+
+assign mul_ln38_62_fu_4091_p0 = in2_loc_62_q0;
+
+assign mul_ln38_62_fu_4091_p2 = ($signed(mul_ln38_62_fu_4091_p0) * $signed(in1_loc_62_load_reg_5352));
+
+assign mul_ln38_63_fu_4096_p0 = in2_loc_63_q0;
+
+assign mul_ln38_63_fu_4096_p2 = ($signed(mul_ln38_63_fu_4096_p0) * $signed(in1_loc_63_load_reg_5357));
+
+assign mul_ln38_6_fu_3811_p0 = in2_loc_6_q0;
+
+assign mul_ln38_6_fu_3811_p2 = ($signed(mul_ln38_6_fu_3811_p0) * $signed(in1_loc_6_load_reg_5072));
+
+assign mul_ln38_7_fu_3816_p0 = in2_loc_7_q0;
+
+assign mul_ln38_7_fu_3816_p2 = ($signed(mul_ln38_7_fu_3816_p0) * $signed(in1_loc_7_load_reg_5077));
+
+assign mul_ln38_8_fu_3821_p0 = in2_loc_8_q0;
+
+assign mul_ln38_8_fu_3821_p2 = ($signed(mul_ln38_8_fu_3821_p0) * $signed(in1_loc_8_load_reg_5082));
+
+assign mul_ln38_9_fu_3826_p0 = in2_loc_9_q0;
+
+assign mul_ln38_9_fu_3826_p2 = ($signed(mul_ln38_9_fu_3826_p0) * $signed(in1_loc_9_load_reg_5087));
+
+assign mul_ln38_fu_3781_p0 = in2_loc_0_q0;
+
+assign mul_ln38_fu_3781_p2 = ($signed(mul_ln38_fu_3781_p0) * $signed(in1_loc_0_load_reg_5042));
+
+assign out_loc_d0 = (add_ln38_30_fu_4438_p2 + add_ln38_62_fu_4462_p2);
+
+assign sext_ln38_1_fu_3776_p1 = $signed(add_ln38_64_fu_3771_p2);
+
+assign sext_ln38_fu_3699_p1 = j_0_reg_3328;
+
+assign trunc_ln27_fu_3430_p1 = phi_ln27_reg_3295[5:0];
+
+assign trunc_ln28_fu_3513_p1 = phi_ln28_reg_3306[5:0];
+
+assign trunc_ln38_1_fu_3767_p1 = j_0_reg_3328[13:0];
+
+assign trunc_ln38_fu_3677_p1 = i_0_reg_3317[7:0];
+
+assign zext_ln27_fu_3434_p1 = lshr_ln_reg_4540_pp0_iter1_reg;
+
+assign zext_ln28_fu_3527_p1 = trunc_ln28_reg_4626_pp1_iter1_reg;
+
+assign zext_ln31_fu_3594_p1 = i_0_reg_3317;
+
+assign zext_ln38_1_cast_fu_3681_p3 = {{trunc_ln38_reg_4712}, {6'd0}};
+
+assign zext_ln38_fu_3609_p1 = i_0_reg_3317;
+
+assign zext_ln42_fu_4487_p1 = phi_ln42_reg_3339;
+
+always @ (posedge ap_clk) begin
+    out_mem_addr_reg_4519[31:30] <= 2'b00;
+    in2_mem_addr_reg_4525[31:30] <= 2'b00;
+    zext_ln38_1_cast_reg_5037[5:0] <= 6'b000000;
+end
+
+endmodule //mmult
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in1_loc_0.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in1_loc_0.v
new file mode 100755
index 0000000..7a7e881
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in1_loc_0.v
@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_0_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 6;
+parameter MEM_SIZE = 64;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_0(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd64;
+parameter AddressWidth = 32'd6;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_in1_loc_0_ram mmult_in1_loc_0_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in1_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in1_mem_m_axi.v
new file mode 100755
index 0000000..81f7248
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in1_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in1_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in1_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in1_mem_m_axi_write
+mmult_in1_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in1_mem_m_axi_read
+mmult_in1_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in1_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in1_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in1_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in1_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in1_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in2_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in2_mem_m_axi.v
new file mode 100755
index 0000000..a2eab07
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_in2_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in2_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in2_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in2_mem_m_axi_write
+mmult_in2_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in2_mem_m_axi_read
+mmult_in2_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in2_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in2_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in2_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in2_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in2_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_out_loc.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_out_loc.v
new file mode 100755
index 0000000..dedfa23
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_out_loc.v
@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_out_loc_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_out_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_out_loc_ram mmult_out_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_out_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_out_mem_m_axi.v
new file mode 100755
index 0000000..cc472db
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_out_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_out_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_out_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_out_mem_m_axi_write
+mmult_out_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_out_mem_m_axi_read
+mmult_out_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_out_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_out_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_out_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_out_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_out_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_params_s_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_params_s_axi.v
new file mode 100755
index 0000000..d470352
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/verilog/mmult_params_s_axi.v
@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult.vhd
new file mode 100755
index 0000000..bd183ca
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult.vhd
@@ -0,0 +1,9139 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+-- Version: 2020.1
+-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult is
+generic (
+    C_M_AXI_IN1_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_S_AXI_PARAMS_ADDR_WIDTH : INTEGER := 6;
+    C_S_AXI_PARAMS_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_IN2_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_OUT_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_CACHE_VALUE : INTEGER := 3 );
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    m_axi_in1_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in1_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_WREADY : IN STD_LOGIC;
+    m_axi_in1_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in1_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in1_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in1_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RVALID : IN STD_LOGIC;
+    m_axi_in1_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_RLAST : IN STD_LOGIC;
+    m_axi_in1_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BVALID : IN STD_LOGIC;
+    m_axi_in1_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in2_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_WREADY : IN STD_LOGIC;
+    m_axi_in2_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in2_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in2_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in2_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RVALID : IN STD_LOGIC;
+    m_axi_in2_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_RLAST : IN STD_LOGIC;
+    m_axi_in2_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BVALID : IN STD_LOGIC;
+    m_axi_in2_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_out_mem_AWREADY : IN STD_LOGIC;
+    m_axi_out_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_WVALID : OUT STD_LOGIC;
+    m_axi_out_mem_WREADY : IN STD_LOGIC;
+    m_axi_out_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_out_mem_WLAST : OUT STD_LOGIC;
+    m_axi_out_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_out_mem_ARREADY : IN STD_LOGIC;
+    m_axi_out_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RVALID : IN STD_LOGIC;
+    m_axi_out_mem_RREADY : OUT STD_LOGIC;
+    m_axi_out_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_RLAST : IN STD_LOGIC;
+    m_axi_out_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BVALID : IN STD_LOGIC;
+    m_axi_out_mem_BREADY : OUT STD_LOGIC;
+    m_axi_out_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_BUSER_WIDTH-1 downto 0);
+    s_axi_params_AWVALID : IN STD_LOGIC;
+    s_axi_params_AWREADY : OUT STD_LOGIC;
+    s_axi_params_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_WVALID : IN STD_LOGIC;
+    s_axi_params_WREADY : OUT STD_LOGIC;
+    s_axi_params_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH/8-1 downto 0);
+    s_axi_params_ARVALID : IN STD_LOGIC;
+    s_axi_params_ARREADY : OUT STD_LOGIC;
+    s_axi_params_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_RVALID : OUT STD_LOGIC;
+    s_axi_params_RREADY : IN STD_LOGIC;
+    s_axi_params_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    s_axi_params_BVALID : OUT STD_LOGIC;
+    s_axi_params_BREADY : IN STD_LOGIC;
+    s_axi_params_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    interrupt : OUT STD_LOGIC );
+end;
+
+
+architecture behav of mmult is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=24795,HLS_SYN_TPT=none,HLS_SYN_MEM=142,HLS_SYN_DSP=192,HLS_SYN_FF=4685,HLS_SYN_LUT=8017,HLS_VERSION=2020_1}";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000000000001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000000000010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000000000100";
+    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000000001000";
+    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000000010000";
+    constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000000100000";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000001000000";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000010000000";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000100000000";
+    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000001000000000";
+    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000010000000000";
+    constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000100000000000";
+    constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000001000000000000";
+    constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000010000000000000";
+    constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000100000000000000";
+    constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000001000000000000000";
+    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000010000000000000000";
+    constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000100000000000000000";
+    constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (28 downto 0) := "00000000001000000000000000000";
+    constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (28 downto 0) := "00000000010000000000000000000";
+    constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (28 downto 0) := "00000000100000000000000000000";
+    constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (28 downto 0) := "00000001000000000000000000000";
+    constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (28 downto 0) := "00000010000000000000000000000";
+    constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (28 downto 0) := "00000100000000000000000000000";
+    constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (28 downto 0) := "00001000000000000000000000000";
+    constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (28 downto 0) := "00010000000000000000000000000";
+    constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (28 downto 0) := "00100000000000000000000000000";
+    constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (28 downto 0) := "01000000000000000000000000000";
+    constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (28 downto 0) := "10000000000000000000000000000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
+    constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
+    constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
+    constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
+    constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
+    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
+    constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
+    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
+    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
+    constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
+    constant ap_const_lv32_1000 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000001000000000000";
+    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
+    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
+    constant ap_const_lv6_3E : STD_LOGIC_VECTOR (5 downto 0) := "111110";
+    constant ap_const_lv6_3D : STD_LOGIC_VECTOR (5 downto 0) := "111101";
+    constant ap_const_lv6_3C : STD_LOGIC_VECTOR (5 downto 0) := "111100";
+    constant ap_const_lv6_3B : STD_LOGIC_VECTOR (5 downto 0) := "111011";
+    constant ap_const_lv6_3A : STD_LOGIC_VECTOR (5 downto 0) := "111010";
+    constant ap_const_lv6_39 : STD_LOGIC_VECTOR (5 downto 0) := "111001";
+    constant ap_const_lv6_38 : STD_LOGIC_VECTOR (5 downto 0) := "111000";
+    constant ap_const_lv6_37 : STD_LOGIC_VECTOR (5 downto 0) := "110111";
+    constant ap_const_lv6_36 : STD_LOGIC_VECTOR (5 downto 0) := "110110";
+    constant ap_const_lv6_35 : STD_LOGIC_VECTOR (5 downto 0) := "110101";
+    constant ap_const_lv6_34 : STD_LOGIC_VECTOR (5 downto 0) := "110100";
+    constant ap_const_lv6_33 : STD_LOGIC_VECTOR (5 downto 0) := "110011";
+    constant ap_const_lv6_32 : STD_LOGIC_VECTOR (5 downto 0) := "110010";
+    constant ap_const_lv6_31 : STD_LOGIC_VECTOR (5 downto 0) := "110001";
+    constant ap_const_lv6_30 : STD_LOGIC_VECTOR (5 downto 0) := "110000";
+    constant ap_const_lv6_2F : STD_LOGIC_VECTOR (5 downto 0) := "101111";
+    constant ap_const_lv6_2E : STD_LOGIC_VECTOR (5 downto 0) := "101110";
+    constant ap_const_lv6_2D : STD_LOGIC_VECTOR (5 downto 0) := "101101";
+    constant ap_const_lv6_2C : STD_LOGIC_VECTOR (5 downto 0) := "101100";
+    constant ap_const_lv6_2B : STD_LOGIC_VECTOR (5 downto 0) := "101011";
+    constant ap_const_lv6_2A : STD_LOGIC_VECTOR (5 downto 0) := "101010";
+    constant ap_const_lv6_29 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
+    constant ap_const_lv6_28 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
+    constant ap_const_lv6_27 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
+    constant ap_const_lv6_26 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
+    constant ap_const_lv6_25 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
+    constant ap_const_lv6_24 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
+    constant ap_const_lv6_23 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
+    constant ap_const_lv6_22 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
+    constant ap_const_lv6_21 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
+    constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
+    constant ap_const_lv6_1F : STD_LOGIC_VECTOR (5 downto 0) := "011111";
+    constant ap_const_lv6_1E : STD_LOGIC_VECTOR (5 downto 0) := "011110";
+    constant ap_const_lv6_1D : STD_LOGIC_VECTOR (5 downto 0) := "011101";
+    constant ap_const_lv6_1C : STD_LOGIC_VECTOR (5 downto 0) := "011100";
+    constant ap_const_lv6_1B : STD_LOGIC_VECTOR (5 downto 0) := "011011";
+    constant ap_const_lv6_1A : STD_LOGIC_VECTOR (5 downto 0) := "011010";
+    constant ap_const_lv6_19 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
+    constant ap_const_lv6_18 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
+    constant ap_const_lv6_17 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
+    constant ap_const_lv6_16 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
+    constant ap_const_lv6_15 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
+    constant ap_const_lv6_14 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
+    constant ap_const_lv6_13 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
+    constant ap_const_lv6_12 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
+    constant ap_const_lv6_11 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
+    constant ap_const_lv6_10 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
+    constant ap_const_lv6_F : STD_LOGIC_VECTOR (5 downto 0) := "001111";
+    constant ap_const_lv6_E : STD_LOGIC_VECTOR (5 downto 0) := "001110";
+    constant ap_const_lv6_D : STD_LOGIC_VECTOR (5 downto 0) := "001101";
+    constant ap_const_lv6_C : STD_LOGIC_VECTOR (5 downto 0) := "001100";
+    constant ap_const_lv6_B : STD_LOGIC_VECTOR (5 downto 0) := "001011";
+    constant ap_const_lv6_A : STD_LOGIC_VECTOR (5 downto 0) := "001010";
+    constant ap_const_lv6_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
+    constant ap_const_lv6_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
+    constant ap_const_lv6_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
+    constant ap_const_lv6_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
+    constant ap_const_lv6_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
+    constant ap_const_lv6_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
+    constant ap_const_lv6_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
+    constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
+    constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
+    constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
+    constant ap_const_lv6_3F : STD_LOGIC_VECTOR (5 downto 0) := "111111";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv13_1000 : STD_LOGIC_VECTOR (12 downto 0) := "1000000000000";
+    constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
+    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
+    constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
+    constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
+    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal ap_start : STD_LOGIC;
+    signal ap_done : STD_LOGIC;
+    signal ap_idle : STD_LOGIC;
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000000000000000001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal ap_ready : STD_LOGIC;
+    signal in1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_r : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal in1_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal in2_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state12 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
+    signal in2_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
+    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp1_stage0 : BOOLEAN;
+    signal out_mem_blk_n_AW : STD_LOGIC;
+    signal ap_CS_fsm_state23 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state23 : signal is "none";
+    signal icmp_ln31_fu_3598_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_W : STD_LOGIC;
+    signal ap_enable_reg_pp2_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp2_stage0 : BOOLEAN;
+    signal icmp_ln42_reg_5750 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln42_reg_5750_pp2_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_B : STD_LOGIC;
+    signal ap_CS_fsm_state35 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state35 : signal is "none";
+    signal in1_mem_AWREADY : STD_LOGIC;
+    signal in1_mem_WREADY : STD_LOGIC;
+    signal in1_mem_ARVALID : STD_LOGIC;
+    signal in1_mem_ARREADY : STD_LOGIC;
+    signal in1_mem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RVALID : STD_LOGIC;
+    signal in1_mem_RREADY : STD_LOGIC;
+    signal in1_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RLAST : STD_LOGIC;
+    signal in1_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BVALID : STD_LOGIC;
+    signal in1_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_AWREADY : STD_LOGIC;
+    signal in2_mem_WREADY : STD_LOGIC;
+    signal in2_mem_ARVALID : STD_LOGIC;
+    signal in2_mem_ARREADY : STD_LOGIC;
+    signal in2_mem_RVALID : STD_LOGIC;
+    signal in2_mem_RREADY : STD_LOGIC;
+    signal in2_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_RLAST : STD_LOGIC;
+    signal in2_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BVALID : STD_LOGIC;
+    signal in2_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_AWVALID : STD_LOGIC;
+    signal out_mem_AWREADY : STD_LOGIC;
+    signal out_mem_WVALID : STD_LOGIC;
+    signal out_mem_WREADY : STD_LOGIC;
+    signal out_mem_ARREADY : STD_LOGIC;
+    signal out_mem_RVALID : STD_LOGIC;
+    signal out_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_RLAST : STD_LOGIC;
+    signal out_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BVALID : STD_LOGIC;
+    signal out_mem_BREADY : STD_LOGIC;
+    signal out_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal phi_ln27_reg_3295 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln28_reg_3306 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln42_reg_3339 : STD_LOGIC_VECTOR (12 downto 0);
+    signal dim_read_reg_4492 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out5_reg_4498 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in_reg_4503 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in3_reg_4508 : STD_LOGIC_VECTOR (29 downto 0);
+    signal out_mem_addr_reg_4519 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
+    signal in2_mem_addr_reg_4525 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln27_fu_3408_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state9_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state11_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal add_ln27_fu_3414_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal lshr_ln_reg_4540 : STD_LOGIC_VECTOR (6 downto 0);
+    signal lshr_ln_reg_4540_pp0_iter1_reg : STD_LOGIC_VECTOR (6 downto 0);
+    signal trunc_ln27_fu_3430_p1 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln27_reg_4545 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln27_reg_4545_pp0_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_mem_addr_read_reg_4549 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln28_fu_3501_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state19_pp1_stage0_iter0 : BOOLEAN;
+    signal ap_block_state20_pp1_stage0_iter1 : BOOLEAN;
+    signal ap_block_state21_pp1_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp1_stage0_11001 : BOOLEAN;
+    signal add_ln28_fu_3507_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
+    signal trunc_ln28_fu_3513_p1 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln28_reg_4626 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln28_reg_4626_pp1_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln1_reg_4631 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln1_reg_4631_pp1_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_mem_addr_read_reg_4635 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state23_io : BOOLEAN;
+    signal i_fu_3603_p2 : STD_LOGIC_VECTOR (30 downto 0);
+    signal i_reg_4707 : STD_LOGIC_VECTOR (30 downto 0);
+    signal trunc_ln38_fu_3677_p1 : STD_LOGIC_VECTOR (7 downto 0);
+    signal trunc_ln38_reg_4712 : STD_LOGIC_VECTOR (7 downto 0);
+    signal zext_ln38_1_cast_fu_3681_p3 : STD_LOGIC_VECTOR (13 downto 0);
+    signal zext_ln38_1_cast_reg_5037 : STD_LOGIC_VECTOR (13 downto 0);
+    signal ap_CS_fsm_state24 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state24 : signal is "none";
+    signal in1_loc_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_0_load_reg_5042 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_1_load_reg_5047 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_2_load_reg_5052 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_3_load_reg_5057 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_4_load_reg_5062 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_5_load_reg_5067 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_6_load_reg_5072 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_7_load_reg_5077 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_8_load_reg_5082 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_9_load_reg_5087 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_10_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_10_load_reg_5092 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_11_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_11_load_reg_5097 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_12_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_12_load_reg_5102 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_13_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_13_load_reg_5107 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_14_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_14_load_reg_5112 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_15_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_15_load_reg_5117 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_16_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_16_load_reg_5122 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_17_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_17_load_reg_5127 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_18_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_18_load_reg_5132 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_19_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_19_load_reg_5137 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_20_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_20_load_reg_5142 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_21_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_21_load_reg_5147 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_22_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_22_load_reg_5152 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_23_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_23_load_reg_5157 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_24_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_24_load_reg_5162 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_25_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_25_load_reg_5167 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_26_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_26_load_reg_5172 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_27_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_27_load_reg_5177 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_28_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_28_load_reg_5182 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_29_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_29_load_reg_5187 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_30_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_30_load_reg_5192 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_31_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_31_load_reg_5197 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_32_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_32_load_reg_5202 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_33_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_33_load_reg_5207 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_34_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_34_load_reg_5212 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_35_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_35_load_reg_5217 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_36_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_36_load_reg_5222 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_37_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_37_load_reg_5227 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_38_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_38_load_reg_5232 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_39_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_39_load_reg_5237 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_40_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_40_load_reg_5242 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_41_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_41_load_reg_5247 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_42_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_42_load_reg_5252 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_43_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_43_load_reg_5257 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_44_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_44_load_reg_5262 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_45_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_45_load_reg_5267 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_46_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_46_load_reg_5272 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_47_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_47_load_reg_5277 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_48_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_48_load_reg_5282 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_49_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_49_load_reg_5287 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_50_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_50_load_reg_5292 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_51_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_51_load_reg_5297 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_52_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_52_load_reg_5302 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_53_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_53_load_reg_5307 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_54_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_54_load_reg_5312 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_55_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_55_load_reg_5317 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_56_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_56_load_reg_5322 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_57_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_57_load_reg_5327 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_58_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_58_load_reg_5332 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_59_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_59_load_reg_5337 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_60_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_60_load_reg_5342 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_61_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_61_load_reg_5347 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_62_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_62_load_reg_5352 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_63_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_63_load_reg_5357 : STD_LOGIC_VECTOR (31 downto 0);
+    signal j_fu_3693_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal j_reg_5365 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state25 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
+    signal out_loc_addr_reg_5370 : STD_LOGIC_VECTOR (11 downto 0);
+    signal icmp_ln33_fu_3688_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln38_6_fu_4137_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_6_reg_5695 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state26 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
+    signal add_ln38_9_fu_4155_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_9_reg_5700 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_12_fu_4173_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_12_reg_5705 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_fu_4215_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_reg_5710 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_28_fu_4257_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_28_reg_5715 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_fu_4299_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_reg_5720 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_40_fu_4317_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_40_reg_5725 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_43_fu_4335_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_43_reg_5730 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_fu_4377_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_reg_5735 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_55_fu_4395_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_55_reg_5740 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_59_fu_4419_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_59_reg_5745 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln42_fu_4475_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
+    signal ap_block_state28_pp2_stage0_iter0 : BOOLEAN;
+    signal ap_block_state29_pp2_stage0_iter1 : BOOLEAN;
+    signal ap_block_state30_pp2_stage0_iter2 : BOOLEAN;
+    signal ap_block_state30_io : BOOLEAN;
+    signal ap_block_pp2_stage0_11001 : BOOLEAN;
+    signal add_ln42_fu_4481_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
+    signal out_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_load_reg_5764 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state9 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_CS_fsm_state18 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
+    signal ap_block_pp1_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp1_exit_iter0_state19 : STD_LOGIC;
+    signal ap_enable_reg_pp1_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp2_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp2_exit_iter0_state28 : STD_LOGIC;
+    signal in1_loc_0_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_0_ce0 : STD_LOGIC;
+    signal in1_loc_0_we0 : STD_LOGIC;
+    signal in1_loc_1_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_1_ce0 : STD_LOGIC;
+    signal in1_loc_1_we0 : STD_LOGIC;
+    signal in1_loc_2_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_2_ce0 : STD_LOGIC;
+    signal in1_loc_2_we0 : STD_LOGIC;
+    signal in1_loc_3_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_3_ce0 : STD_LOGIC;
+    signal in1_loc_3_we0 : STD_LOGIC;
+    signal in1_loc_4_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_4_ce0 : STD_LOGIC;
+    signal in1_loc_4_we0 : STD_LOGIC;
+    signal in1_loc_5_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_5_ce0 : STD_LOGIC;
+    signal in1_loc_5_we0 : STD_LOGIC;
+    signal in1_loc_6_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_6_ce0 : STD_LOGIC;
+    signal in1_loc_6_we0 : STD_LOGIC;
+    signal in1_loc_7_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_7_ce0 : STD_LOGIC;
+    signal in1_loc_7_we0 : STD_LOGIC;
+    signal in1_loc_8_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_8_ce0 : STD_LOGIC;
+    signal in1_loc_8_we0 : STD_LOGIC;
+    signal in1_loc_9_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_9_ce0 : STD_LOGIC;
+    signal in1_loc_9_we0 : STD_LOGIC;
+    signal in1_loc_10_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_10_ce0 : STD_LOGIC;
+    signal in1_loc_10_we0 : STD_LOGIC;
+    signal in1_loc_11_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_11_ce0 : STD_LOGIC;
+    signal in1_loc_11_we0 : STD_LOGIC;
+    signal in1_loc_12_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_12_ce0 : STD_LOGIC;
+    signal in1_loc_12_we0 : STD_LOGIC;
+    signal in1_loc_13_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_13_ce0 : STD_LOGIC;
+    signal in1_loc_13_we0 : STD_LOGIC;
+    signal in1_loc_14_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_14_ce0 : STD_LOGIC;
+    signal in1_loc_14_we0 : STD_LOGIC;
+    signal in1_loc_15_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_15_ce0 : STD_LOGIC;
+    signal in1_loc_15_we0 : STD_LOGIC;
+    signal in1_loc_16_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_16_ce0 : STD_LOGIC;
+    signal in1_loc_16_we0 : STD_LOGIC;
+    signal in1_loc_17_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_17_ce0 : STD_LOGIC;
+    signal in1_loc_17_we0 : STD_LOGIC;
+    signal in1_loc_18_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_18_ce0 : STD_LOGIC;
+    signal in1_loc_18_we0 : STD_LOGIC;
+    signal in1_loc_19_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_19_ce0 : STD_LOGIC;
+    signal in1_loc_19_we0 : STD_LOGIC;
+    signal in1_loc_20_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_20_ce0 : STD_LOGIC;
+    signal in1_loc_20_we0 : STD_LOGIC;
+    signal in1_loc_21_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_21_ce0 : STD_LOGIC;
+    signal in1_loc_21_we0 : STD_LOGIC;
+    signal in1_loc_22_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_22_ce0 : STD_LOGIC;
+    signal in1_loc_22_we0 : STD_LOGIC;
+    signal in1_loc_23_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_23_ce0 : STD_LOGIC;
+    signal in1_loc_23_we0 : STD_LOGIC;
+    signal in1_loc_24_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_24_ce0 : STD_LOGIC;
+    signal in1_loc_24_we0 : STD_LOGIC;
+    signal in1_loc_25_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_25_ce0 : STD_LOGIC;
+    signal in1_loc_25_we0 : STD_LOGIC;
+    signal in1_loc_26_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_26_ce0 : STD_LOGIC;
+    signal in1_loc_26_we0 : STD_LOGIC;
+    signal in1_loc_27_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_27_ce0 : STD_LOGIC;
+    signal in1_loc_27_we0 : STD_LOGIC;
+    signal in1_loc_28_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_28_ce0 : STD_LOGIC;
+    signal in1_loc_28_we0 : STD_LOGIC;
+    signal in1_loc_29_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_29_ce0 : STD_LOGIC;
+    signal in1_loc_29_we0 : STD_LOGIC;
+    signal in1_loc_30_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_30_ce0 : STD_LOGIC;
+    signal in1_loc_30_we0 : STD_LOGIC;
+    signal in1_loc_31_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_31_ce0 : STD_LOGIC;
+    signal in1_loc_31_we0 : STD_LOGIC;
+    signal in1_loc_32_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_32_ce0 : STD_LOGIC;
+    signal in1_loc_32_we0 : STD_LOGIC;
+    signal in1_loc_33_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_33_ce0 : STD_LOGIC;
+    signal in1_loc_33_we0 : STD_LOGIC;
+    signal in1_loc_34_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_34_ce0 : STD_LOGIC;
+    signal in1_loc_34_we0 : STD_LOGIC;
+    signal in1_loc_35_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_35_ce0 : STD_LOGIC;
+    signal in1_loc_35_we0 : STD_LOGIC;
+    signal in1_loc_36_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_36_ce0 : STD_LOGIC;
+    signal in1_loc_36_we0 : STD_LOGIC;
+    signal in1_loc_37_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_37_ce0 : STD_LOGIC;
+    signal in1_loc_37_we0 : STD_LOGIC;
+    signal in1_loc_38_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_38_ce0 : STD_LOGIC;
+    signal in1_loc_38_we0 : STD_LOGIC;
+    signal in1_loc_39_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_39_ce0 : STD_LOGIC;
+    signal in1_loc_39_we0 : STD_LOGIC;
+    signal in1_loc_40_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_40_ce0 : STD_LOGIC;
+    signal in1_loc_40_we0 : STD_LOGIC;
+    signal in1_loc_41_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_41_ce0 : STD_LOGIC;
+    signal in1_loc_41_we0 : STD_LOGIC;
+    signal in1_loc_42_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_42_ce0 : STD_LOGIC;
+    signal in1_loc_42_we0 : STD_LOGIC;
+    signal in1_loc_43_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_43_ce0 : STD_LOGIC;
+    signal in1_loc_43_we0 : STD_LOGIC;
+    signal in1_loc_44_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_44_ce0 : STD_LOGIC;
+    signal in1_loc_44_we0 : STD_LOGIC;
+    signal in1_loc_45_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_45_ce0 : STD_LOGIC;
+    signal in1_loc_45_we0 : STD_LOGIC;
+    signal in1_loc_46_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_46_ce0 : STD_LOGIC;
+    signal in1_loc_46_we0 : STD_LOGIC;
+    signal in1_loc_47_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_47_ce0 : STD_LOGIC;
+    signal in1_loc_47_we0 : STD_LOGIC;
+    signal in1_loc_48_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_48_ce0 : STD_LOGIC;
+    signal in1_loc_48_we0 : STD_LOGIC;
+    signal in1_loc_49_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_49_ce0 : STD_LOGIC;
+    signal in1_loc_49_we0 : STD_LOGIC;
+    signal in1_loc_50_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_50_ce0 : STD_LOGIC;
+    signal in1_loc_50_we0 : STD_LOGIC;
+    signal in1_loc_51_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_51_ce0 : STD_LOGIC;
+    signal in1_loc_51_we0 : STD_LOGIC;
+    signal in1_loc_52_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_52_ce0 : STD_LOGIC;
+    signal in1_loc_52_we0 : STD_LOGIC;
+    signal in1_loc_53_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_53_ce0 : STD_LOGIC;
+    signal in1_loc_53_we0 : STD_LOGIC;
+    signal in1_loc_54_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_54_ce0 : STD_LOGIC;
+    signal in1_loc_54_we0 : STD_LOGIC;
+    signal in1_loc_55_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_55_ce0 : STD_LOGIC;
+    signal in1_loc_55_we0 : STD_LOGIC;
+    signal in1_loc_56_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_56_ce0 : STD_LOGIC;
+    signal in1_loc_56_we0 : STD_LOGIC;
+    signal in1_loc_57_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_57_ce0 : STD_LOGIC;
+    signal in1_loc_57_we0 : STD_LOGIC;
+    signal in1_loc_58_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_58_ce0 : STD_LOGIC;
+    signal in1_loc_58_we0 : STD_LOGIC;
+    signal in1_loc_59_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_59_ce0 : STD_LOGIC;
+    signal in1_loc_59_we0 : STD_LOGIC;
+    signal in1_loc_60_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_60_ce0 : STD_LOGIC;
+    signal in1_loc_60_we0 : STD_LOGIC;
+    signal in1_loc_61_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_61_ce0 : STD_LOGIC;
+    signal in1_loc_61_we0 : STD_LOGIC;
+    signal in1_loc_62_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_62_ce0 : STD_LOGIC;
+    signal in1_loc_62_we0 : STD_LOGIC;
+    signal in1_loc_63_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_63_ce0 : STD_LOGIC;
+    signal in1_loc_63_we0 : STD_LOGIC;
+    signal in2_loc_0_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_0_ce0 : STD_LOGIC;
+    signal in2_loc_0_we0 : STD_LOGIC;
+    signal in2_loc_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_1_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_1_ce0 : STD_LOGIC;
+    signal in2_loc_1_we0 : STD_LOGIC;
+    signal in2_loc_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_2_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_2_ce0 : STD_LOGIC;
+    signal in2_loc_2_we0 : STD_LOGIC;
+    signal in2_loc_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_3_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_3_ce0 : STD_LOGIC;
+    signal in2_loc_3_we0 : STD_LOGIC;
+    signal in2_loc_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_4_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_4_ce0 : STD_LOGIC;
+    signal in2_loc_4_we0 : STD_LOGIC;
+    signal in2_loc_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_5_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_5_ce0 : STD_LOGIC;
+    signal in2_loc_5_we0 : STD_LOGIC;
+    signal in2_loc_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_6_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_6_ce0 : STD_LOGIC;
+    signal in2_loc_6_we0 : STD_LOGIC;
+    signal in2_loc_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_7_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_7_ce0 : STD_LOGIC;
+    signal in2_loc_7_we0 : STD_LOGIC;
+    signal in2_loc_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_8_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_8_ce0 : STD_LOGIC;
+    signal in2_loc_8_we0 : STD_LOGIC;
+    signal in2_loc_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_9_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_9_ce0 : STD_LOGIC;
+    signal in2_loc_9_we0 : STD_LOGIC;
+    signal in2_loc_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_10_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_10_ce0 : STD_LOGIC;
+    signal in2_loc_10_we0 : STD_LOGIC;
+    signal in2_loc_10_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_11_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_11_ce0 : STD_LOGIC;
+    signal in2_loc_11_we0 : STD_LOGIC;
+    signal in2_loc_11_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_12_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_12_ce0 : STD_LOGIC;
+    signal in2_loc_12_we0 : STD_LOGIC;
+    signal in2_loc_12_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_13_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_13_ce0 : STD_LOGIC;
+    signal in2_loc_13_we0 : STD_LOGIC;
+    signal in2_loc_13_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_14_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_14_ce0 : STD_LOGIC;
+    signal in2_loc_14_we0 : STD_LOGIC;
+    signal in2_loc_14_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_15_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_15_ce0 : STD_LOGIC;
+    signal in2_loc_15_we0 : STD_LOGIC;
+    signal in2_loc_15_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_16_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_16_ce0 : STD_LOGIC;
+    signal in2_loc_16_we0 : STD_LOGIC;
+    signal in2_loc_16_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_17_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_17_ce0 : STD_LOGIC;
+    signal in2_loc_17_we0 : STD_LOGIC;
+    signal in2_loc_17_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_18_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_18_ce0 : STD_LOGIC;
+    signal in2_loc_18_we0 : STD_LOGIC;
+    signal in2_loc_18_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_19_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_19_ce0 : STD_LOGIC;
+    signal in2_loc_19_we0 : STD_LOGIC;
+    signal in2_loc_19_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_20_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_20_ce0 : STD_LOGIC;
+    signal in2_loc_20_we0 : STD_LOGIC;
+    signal in2_loc_20_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_21_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_21_ce0 : STD_LOGIC;
+    signal in2_loc_21_we0 : STD_LOGIC;
+    signal in2_loc_21_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_22_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_22_ce0 : STD_LOGIC;
+    signal in2_loc_22_we0 : STD_LOGIC;
+    signal in2_loc_22_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_23_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_23_ce0 : STD_LOGIC;
+    signal in2_loc_23_we0 : STD_LOGIC;
+    signal in2_loc_23_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_24_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_24_ce0 : STD_LOGIC;
+    signal in2_loc_24_we0 : STD_LOGIC;
+    signal in2_loc_24_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_25_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_25_ce0 : STD_LOGIC;
+    signal in2_loc_25_we0 : STD_LOGIC;
+    signal in2_loc_25_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_26_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_26_ce0 : STD_LOGIC;
+    signal in2_loc_26_we0 : STD_LOGIC;
+    signal in2_loc_26_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_27_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_27_ce0 : STD_LOGIC;
+    signal in2_loc_27_we0 : STD_LOGIC;
+    signal in2_loc_27_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_28_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_28_ce0 : STD_LOGIC;
+    signal in2_loc_28_we0 : STD_LOGIC;
+    signal in2_loc_28_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_29_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_29_ce0 : STD_LOGIC;
+    signal in2_loc_29_we0 : STD_LOGIC;
+    signal in2_loc_29_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_30_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_30_ce0 : STD_LOGIC;
+    signal in2_loc_30_we0 : STD_LOGIC;
+    signal in2_loc_30_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_31_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_31_ce0 : STD_LOGIC;
+    signal in2_loc_31_we0 : STD_LOGIC;
+    signal in2_loc_31_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_32_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_32_ce0 : STD_LOGIC;
+    signal in2_loc_32_we0 : STD_LOGIC;
+    signal in2_loc_32_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_33_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_33_ce0 : STD_LOGIC;
+    signal in2_loc_33_we0 : STD_LOGIC;
+    signal in2_loc_33_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_34_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_34_ce0 : STD_LOGIC;
+    signal in2_loc_34_we0 : STD_LOGIC;
+    signal in2_loc_34_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_35_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_35_ce0 : STD_LOGIC;
+    signal in2_loc_35_we0 : STD_LOGIC;
+    signal in2_loc_35_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_36_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_36_ce0 : STD_LOGIC;
+    signal in2_loc_36_we0 : STD_LOGIC;
+    signal in2_loc_36_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_37_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_37_ce0 : STD_LOGIC;
+    signal in2_loc_37_we0 : STD_LOGIC;
+    signal in2_loc_37_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_38_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_38_ce0 : STD_LOGIC;
+    signal in2_loc_38_we0 : STD_LOGIC;
+    signal in2_loc_38_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_39_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_39_ce0 : STD_LOGIC;
+    signal in2_loc_39_we0 : STD_LOGIC;
+    signal in2_loc_39_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_40_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_40_ce0 : STD_LOGIC;
+    signal in2_loc_40_we0 : STD_LOGIC;
+    signal in2_loc_40_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_41_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_41_ce0 : STD_LOGIC;
+    signal in2_loc_41_we0 : STD_LOGIC;
+    signal in2_loc_41_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_42_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_42_ce0 : STD_LOGIC;
+    signal in2_loc_42_we0 : STD_LOGIC;
+    signal in2_loc_42_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_43_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_43_ce0 : STD_LOGIC;
+    signal in2_loc_43_we0 : STD_LOGIC;
+    signal in2_loc_43_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_44_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_44_ce0 : STD_LOGIC;
+    signal in2_loc_44_we0 : STD_LOGIC;
+    signal in2_loc_44_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_45_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_45_ce0 : STD_LOGIC;
+    signal in2_loc_45_we0 : STD_LOGIC;
+    signal in2_loc_45_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_46_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_46_ce0 : STD_LOGIC;
+    signal in2_loc_46_we0 : STD_LOGIC;
+    signal in2_loc_46_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_47_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_47_ce0 : STD_LOGIC;
+    signal in2_loc_47_we0 : STD_LOGIC;
+    signal in2_loc_47_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_48_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_48_ce0 : STD_LOGIC;
+    signal in2_loc_48_we0 : STD_LOGIC;
+    signal in2_loc_48_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_49_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_49_ce0 : STD_LOGIC;
+    signal in2_loc_49_we0 : STD_LOGIC;
+    signal in2_loc_49_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_50_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_50_ce0 : STD_LOGIC;
+    signal in2_loc_50_we0 : STD_LOGIC;
+    signal in2_loc_50_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_51_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_51_ce0 : STD_LOGIC;
+    signal in2_loc_51_we0 : STD_LOGIC;
+    signal in2_loc_51_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_52_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_52_ce0 : STD_LOGIC;
+    signal in2_loc_52_we0 : STD_LOGIC;
+    signal in2_loc_52_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_53_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_53_ce0 : STD_LOGIC;
+    signal in2_loc_53_we0 : STD_LOGIC;
+    signal in2_loc_53_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_54_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_54_ce0 : STD_LOGIC;
+    signal in2_loc_54_we0 : STD_LOGIC;
+    signal in2_loc_54_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_55_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_55_ce0 : STD_LOGIC;
+    signal in2_loc_55_we0 : STD_LOGIC;
+    signal in2_loc_55_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_56_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_56_ce0 : STD_LOGIC;
+    signal in2_loc_56_we0 : STD_LOGIC;
+    signal in2_loc_56_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_57_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_57_ce0 : STD_LOGIC;
+    signal in2_loc_57_we0 : STD_LOGIC;
+    signal in2_loc_57_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_58_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_58_ce0 : STD_LOGIC;
+    signal in2_loc_58_we0 : STD_LOGIC;
+    signal in2_loc_58_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_59_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_59_ce0 : STD_LOGIC;
+    signal in2_loc_59_we0 : STD_LOGIC;
+    signal in2_loc_59_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_60_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_60_ce0 : STD_LOGIC;
+    signal in2_loc_60_we0 : STD_LOGIC;
+    signal in2_loc_60_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_61_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_61_ce0 : STD_LOGIC;
+    signal in2_loc_61_we0 : STD_LOGIC;
+    signal in2_loc_61_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_62_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_62_ce0 : STD_LOGIC;
+    signal in2_loc_62_we0 : STD_LOGIC;
+    signal in2_loc_62_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_63_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_63_ce0 : STD_LOGIC;
+    signal in2_loc_63_we0 : STD_LOGIC;
+    signal in2_loc_63_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_ce0 : STD_LOGIC;
+    signal out_loc_we0 : STD_LOGIC;
+    signal out_loc_d0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal i_0_reg_3317 : STD_LOGIC_VECTOR (30 downto 0);
+    signal ap_CS_fsm_state22 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
+    signal j_0_reg_3328 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state27 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
+    signal zext_ln27_fu_3434_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln28_fu_3527_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln38_fu_3609_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_1_fu_3776_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_fu_3699_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln42_fu_4487_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_8_fu_3380_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_fu_3390_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_7_fu_3399_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp2_stage0_01001 : BOOLEAN;
+    signal zext_ln31_fu_3594_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal trunc_ln38_1_fu_3767_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_64_fu_3771_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_fu_3781_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_fu_3786_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_fu_3791_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_fu_3796_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_fu_3801_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_fu_3806_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_fu_3811_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_fu_3816_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_fu_3821_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_fu_3826_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_fu_3831_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_fu_3836_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_fu_3841_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_fu_3846_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_fu_3851_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_fu_3856_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_fu_3861_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_fu_3866_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_fu_3871_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_fu_3876_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_fu_3881_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_fu_3886_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_fu_3891_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_fu_3896_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_fu_3901_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_fu_3906_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_fu_3911_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_fu_3916_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_fu_3921_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_fu_3926_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_fu_3931_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_fu_3936_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_fu_3941_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_fu_3946_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_fu_3951_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_fu_3956_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_fu_3961_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_fu_3966_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_fu_3971_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_fu_3976_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_fu_3981_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_fu_3986_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_fu_3991_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_fu_3996_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_fu_4001_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_fu_4006_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_fu_4011_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_fu_4016_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_fu_4021_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_fu_4026_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_fu_4031_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_fu_4036_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_fu_4041_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_fu_4046_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_fu_4051_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_fu_4056_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_fu_4061_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_fu_4066_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_fu_4071_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_fu_4076_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_fu_4081_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_fu_4086_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_fu_4091_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_fu_4096_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_fu_3781_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_fu_3791_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_fu_3786_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_fu_4101_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_1_fu_4107_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_fu_3801_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_fu_3796_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_fu_3811_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_fu_3806_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_3_fu_4119_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_4_fu_4125_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_2_fu_4113_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_5_fu_4131_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_fu_3821_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_fu_3816_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_fu_3831_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_fu_3826_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_7_fu_4143_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_8_fu_4149_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_fu_3841_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_fu_3836_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_fu_3851_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_fu_3846_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_10_fu_4161_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_11_fu_4167_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_fu_3861_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_fu_3856_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_fu_3871_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_fu_3866_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_15_fu_4179_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_16_fu_4185_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_fu_3881_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_fu_3876_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_fu_3891_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_fu_3886_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_18_fu_4197_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_19_fu_4203_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_17_fu_4191_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_20_fu_4209_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_fu_3901_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_fu_3896_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_fu_3911_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_fu_3906_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_22_fu_4221_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_23_fu_4227_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_fu_3921_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_fu_3916_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_fu_3931_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_fu_3926_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_25_fu_4239_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_26_fu_4245_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_24_fu_4233_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_27_fu_4251_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_fu_3941_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_fu_3936_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_fu_3951_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_fu_3946_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_31_fu_4263_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_32_fu_4269_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_fu_3961_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_fu_3956_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_fu_3971_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_fu_3966_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_34_fu_4281_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_35_fu_4287_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_33_fu_4275_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_36_fu_4293_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_fu_3981_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_fu_3976_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_fu_3991_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_fu_3986_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_38_fu_4305_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_39_fu_4311_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_fu_4001_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_fu_3996_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_fu_4011_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_fu_4006_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_41_fu_4323_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_42_fu_4329_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_fu_4021_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_fu_4016_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_fu_4031_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_fu_4026_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_46_fu_4341_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_47_fu_4347_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_fu_4041_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_fu_4036_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_fu_4051_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_fu_4046_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_49_fu_4359_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_50_fu_4365_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_48_fu_4353_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_51_fu_4371_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_fu_4061_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_fu_4056_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_fu_4071_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_fu_4066_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_53_fu_4383_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_54_fu_4389_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_fu_4081_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_fu_4076_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_fu_4096_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_fu_4091_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_fu_4086_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_57_fu_4407_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_56_fu_4401_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_58_fu_4413_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_13_fu_4425_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_14_fu_4429_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_29_fu_4434_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_44_fu_4444_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_60_fu_4453_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_45_fu_4448_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_61_fu_4457_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_30_fu_4438_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_62_fu_4462_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (28 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal ap_idle_pp1 : STD_LOGIC;
+    signal ap_enable_pp1 : STD_LOGIC;
+    signal ap_idle_pp2 : STD_LOGIC;
+    signal ap_enable_pp2 : STD_LOGIC;
+
+    component mmult_in1_loc_0 IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (5 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_out_loc IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_params_s_axi IS
+    generic (
+        C_S_AXI_ADDR_WIDTH : INTEGER;
+        C_S_AXI_DATA_WIDTH : INTEGER );
+    port (
+        AWVALID : IN STD_LOGIC;
+        AWREADY : OUT STD_LOGIC;
+        AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        WVALID : IN STD_LOGIC;
+        WREADY : OUT STD_LOGIC;
+        WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
+        ARVALID : IN STD_LOGIC;
+        ARREADY : OUT STD_LOGIC;
+        ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        RVALID : OUT STD_LOGIC;
+        RREADY : IN STD_LOGIC;
+        RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : OUT STD_LOGIC;
+        BREADY : IN STD_LOGIC;
+        BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        ap_start : OUT STD_LOGIC;
+        interrupt : OUT STD_LOGIC;
+        ap_ready : IN STD_LOGIC;
+        ap_done : IN STD_LOGIC;
+        ap_idle : IN STD_LOGIC;
+        in1 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        in2 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        out_r : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dim : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_in2_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_out_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+
+begin
+    mmult_params_s_axi_U : component mmult_params_s_axi
+    generic map (
+        C_S_AXI_ADDR_WIDTH => C_S_AXI_PARAMS_ADDR_WIDTH,
+        C_S_AXI_DATA_WIDTH => C_S_AXI_PARAMS_DATA_WIDTH)
+    port map (
+        AWVALID => s_axi_params_AWVALID,
+        AWREADY => s_axi_params_AWREADY,
+        AWADDR => s_axi_params_AWADDR,
+        WVALID => s_axi_params_WVALID,
+        WREADY => s_axi_params_WREADY,
+        WDATA => s_axi_params_WDATA,
+        WSTRB => s_axi_params_WSTRB,
+        ARVALID => s_axi_params_ARVALID,
+        ARREADY => s_axi_params_ARREADY,
+        ARADDR => s_axi_params_ARADDR,
+        RVALID => s_axi_params_RVALID,
+        RREADY => s_axi_params_RREADY,
+        RDATA => s_axi_params_RDATA,
+        RRESP => s_axi_params_RRESP,
+        BVALID => s_axi_params_BVALID,
+        BREADY => s_axi_params_BREADY,
+        BRESP => s_axi_params_BRESP,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        ap_start => ap_start,
+        interrupt => interrupt,
+        ap_ready => ap_ready,
+        ap_done => ap_done,
+        ap_idle => ap_idle,
+        in1 => in1,
+        in2 => in2,
+        out_r => out_r,
+        dim => dim);
+
+    mmult_in1_mem_m_axi_U : component mmult_in1_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN1_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN1_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN1_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN1_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN1_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN1_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN1_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN1_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN1_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN1_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN1_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in1_mem_AWVALID,
+        AWREADY => m_axi_in1_mem_AWREADY,
+        AWADDR => m_axi_in1_mem_AWADDR,
+        AWID => m_axi_in1_mem_AWID,
+        AWLEN => m_axi_in1_mem_AWLEN,
+        AWSIZE => m_axi_in1_mem_AWSIZE,
+        AWBURST => m_axi_in1_mem_AWBURST,
+        AWLOCK => m_axi_in1_mem_AWLOCK,
+        AWCACHE => m_axi_in1_mem_AWCACHE,
+        AWPROT => m_axi_in1_mem_AWPROT,
+        AWQOS => m_axi_in1_mem_AWQOS,
+        AWREGION => m_axi_in1_mem_AWREGION,
+        AWUSER => m_axi_in1_mem_AWUSER,
+        WVALID => m_axi_in1_mem_WVALID,
+        WREADY => m_axi_in1_mem_WREADY,
+        WDATA => m_axi_in1_mem_WDATA,
+        WSTRB => m_axi_in1_mem_WSTRB,
+        WLAST => m_axi_in1_mem_WLAST,
+        WID => m_axi_in1_mem_WID,
+        WUSER => m_axi_in1_mem_WUSER,
+        ARVALID => m_axi_in1_mem_ARVALID,
+        ARREADY => m_axi_in1_mem_ARREADY,
+        ARADDR => m_axi_in1_mem_ARADDR,
+        ARID => m_axi_in1_mem_ARID,
+        ARLEN => m_axi_in1_mem_ARLEN,
+        ARSIZE => m_axi_in1_mem_ARSIZE,
+        ARBURST => m_axi_in1_mem_ARBURST,
+        ARLOCK => m_axi_in1_mem_ARLOCK,
+        ARCACHE => m_axi_in1_mem_ARCACHE,
+        ARPROT => m_axi_in1_mem_ARPROT,
+        ARQOS => m_axi_in1_mem_ARQOS,
+        ARREGION => m_axi_in1_mem_ARREGION,
+        ARUSER => m_axi_in1_mem_ARUSER,
+        RVALID => m_axi_in1_mem_RVALID,
+        RREADY => m_axi_in1_mem_RREADY,
+        RDATA => m_axi_in1_mem_RDATA,
+        RLAST => m_axi_in1_mem_RLAST,
+        RID => m_axi_in1_mem_RID,
+        RUSER => m_axi_in1_mem_RUSER,
+        RRESP => m_axi_in1_mem_RRESP,
+        BVALID => m_axi_in1_mem_BVALID,
+        BREADY => m_axi_in1_mem_BREADY,
+        BRESP => m_axi_in1_mem_BRESP,
+        BID => m_axi_in1_mem_BID,
+        BUSER => m_axi_in1_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in1_mem_ARVALID,
+        I_ARREADY => in1_mem_ARREADY,
+        I_ARADDR => in1_mem_ARADDR,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in1_mem_RVALID,
+        I_RREADY => in1_mem_RREADY,
+        I_RDATA => in1_mem_RDATA,
+        I_RID => in1_mem_RID,
+        I_RUSER => in1_mem_RUSER,
+        I_RRESP => in1_mem_RRESP,
+        I_RLAST => in1_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in1_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in1_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in1_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in1_mem_BRESP,
+        I_BID => in1_mem_BID,
+        I_BUSER => in1_mem_BUSER);
+
+    mmult_in2_mem_m_axi_U : component mmult_in2_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN2_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN2_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN2_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN2_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN2_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN2_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN2_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN2_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN2_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN2_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN2_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in2_mem_AWVALID,
+        AWREADY => m_axi_in2_mem_AWREADY,
+        AWADDR => m_axi_in2_mem_AWADDR,
+        AWID => m_axi_in2_mem_AWID,
+        AWLEN => m_axi_in2_mem_AWLEN,
+        AWSIZE => m_axi_in2_mem_AWSIZE,
+        AWBURST => m_axi_in2_mem_AWBURST,
+        AWLOCK => m_axi_in2_mem_AWLOCK,
+        AWCACHE => m_axi_in2_mem_AWCACHE,
+        AWPROT => m_axi_in2_mem_AWPROT,
+        AWQOS => m_axi_in2_mem_AWQOS,
+        AWREGION => m_axi_in2_mem_AWREGION,
+        AWUSER => m_axi_in2_mem_AWUSER,
+        WVALID => m_axi_in2_mem_WVALID,
+        WREADY => m_axi_in2_mem_WREADY,
+        WDATA => m_axi_in2_mem_WDATA,
+        WSTRB => m_axi_in2_mem_WSTRB,
+        WLAST => m_axi_in2_mem_WLAST,
+        WID => m_axi_in2_mem_WID,
+        WUSER => m_axi_in2_mem_WUSER,
+        ARVALID => m_axi_in2_mem_ARVALID,
+        ARREADY => m_axi_in2_mem_ARREADY,
+        ARADDR => m_axi_in2_mem_ARADDR,
+        ARID => m_axi_in2_mem_ARID,
+        ARLEN => m_axi_in2_mem_ARLEN,
+        ARSIZE => m_axi_in2_mem_ARSIZE,
+        ARBURST => m_axi_in2_mem_ARBURST,
+        ARLOCK => m_axi_in2_mem_ARLOCK,
+        ARCACHE => m_axi_in2_mem_ARCACHE,
+        ARPROT => m_axi_in2_mem_ARPROT,
+        ARQOS => m_axi_in2_mem_ARQOS,
+        ARREGION => m_axi_in2_mem_ARREGION,
+        ARUSER => m_axi_in2_mem_ARUSER,
+        RVALID => m_axi_in2_mem_RVALID,
+        RREADY => m_axi_in2_mem_RREADY,
+        RDATA => m_axi_in2_mem_RDATA,
+        RLAST => m_axi_in2_mem_RLAST,
+        RID => m_axi_in2_mem_RID,
+        RUSER => m_axi_in2_mem_RUSER,
+        RRESP => m_axi_in2_mem_RRESP,
+        BVALID => m_axi_in2_mem_BVALID,
+        BREADY => m_axi_in2_mem_BREADY,
+        BRESP => m_axi_in2_mem_BRESP,
+        BID => m_axi_in2_mem_BID,
+        BUSER => m_axi_in2_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in2_mem_ARVALID,
+        I_ARREADY => in2_mem_ARREADY,
+        I_ARADDR => in2_mem_addr_reg_4525,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in2_mem_RVALID,
+        I_RREADY => in2_mem_RREADY,
+        I_RDATA => in2_mem_RDATA,
+        I_RID => in2_mem_RID,
+        I_RUSER => in2_mem_RUSER,
+        I_RRESP => in2_mem_RRESP,
+        I_RLAST => in2_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in2_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in2_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in2_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in2_mem_BRESP,
+        I_BID => in2_mem_BID,
+        I_BUSER => in2_mem_BUSER);
+
+    mmult_out_mem_m_axi_U : component mmult_out_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_OUT_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_OUT_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_OUT_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_OUT_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_OUT_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_OUT_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_OUT_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_OUT_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_OUT_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_OUT_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_OUT_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_out_mem_AWVALID,
+        AWREADY => m_axi_out_mem_AWREADY,
+        AWADDR => m_axi_out_mem_AWADDR,
+        AWID => m_axi_out_mem_AWID,
+        AWLEN => m_axi_out_mem_AWLEN,
+        AWSIZE => m_axi_out_mem_AWSIZE,
+        AWBURST => m_axi_out_mem_AWBURST,
+        AWLOCK => m_axi_out_mem_AWLOCK,
+        AWCACHE => m_axi_out_mem_AWCACHE,
+        AWPROT => m_axi_out_mem_AWPROT,
+        AWQOS => m_axi_out_mem_AWQOS,
+        AWREGION => m_axi_out_mem_AWREGION,
+        AWUSER => m_axi_out_mem_AWUSER,
+        WVALID => m_axi_out_mem_WVALID,
+        WREADY => m_axi_out_mem_WREADY,
+        WDATA => m_axi_out_mem_WDATA,
+        WSTRB => m_axi_out_mem_WSTRB,
+        WLAST => m_axi_out_mem_WLAST,
+        WID => m_axi_out_mem_WID,
+        WUSER => m_axi_out_mem_WUSER,
+        ARVALID => m_axi_out_mem_ARVALID,
+        ARREADY => m_axi_out_mem_ARREADY,
+        ARADDR => m_axi_out_mem_ARADDR,
+        ARID => m_axi_out_mem_ARID,
+        ARLEN => m_axi_out_mem_ARLEN,
+        ARSIZE => m_axi_out_mem_ARSIZE,
+        ARBURST => m_axi_out_mem_ARBURST,
+        ARLOCK => m_axi_out_mem_ARLOCK,
+        ARCACHE => m_axi_out_mem_ARCACHE,
+        ARPROT => m_axi_out_mem_ARPROT,
+        ARQOS => m_axi_out_mem_ARQOS,
+        ARREGION => m_axi_out_mem_ARREGION,
+        ARUSER => m_axi_out_mem_ARUSER,
+        RVALID => m_axi_out_mem_RVALID,
+        RREADY => m_axi_out_mem_RREADY,
+        RDATA => m_axi_out_mem_RDATA,
+        RLAST => m_axi_out_mem_RLAST,
+        RID => m_axi_out_mem_RID,
+        RUSER => m_axi_out_mem_RUSER,
+        RRESP => m_axi_out_mem_RRESP,
+        BVALID => m_axi_out_mem_BVALID,
+        BREADY => m_axi_out_mem_BREADY,
+        BRESP => m_axi_out_mem_BRESP,
+        BID => m_axi_out_mem_BID,
+        BUSER => m_axi_out_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => ap_const_logic_0,
+        I_ARREADY => out_mem_ARREADY,
+        I_ARADDR => ap_const_lv32_0,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_0,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => out_mem_RVALID,
+        I_RREADY => ap_const_logic_0,
+        I_RDATA => out_mem_RDATA,
+        I_RID => out_mem_RID,
+        I_RUSER => out_mem_RUSER,
+        I_RRESP => out_mem_RRESP,
+        I_RLAST => out_mem_RLAST,
+        I_AWVALID => out_mem_AWVALID,
+        I_AWREADY => out_mem_AWREADY,
+        I_AWADDR => out_mem_addr_reg_4519,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_1000,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => out_mem_WVALID,
+        I_WREADY => out_mem_WREADY,
+        I_WDATA => out_loc_load_reg_5764,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_F,
+        I_BVALID => out_mem_BVALID,
+        I_BREADY => out_mem_BREADY,
+        I_BRESP => out_mem_BRESP,
+        I_BID => out_mem_BID,
+        I_BUSER => out_mem_BUSER);
+
+    in1_loc_0_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_0_address0,
+        ce0 => in1_loc_0_ce0,
+        we0 => in1_loc_0_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_0_q0);
+
+    in1_loc_1_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_1_address0,
+        ce0 => in1_loc_1_ce0,
+        we0 => in1_loc_1_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_1_q0);
+
+    in1_loc_2_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_2_address0,
+        ce0 => in1_loc_2_ce0,
+        we0 => in1_loc_2_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_2_q0);
+
+    in1_loc_3_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_3_address0,
+        ce0 => in1_loc_3_ce0,
+        we0 => in1_loc_3_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_3_q0);
+
+    in1_loc_4_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_4_address0,
+        ce0 => in1_loc_4_ce0,
+        we0 => in1_loc_4_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_4_q0);
+
+    in1_loc_5_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_5_address0,
+        ce0 => in1_loc_5_ce0,
+        we0 => in1_loc_5_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_5_q0);
+
+    in1_loc_6_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_6_address0,
+        ce0 => in1_loc_6_ce0,
+        we0 => in1_loc_6_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_6_q0);
+
+    in1_loc_7_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_7_address0,
+        ce0 => in1_loc_7_ce0,
+        we0 => in1_loc_7_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_7_q0);
+
+    in1_loc_8_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_8_address0,
+        ce0 => in1_loc_8_ce0,
+        we0 => in1_loc_8_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_8_q0);
+
+    in1_loc_9_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_9_address0,
+        ce0 => in1_loc_9_ce0,
+        we0 => in1_loc_9_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_9_q0);
+
+    in1_loc_10_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_10_address0,
+        ce0 => in1_loc_10_ce0,
+        we0 => in1_loc_10_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_10_q0);
+
+    in1_loc_11_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_11_address0,
+        ce0 => in1_loc_11_ce0,
+        we0 => in1_loc_11_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_11_q0);
+
+    in1_loc_12_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_12_address0,
+        ce0 => in1_loc_12_ce0,
+        we0 => in1_loc_12_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_12_q0);
+
+    in1_loc_13_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_13_address0,
+        ce0 => in1_loc_13_ce0,
+        we0 => in1_loc_13_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_13_q0);
+
+    in1_loc_14_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_14_address0,
+        ce0 => in1_loc_14_ce0,
+        we0 => in1_loc_14_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_14_q0);
+
+    in1_loc_15_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_15_address0,
+        ce0 => in1_loc_15_ce0,
+        we0 => in1_loc_15_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_15_q0);
+
+    in1_loc_16_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_16_address0,
+        ce0 => in1_loc_16_ce0,
+        we0 => in1_loc_16_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_16_q0);
+
+    in1_loc_17_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_17_address0,
+        ce0 => in1_loc_17_ce0,
+        we0 => in1_loc_17_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_17_q0);
+
+    in1_loc_18_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_18_address0,
+        ce0 => in1_loc_18_ce0,
+        we0 => in1_loc_18_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_18_q0);
+
+    in1_loc_19_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_19_address0,
+        ce0 => in1_loc_19_ce0,
+        we0 => in1_loc_19_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_19_q0);
+
+    in1_loc_20_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_20_address0,
+        ce0 => in1_loc_20_ce0,
+        we0 => in1_loc_20_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_20_q0);
+
+    in1_loc_21_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_21_address0,
+        ce0 => in1_loc_21_ce0,
+        we0 => in1_loc_21_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_21_q0);
+
+    in1_loc_22_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_22_address0,
+        ce0 => in1_loc_22_ce0,
+        we0 => in1_loc_22_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_22_q0);
+
+    in1_loc_23_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_23_address0,
+        ce0 => in1_loc_23_ce0,
+        we0 => in1_loc_23_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_23_q0);
+
+    in1_loc_24_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_24_address0,
+        ce0 => in1_loc_24_ce0,
+        we0 => in1_loc_24_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_24_q0);
+
+    in1_loc_25_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_25_address0,
+        ce0 => in1_loc_25_ce0,
+        we0 => in1_loc_25_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_25_q0);
+
+    in1_loc_26_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_26_address0,
+        ce0 => in1_loc_26_ce0,
+        we0 => in1_loc_26_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_26_q0);
+
+    in1_loc_27_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_27_address0,
+        ce0 => in1_loc_27_ce0,
+        we0 => in1_loc_27_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_27_q0);
+
+    in1_loc_28_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_28_address0,
+        ce0 => in1_loc_28_ce0,
+        we0 => in1_loc_28_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_28_q0);
+
+    in1_loc_29_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_29_address0,
+        ce0 => in1_loc_29_ce0,
+        we0 => in1_loc_29_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_29_q0);
+
+    in1_loc_30_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_30_address0,
+        ce0 => in1_loc_30_ce0,
+        we0 => in1_loc_30_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_30_q0);
+
+    in1_loc_31_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_31_address0,
+        ce0 => in1_loc_31_ce0,
+        we0 => in1_loc_31_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_31_q0);
+
+    in1_loc_32_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_32_address0,
+        ce0 => in1_loc_32_ce0,
+        we0 => in1_loc_32_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_32_q0);
+
+    in1_loc_33_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_33_address0,
+        ce0 => in1_loc_33_ce0,
+        we0 => in1_loc_33_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_33_q0);
+
+    in1_loc_34_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_34_address0,
+        ce0 => in1_loc_34_ce0,
+        we0 => in1_loc_34_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_34_q0);
+
+    in1_loc_35_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_35_address0,
+        ce0 => in1_loc_35_ce0,
+        we0 => in1_loc_35_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_35_q0);
+
+    in1_loc_36_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_36_address0,
+        ce0 => in1_loc_36_ce0,
+        we0 => in1_loc_36_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_36_q0);
+
+    in1_loc_37_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_37_address0,
+        ce0 => in1_loc_37_ce0,
+        we0 => in1_loc_37_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_37_q0);
+
+    in1_loc_38_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_38_address0,
+        ce0 => in1_loc_38_ce0,
+        we0 => in1_loc_38_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_38_q0);
+
+    in1_loc_39_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_39_address0,
+        ce0 => in1_loc_39_ce0,
+        we0 => in1_loc_39_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_39_q0);
+
+    in1_loc_40_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_40_address0,
+        ce0 => in1_loc_40_ce0,
+        we0 => in1_loc_40_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_40_q0);
+
+    in1_loc_41_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_41_address0,
+        ce0 => in1_loc_41_ce0,
+        we0 => in1_loc_41_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_41_q0);
+
+    in1_loc_42_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_42_address0,
+        ce0 => in1_loc_42_ce0,
+        we0 => in1_loc_42_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_42_q0);
+
+    in1_loc_43_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_43_address0,
+        ce0 => in1_loc_43_ce0,
+        we0 => in1_loc_43_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_43_q0);
+
+    in1_loc_44_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_44_address0,
+        ce0 => in1_loc_44_ce0,
+        we0 => in1_loc_44_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_44_q0);
+
+    in1_loc_45_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_45_address0,
+        ce0 => in1_loc_45_ce0,
+        we0 => in1_loc_45_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_45_q0);
+
+    in1_loc_46_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_46_address0,
+        ce0 => in1_loc_46_ce0,
+        we0 => in1_loc_46_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_46_q0);
+
+    in1_loc_47_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_47_address0,
+        ce0 => in1_loc_47_ce0,
+        we0 => in1_loc_47_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_47_q0);
+
+    in1_loc_48_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_48_address0,
+        ce0 => in1_loc_48_ce0,
+        we0 => in1_loc_48_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_48_q0);
+
+    in1_loc_49_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_49_address0,
+        ce0 => in1_loc_49_ce0,
+        we0 => in1_loc_49_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_49_q0);
+
+    in1_loc_50_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_50_address0,
+        ce0 => in1_loc_50_ce0,
+        we0 => in1_loc_50_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_50_q0);
+
+    in1_loc_51_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_51_address0,
+        ce0 => in1_loc_51_ce0,
+        we0 => in1_loc_51_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_51_q0);
+
+    in1_loc_52_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_52_address0,
+        ce0 => in1_loc_52_ce0,
+        we0 => in1_loc_52_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_52_q0);
+
+    in1_loc_53_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_53_address0,
+        ce0 => in1_loc_53_ce0,
+        we0 => in1_loc_53_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_53_q0);
+
+    in1_loc_54_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_54_address0,
+        ce0 => in1_loc_54_ce0,
+        we0 => in1_loc_54_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_54_q0);
+
+    in1_loc_55_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_55_address0,
+        ce0 => in1_loc_55_ce0,
+        we0 => in1_loc_55_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_55_q0);
+
+    in1_loc_56_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_56_address0,
+        ce0 => in1_loc_56_ce0,
+        we0 => in1_loc_56_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_56_q0);
+
+    in1_loc_57_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_57_address0,
+        ce0 => in1_loc_57_ce0,
+        we0 => in1_loc_57_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_57_q0);
+
+    in1_loc_58_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_58_address0,
+        ce0 => in1_loc_58_ce0,
+        we0 => in1_loc_58_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_58_q0);
+
+    in1_loc_59_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_59_address0,
+        ce0 => in1_loc_59_ce0,
+        we0 => in1_loc_59_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_59_q0);
+
+    in1_loc_60_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_60_address0,
+        ce0 => in1_loc_60_ce0,
+        we0 => in1_loc_60_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_60_q0);
+
+    in1_loc_61_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_61_address0,
+        ce0 => in1_loc_61_ce0,
+        we0 => in1_loc_61_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_61_q0);
+
+    in1_loc_62_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_62_address0,
+        ce0 => in1_loc_62_ce0,
+        we0 => in1_loc_62_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_62_q0);
+
+    in1_loc_63_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_63_address0,
+        ce0 => in1_loc_63_ce0,
+        we0 => in1_loc_63_we0,
+        d0 => in1_mem_addr_read_reg_4549,
+        q0 => in1_loc_63_q0);
+
+    in2_loc_0_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_0_address0,
+        ce0 => in2_loc_0_ce0,
+        we0 => in2_loc_0_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_0_q0);
+
+    in2_loc_1_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_1_address0,
+        ce0 => in2_loc_1_ce0,
+        we0 => in2_loc_1_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_1_q0);
+
+    in2_loc_2_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_2_address0,
+        ce0 => in2_loc_2_ce0,
+        we0 => in2_loc_2_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_2_q0);
+
+    in2_loc_3_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_3_address0,
+        ce0 => in2_loc_3_ce0,
+        we0 => in2_loc_3_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_3_q0);
+
+    in2_loc_4_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_4_address0,
+        ce0 => in2_loc_4_ce0,
+        we0 => in2_loc_4_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_4_q0);
+
+    in2_loc_5_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_5_address0,
+        ce0 => in2_loc_5_ce0,
+        we0 => in2_loc_5_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_5_q0);
+
+    in2_loc_6_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_6_address0,
+        ce0 => in2_loc_6_ce0,
+        we0 => in2_loc_6_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_6_q0);
+
+    in2_loc_7_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_7_address0,
+        ce0 => in2_loc_7_ce0,
+        we0 => in2_loc_7_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_7_q0);
+
+    in2_loc_8_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_8_address0,
+        ce0 => in2_loc_8_ce0,
+        we0 => in2_loc_8_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_8_q0);
+
+    in2_loc_9_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_9_address0,
+        ce0 => in2_loc_9_ce0,
+        we0 => in2_loc_9_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_9_q0);
+
+    in2_loc_10_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_10_address0,
+        ce0 => in2_loc_10_ce0,
+        we0 => in2_loc_10_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_10_q0);
+
+    in2_loc_11_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_11_address0,
+        ce0 => in2_loc_11_ce0,
+        we0 => in2_loc_11_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_11_q0);
+
+    in2_loc_12_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_12_address0,
+        ce0 => in2_loc_12_ce0,
+        we0 => in2_loc_12_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_12_q0);
+
+    in2_loc_13_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_13_address0,
+        ce0 => in2_loc_13_ce0,
+        we0 => in2_loc_13_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_13_q0);
+
+    in2_loc_14_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_14_address0,
+        ce0 => in2_loc_14_ce0,
+        we0 => in2_loc_14_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_14_q0);
+
+    in2_loc_15_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_15_address0,
+        ce0 => in2_loc_15_ce0,
+        we0 => in2_loc_15_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_15_q0);
+
+    in2_loc_16_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_16_address0,
+        ce0 => in2_loc_16_ce0,
+        we0 => in2_loc_16_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_16_q0);
+
+    in2_loc_17_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_17_address0,
+        ce0 => in2_loc_17_ce0,
+        we0 => in2_loc_17_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_17_q0);
+
+    in2_loc_18_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_18_address0,
+        ce0 => in2_loc_18_ce0,
+        we0 => in2_loc_18_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_18_q0);
+
+    in2_loc_19_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_19_address0,
+        ce0 => in2_loc_19_ce0,
+        we0 => in2_loc_19_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_19_q0);
+
+    in2_loc_20_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_20_address0,
+        ce0 => in2_loc_20_ce0,
+        we0 => in2_loc_20_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_20_q0);
+
+    in2_loc_21_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_21_address0,
+        ce0 => in2_loc_21_ce0,
+        we0 => in2_loc_21_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_21_q0);
+
+    in2_loc_22_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_22_address0,
+        ce0 => in2_loc_22_ce0,
+        we0 => in2_loc_22_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_22_q0);
+
+    in2_loc_23_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_23_address0,
+        ce0 => in2_loc_23_ce0,
+        we0 => in2_loc_23_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_23_q0);
+
+    in2_loc_24_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_24_address0,
+        ce0 => in2_loc_24_ce0,
+        we0 => in2_loc_24_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_24_q0);
+
+    in2_loc_25_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_25_address0,
+        ce0 => in2_loc_25_ce0,
+        we0 => in2_loc_25_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_25_q0);
+
+    in2_loc_26_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_26_address0,
+        ce0 => in2_loc_26_ce0,
+        we0 => in2_loc_26_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_26_q0);
+
+    in2_loc_27_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_27_address0,
+        ce0 => in2_loc_27_ce0,
+        we0 => in2_loc_27_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_27_q0);
+
+    in2_loc_28_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_28_address0,
+        ce0 => in2_loc_28_ce0,
+        we0 => in2_loc_28_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_28_q0);
+
+    in2_loc_29_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_29_address0,
+        ce0 => in2_loc_29_ce0,
+        we0 => in2_loc_29_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_29_q0);
+
+    in2_loc_30_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_30_address0,
+        ce0 => in2_loc_30_ce0,
+        we0 => in2_loc_30_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_30_q0);
+
+    in2_loc_31_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_31_address0,
+        ce0 => in2_loc_31_ce0,
+        we0 => in2_loc_31_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_31_q0);
+
+    in2_loc_32_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_32_address0,
+        ce0 => in2_loc_32_ce0,
+        we0 => in2_loc_32_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_32_q0);
+
+    in2_loc_33_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_33_address0,
+        ce0 => in2_loc_33_ce0,
+        we0 => in2_loc_33_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_33_q0);
+
+    in2_loc_34_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_34_address0,
+        ce0 => in2_loc_34_ce0,
+        we0 => in2_loc_34_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_34_q0);
+
+    in2_loc_35_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_35_address0,
+        ce0 => in2_loc_35_ce0,
+        we0 => in2_loc_35_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_35_q0);
+
+    in2_loc_36_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_36_address0,
+        ce0 => in2_loc_36_ce0,
+        we0 => in2_loc_36_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_36_q0);
+
+    in2_loc_37_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_37_address0,
+        ce0 => in2_loc_37_ce0,
+        we0 => in2_loc_37_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_37_q0);
+
+    in2_loc_38_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_38_address0,
+        ce0 => in2_loc_38_ce0,
+        we0 => in2_loc_38_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_38_q0);
+
+    in2_loc_39_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_39_address0,
+        ce0 => in2_loc_39_ce0,
+        we0 => in2_loc_39_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_39_q0);
+
+    in2_loc_40_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_40_address0,
+        ce0 => in2_loc_40_ce0,
+        we0 => in2_loc_40_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_40_q0);
+
+    in2_loc_41_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_41_address0,
+        ce0 => in2_loc_41_ce0,
+        we0 => in2_loc_41_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_41_q0);
+
+    in2_loc_42_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_42_address0,
+        ce0 => in2_loc_42_ce0,
+        we0 => in2_loc_42_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_42_q0);
+
+    in2_loc_43_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_43_address0,
+        ce0 => in2_loc_43_ce0,
+        we0 => in2_loc_43_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_43_q0);
+
+    in2_loc_44_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_44_address0,
+        ce0 => in2_loc_44_ce0,
+        we0 => in2_loc_44_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_44_q0);
+
+    in2_loc_45_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_45_address0,
+        ce0 => in2_loc_45_ce0,
+        we0 => in2_loc_45_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_45_q0);
+
+    in2_loc_46_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_46_address0,
+        ce0 => in2_loc_46_ce0,
+        we0 => in2_loc_46_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_46_q0);
+
+    in2_loc_47_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_47_address0,
+        ce0 => in2_loc_47_ce0,
+        we0 => in2_loc_47_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_47_q0);
+
+    in2_loc_48_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_48_address0,
+        ce0 => in2_loc_48_ce0,
+        we0 => in2_loc_48_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_48_q0);
+
+    in2_loc_49_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_49_address0,
+        ce0 => in2_loc_49_ce0,
+        we0 => in2_loc_49_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_49_q0);
+
+    in2_loc_50_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_50_address0,
+        ce0 => in2_loc_50_ce0,
+        we0 => in2_loc_50_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_50_q0);
+
+    in2_loc_51_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_51_address0,
+        ce0 => in2_loc_51_ce0,
+        we0 => in2_loc_51_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_51_q0);
+
+    in2_loc_52_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_52_address0,
+        ce0 => in2_loc_52_ce0,
+        we0 => in2_loc_52_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_52_q0);
+
+    in2_loc_53_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_53_address0,
+        ce0 => in2_loc_53_ce0,
+        we0 => in2_loc_53_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_53_q0);
+
+    in2_loc_54_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_54_address0,
+        ce0 => in2_loc_54_ce0,
+        we0 => in2_loc_54_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_54_q0);
+
+    in2_loc_55_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_55_address0,
+        ce0 => in2_loc_55_ce0,
+        we0 => in2_loc_55_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_55_q0);
+
+    in2_loc_56_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_56_address0,
+        ce0 => in2_loc_56_ce0,
+        we0 => in2_loc_56_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_56_q0);
+
+    in2_loc_57_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_57_address0,
+        ce0 => in2_loc_57_ce0,
+        we0 => in2_loc_57_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_57_q0);
+
+    in2_loc_58_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_58_address0,
+        ce0 => in2_loc_58_ce0,
+        we0 => in2_loc_58_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_58_q0);
+
+    in2_loc_59_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_59_address0,
+        ce0 => in2_loc_59_ce0,
+        we0 => in2_loc_59_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_59_q0);
+
+    in2_loc_60_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_60_address0,
+        ce0 => in2_loc_60_ce0,
+        we0 => in2_loc_60_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_60_q0);
+
+    in2_loc_61_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_61_address0,
+        ce0 => in2_loc_61_ce0,
+        we0 => in2_loc_61_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_61_q0);
+
+    in2_loc_62_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_62_address0,
+        ce0 => in2_loc_62_ce0,
+        we0 => in2_loc_62_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_62_q0);
+
+    in2_loc_63_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_63_address0,
+        ce0 => in2_loc_63_ce0,
+        we0 => in2_loc_63_we0,
+        d0 => in2_mem_addr_read_reg_4635,
+        q0 => in2_loc_63_q0);
+
+    out_loc_U : component mmult_out_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => out_loc_address0,
+        ce0 => out_loc_ce0,
+        we0 => out_loc_we0,
+        d0 => out_loc_d0,
+        q0 => out_loc_q0);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state9);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19)) then 
+                        ap_enable_reg_pp1_iter1 <= (ap_const_logic_1 xor ap_condition_pp1_exit_iter0_state19);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_condition_pp2_exit_iter0_state28) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+                elsif (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_3598_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp2_exit_iter0_state28)) then 
+                        ap_enable_reg_pp2_iter1 <= (ap_const_logic_1 xor ap_condition_pp2_exit_iter0_state28);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+                elsif (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_3598_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+                    ap_enable_reg_pp2_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0_reg_3317_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                i_0_reg_3317 <= ap_const_lv31_0;
+            elsif (((icmp_ln33_fu_3688_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then 
+                i_0_reg_3317 <= i_reg_4707;
+            end if; 
+        end if;
+    end process;
+
+    j_0_reg_3328_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state27)) then 
+                j_0_reg_3328 <= j_reg_5365;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                j_0_reg_3328 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln27_reg_3295_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_fu_3408_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                phi_ln27_reg_3295 <= add_ln27_fu_3414_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                phi_ln27_reg_3295 <= ap_const_lv13_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln28_reg_3306_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                phi_ln28_reg_3306 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_fu_3501_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+                phi_ln28_reg_3306 <= add_ln28_fu_3507_p2;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln42_reg_3339_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_3598_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+                phi_ln42_reg_3339 <= ap_const_lv13_0;
+            elsif (((icmp_ln42_fu_4475_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001))) then 
+                phi_ln42_reg_3339 <= add_ln42_fu_4481_p2;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state26)) then
+                add_ln38_12_reg_5705 <= add_ln38_12_fu_4173_p2;
+                add_ln38_21_reg_5710 <= add_ln38_21_fu_4215_p2;
+                add_ln38_28_reg_5715 <= add_ln38_28_fu_4257_p2;
+                add_ln38_37_reg_5720 <= add_ln38_37_fu_4299_p2;
+                add_ln38_40_reg_5725 <= add_ln38_40_fu_4317_p2;
+                add_ln38_43_reg_5730 <= add_ln38_43_fu_4335_p2;
+                add_ln38_52_reg_5735 <= add_ln38_52_fu_4377_p2;
+                add_ln38_55_reg_5740 <= add_ln38_55_fu_4395_p2;
+                add_ln38_59_reg_5745 <= add_ln38_59_fu_4419_p2;
+                add_ln38_6_reg_5695 <= add_ln38_6_fu_4137_p2;
+                add_ln38_9_reg_5700 <= add_ln38_9_fu_4155_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                dim_read_reg_4492 <= dim;
+                in3_reg_4508 <= in1(31 downto 2);
+                in_reg_4503 <= in2(31 downto 2);
+                out5_reg_4498 <= out_r(31 downto 2);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                i_reg_4707 <= i_fu_3603_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001))) then
+                icmp_ln42_reg_5750 <= icmp_ln42_fu_4475_p2;
+                icmp_ln42_reg_5750_pp2_iter1_reg <= icmp_ln42_reg_5750;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state24)) then
+                in1_loc_0_load_reg_5042 <= in1_loc_0_q0;
+                in1_loc_10_load_reg_5092 <= in1_loc_10_q0;
+                in1_loc_11_load_reg_5097 <= in1_loc_11_q0;
+                in1_loc_12_load_reg_5102 <= in1_loc_12_q0;
+                in1_loc_13_load_reg_5107 <= in1_loc_13_q0;
+                in1_loc_14_load_reg_5112 <= in1_loc_14_q0;
+                in1_loc_15_load_reg_5117 <= in1_loc_15_q0;
+                in1_loc_16_load_reg_5122 <= in1_loc_16_q0;
+                in1_loc_17_load_reg_5127 <= in1_loc_17_q0;
+                in1_loc_18_load_reg_5132 <= in1_loc_18_q0;
+                in1_loc_19_load_reg_5137 <= in1_loc_19_q0;
+                in1_loc_1_load_reg_5047 <= in1_loc_1_q0;
+                in1_loc_20_load_reg_5142 <= in1_loc_20_q0;
+                in1_loc_21_load_reg_5147 <= in1_loc_21_q0;
+                in1_loc_22_load_reg_5152 <= in1_loc_22_q0;
+                in1_loc_23_load_reg_5157 <= in1_loc_23_q0;
+                in1_loc_24_load_reg_5162 <= in1_loc_24_q0;
+                in1_loc_25_load_reg_5167 <= in1_loc_25_q0;
+                in1_loc_26_load_reg_5172 <= in1_loc_26_q0;
+                in1_loc_27_load_reg_5177 <= in1_loc_27_q0;
+                in1_loc_28_load_reg_5182 <= in1_loc_28_q0;
+                in1_loc_29_load_reg_5187 <= in1_loc_29_q0;
+                in1_loc_2_load_reg_5052 <= in1_loc_2_q0;
+                in1_loc_30_load_reg_5192 <= in1_loc_30_q0;
+                in1_loc_31_load_reg_5197 <= in1_loc_31_q0;
+                in1_loc_32_load_reg_5202 <= in1_loc_32_q0;
+                in1_loc_33_load_reg_5207 <= in1_loc_33_q0;
+                in1_loc_34_load_reg_5212 <= in1_loc_34_q0;
+                in1_loc_35_load_reg_5217 <= in1_loc_35_q0;
+                in1_loc_36_load_reg_5222 <= in1_loc_36_q0;
+                in1_loc_37_load_reg_5227 <= in1_loc_37_q0;
+                in1_loc_38_load_reg_5232 <= in1_loc_38_q0;
+                in1_loc_39_load_reg_5237 <= in1_loc_39_q0;
+                in1_loc_3_load_reg_5057 <= in1_loc_3_q0;
+                in1_loc_40_load_reg_5242 <= in1_loc_40_q0;
+                in1_loc_41_load_reg_5247 <= in1_loc_41_q0;
+                in1_loc_42_load_reg_5252 <= in1_loc_42_q0;
+                in1_loc_43_load_reg_5257 <= in1_loc_43_q0;
+                in1_loc_44_load_reg_5262 <= in1_loc_44_q0;
+                in1_loc_45_load_reg_5267 <= in1_loc_45_q0;
+                in1_loc_46_load_reg_5272 <= in1_loc_46_q0;
+                in1_loc_47_load_reg_5277 <= in1_loc_47_q0;
+                in1_loc_48_load_reg_5282 <= in1_loc_48_q0;
+                in1_loc_49_load_reg_5287 <= in1_loc_49_q0;
+                in1_loc_4_load_reg_5062 <= in1_loc_4_q0;
+                in1_loc_50_load_reg_5292 <= in1_loc_50_q0;
+                in1_loc_51_load_reg_5297 <= in1_loc_51_q0;
+                in1_loc_52_load_reg_5302 <= in1_loc_52_q0;
+                in1_loc_53_load_reg_5307 <= in1_loc_53_q0;
+                in1_loc_54_load_reg_5312 <= in1_loc_54_q0;
+                in1_loc_55_load_reg_5317 <= in1_loc_55_q0;
+                in1_loc_56_load_reg_5322 <= in1_loc_56_q0;
+                in1_loc_57_load_reg_5327 <= in1_loc_57_q0;
+                in1_loc_58_load_reg_5332 <= in1_loc_58_q0;
+                in1_loc_59_load_reg_5337 <= in1_loc_59_q0;
+                in1_loc_5_load_reg_5067 <= in1_loc_5_q0;
+                in1_loc_60_load_reg_5342 <= in1_loc_60_q0;
+                in1_loc_61_load_reg_5347 <= in1_loc_61_q0;
+                in1_loc_62_load_reg_5352 <= in1_loc_62_q0;
+                in1_loc_63_load_reg_5357 <= in1_loc_63_q0;
+                in1_loc_6_load_reg_5072 <= in1_loc_6_q0;
+                in1_loc_7_load_reg_5077 <= in1_loc_7_q0;
+                in1_loc_8_load_reg_5082 <= in1_loc_8_q0;
+                in1_loc_9_load_reg_5087 <= in1_loc_9_q0;
+                    zext_ln38_1_cast_reg_5037(13 downto 6) <= zext_ln38_1_cast_fu_3681_p3(13 downto 6);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                in1_mem_addr_read_reg_4549 <= in1_mem_RDATA;
+                lshr_ln_reg_4540_pp0_iter1_reg <= lshr_ln_reg_4540;
+                trunc_ln27_reg_4545_pp0_iter1_reg <= trunc_ln27_reg_4545;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                in2_mem_addr_read_reg_4635 <= in2_mem_RDATA;
+                trunc_ln1_reg_4631_pp1_iter1_reg <= trunc_ln1_reg_4631;
+                trunc_ln28_reg_4626_pp1_iter1_reg <= trunc_ln28_reg_4626;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
+                    in2_mem_addr_reg_4525(29 downto 0) <= empty_7_fu_3399_p1(32 - 1 downto 0)(29 downto 0);
+                    out_mem_addr_reg_4519(29 downto 0) <= empty_fu_3390_p1(32 - 1 downto 0)(29 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state25)) then
+                j_reg_5365 <= j_fu_3693_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_fu_3408_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                lshr_ln_reg_4540 <= phi_ln27_reg_3295(12 downto 6);
+                trunc_ln27_reg_4545 <= trunc_ln27_fu_3430_p1;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln33_fu_3688_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state25))) then
+                out_loc_addr_reg_5370 <= sext_ln38_1_fu_3776_p1(12 - 1 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln42_reg_5750 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001))) then
+                out_loc_load_reg_5764 <= out_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_fu_3501_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                trunc_ln1_reg_4631 <= phi_ln28_reg_3306(11 downto 6);
+                trunc_ln28_reg_4626 <= trunc_ln28_fu_3513_p1;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_3598_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                trunc_ln38_reg_4712 <= trunc_ln38_fu_3677_p1;
+            end if;
+        end if;
+    end process;
+    out_mem_addr_reg_4519(31 downto 30) <= "00";
+    in2_mem_addr_reg_4525(31 downto 30) <= "00";
+    zext_ln38_1_cast_reg_5037(5 downto 0) <= "000000";
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_enable_reg_pp0_iter1, ap_CS_fsm_state12, ap_enable_reg_pp1_iter1, ap_CS_fsm_state23, icmp_ln31_fu_3598_p2, ap_enable_reg_pp2_iter2, ap_CS_fsm_state35, in1_mem_ARREADY, in2_mem_ARREADY, out_mem_BVALID, icmp_ln27_fu_3408_p2, ap_enable_reg_pp0_iter0, icmp_ln28_fu_3501_p2, ap_enable_reg_pp1_iter0, ap_block_state23_io, ap_CS_fsm_state25, icmp_ln33_fu_3688_p2, icmp_ln42_fu_4475_p2, ap_enable_reg_pp2_iter0, ap_enable_reg_pp2_iter1, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter2, ap_block_pp1_stage0_subdone, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0_subdone)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when ap_ST_fsm_state3 => 
+                ap_NS_fsm <= ap_ST_fsm_state4;
+            when ap_ST_fsm_state4 => 
+                ap_NS_fsm <= ap_ST_fsm_state5;
+            when ap_ST_fsm_state5 => 
+                ap_NS_fsm <= ap_ST_fsm_state6;
+            when ap_ST_fsm_state6 => 
+                ap_NS_fsm <= ap_ST_fsm_state7;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state8;
+            when ap_ST_fsm_state8 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((icmp_ln27_fu_3408_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) and not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((icmp_ln27_fu_3408_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state12 => 
+                if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then
+                    ap_NS_fsm <= ap_ST_fsm_state13;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                end if;
+            when ap_ST_fsm_state13 => 
+                ap_NS_fsm <= ap_ST_fsm_state14;
+            when ap_ST_fsm_state14 => 
+                ap_NS_fsm <= ap_ST_fsm_state15;
+            when ap_ST_fsm_state15 => 
+                ap_NS_fsm <= ap_ST_fsm_state16;
+            when ap_ST_fsm_state16 => 
+                ap_NS_fsm <= ap_ST_fsm_state17;
+            when ap_ST_fsm_state17 => 
+                ap_NS_fsm <= ap_ST_fsm_state18;
+            when ap_ST_fsm_state18 => 
+                ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+            when ap_ST_fsm_pp1_stage0 => 
+                if ((not(((icmp_ln28_fu_3501_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) and not(((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                elsif ((((icmp_ln28_fu_3501_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) or ((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state22;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                end if;
+            when ap_ST_fsm_state22 => 
+                ap_NS_fsm <= ap_ST_fsm_state23;
+            when ap_ST_fsm_state23 => 
+                if (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_3598_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                elsif (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_3598_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state23))) then
+                    ap_NS_fsm <= ap_ST_fsm_state24;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state23;
+                end if;
+            when ap_ST_fsm_state24 => 
+                ap_NS_fsm <= ap_ST_fsm_state25;
+            when ap_ST_fsm_state25 => 
+                if (((icmp_ln33_fu_3688_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state25))) then
+                    ap_NS_fsm <= ap_ST_fsm_state23;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state26;
+                end if;
+            when ap_ST_fsm_state26 => 
+                ap_NS_fsm <= ap_ST_fsm_state27;
+            when ap_ST_fsm_state27 => 
+                ap_NS_fsm <= ap_ST_fsm_state25;
+            when ap_ST_fsm_pp2_stage0 => 
+                if ((not(((icmp_ln42_fu_4475_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))) and not(((ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                elsif ((((ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0)) or ((icmp_ln42_fu_4475_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state31;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                end if;
+            when ap_ST_fsm_state31 => 
+                ap_NS_fsm <= ap_ST_fsm_state32;
+            when ap_ST_fsm_state32 => 
+                ap_NS_fsm <= ap_ST_fsm_state33;
+            when ap_ST_fsm_state33 => 
+                ap_NS_fsm <= ap_ST_fsm_state34;
+            when ap_ST_fsm_state34 => 
+                ap_NS_fsm <= ap_ST_fsm_state35;
+            when ap_ST_fsm_state35 => 
+                if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state35))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state35;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+        end case;
+    end process;
+    add_ln27_fu_3414_p2 <= std_logic_vector(unsigned(phi_ln27_reg_3295) + unsigned(ap_const_lv13_1));
+    add_ln28_fu_3507_p2 <= std_logic_vector(unsigned(phi_ln28_reg_3306) + unsigned(ap_const_lv13_1));
+    add_ln38_10_fu_4161_p2 <= std_logic_vector(unsigned(mul_ln38_12_fu_3841_p2) + unsigned(mul_ln38_11_fu_3836_p2));
+    add_ln38_11_fu_4167_p2 <= std_logic_vector(unsigned(mul_ln38_14_fu_3851_p2) + unsigned(mul_ln38_13_fu_3846_p2));
+    add_ln38_12_fu_4173_p2 <= std_logic_vector(unsigned(add_ln38_10_fu_4161_p2) + unsigned(add_ln38_11_fu_4167_p2));
+    add_ln38_13_fu_4425_p2 <= std_logic_vector(unsigned(add_ln38_9_reg_5700) + unsigned(add_ln38_12_reg_5705));
+    add_ln38_14_fu_4429_p2 <= std_logic_vector(unsigned(add_ln38_6_reg_5695) + unsigned(add_ln38_13_fu_4425_p2));
+    add_ln38_15_fu_4179_p2 <= std_logic_vector(unsigned(mul_ln38_16_fu_3861_p2) + unsigned(mul_ln38_15_fu_3856_p2));
+    add_ln38_16_fu_4185_p2 <= std_logic_vector(unsigned(mul_ln38_18_fu_3871_p2) + unsigned(mul_ln38_17_fu_3866_p2));
+    add_ln38_17_fu_4191_p2 <= std_logic_vector(unsigned(add_ln38_15_fu_4179_p2) + unsigned(add_ln38_16_fu_4185_p2));
+    add_ln38_18_fu_4197_p2 <= std_logic_vector(unsigned(mul_ln38_20_fu_3881_p2) + unsigned(mul_ln38_19_fu_3876_p2));
+    add_ln38_19_fu_4203_p2 <= std_logic_vector(unsigned(mul_ln38_22_fu_3891_p2) + unsigned(mul_ln38_21_fu_3886_p2));
+    add_ln38_1_fu_4107_p2 <= std_logic_vector(unsigned(mul_ln38_2_fu_3791_p2) + unsigned(mul_ln38_1_fu_3786_p2));
+    add_ln38_20_fu_4209_p2 <= std_logic_vector(unsigned(add_ln38_18_fu_4197_p2) + unsigned(add_ln38_19_fu_4203_p2));
+    add_ln38_21_fu_4215_p2 <= std_logic_vector(unsigned(add_ln38_17_fu_4191_p2) + unsigned(add_ln38_20_fu_4209_p2));
+    add_ln38_22_fu_4221_p2 <= std_logic_vector(unsigned(mul_ln38_24_fu_3901_p2) + unsigned(mul_ln38_23_fu_3896_p2));
+    add_ln38_23_fu_4227_p2 <= std_logic_vector(unsigned(mul_ln38_26_fu_3911_p2) + unsigned(mul_ln38_25_fu_3906_p2));
+    add_ln38_24_fu_4233_p2 <= std_logic_vector(unsigned(add_ln38_22_fu_4221_p2) + unsigned(add_ln38_23_fu_4227_p2));
+    add_ln38_25_fu_4239_p2 <= std_logic_vector(unsigned(mul_ln38_28_fu_3921_p2) + unsigned(mul_ln38_27_fu_3916_p2));
+    add_ln38_26_fu_4245_p2 <= std_logic_vector(unsigned(mul_ln38_30_fu_3931_p2) + unsigned(mul_ln38_29_fu_3926_p2));
+    add_ln38_27_fu_4251_p2 <= std_logic_vector(unsigned(add_ln38_25_fu_4239_p2) + unsigned(add_ln38_26_fu_4245_p2));
+    add_ln38_28_fu_4257_p2 <= std_logic_vector(unsigned(add_ln38_24_fu_4233_p2) + unsigned(add_ln38_27_fu_4251_p2));
+    add_ln38_29_fu_4434_p2 <= std_logic_vector(unsigned(add_ln38_21_reg_5710) + unsigned(add_ln38_28_reg_5715));
+    add_ln38_2_fu_4113_p2 <= std_logic_vector(unsigned(add_ln38_fu_4101_p2) + unsigned(add_ln38_1_fu_4107_p2));
+    add_ln38_30_fu_4438_p2 <= std_logic_vector(unsigned(add_ln38_14_fu_4429_p2) + unsigned(add_ln38_29_fu_4434_p2));
+    add_ln38_31_fu_4263_p2 <= std_logic_vector(unsigned(mul_ln38_32_fu_3941_p2) + unsigned(mul_ln38_31_fu_3936_p2));
+    add_ln38_32_fu_4269_p2 <= std_logic_vector(unsigned(mul_ln38_34_fu_3951_p2) + unsigned(mul_ln38_33_fu_3946_p2));
+    add_ln38_33_fu_4275_p2 <= std_logic_vector(unsigned(add_ln38_31_fu_4263_p2) + unsigned(add_ln38_32_fu_4269_p2));
+    add_ln38_34_fu_4281_p2 <= std_logic_vector(unsigned(mul_ln38_36_fu_3961_p2) + unsigned(mul_ln38_35_fu_3956_p2));
+    add_ln38_35_fu_4287_p2 <= std_logic_vector(unsigned(mul_ln38_38_fu_3971_p2) + unsigned(mul_ln38_37_fu_3966_p2));
+    add_ln38_36_fu_4293_p2 <= std_logic_vector(unsigned(add_ln38_34_fu_4281_p2) + unsigned(add_ln38_35_fu_4287_p2));
+    add_ln38_37_fu_4299_p2 <= std_logic_vector(unsigned(add_ln38_33_fu_4275_p2) + unsigned(add_ln38_36_fu_4293_p2));
+    add_ln38_38_fu_4305_p2 <= std_logic_vector(unsigned(mul_ln38_40_fu_3981_p2) + unsigned(mul_ln38_39_fu_3976_p2));
+    add_ln38_39_fu_4311_p2 <= std_logic_vector(unsigned(mul_ln38_42_fu_3991_p2) + unsigned(mul_ln38_41_fu_3986_p2));
+    add_ln38_3_fu_4119_p2 <= std_logic_vector(unsigned(mul_ln38_4_fu_3801_p2) + unsigned(mul_ln38_3_fu_3796_p2));
+    add_ln38_40_fu_4317_p2 <= std_logic_vector(unsigned(add_ln38_38_fu_4305_p2) + unsigned(add_ln38_39_fu_4311_p2));
+    add_ln38_41_fu_4323_p2 <= std_logic_vector(unsigned(mul_ln38_44_fu_4001_p2) + unsigned(mul_ln38_43_fu_3996_p2));
+    add_ln38_42_fu_4329_p2 <= std_logic_vector(unsigned(mul_ln38_46_fu_4011_p2) + unsigned(mul_ln38_45_fu_4006_p2));
+    add_ln38_43_fu_4335_p2 <= std_logic_vector(unsigned(add_ln38_41_fu_4323_p2) + unsigned(add_ln38_42_fu_4329_p2));
+    add_ln38_44_fu_4444_p2 <= std_logic_vector(unsigned(add_ln38_40_reg_5725) + unsigned(add_ln38_43_reg_5730));
+    add_ln38_45_fu_4448_p2 <= std_logic_vector(unsigned(add_ln38_37_reg_5720) + unsigned(add_ln38_44_fu_4444_p2));
+    add_ln38_46_fu_4341_p2 <= std_logic_vector(unsigned(mul_ln38_48_fu_4021_p2) + unsigned(mul_ln38_47_fu_4016_p2));
+    add_ln38_47_fu_4347_p2 <= std_logic_vector(unsigned(mul_ln38_50_fu_4031_p2) + unsigned(mul_ln38_49_fu_4026_p2));
+    add_ln38_48_fu_4353_p2 <= std_logic_vector(unsigned(add_ln38_46_fu_4341_p2) + unsigned(add_ln38_47_fu_4347_p2));
+    add_ln38_49_fu_4359_p2 <= std_logic_vector(unsigned(mul_ln38_52_fu_4041_p2) + unsigned(mul_ln38_51_fu_4036_p2));
+    add_ln38_4_fu_4125_p2 <= std_logic_vector(unsigned(mul_ln38_6_fu_3811_p2) + unsigned(mul_ln38_5_fu_3806_p2));
+    add_ln38_50_fu_4365_p2 <= std_logic_vector(unsigned(mul_ln38_54_fu_4051_p2) + unsigned(mul_ln38_53_fu_4046_p2));
+    add_ln38_51_fu_4371_p2 <= std_logic_vector(unsigned(add_ln38_49_fu_4359_p2) + unsigned(add_ln38_50_fu_4365_p2));
+    add_ln38_52_fu_4377_p2 <= std_logic_vector(unsigned(add_ln38_48_fu_4353_p2) + unsigned(add_ln38_51_fu_4371_p2));
+    add_ln38_53_fu_4383_p2 <= std_logic_vector(unsigned(mul_ln38_56_fu_4061_p2) + unsigned(mul_ln38_55_fu_4056_p2));
+    add_ln38_54_fu_4389_p2 <= std_logic_vector(unsigned(mul_ln38_58_fu_4071_p2) + unsigned(mul_ln38_57_fu_4066_p2));
+    add_ln38_55_fu_4395_p2 <= std_logic_vector(unsigned(add_ln38_53_fu_4383_p2) + unsigned(add_ln38_54_fu_4389_p2));
+    add_ln38_56_fu_4401_p2 <= std_logic_vector(unsigned(mul_ln38_60_fu_4081_p2) + unsigned(mul_ln38_59_fu_4076_p2));
+    add_ln38_57_fu_4407_p2 <= std_logic_vector(unsigned(mul_ln38_63_fu_4096_p2) + unsigned(mul_ln38_62_fu_4091_p2));
+    add_ln38_58_fu_4413_p2 <= std_logic_vector(unsigned(mul_ln38_61_fu_4086_p2) + unsigned(add_ln38_57_fu_4407_p2));
+    add_ln38_59_fu_4419_p2 <= std_logic_vector(unsigned(add_ln38_56_fu_4401_p2) + unsigned(add_ln38_58_fu_4413_p2));
+    add_ln38_5_fu_4131_p2 <= std_logic_vector(unsigned(add_ln38_3_fu_4119_p2) + unsigned(add_ln38_4_fu_4125_p2));
+    add_ln38_60_fu_4453_p2 <= std_logic_vector(unsigned(add_ln38_55_reg_5740) + unsigned(add_ln38_59_reg_5745));
+    add_ln38_61_fu_4457_p2 <= std_logic_vector(unsigned(add_ln38_52_reg_5735) + unsigned(add_ln38_60_fu_4453_p2));
+    add_ln38_62_fu_4462_p2 <= std_logic_vector(unsigned(add_ln38_45_fu_4448_p2) + unsigned(add_ln38_61_fu_4457_p2));
+    add_ln38_64_fu_3771_p2 <= std_logic_vector(unsigned(zext_ln38_1_cast_reg_5037) + unsigned(trunc_ln38_1_fu_3767_p1));
+    add_ln38_6_fu_4137_p2 <= std_logic_vector(unsigned(add_ln38_2_fu_4113_p2) + unsigned(add_ln38_5_fu_4131_p2));
+    add_ln38_7_fu_4143_p2 <= std_logic_vector(unsigned(mul_ln38_8_fu_3821_p2) + unsigned(mul_ln38_7_fu_3816_p2));
+    add_ln38_8_fu_4149_p2 <= std_logic_vector(unsigned(mul_ln38_10_fu_3831_p2) + unsigned(mul_ln38_9_fu_3826_p2));
+    add_ln38_9_fu_4155_p2 <= std_logic_vector(unsigned(add_ln38_7_fu_4143_p2) + unsigned(add_ln38_8_fu_4149_p2));
+    add_ln38_fu_4101_p2 <= std_logic_vector(unsigned(mul_ln38_fu_3781_p2) + unsigned(out_loc_q0));
+    add_ln42_fu_4481_p2 <= std_logic_vector(unsigned(phi_ln42_reg_3339) + unsigned(ap_const_lv13_1));
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(8);
+    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(16);
+    ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(23);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state12 <= ap_CS_fsm(9);
+    ap_CS_fsm_state18 <= ap_CS_fsm(15);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state22 <= ap_CS_fsm(17);
+    ap_CS_fsm_state23 <= ap_CS_fsm(18);
+    ap_CS_fsm_state24 <= ap_CS_fsm(19);
+    ap_CS_fsm_state25 <= ap_CS_fsm(20);
+    ap_CS_fsm_state26 <= ap_CS_fsm(21);
+    ap_CS_fsm_state27 <= ap_CS_fsm(22);
+    ap_CS_fsm_state35 <= ap_CS_fsm(28);
+    ap_CS_fsm_state8 <= ap_CS_fsm(7);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_11001_assign_proc : process(ap_enable_reg_pp0_iter1, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_11001 <= ((in1_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(ap_enable_reg_pp0_iter1, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_subdone <= ((in1_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp1_stage0_11001_assign_proc : process(ap_enable_reg_pp1_iter1, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_11001 <= ((in2_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp1_stage0_subdone_assign_proc : process(ap_enable_reg_pp1_iter1, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_subdone <= ((in2_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp2_stage0_01001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp2_stage0_11001_assign_proc : process(ap_enable_reg_pp2_iter2, ap_block_state30_io)
+    begin
+                ap_block_pp2_stage0_11001 <= ((ap_const_boolean_1 = ap_block_state30_io) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp2_stage0_subdone_assign_proc : process(ap_enable_reg_pp2_iter2, ap_block_state30_io)
+    begin
+                ap_block_pp2_stage0_subdone <= ((ap_const_boolean_1 = ap_block_state30_io) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state10_pp0_stage0_iter1_assign_proc : process(in1_mem_RVALID)
+    begin
+                ap_block_state10_pp0_stage0_iter1 <= (in1_mem_RVALID = ap_const_logic_0);
+    end process;
+
+        ap_block_state11_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state19_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state20_pp1_stage0_iter1_assign_proc : process(in2_mem_RVALID)
+    begin
+                ap_block_state20_pp1_stage0_iter1 <= (in2_mem_RVALID = ap_const_logic_0);
+    end process;
+
+        ap_block_state21_pp1_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state23_io_assign_proc : process(icmp_ln31_fu_3598_p2, out_mem_AWREADY)
+    begin
+                ap_block_state23_io <= ((out_mem_AWREADY = ap_const_logic_0) and (icmp_ln31_fu_3598_p2 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state28_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state29_pp2_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state30_io_assign_proc : process(icmp_ln42_reg_5750_pp2_iter1_reg, out_mem_WREADY)
+    begin
+                ap_block_state30_io <= ((out_mem_WREADY = ap_const_logic_0) and (icmp_ln42_reg_5750_pp2_iter1_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state30_pp2_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state9_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state9_assign_proc : process(icmp_ln27_fu_3408_p2)
+    begin
+        if ((icmp_ln27_fu_3408_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp1_exit_iter0_state19_assign_proc : process(icmp_ln28_fu_3501_p2)
+    begin
+        if ((icmp_ln28_fu_3501_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_1;
+        else 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp2_exit_iter0_state28_assign_proc : process(icmp_ln42_fu_4475_p2)
+    begin
+        if ((icmp_ln42_fu_4475_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp2_exit_iter0_state28 <= ap_const_logic_1;
+        else 
+            ap_condition_pp2_exit_iter0_state28 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_CS_fsm_state35, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state35))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
+    ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp1 <= ap_const_logic_1;
+        else 
+            ap_idle_pp1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter2, ap_enable_reg_pp2_iter0, ap_enable_reg_pp2_iter1)
+    begin
+        if (((ap_enable_reg_pp2_iter2 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0))) then 
+            ap_idle_pp2 <= ap_const_logic_1;
+        else 
+            ap_idle_pp2 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state35, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state35))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    empty_7_fu_3399_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in_reg_4503),64));
+    empty_8_fu_3380_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in3_reg_4508),64));
+    empty_fu_3390_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(out5_reg_4498),64));
+    i_fu_3603_p2 <= std_logic_vector(unsigned(i_0_reg_3317) + unsigned(ap_const_lv31_1));
+    icmp_ln27_fu_3408_p2 <= "1" when (phi_ln27_reg_3295 = ap_const_lv13_1000) else "0";
+    icmp_ln28_fu_3501_p2 <= "1" when (phi_ln28_reg_3306 = ap_const_lv13_1000) else "0";
+    icmp_ln31_fu_3598_p2 <= "1" when (signed(zext_ln31_fu_3594_p1) < signed(dim_read_reg_4492)) else "0";
+    icmp_ln33_fu_3688_p2 <= "1" when (j_0_reg_3328 = dim_read_reg_4492) else "0";
+    icmp_ln42_fu_4475_p2 <= "1" when (phi_ln42_reg_3339 = ap_const_lv13_1000) else "0";
+
+    in1_loc_0_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_0_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_0_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_0_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_0_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_0_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_0_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_0_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_0_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_10_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_10_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_10_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_10_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_10_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_10_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_10_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_10_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_11_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_11_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_11_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_11_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_11_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_11_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_11_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_11_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_11_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_11_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_12_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_12_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_12_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_12_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_12_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_12_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_12_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_12_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_12_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_12_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_13_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_13_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_13_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_13_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_13_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_13_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_13_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_13_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_14_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_14_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_14_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_14_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_14_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_14_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_14_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_14_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_15_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_15_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_15_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_15_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_15_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_15_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_15_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_15_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_15_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_15_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_16_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_16_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_16_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_16_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_16_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_16_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_16_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_16_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_10) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_16_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_16_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_17_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_17_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_17_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_17_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_17_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_17_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_17_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_11) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_17_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_18_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_18_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_18_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_18_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_18_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_18_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_18_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_12) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_18_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_19_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_19_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_19_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_19_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_19_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_19_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_19_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_19_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_13) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_19_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_19_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_1_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_1_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_1_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_1_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_1_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_1_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_1_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_1_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_1_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_20_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_20_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_20_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_20_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_20_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_20_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_20_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_20_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_14) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_20_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_20_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_21_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_21_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_21_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_21_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_21_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_21_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_21_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_21_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_15) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_21_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_21_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_22_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_22_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_22_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_22_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_22_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_22_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_22_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_22_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_16) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_22_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_22_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_23_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_23_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_23_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_23_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_23_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_23_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_23_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_23_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_17) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_23_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_23_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_24_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_24_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_24_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_24_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_24_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_24_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_24_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_24_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_18) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_24_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_24_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_25_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_25_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_25_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_25_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_25_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_25_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_25_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_19) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_25_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_26_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_26_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_26_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_26_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_26_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_26_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_26_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_1A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_26_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_27_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_27_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_27_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_27_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_27_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_27_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_27_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_27_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_1B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_27_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_27_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_28_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_28_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_28_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_28_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_28_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_28_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_28_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_28_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_1C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_28_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_28_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_29_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_29_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_29_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_29_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_29_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_29_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_29_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_29_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_1D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_29_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_29_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_2_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_2_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_2_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_2_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_2_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_2_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_2_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_2) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_2_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_2_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_30_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_30_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_30_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_30_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_30_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_30_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_30_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_30_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_1E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_30_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_30_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_31_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_31_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_31_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_31_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_31_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_31_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_31_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_31_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_1F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_31_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_31_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_32_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_32_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_32_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_32_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_32_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_32_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_32_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_32_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_20) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_32_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_32_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_33_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_33_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_33_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_33_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_33_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_33_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_33_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_21) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_33_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_34_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_34_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_34_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_34_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_34_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_34_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_34_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_22) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_34_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_35_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_35_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_35_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_35_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_35_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_35_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_35_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_35_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_23) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_35_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_35_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_36_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_36_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_36_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_36_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_36_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_36_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_36_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_36_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_24) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_36_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_36_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_37_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_37_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_37_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_37_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_37_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_37_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_37_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_37_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_25) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_37_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_37_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_38_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_38_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_38_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_38_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_38_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_38_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_38_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_38_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_26) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_38_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_38_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_39_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_39_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_39_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_39_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_39_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_39_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_39_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_39_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_27) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_39_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_39_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_3_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_3_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_3_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_3_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_3_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_3_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_3_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_3) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_3_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_3_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_40_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_40_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_40_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_40_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_40_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_40_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_40_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_40_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_28) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_40_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_40_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_41_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_41_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_41_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_41_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_41_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_41_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_41_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_29) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_41_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_42_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_42_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_42_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_42_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_42_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_42_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_42_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_2A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_42_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_43_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_43_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_43_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_43_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_43_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_43_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_43_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_43_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_2B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_43_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_43_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_44_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_44_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_44_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_44_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_44_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_44_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_44_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_44_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_2C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_44_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_44_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_45_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_45_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_45_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_45_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_45_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_45_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_45_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_2D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_45_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_46_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_46_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_46_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_46_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_46_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_46_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_46_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_2E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_46_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_47_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_47_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_47_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_47_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_47_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_47_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_47_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_47_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_2F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_47_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_47_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_48_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_48_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_48_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_48_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_48_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_48_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_48_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_48_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_30) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_48_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_48_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_49_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_49_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_49_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_49_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_49_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_49_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_49_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_31) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_49_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_4_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_4_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_4_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_4_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_4_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_4_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_4_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_4) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_4_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_4_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_50_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_50_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_50_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_50_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_50_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_50_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_50_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_32) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_50_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_51_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_51_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_51_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_51_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_51_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_51_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_51_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_51_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_33) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_51_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_51_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_52_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_52_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_52_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_52_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_52_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_52_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_52_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_52_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_34) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_52_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_52_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_53_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_53_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_53_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_53_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_53_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_53_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_53_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_53_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_35) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_53_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_53_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_54_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_54_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_54_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_54_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_54_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_54_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_54_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_54_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_36) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_54_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_54_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_55_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_55_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_55_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_55_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_55_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_55_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_55_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_55_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_37) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_55_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_55_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_56_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_56_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_56_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_56_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_56_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_56_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_56_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_56_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_38) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_56_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_56_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_57_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_57_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_57_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_57_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_57_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_57_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_57_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_39) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_57_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_58_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_58_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_58_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_58_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_58_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_58_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_58_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_3A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_58_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_59_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_59_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_59_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_59_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_59_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_59_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_59_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_59_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_3B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_59_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_59_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_5_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_5_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_5_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_5_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_5_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_5_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_5_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_5) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_5_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_5_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_60_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_60_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_60_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_60_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_60_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_60_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_60_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_60_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_3C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_60_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_60_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_61_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_61_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_61_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_61_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_61_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_61_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_61_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_3D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_61_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_62_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_62_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_62_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_62_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_62_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_62_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_62_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_62_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_3E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_62_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_62_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_63_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_63_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_63_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_63_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_63_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_63_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_63_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_63_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_3F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_63_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_63_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_6_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_6_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_6_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_6_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_6_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_6_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_6_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_6) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_6_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_6_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_7_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_7_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_7_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_7_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_7_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_7_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_7_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_7) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_7_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_7_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_8_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_8_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_8_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_8_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_8_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_8_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_8_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_8) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_8_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_8_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_9_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_state23, ap_enable_reg_pp0_iter2, zext_ln27_fu_3434_p1, zext_ln38_fu_3609_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state23)) then 
+            in1_loc_9_address0 <= zext_ln38_fu_3609_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_address0 <= zext_ln27_fu_3434_p1(6 - 1 downto 0);
+        else 
+            in1_loc_9_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_9_ce0_assign_proc : process(ap_CS_fsm_state23, ap_block_pp0_stage0_11001, ap_block_state23_io, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_state23_io) and (ap_const_logic_1 = ap_CS_fsm_state23)))) then 
+            in1_loc_9_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_9_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4545_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4545_pp0_iter1_reg = ap_const_lv6_9) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_9_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    in1_mem_ARADDR <= empty_8_fu_3380_p1(32 - 1 downto 0);
+
+    in1_mem_ARVALID_assign_proc : process(ap_CS_fsm_state2, in1_mem_ARREADY)
+    begin
+        if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            in1_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in1_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_RREADY <= ap_const_logic_1;
+        else 
+            in1_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_AR_assign_proc : process(m_axi_in1_mem_ARREADY, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            in1_mem_blk_n_AR <= m_axi_in1_mem_ARREADY;
+        else 
+            in1_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_R_assign_proc : process(m_axi_in1_mem_RVALID, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_blk_n_R <= m_axi_in1_mem_RVALID;
+        else 
+            in1_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_loc_0_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_0_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_0_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_0_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_0_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_0_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_0_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_0_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_0_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_10_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_10_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_10_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_10_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_10_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_10_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_10_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_10_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_11_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_11_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_11_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_11_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_11_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_11_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_11_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_11_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_11_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_11_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_12_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_12_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_12_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_12_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_12_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_12_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_12_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_12_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_12_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_12_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_13_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_13_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_13_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_13_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_13_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_13_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_13_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_13_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_14_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_14_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_14_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_14_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_14_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_14_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_14_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_14_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_15_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_15_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_15_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_15_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_15_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_15_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_15_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_15_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_15_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_15_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_16_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_16_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_16_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_16_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_16_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_16_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_16_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_16_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_10) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_16_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_16_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_17_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_17_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_17_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_17_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_17_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_17_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_17_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_11) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_17_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_18_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_18_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_18_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_18_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_18_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_18_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_18_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_12) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_18_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_19_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_19_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_19_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_19_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_19_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_19_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_19_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_19_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_13) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_19_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_19_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_1_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_1_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_1_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_1_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_1_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_1_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_1_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_1_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_1_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_20_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_20_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_20_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_20_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_20_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_20_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_20_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_20_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_14) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_20_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_20_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_21_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_21_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_21_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_21_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_21_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_21_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_21_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_21_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_15) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_21_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_21_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_22_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_22_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_22_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_22_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_22_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_22_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_22_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_22_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_16) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_22_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_22_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_23_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_23_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_23_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_23_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_23_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_23_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_23_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_23_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_17) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_23_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_23_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_24_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_24_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_24_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_24_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_24_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_24_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_24_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_24_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_18) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_24_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_24_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_25_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_25_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_25_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_25_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_25_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_25_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_25_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_19) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_25_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_26_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_26_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_26_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_26_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_26_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_26_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_26_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_1A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_26_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_27_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_27_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_27_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_27_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_27_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_27_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_27_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_27_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_1B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_27_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_27_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_28_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_28_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_28_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_28_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_28_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_28_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_28_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_28_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_1C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_28_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_28_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_29_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_29_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_29_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_29_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_29_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_29_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_29_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_29_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_1D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_29_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_29_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_2_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_2_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_2_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_2_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_2_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_2_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_2_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_2) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_2_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_2_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_30_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_30_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_30_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_30_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_30_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_30_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_30_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_30_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_1E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_30_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_30_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_31_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_31_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_31_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_31_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_31_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_31_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_31_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_31_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_1F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_31_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_31_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_32_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_32_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_32_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_32_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_32_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_32_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_32_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_32_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_20) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_32_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_32_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_33_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_33_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_33_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_33_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_33_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_33_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_33_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_21) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_33_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_34_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_34_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_34_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_34_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_34_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_34_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_34_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_22) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_34_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_35_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_35_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_35_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_35_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_35_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_35_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_35_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_35_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_23) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_35_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_35_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_36_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_36_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_36_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_36_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_36_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_36_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_36_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_36_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_24) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_36_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_36_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_37_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_37_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_37_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_37_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_37_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_37_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_37_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_37_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_25) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_37_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_37_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_38_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_38_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_38_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_38_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_38_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_38_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_38_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_38_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_26) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_38_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_38_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_39_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_39_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_39_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_39_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_39_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_39_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_39_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_39_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_27) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_39_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_39_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_3_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_3_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_3_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_3_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_3_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_3_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_3_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_3) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_3_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_3_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_40_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_40_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_40_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_40_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_40_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_40_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_40_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_40_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_28) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_40_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_40_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_41_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_41_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_41_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_41_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_41_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_41_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_41_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_29) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_41_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_42_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_42_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_42_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_42_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_42_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_42_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_42_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_2A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_42_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_43_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_43_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_43_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_43_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_43_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_43_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_43_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_43_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_2B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_43_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_43_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_44_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_44_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_44_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_44_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_44_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_44_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_44_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_44_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_2C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_44_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_44_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_45_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_45_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_45_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_45_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_45_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_45_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_45_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_2D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_45_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_46_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_46_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_46_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_46_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_46_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_46_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_46_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_2E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_46_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_47_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_47_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_47_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_47_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_47_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_47_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_47_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_47_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_2F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_47_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_47_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_48_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_48_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_48_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_48_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_48_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_48_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_48_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_48_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_30) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_48_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_48_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_49_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_49_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_49_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_49_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_49_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_49_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_49_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_31) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_49_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_4_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_4_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_4_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_4_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_4_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_4_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_4_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_4) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_4_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_4_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_50_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_50_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_50_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_50_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_50_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_50_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_50_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_32) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_50_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_51_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_51_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_51_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_51_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_51_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_51_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_51_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_51_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_33) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_51_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_51_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_52_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_52_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_52_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_52_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_52_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_52_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_52_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_52_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_34) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_52_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_52_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_53_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_53_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_53_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_53_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_53_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_53_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_53_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_53_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_35) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_53_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_53_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_54_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_54_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_54_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_54_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_54_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_54_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_54_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_54_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_36) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_54_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_54_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_55_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_55_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_55_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_55_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_55_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_55_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_55_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_55_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_37) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_55_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_55_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_56_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_56_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_56_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_56_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_56_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_56_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_56_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_56_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_38) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_56_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_56_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_57_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_57_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_57_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_57_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_57_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_57_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_57_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_39) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_57_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_58_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_58_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_58_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_58_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_58_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_58_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_58_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_3A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_58_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_59_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_59_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_59_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_59_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_59_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_59_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_59_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_59_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_3B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_59_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_59_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_5_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_5_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_5_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_5_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_5_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_5_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_5_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_5) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_5_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_5_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_60_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_60_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_60_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_60_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_60_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_60_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_60_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_60_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_3C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_60_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_60_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_61_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_61_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_61_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_61_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_61_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_61_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_61_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_3D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_61_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_62_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_62_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_62_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_62_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_62_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_62_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_62_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_62_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_3E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_62_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_62_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_63_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_63_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_63_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_63_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_63_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_63_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_63_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_63_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_3F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_63_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_63_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_6_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_6_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_6_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_6_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_6_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_6_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_6_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_6) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_6_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_6_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_7_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_7_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_7_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_7_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_7_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_7_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_7_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_7) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_7_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_7_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_8_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_8_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_8_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_8_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_8_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_8_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_8_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_8) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_8_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_8_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_9_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2, zext_ln28_fu_3527_p1, sext_ln38_fu_3699_p1)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            in2_loc_9_address0 <= sext_ln38_fu_3699_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_address0 <= zext_ln28_fu_3527_p1(6 - 1 downto 0);
+        else 
+            in2_loc_9_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_9_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_state25, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_9_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_9_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4631_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4631_pp1_iter1_reg = ap_const_lv6_9) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_9_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_ARVALID_assign_proc : process(ap_CS_fsm_state12, in2_mem_ARREADY)
+    begin
+        if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then 
+            in2_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in2_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_RREADY_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_RREADY <= ap_const_logic_1;
+        else 
+            in2_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_AR_assign_proc : process(m_axi_in2_mem_ARREADY, ap_CS_fsm_state12)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state12)) then 
+            in2_mem_blk_n_AR <= m_axi_in2_mem_ARREADY;
+        else 
+            in2_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_R_assign_proc : process(m_axi_in2_mem_RVALID, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_blk_n_R <= m_axi_in2_mem_RVALID;
+        else 
+            in2_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    j_fu_3693_p2 <= std_logic_vector(signed(j_0_reg_3328) + signed(ap_const_lv32_1));
+    mul_ln38_10_fu_3831_p0 <= in2_loc_10_q0;
+    mul_ln38_10_fu_3831_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_10_fu_3831_p0) * signed(in1_loc_10_load_reg_5092))), 32));
+    mul_ln38_11_fu_3836_p0 <= in2_loc_11_q0;
+    mul_ln38_11_fu_3836_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_11_fu_3836_p0) * signed(in1_loc_11_load_reg_5097))), 32));
+    mul_ln38_12_fu_3841_p0 <= in2_loc_12_q0;
+    mul_ln38_12_fu_3841_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_12_fu_3841_p0) * signed(in1_loc_12_load_reg_5102))), 32));
+    mul_ln38_13_fu_3846_p0 <= in2_loc_13_q0;
+    mul_ln38_13_fu_3846_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_13_fu_3846_p0) * signed(in1_loc_13_load_reg_5107))), 32));
+    mul_ln38_14_fu_3851_p0 <= in2_loc_14_q0;
+    mul_ln38_14_fu_3851_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_14_fu_3851_p0) * signed(in1_loc_14_load_reg_5112))), 32));
+    mul_ln38_15_fu_3856_p0 <= in2_loc_15_q0;
+    mul_ln38_15_fu_3856_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_15_fu_3856_p0) * signed(in1_loc_15_load_reg_5117))), 32));
+    mul_ln38_16_fu_3861_p0 <= in2_loc_16_q0;
+    mul_ln38_16_fu_3861_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_16_fu_3861_p0) * signed(in1_loc_16_load_reg_5122))), 32));
+    mul_ln38_17_fu_3866_p0 <= in2_loc_17_q0;
+    mul_ln38_17_fu_3866_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_17_fu_3866_p0) * signed(in1_loc_17_load_reg_5127))), 32));
+    mul_ln38_18_fu_3871_p0 <= in2_loc_18_q0;
+    mul_ln38_18_fu_3871_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_18_fu_3871_p0) * signed(in1_loc_18_load_reg_5132))), 32));
+    mul_ln38_19_fu_3876_p0 <= in2_loc_19_q0;
+    mul_ln38_19_fu_3876_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_19_fu_3876_p0) * signed(in1_loc_19_load_reg_5137))), 32));
+    mul_ln38_1_fu_3786_p0 <= in2_loc_1_q0;
+    mul_ln38_1_fu_3786_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_1_fu_3786_p0) * signed(in1_loc_1_load_reg_5047))), 32));
+    mul_ln38_20_fu_3881_p0 <= in2_loc_20_q0;
+    mul_ln38_20_fu_3881_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_20_fu_3881_p0) * signed(in1_loc_20_load_reg_5142))), 32));
+    mul_ln38_21_fu_3886_p0 <= in2_loc_21_q0;
+    mul_ln38_21_fu_3886_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_21_fu_3886_p0) * signed(in1_loc_21_load_reg_5147))), 32));
+    mul_ln38_22_fu_3891_p0 <= in2_loc_22_q0;
+    mul_ln38_22_fu_3891_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_22_fu_3891_p0) * signed(in1_loc_22_load_reg_5152))), 32));
+    mul_ln38_23_fu_3896_p0 <= in2_loc_23_q0;
+    mul_ln38_23_fu_3896_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_23_fu_3896_p0) * signed(in1_loc_23_load_reg_5157))), 32));
+    mul_ln38_24_fu_3901_p0 <= in2_loc_24_q0;
+    mul_ln38_24_fu_3901_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_24_fu_3901_p0) * signed(in1_loc_24_load_reg_5162))), 32));
+    mul_ln38_25_fu_3906_p0 <= in2_loc_25_q0;
+    mul_ln38_25_fu_3906_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_25_fu_3906_p0) * signed(in1_loc_25_load_reg_5167))), 32));
+    mul_ln38_26_fu_3911_p0 <= in2_loc_26_q0;
+    mul_ln38_26_fu_3911_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_26_fu_3911_p0) * signed(in1_loc_26_load_reg_5172))), 32));
+    mul_ln38_27_fu_3916_p0 <= in2_loc_27_q0;
+    mul_ln38_27_fu_3916_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_27_fu_3916_p0) * signed(in1_loc_27_load_reg_5177))), 32));
+    mul_ln38_28_fu_3921_p0 <= in2_loc_28_q0;
+    mul_ln38_28_fu_3921_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_28_fu_3921_p0) * signed(in1_loc_28_load_reg_5182))), 32));
+    mul_ln38_29_fu_3926_p0 <= in2_loc_29_q0;
+    mul_ln38_29_fu_3926_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_29_fu_3926_p0) * signed(in1_loc_29_load_reg_5187))), 32));
+    mul_ln38_2_fu_3791_p0 <= in2_loc_2_q0;
+    mul_ln38_2_fu_3791_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_2_fu_3791_p0) * signed(in1_loc_2_load_reg_5052))), 32));
+    mul_ln38_30_fu_3931_p0 <= in2_loc_30_q0;
+    mul_ln38_30_fu_3931_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_30_fu_3931_p0) * signed(in1_loc_30_load_reg_5192))), 32));
+    mul_ln38_31_fu_3936_p0 <= in2_loc_31_q0;
+    mul_ln38_31_fu_3936_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_31_fu_3936_p0) * signed(in1_loc_31_load_reg_5197))), 32));
+    mul_ln38_32_fu_3941_p0 <= in2_loc_32_q0;
+    mul_ln38_32_fu_3941_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_32_fu_3941_p0) * signed(in1_loc_32_load_reg_5202))), 32));
+    mul_ln38_33_fu_3946_p0 <= in2_loc_33_q0;
+    mul_ln38_33_fu_3946_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_33_fu_3946_p0) * signed(in1_loc_33_load_reg_5207))), 32));
+    mul_ln38_34_fu_3951_p0 <= in2_loc_34_q0;
+    mul_ln38_34_fu_3951_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_34_fu_3951_p0) * signed(in1_loc_34_load_reg_5212))), 32));
+    mul_ln38_35_fu_3956_p0 <= in2_loc_35_q0;
+    mul_ln38_35_fu_3956_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_35_fu_3956_p0) * signed(in1_loc_35_load_reg_5217))), 32));
+    mul_ln38_36_fu_3961_p0 <= in2_loc_36_q0;
+    mul_ln38_36_fu_3961_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_36_fu_3961_p0) * signed(in1_loc_36_load_reg_5222))), 32));
+    mul_ln38_37_fu_3966_p0 <= in2_loc_37_q0;
+    mul_ln38_37_fu_3966_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_37_fu_3966_p0) * signed(in1_loc_37_load_reg_5227))), 32));
+    mul_ln38_38_fu_3971_p0 <= in2_loc_38_q0;
+    mul_ln38_38_fu_3971_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_38_fu_3971_p0) * signed(in1_loc_38_load_reg_5232))), 32));
+    mul_ln38_39_fu_3976_p0 <= in2_loc_39_q0;
+    mul_ln38_39_fu_3976_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_39_fu_3976_p0) * signed(in1_loc_39_load_reg_5237))), 32));
+    mul_ln38_3_fu_3796_p0 <= in2_loc_3_q0;
+    mul_ln38_3_fu_3796_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_3_fu_3796_p0) * signed(in1_loc_3_load_reg_5057))), 32));
+    mul_ln38_40_fu_3981_p0 <= in2_loc_40_q0;
+    mul_ln38_40_fu_3981_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_40_fu_3981_p0) * signed(in1_loc_40_load_reg_5242))), 32));
+    mul_ln38_41_fu_3986_p0 <= in2_loc_41_q0;
+    mul_ln38_41_fu_3986_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_41_fu_3986_p0) * signed(in1_loc_41_load_reg_5247))), 32));
+    mul_ln38_42_fu_3991_p0 <= in2_loc_42_q0;
+    mul_ln38_42_fu_3991_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_42_fu_3991_p0) * signed(in1_loc_42_load_reg_5252))), 32));
+    mul_ln38_43_fu_3996_p0 <= in2_loc_43_q0;
+    mul_ln38_43_fu_3996_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_43_fu_3996_p0) * signed(in1_loc_43_load_reg_5257))), 32));
+    mul_ln38_44_fu_4001_p0 <= in2_loc_44_q0;
+    mul_ln38_44_fu_4001_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_44_fu_4001_p0) * signed(in1_loc_44_load_reg_5262))), 32));
+    mul_ln38_45_fu_4006_p0 <= in2_loc_45_q0;
+    mul_ln38_45_fu_4006_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_45_fu_4006_p0) * signed(in1_loc_45_load_reg_5267))), 32));
+    mul_ln38_46_fu_4011_p0 <= in2_loc_46_q0;
+    mul_ln38_46_fu_4011_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_46_fu_4011_p0) * signed(in1_loc_46_load_reg_5272))), 32));
+    mul_ln38_47_fu_4016_p0 <= in2_loc_47_q0;
+    mul_ln38_47_fu_4016_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_47_fu_4016_p0) * signed(in1_loc_47_load_reg_5277))), 32));
+    mul_ln38_48_fu_4021_p0 <= in2_loc_48_q0;
+    mul_ln38_48_fu_4021_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_48_fu_4021_p0) * signed(in1_loc_48_load_reg_5282))), 32));
+    mul_ln38_49_fu_4026_p0 <= in2_loc_49_q0;
+    mul_ln38_49_fu_4026_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_49_fu_4026_p0) * signed(in1_loc_49_load_reg_5287))), 32));
+    mul_ln38_4_fu_3801_p0 <= in2_loc_4_q0;
+    mul_ln38_4_fu_3801_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_4_fu_3801_p0) * signed(in1_loc_4_load_reg_5062))), 32));
+    mul_ln38_50_fu_4031_p0 <= in2_loc_50_q0;
+    mul_ln38_50_fu_4031_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_50_fu_4031_p0) * signed(in1_loc_50_load_reg_5292))), 32));
+    mul_ln38_51_fu_4036_p0 <= in2_loc_51_q0;
+    mul_ln38_51_fu_4036_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_51_fu_4036_p0) * signed(in1_loc_51_load_reg_5297))), 32));
+    mul_ln38_52_fu_4041_p0 <= in2_loc_52_q0;
+    mul_ln38_52_fu_4041_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_52_fu_4041_p0) * signed(in1_loc_52_load_reg_5302))), 32));
+    mul_ln38_53_fu_4046_p0 <= in2_loc_53_q0;
+    mul_ln38_53_fu_4046_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_53_fu_4046_p0) * signed(in1_loc_53_load_reg_5307))), 32));
+    mul_ln38_54_fu_4051_p0 <= in2_loc_54_q0;
+    mul_ln38_54_fu_4051_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_54_fu_4051_p0) * signed(in1_loc_54_load_reg_5312))), 32));
+    mul_ln38_55_fu_4056_p0 <= in2_loc_55_q0;
+    mul_ln38_55_fu_4056_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_55_fu_4056_p0) * signed(in1_loc_55_load_reg_5317))), 32));
+    mul_ln38_56_fu_4061_p0 <= in2_loc_56_q0;
+    mul_ln38_56_fu_4061_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_56_fu_4061_p0) * signed(in1_loc_56_load_reg_5322))), 32));
+    mul_ln38_57_fu_4066_p0 <= in2_loc_57_q0;
+    mul_ln38_57_fu_4066_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_57_fu_4066_p0) * signed(in1_loc_57_load_reg_5327))), 32));
+    mul_ln38_58_fu_4071_p0 <= in2_loc_58_q0;
+    mul_ln38_58_fu_4071_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_58_fu_4071_p0) * signed(in1_loc_58_load_reg_5332))), 32));
+    mul_ln38_59_fu_4076_p0 <= in2_loc_59_q0;
+    mul_ln38_59_fu_4076_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_59_fu_4076_p0) * signed(in1_loc_59_load_reg_5337))), 32));
+    mul_ln38_5_fu_3806_p0 <= in2_loc_5_q0;
+    mul_ln38_5_fu_3806_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_5_fu_3806_p0) * signed(in1_loc_5_load_reg_5067))), 32));
+    mul_ln38_60_fu_4081_p0 <= in2_loc_60_q0;
+    mul_ln38_60_fu_4081_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_60_fu_4081_p0) * signed(in1_loc_60_load_reg_5342))), 32));
+    mul_ln38_61_fu_4086_p0 <= in2_loc_61_q0;
+    mul_ln38_61_fu_4086_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_61_fu_4086_p0) * signed(in1_loc_61_load_reg_5347))), 32));
+    mul_ln38_62_fu_4091_p0 <= in2_loc_62_q0;
+    mul_ln38_62_fu_4091_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_62_fu_4091_p0) * signed(in1_loc_62_load_reg_5352))), 32));
+    mul_ln38_63_fu_4096_p0 <= in2_loc_63_q0;
+    mul_ln38_63_fu_4096_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_63_fu_4096_p0) * signed(in1_loc_63_load_reg_5357))), 32));
+    mul_ln38_6_fu_3811_p0 <= in2_loc_6_q0;
+    mul_ln38_6_fu_3811_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_6_fu_3811_p0) * signed(in1_loc_6_load_reg_5072))), 32));
+    mul_ln38_7_fu_3816_p0 <= in2_loc_7_q0;
+    mul_ln38_7_fu_3816_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_7_fu_3816_p0) * signed(in1_loc_7_load_reg_5077))), 32));
+    mul_ln38_8_fu_3821_p0 <= in2_loc_8_q0;
+    mul_ln38_8_fu_3821_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_8_fu_3821_p0) * signed(in1_loc_8_load_reg_5082))), 32));
+    mul_ln38_9_fu_3826_p0 <= in2_loc_9_q0;
+    mul_ln38_9_fu_3826_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_9_fu_3826_p0) * signed(in1_loc_9_load_reg_5087))), 32));
+    mul_ln38_fu_3781_p0 <= in2_loc_0_q0;
+    mul_ln38_fu_3781_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_fu_3781_p0) * signed(in1_loc_0_load_reg_5042))), 32));
+
+    out_loc_address0_assign_proc : process(ap_block_pp2_stage0, ap_CS_fsm_state25, out_loc_addr_reg_5370, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_CS_fsm_state27, sext_ln38_1_fu_3776_p1, zext_ln42_fu_4487_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            out_loc_address0 <= zext_ln42_fu_4487_p1(12 - 1 downto 0);
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state27)) then 
+            out_loc_address0 <= out_loc_addr_reg_5370;
+        elsif ((ap_const_logic_1 = ap_CS_fsm_state25)) then 
+            out_loc_address0 <= sext_ln38_1_fu_3776_p1(12 - 1 downto 0);
+        else 
+            out_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    out_loc_ce0_assign_proc : process(ap_CS_fsm_state25, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_CS_fsm_state27)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state25) or (ap_const_logic_1 = ap_CS_fsm_state27) or ((ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001)))) then 
+            out_loc_ce0 <= ap_const_logic_1;
+        else 
+            out_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    out_loc_d0 <= std_logic_vector(unsigned(add_ln38_30_fu_4438_p2) + unsigned(add_ln38_62_fu_4462_p2));
+
+    out_loc_we0_assign_proc : process(ap_CS_fsm_state27)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state27)) then 
+            out_loc_we0 <= ap_const_logic_1;
+        else 
+            out_loc_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_AWVALID_assign_proc : process(ap_CS_fsm_state23, icmp_ln31_fu_3598_p2, ap_block_state23_io)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state23_io) and (icmp_ln31_fu_3598_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+            out_mem_AWVALID <= ap_const_logic_1;
+        else 
+            out_mem_AWVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_BREADY_assign_proc : process(ap_CS_fsm_state35, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state35))) then 
+            out_mem_BREADY <= ap_const_logic_1;
+        else 
+            out_mem_BREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_WVALID_assign_proc : process(ap_enable_reg_pp2_iter2, icmp_ln42_reg_5750_pp2_iter1_reg, ap_block_pp2_stage0_11001)
+    begin
+        if (((icmp_ln42_reg_5750_pp2_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001))) then 
+            out_mem_WVALID <= ap_const_logic_1;
+        else 
+            out_mem_WVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AW_assign_proc : process(m_axi_out_mem_AWREADY, ap_CS_fsm_state23, icmp_ln31_fu_3598_p2)
+    begin
+        if (((icmp_ln31_fu_3598_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state23))) then 
+            out_mem_blk_n_AW <= m_axi_out_mem_AWREADY;
+        else 
+            out_mem_blk_n_AW <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_B_assign_proc : process(m_axi_out_mem_BVALID, ap_CS_fsm_state35)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state35)) then 
+            out_mem_blk_n_B <= m_axi_out_mem_BVALID;
+        else 
+            out_mem_blk_n_B <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_W_assign_proc : process(m_axi_out_mem_WREADY, ap_enable_reg_pp2_iter2, ap_block_pp2_stage0, icmp_ln42_reg_5750_pp2_iter1_reg)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (icmp_ln42_reg_5750_pp2_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            out_mem_blk_n_W <= m_axi_out_mem_WREADY;
+        else 
+            out_mem_blk_n_W <= ap_const_logic_1;
+        end if; 
+    end process;
+
+        sext_ln38_1_fu_3776_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(add_ln38_64_fu_3771_p2),64));
+
+        sext_ln38_fu_3699_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(j_0_reg_3328),64));
+
+    trunc_ln27_fu_3430_p1 <= phi_ln27_reg_3295(6 - 1 downto 0);
+    trunc_ln28_fu_3513_p1 <= phi_ln28_reg_3306(6 - 1 downto 0);
+    trunc_ln38_1_fu_3767_p1 <= j_0_reg_3328(14 - 1 downto 0);
+    trunc_ln38_fu_3677_p1 <= i_0_reg_3317(8 - 1 downto 0);
+    zext_ln27_fu_3434_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(lshr_ln_reg_4540_pp0_iter1_reg),64));
+    zext_ln28_fu_3527_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(trunc_ln28_reg_4626_pp1_iter1_reg),64));
+    zext_ln31_fu_3594_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_0_reg_3317),32));
+    zext_ln38_1_cast_fu_3681_p3 <= (trunc_ln38_reg_4712 & ap_const_lv6_0);
+    zext_ln38_fu_3609_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_0_reg_3317),64));
+    zext_ln42_fu_4487_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln42_reg_3339),64));
+end behav;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in1_loc_0.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in1_loc_0.vhd
new file mode 100755
index 0000000..609e4b6
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in1_loc_0.vhd
@@ -0,0 +1,112 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_in1_loc_0_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 6; 
+            MEM_SIZE    : integer := 64
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_in1_loc_0_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_in1_loc_0 is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 64;
+        AddressWidth : INTEGER := 6);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_in1_loc_0 is
+    component mmult_in1_loc_0_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_in1_loc_0_ram_U :  component mmult_in1_loc_0_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in1_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in1_mem_m_axi.vhd
new file mode 100755
index 0000000..5d4f5b4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in1_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi;
+
+architecture behave of mmult_in1_mem_m_axi is
+    component mmult_in1_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_write;
+
+    component mmult_in1_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_read;
+
+    component mmult_in1_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in1_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in1_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in1_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in1_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in1_mem_m_axi_fifo;
+
+architecture behave of mmult_in1_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in1_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in1_mem_m_axi_decoder;
+
+architecture behav of mmult_in1_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in1_mem_m_axi_throttl;
+
+architecture behav of mmult_in1_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in1_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in1_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_read;
+
+architecture behave of mmult_in1_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_write;
+
+architecture behave of mmult_in1_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in1_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in1_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in2_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in2_mem_m_axi.vhd
new file mode 100755
index 0000000..84687e2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_in2_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi;
+
+architecture behave of mmult_in2_mem_m_axi is
+    component mmult_in2_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_write;
+
+    component mmult_in2_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_read;
+
+    component mmult_in2_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in2_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in2_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in2_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in2_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in2_mem_m_axi_fifo;
+
+architecture behave of mmult_in2_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in2_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in2_mem_m_axi_decoder;
+
+architecture behav of mmult_in2_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in2_mem_m_axi_throttl;
+
+architecture behav of mmult_in2_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in2_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in2_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_read;
+
+architecture behave of mmult_in2_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_write;
+
+architecture behave of mmult_in2_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in2_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in2_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_out_loc.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_out_loc.vhd
new file mode 100755
index 0000000..ec49d88
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_out_loc.vhd
@@ -0,0 +1,112 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_out_loc_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 12; 
+            MEM_SIZE    : integer := 4096
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_out_loc_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_out_loc is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 4096;
+        AddressWidth : INTEGER := 12);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_out_loc is
+    component mmult_out_loc_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_out_loc_ram_U :  component mmult_out_loc_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_out_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_out_mem_m_axi.vhd
new file mode 100755
index 0000000..f2bd717
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_out_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi;
+
+architecture behave of mmult_out_mem_m_axi is
+    component mmult_out_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_write;
+
+    component mmult_out_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_read;
+
+    component mmult_out_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_out_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_out_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_out_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi_reg_slice;
+
+architecture behave of mmult_out_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_out_mem_m_axi_fifo;
+
+architecture behave of mmult_out_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_out_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_out_mem_m_axi_decoder;
+
+architecture behav of mmult_out_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_out_mem_m_axi_throttl;
+
+architecture behav of mmult_out_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_out_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_out_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_read;
+
+architecture behave of mmult_out_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_write;
+
+architecture behave of mmult_out_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_out_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_out_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_params_s_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_params_s_axi.vhd
new file mode 100755
index 0000000..1f9adde
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/hdl/vhdl/mmult_params_s_axi.vhd
@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/misc/logo.png b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/misc/logo.png
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HcmV?d00001

diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/xgui/mmult_v6_0.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/xgui/mmult_v6_0.tcl
new file mode 100755
index 0000000..0276fbf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_6/xgui/mmult_v6_0.tcl
@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/component.xml b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/component.xml
new file mode 100755
index 0000000..6f89397
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/component.xml
@@ -0,0 +1,5578 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>hls</spirit:library>
+  <spirit:name>mmult</spirit:name>
+  <spirit:version>7.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_params"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.ADDR_WIDTH">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi_params:m_axi_in1_mem:m_axi_in2_mem:m_axi_out_mem</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interrupt</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in1_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in1_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in2_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in2_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_out_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_out_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in1_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in2_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_out_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_BASE_PARAM">C_S_AXI_PARAMS_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_HIGH_PARAM">C_S_AXI_PARAMS_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>CTRL</spirit:name>
+          <spirit:displayName>CTRL</spirit:displayName>
+          <spirit:description>Control signals</spirit:description>
+          <spirit:addressOffset>0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>AP_START</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_start&apos;.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_DONE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_done&apos;.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_IDLE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_idle&apos;.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_READY</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_ready&apos;.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_1</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">3</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AUTO_RESTART</spirit:name>
+            <spirit:description>Control signal Register for &apos;auto_restart&apos;.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_2</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">24</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GIER</spirit:name>
+          <spirit:displayName>GIER</spirit:displayName>
+          <spirit:description>Global Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>4</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Enable</spirit:name>
+            <spirit:description>Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">31</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_IER</spirit:name>
+          <spirit:displayName>IP_IER</spirit:displayName>
+          <spirit:description>IP Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>8</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
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+      <spirit:displayName>Enable USER ports</spirit:displayName>
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+      <spirit:name>C_M_AXI_IN2_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
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+      <spirit:displayName>ARUSER width</spirit:displayName>
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+      <spirit:name>C_M_AXI_IN2_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
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+      <spirit:name>C_M_AXI_IN2_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
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+      <spirit:name>C_M_AXI_IN2_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE" spirit:order="24" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE" spirit:order="25" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" spirit:order="26" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH" spirit:order="27" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="28" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" spirit:order="29" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH" spirit:order="30" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH" spirit:order="31" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH" spirit:order="32" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH" spirit:order="33" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH" spirit:order="34" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE" spirit:order="35" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE" spirit:order="36" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE" spirit:order="37" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mmult_v7_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>clk_period</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.clk_period" spirit:order="38">10</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>machine</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.machine" spirit:order="39">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>combinational</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.combinational" spirit:order="40">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>latency</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.latency" spirit:order="41">16413</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>II</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.II" spirit:order="42">x</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/VIVADO_HLS_IP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>Mmult</xilinx:displayName>
+      <xilinx:definitionSource>HLS</xilinx:definitionSource>
+      <xilinx:coreRevision>2105141712</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2021-05-14T15:12:46Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b5dd57e8"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="c6fd4807"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5ce530f0"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="647ff66b"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="7681d788"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c9a673dd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="98401738"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/constraints/mmult_ooc.xdc b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/constraints/mmult_ooc.xdc
new file mode 100755
index 0000000..2ed5eee
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/constraints/mmult_ooc.xdc
@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/doc/ReleaseNotes.txt b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/doc/ReleaseNotes.txt
new file mode 100755
index 0000000..48cc01b
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/doc/ReleaseNotes.txt
@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/data/mmult.mdd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/data/mmult.mdd
new file mode 100755
index 0000000..09ec73b
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/data/mmult.mdd
@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v7_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 7.0;
+
+END driver
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/data/mmult.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/data/mmult.tcl
new file mode 100755
index 0000000..0de7a9c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/data/mmult.tcl
@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/Makefile b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/Makefile
new file mode 100755
index 0000000..7f76086
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/Makefile
@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult.c
new file mode 100755
index 0000000..fb9a1fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult.c
@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult.h
new file mode 100755
index 0000000..4983669
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult.h
@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_hw.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_hw.h
new file mode 100755
index 0000000..3a0a2a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_hw.h
@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_linux.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_linux.c
new file mode 100755
index 0000000..c8dbb33
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_linux.c
@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_sinit.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_sinit.c
new file mode 100755
index 0000000..f099590
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/drivers/mmult_v7_0/src/xmmult_sinit.c
@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult.v
new file mode 100755
index 0000000..9583927
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult.v
@@ -0,0 +1,8287 @@
+// ==============================================================
+// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+// Version: 2020.1
+// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+// 
+// ===========================================================
+
+`timescale 1 ns / 1 ps 
+
+(* CORE_GENERATION_INFO="mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=16413,HLS_SYN_TPT=none,HLS_SYN_MEM=142,HLS_SYN_DSP=260,HLS_SYN_FF=2859,HLS_SYN_LUT=8200,HLS_VERSION=2020_1}" *)
+
+module mmult (
+        ap_clk,
+        ap_rst_n,
+        m_axi_in1_mem_AWVALID,
+        m_axi_in1_mem_AWREADY,
+        m_axi_in1_mem_AWADDR,
+        m_axi_in1_mem_AWID,
+        m_axi_in1_mem_AWLEN,
+        m_axi_in1_mem_AWSIZE,
+        m_axi_in1_mem_AWBURST,
+        m_axi_in1_mem_AWLOCK,
+        m_axi_in1_mem_AWCACHE,
+        m_axi_in1_mem_AWPROT,
+        m_axi_in1_mem_AWQOS,
+        m_axi_in1_mem_AWREGION,
+        m_axi_in1_mem_AWUSER,
+        m_axi_in1_mem_WVALID,
+        m_axi_in1_mem_WREADY,
+        m_axi_in1_mem_WDATA,
+        m_axi_in1_mem_WSTRB,
+        m_axi_in1_mem_WLAST,
+        m_axi_in1_mem_WID,
+        m_axi_in1_mem_WUSER,
+        m_axi_in1_mem_ARVALID,
+        m_axi_in1_mem_ARREADY,
+        m_axi_in1_mem_ARADDR,
+        m_axi_in1_mem_ARID,
+        m_axi_in1_mem_ARLEN,
+        m_axi_in1_mem_ARSIZE,
+        m_axi_in1_mem_ARBURST,
+        m_axi_in1_mem_ARLOCK,
+        m_axi_in1_mem_ARCACHE,
+        m_axi_in1_mem_ARPROT,
+        m_axi_in1_mem_ARQOS,
+        m_axi_in1_mem_ARREGION,
+        m_axi_in1_mem_ARUSER,
+        m_axi_in1_mem_RVALID,
+        m_axi_in1_mem_RREADY,
+        m_axi_in1_mem_RDATA,
+        m_axi_in1_mem_RLAST,
+        m_axi_in1_mem_RID,
+        m_axi_in1_mem_RUSER,
+        m_axi_in1_mem_RRESP,
+        m_axi_in1_mem_BVALID,
+        m_axi_in1_mem_BREADY,
+        m_axi_in1_mem_BRESP,
+        m_axi_in1_mem_BID,
+        m_axi_in1_mem_BUSER,
+        m_axi_in2_mem_AWVALID,
+        m_axi_in2_mem_AWREADY,
+        m_axi_in2_mem_AWADDR,
+        m_axi_in2_mem_AWID,
+        m_axi_in2_mem_AWLEN,
+        m_axi_in2_mem_AWSIZE,
+        m_axi_in2_mem_AWBURST,
+        m_axi_in2_mem_AWLOCK,
+        m_axi_in2_mem_AWCACHE,
+        m_axi_in2_mem_AWPROT,
+        m_axi_in2_mem_AWQOS,
+        m_axi_in2_mem_AWREGION,
+        m_axi_in2_mem_AWUSER,
+        m_axi_in2_mem_WVALID,
+        m_axi_in2_mem_WREADY,
+        m_axi_in2_mem_WDATA,
+        m_axi_in2_mem_WSTRB,
+        m_axi_in2_mem_WLAST,
+        m_axi_in2_mem_WID,
+        m_axi_in2_mem_WUSER,
+        m_axi_in2_mem_ARVALID,
+        m_axi_in2_mem_ARREADY,
+        m_axi_in2_mem_ARADDR,
+        m_axi_in2_mem_ARID,
+        m_axi_in2_mem_ARLEN,
+        m_axi_in2_mem_ARSIZE,
+        m_axi_in2_mem_ARBURST,
+        m_axi_in2_mem_ARLOCK,
+        m_axi_in2_mem_ARCACHE,
+        m_axi_in2_mem_ARPROT,
+        m_axi_in2_mem_ARQOS,
+        m_axi_in2_mem_ARREGION,
+        m_axi_in2_mem_ARUSER,
+        m_axi_in2_mem_RVALID,
+        m_axi_in2_mem_RREADY,
+        m_axi_in2_mem_RDATA,
+        m_axi_in2_mem_RLAST,
+        m_axi_in2_mem_RID,
+        m_axi_in2_mem_RUSER,
+        m_axi_in2_mem_RRESP,
+        m_axi_in2_mem_BVALID,
+        m_axi_in2_mem_BREADY,
+        m_axi_in2_mem_BRESP,
+        m_axi_in2_mem_BID,
+        m_axi_in2_mem_BUSER,
+        m_axi_out_mem_AWVALID,
+        m_axi_out_mem_AWREADY,
+        m_axi_out_mem_AWADDR,
+        m_axi_out_mem_AWID,
+        m_axi_out_mem_AWLEN,
+        m_axi_out_mem_AWSIZE,
+        m_axi_out_mem_AWBURST,
+        m_axi_out_mem_AWLOCK,
+        m_axi_out_mem_AWCACHE,
+        m_axi_out_mem_AWPROT,
+        m_axi_out_mem_AWQOS,
+        m_axi_out_mem_AWREGION,
+        m_axi_out_mem_AWUSER,
+        m_axi_out_mem_WVALID,
+        m_axi_out_mem_WREADY,
+        m_axi_out_mem_WDATA,
+        m_axi_out_mem_WSTRB,
+        m_axi_out_mem_WLAST,
+        m_axi_out_mem_WID,
+        m_axi_out_mem_WUSER,
+        m_axi_out_mem_ARVALID,
+        m_axi_out_mem_ARREADY,
+        m_axi_out_mem_ARADDR,
+        m_axi_out_mem_ARID,
+        m_axi_out_mem_ARLEN,
+        m_axi_out_mem_ARSIZE,
+        m_axi_out_mem_ARBURST,
+        m_axi_out_mem_ARLOCK,
+        m_axi_out_mem_ARCACHE,
+        m_axi_out_mem_ARPROT,
+        m_axi_out_mem_ARQOS,
+        m_axi_out_mem_ARREGION,
+        m_axi_out_mem_ARUSER,
+        m_axi_out_mem_RVALID,
+        m_axi_out_mem_RREADY,
+        m_axi_out_mem_RDATA,
+        m_axi_out_mem_RLAST,
+        m_axi_out_mem_RID,
+        m_axi_out_mem_RUSER,
+        m_axi_out_mem_RRESP,
+        m_axi_out_mem_BVALID,
+        m_axi_out_mem_BREADY,
+        m_axi_out_mem_BRESP,
+        m_axi_out_mem_BID,
+        m_axi_out_mem_BUSER,
+        s_axi_params_AWVALID,
+        s_axi_params_AWREADY,
+        s_axi_params_AWADDR,
+        s_axi_params_WVALID,
+        s_axi_params_WREADY,
+        s_axi_params_WDATA,
+        s_axi_params_WSTRB,
+        s_axi_params_ARVALID,
+        s_axi_params_ARREADY,
+        s_axi_params_ARADDR,
+        s_axi_params_RVALID,
+        s_axi_params_RREADY,
+        s_axi_params_RDATA,
+        s_axi_params_RRESP,
+        s_axi_params_BVALID,
+        s_axi_params_BREADY,
+        s_axi_params_BRESP,
+        interrupt
+);
+
+parameter    ap_ST_fsm_state1 = 26'd1;
+parameter    ap_ST_fsm_state2 = 26'd2;
+parameter    ap_ST_fsm_state3 = 26'd4;
+parameter    ap_ST_fsm_state4 = 26'd8;
+parameter    ap_ST_fsm_state5 = 26'd16;
+parameter    ap_ST_fsm_state6 = 26'd32;
+parameter    ap_ST_fsm_state7 = 26'd64;
+parameter    ap_ST_fsm_state8 = 26'd128;
+parameter    ap_ST_fsm_pp0_stage0 = 26'd256;
+parameter    ap_ST_fsm_state12 = 26'd512;
+parameter    ap_ST_fsm_state13 = 26'd1024;
+parameter    ap_ST_fsm_state14 = 26'd2048;
+parameter    ap_ST_fsm_state15 = 26'd4096;
+parameter    ap_ST_fsm_state16 = 26'd8192;
+parameter    ap_ST_fsm_state17 = 26'd16384;
+parameter    ap_ST_fsm_state18 = 26'd32768;
+parameter    ap_ST_fsm_pp1_stage0 = 26'd65536;
+parameter    ap_ST_fsm_state22 = 26'd131072;
+parameter    ap_ST_fsm_pp2_stage0 = 26'd262144;
+parameter    ap_ST_fsm_state26 = 26'd524288;
+parameter    ap_ST_fsm_pp3_stage0 = 26'd1048576;
+parameter    ap_ST_fsm_state30 = 26'd2097152;
+parameter    ap_ST_fsm_state31 = 26'd4194304;
+parameter    ap_ST_fsm_state32 = 26'd8388608;
+parameter    ap_ST_fsm_state33 = 26'd16777216;
+parameter    ap_ST_fsm_state34 = 26'd33554432;
+parameter    C_S_AXI_PARAMS_DATA_WIDTH = 32;
+parameter    C_S_AXI_PARAMS_ADDR_WIDTH = 6;
+parameter    C_S_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_OUT_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_CACHE_VALUE = 3;
+
+parameter C_S_AXI_PARAMS_WSTRB_WIDTH = (32 / 8);
+parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN1_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN2_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_OUT_MEM_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+output   m_axi_in1_mem_AWVALID;
+input   m_axi_in1_mem_AWREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_AWADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_AWID;
+output  [7:0] m_axi_in1_mem_AWLEN;
+output  [2:0] m_axi_in1_mem_AWSIZE;
+output  [1:0] m_axi_in1_mem_AWBURST;
+output  [1:0] m_axi_in1_mem_AWLOCK;
+output  [3:0] m_axi_in1_mem_AWCACHE;
+output  [2:0] m_axi_in1_mem_AWPROT;
+output  [3:0] m_axi_in1_mem_AWQOS;
+output  [3:0] m_axi_in1_mem_AWREGION;
+output  [C_M_AXI_IN1_MEM_AWUSER_WIDTH - 1:0] m_axi_in1_mem_AWUSER;
+output   m_axi_in1_mem_WVALID;
+input   m_axi_in1_mem_WREADY;
+output  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_WDATA;
+output  [C_M_AXI_IN1_MEM_WSTRB_WIDTH - 1:0] m_axi_in1_mem_WSTRB;
+output   m_axi_in1_mem_WLAST;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_WID;
+output  [C_M_AXI_IN1_MEM_WUSER_WIDTH - 1:0] m_axi_in1_mem_WUSER;
+output   m_axi_in1_mem_ARVALID;
+input   m_axi_in1_mem_ARREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_ARADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_ARID;
+output  [7:0] m_axi_in1_mem_ARLEN;
+output  [2:0] m_axi_in1_mem_ARSIZE;
+output  [1:0] m_axi_in1_mem_ARBURST;
+output  [1:0] m_axi_in1_mem_ARLOCK;
+output  [3:0] m_axi_in1_mem_ARCACHE;
+output  [2:0] m_axi_in1_mem_ARPROT;
+output  [3:0] m_axi_in1_mem_ARQOS;
+output  [3:0] m_axi_in1_mem_ARREGION;
+output  [C_M_AXI_IN1_MEM_ARUSER_WIDTH - 1:0] m_axi_in1_mem_ARUSER;
+input   m_axi_in1_mem_RVALID;
+output   m_axi_in1_mem_RREADY;
+input  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_RDATA;
+input   m_axi_in1_mem_RLAST;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_RID;
+input  [C_M_AXI_IN1_MEM_RUSER_WIDTH - 1:0] m_axi_in1_mem_RUSER;
+input  [1:0] m_axi_in1_mem_RRESP;
+input   m_axi_in1_mem_BVALID;
+output   m_axi_in1_mem_BREADY;
+input  [1:0] m_axi_in1_mem_BRESP;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_BID;
+input  [C_M_AXI_IN1_MEM_BUSER_WIDTH - 1:0] m_axi_in1_mem_BUSER;
+output   m_axi_in2_mem_AWVALID;
+input   m_axi_in2_mem_AWREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_AWADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_AWID;
+output  [7:0] m_axi_in2_mem_AWLEN;
+output  [2:0] m_axi_in2_mem_AWSIZE;
+output  [1:0] m_axi_in2_mem_AWBURST;
+output  [1:0] m_axi_in2_mem_AWLOCK;
+output  [3:0] m_axi_in2_mem_AWCACHE;
+output  [2:0] m_axi_in2_mem_AWPROT;
+output  [3:0] m_axi_in2_mem_AWQOS;
+output  [3:0] m_axi_in2_mem_AWREGION;
+output  [C_M_AXI_IN2_MEM_AWUSER_WIDTH - 1:0] m_axi_in2_mem_AWUSER;
+output   m_axi_in2_mem_WVALID;
+input   m_axi_in2_mem_WREADY;
+output  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_WDATA;
+output  [C_M_AXI_IN2_MEM_WSTRB_WIDTH - 1:0] m_axi_in2_mem_WSTRB;
+output   m_axi_in2_mem_WLAST;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_WID;
+output  [C_M_AXI_IN2_MEM_WUSER_WIDTH - 1:0] m_axi_in2_mem_WUSER;
+output   m_axi_in2_mem_ARVALID;
+input   m_axi_in2_mem_ARREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_ARADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_ARID;
+output  [7:0] m_axi_in2_mem_ARLEN;
+output  [2:0] m_axi_in2_mem_ARSIZE;
+output  [1:0] m_axi_in2_mem_ARBURST;
+output  [1:0] m_axi_in2_mem_ARLOCK;
+output  [3:0] m_axi_in2_mem_ARCACHE;
+output  [2:0] m_axi_in2_mem_ARPROT;
+output  [3:0] m_axi_in2_mem_ARQOS;
+output  [3:0] m_axi_in2_mem_ARREGION;
+output  [C_M_AXI_IN2_MEM_ARUSER_WIDTH - 1:0] m_axi_in2_mem_ARUSER;
+input   m_axi_in2_mem_RVALID;
+output   m_axi_in2_mem_RREADY;
+input  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_RDATA;
+input   m_axi_in2_mem_RLAST;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_RID;
+input  [C_M_AXI_IN2_MEM_RUSER_WIDTH - 1:0] m_axi_in2_mem_RUSER;
+input  [1:0] m_axi_in2_mem_RRESP;
+input   m_axi_in2_mem_BVALID;
+output   m_axi_in2_mem_BREADY;
+input  [1:0] m_axi_in2_mem_BRESP;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_BID;
+input  [C_M_AXI_IN2_MEM_BUSER_WIDTH - 1:0] m_axi_in2_mem_BUSER;
+output   m_axi_out_mem_AWVALID;
+input   m_axi_out_mem_AWREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_AWADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_AWID;
+output  [7:0] m_axi_out_mem_AWLEN;
+output  [2:0] m_axi_out_mem_AWSIZE;
+output  [1:0] m_axi_out_mem_AWBURST;
+output  [1:0] m_axi_out_mem_AWLOCK;
+output  [3:0] m_axi_out_mem_AWCACHE;
+output  [2:0] m_axi_out_mem_AWPROT;
+output  [3:0] m_axi_out_mem_AWQOS;
+output  [3:0] m_axi_out_mem_AWREGION;
+output  [C_M_AXI_OUT_MEM_AWUSER_WIDTH - 1:0] m_axi_out_mem_AWUSER;
+output   m_axi_out_mem_WVALID;
+input   m_axi_out_mem_WREADY;
+output  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_WDATA;
+output  [C_M_AXI_OUT_MEM_WSTRB_WIDTH - 1:0] m_axi_out_mem_WSTRB;
+output   m_axi_out_mem_WLAST;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_WID;
+output  [C_M_AXI_OUT_MEM_WUSER_WIDTH - 1:0] m_axi_out_mem_WUSER;
+output   m_axi_out_mem_ARVALID;
+input   m_axi_out_mem_ARREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_ARADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_ARID;
+output  [7:0] m_axi_out_mem_ARLEN;
+output  [2:0] m_axi_out_mem_ARSIZE;
+output  [1:0] m_axi_out_mem_ARBURST;
+output  [1:0] m_axi_out_mem_ARLOCK;
+output  [3:0] m_axi_out_mem_ARCACHE;
+output  [2:0] m_axi_out_mem_ARPROT;
+output  [3:0] m_axi_out_mem_ARQOS;
+output  [3:0] m_axi_out_mem_ARREGION;
+output  [C_M_AXI_OUT_MEM_ARUSER_WIDTH - 1:0] m_axi_out_mem_ARUSER;
+input   m_axi_out_mem_RVALID;
+output   m_axi_out_mem_RREADY;
+input  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_RDATA;
+input   m_axi_out_mem_RLAST;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_RID;
+input  [C_M_AXI_OUT_MEM_RUSER_WIDTH - 1:0] m_axi_out_mem_RUSER;
+input  [1:0] m_axi_out_mem_RRESP;
+input   m_axi_out_mem_BVALID;
+output   m_axi_out_mem_BREADY;
+input  [1:0] m_axi_out_mem_BRESP;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_BID;
+input  [C_M_AXI_OUT_MEM_BUSER_WIDTH - 1:0] m_axi_out_mem_BUSER;
+input   s_axi_params_AWVALID;
+output   s_axi_params_AWREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_AWADDR;
+input   s_axi_params_WVALID;
+output   s_axi_params_WREADY;
+input  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_WDATA;
+input  [C_S_AXI_PARAMS_WSTRB_WIDTH - 1:0] s_axi_params_WSTRB;
+input   s_axi_params_ARVALID;
+output   s_axi_params_ARREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_ARADDR;
+output   s_axi_params_RVALID;
+input   s_axi_params_RREADY;
+output  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_RDATA;
+output  [1:0] s_axi_params_RRESP;
+output   s_axi_params_BVALID;
+input   s_axi_params_BREADY;
+output  [1:0] s_axi_params_BRESP;
+output   interrupt;
+
+ reg    ap_rst_n_inv;
+wire    ap_start;
+reg    ap_done;
+reg    ap_idle;
+(* fsm_encoding = "none" *) reg   [25:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    ap_ready;
+wire   [31:0] in1;
+wire   [31:0] in2;
+wire   [31:0] out_r;
+wire   [31:0] dim;
+reg    in1_mem_blk_n_AR;
+wire    ap_CS_fsm_state2;
+reg    in1_mem_blk_n_R;
+wire    ap_CS_fsm_pp0_stage0;
+reg    ap_enable_reg_pp0_iter1;
+wire    ap_block_pp0_stage0;
+reg    in2_mem_blk_n_AR;
+wire    ap_CS_fsm_state12;
+reg    in2_mem_blk_n_R;
+wire    ap_CS_fsm_pp1_stage0;
+reg    ap_enable_reg_pp1_iter1;
+wire    ap_block_pp1_stage0;
+reg    out_mem_blk_n_AW;
+wire    ap_CS_fsm_state26;
+reg    out_mem_blk_n_W;
+reg    ap_enable_reg_pp3_iter2;
+wire    ap_block_pp3_stage0;
+reg   [0:0] icmp_ln42_reg_5549;
+reg   [0:0] icmp_ln42_reg_5549_pp3_iter1_reg;
+reg    out_mem_blk_n_B;
+wire    ap_CS_fsm_state34;
+wire    in1_mem_AWREADY;
+wire    in1_mem_WREADY;
+reg    in1_mem_ARVALID;
+wire    in1_mem_ARREADY;
+wire   [31:0] in1_mem_ARADDR;
+wire    in1_mem_RVALID;
+reg    in1_mem_RREADY;
+wire   [31:0] in1_mem_RDATA;
+wire    in1_mem_RLAST;
+wire   [0:0] in1_mem_RID;
+wire   [0:0] in1_mem_RUSER;
+wire   [1:0] in1_mem_RRESP;
+wire    in1_mem_BVALID;
+wire   [1:0] in1_mem_BRESP;
+wire   [0:0] in1_mem_BID;
+wire   [0:0] in1_mem_BUSER;
+wire    in2_mem_AWREADY;
+wire    in2_mem_WREADY;
+reg    in2_mem_ARVALID;
+wire    in2_mem_ARREADY;
+wire    in2_mem_RVALID;
+reg    in2_mem_RREADY;
+wire   [31:0] in2_mem_RDATA;
+wire    in2_mem_RLAST;
+wire   [0:0] in2_mem_RID;
+wire   [0:0] in2_mem_RUSER;
+wire   [1:0] in2_mem_RRESP;
+wire    in2_mem_BVALID;
+wire   [1:0] in2_mem_BRESP;
+wire   [0:0] in2_mem_BID;
+wire   [0:0] in2_mem_BUSER;
+reg    out_mem_AWVALID;
+wire    out_mem_AWREADY;
+reg    out_mem_WVALID;
+wire    out_mem_WREADY;
+wire    out_mem_ARREADY;
+wire    out_mem_RVALID;
+wire   [31:0] out_mem_RDATA;
+wire    out_mem_RLAST;
+wire   [0:0] out_mem_RID;
+wire   [0:0] out_mem_RUSER;
+wire   [1:0] out_mem_RRESP;
+wire    out_mem_BVALID;
+reg    out_mem_BREADY;
+wire   [1:0] out_mem_BRESP;
+wire   [0:0] out_mem_BID;
+wire   [0:0] out_mem_BUSER;
+reg   [12:0] phi_ln27_reg_3296;
+reg   [12:0] phi_ln28_reg_3307;
+reg   [63:0] indvar_flatten_reg_3318;
+reg   [30:0] i_0_reg_3329;
+reg   [31:0] j_0_reg_3340;
+reg   [12:0] phi_ln42_reg_3351;
+reg   [31:0] dim_read_reg_4593;
+reg   [29:0] out5_reg_4599;
+reg   [29:0] in_reg_4604;
+reg   [29:0] in3_reg_4609;
+reg   [31:0] out_mem_addr_reg_4620;
+wire    ap_CS_fsm_state8;
+reg   [31:0] in2_mem_addr_reg_4626;
+wire   [0:0] icmp_ln27_fu_3420_p2;
+wire    ap_block_state9_pp0_stage0_iter0;
+reg    ap_block_state10_pp0_stage0_iter1;
+wire    ap_block_state11_pp0_stage0_iter2;
+reg    ap_block_pp0_stage0_11001;
+wire   [12:0] add_ln27_fu_3426_p2;
+reg    ap_enable_reg_pp0_iter0;
+reg   [6:0] lshr_ln_reg_4641;
+reg   [6:0] lshr_ln_reg_4641_pp0_iter1_reg;
+wire   [5:0] trunc_ln27_fu_3442_p1;
+reg   [5:0] trunc_ln27_reg_4646;
+reg   [5:0] trunc_ln27_reg_4646_pp0_iter1_reg;
+reg   [31:0] in1_mem_addr_read_reg_4650;
+wire   [0:0] icmp_ln28_fu_3513_p2;
+wire    ap_block_state19_pp1_stage0_iter0;
+reg    ap_block_state20_pp1_stage0_iter1;
+wire    ap_block_state21_pp1_stage0_iter2;
+reg    ap_block_pp1_stage0_11001;
+wire   [12:0] add_ln28_fu_3519_p2;
+reg    ap_enable_reg_pp1_iter0;
+wire   [5:0] trunc_ln28_fu_3525_p1;
+reg   [5:0] trunc_ln28_reg_4727;
+reg   [5:0] trunc_ln28_reg_4727_pp1_iter1_reg;
+reg   [5:0] trunc_ln1_reg_4732;
+reg   [5:0] trunc_ln1_reg_4732_pp1_iter1_reg;
+reg   [31:0] in2_mem_addr_read_reg_4736;
+wire   [63:0] mul_ln31_fu_3609_p2;
+reg   [63:0] mul_ln31_reg_4804;
+wire    ap_CS_fsm_state22;
+wire   [0:0] icmp_ln31_fu_3615_p2;
+reg   [0:0] icmp_ln31_reg_4809;
+wire    ap_CS_fsm_pp2_stage0;
+wire    ap_block_state23_pp2_stage0_iter0;
+wire    ap_block_state24_pp2_stage0_iter1;
+wire    ap_block_state25_pp2_stage0_iter2;
+wire    ap_block_pp2_stage0_11001;
+reg   [0:0] icmp_ln31_reg_4809_pp2_iter1_reg;
+wire   [63:0] add_ln31_fu_3620_p2;
+reg    ap_enable_reg_pp2_iter0;
+wire   [30:0] select_ln31_1_fu_3645_p3;
+reg   [30:0] select_ln31_1_reg_4818;
+reg   [11:0] out_loc_addr_reg_5143;
+reg   [11:0] out_loc_addr_reg_5143_pp2_iter1_reg;
+wire   [31:0] j_fu_3816_p2;
+wire   [31:0] mul_ln38_fu_3822_p2;
+reg   [31:0] mul_ln38_reg_5474;
+wire   [31:0] mul_ln38_1_fu_3828_p2;
+reg   [31:0] mul_ln38_1_reg_5479;
+wire   [31:0] mul_ln38_2_fu_3834_p2;
+reg   [31:0] mul_ln38_2_reg_5484;
+wire   [31:0] add_ln38_3_fu_4206_p2;
+reg   [31:0] add_ln38_3_reg_5489;
+wire   [31:0] add_ln38_4_fu_4212_p2;
+reg   [31:0] add_ln38_4_reg_5494;
+wire   [31:0] add_ln38_9_fu_4230_p2;
+reg   [31:0] add_ln38_9_reg_5499;
+wire   [31:0] add_ln38_12_fu_4248_p2;
+reg   [31:0] add_ln38_12_reg_5504;
+wire   [31:0] add_ln38_21_fu_4290_p2;
+reg   [31:0] add_ln38_21_reg_5509;
+wire   [31:0] add_ln38_28_fu_4332_p2;
+reg   [31:0] add_ln38_28_reg_5514;
+wire   [31:0] add_ln38_37_fu_4374_p2;
+reg   [31:0] add_ln38_37_reg_5519;
+wire   [31:0] add_ln38_40_fu_4392_p2;
+reg   [31:0] add_ln38_40_reg_5524;
+wire   [31:0] add_ln38_43_fu_4410_p2;
+reg   [31:0] add_ln38_43_reg_5529;
+wire   [31:0] add_ln38_52_fu_4452_p2;
+reg   [31:0] add_ln38_52_reg_5534;
+wire   [31:0] add_ln38_55_fu_4470_p2;
+reg   [31:0] add_ln38_55_reg_5539;
+wire   [31:0] add_ln38_59_fu_4494_p2;
+reg   [31:0] add_ln38_59_reg_5544;
+wire   [0:0] icmp_ln42_fu_4576_p2;
+wire    ap_CS_fsm_pp3_stage0;
+wire    ap_block_state27_pp3_stage0_iter0;
+wire    ap_block_state28_pp3_stage0_iter1;
+wire    ap_block_state29_pp3_stage0_iter2;
+reg    ap_block_state29_io;
+reg    ap_block_pp3_stage0_11001;
+wire   [12:0] add_ln42_fu_4582_p2;
+reg    ap_enable_reg_pp3_iter0;
+wire   [31:0] out_loc_q0;
+reg   [31:0] out_loc_load_reg_5563;
+reg    ap_enable_reg_pp3_iter1;
+reg    ap_block_pp0_stage0_subdone;
+reg    ap_condition_pp0_exit_iter0_state9;
+reg    ap_enable_reg_pp0_iter2;
+wire    ap_CS_fsm_state18;
+reg    ap_block_pp1_stage0_subdone;
+reg    ap_condition_pp1_exit_iter0_state19;
+reg    ap_enable_reg_pp1_iter2;
+wire    ap_block_pp2_stage0_subdone;
+reg    ap_condition_pp2_exit_iter0_state23;
+reg    ap_enable_reg_pp2_iter1;
+reg    ap_enable_reg_pp2_iter2;
+reg    ap_block_pp3_stage0_subdone;
+reg    ap_condition_pp3_exit_iter0_state27;
+reg   [5:0] in1_loc_0_address0;
+reg    in1_loc_0_ce0;
+reg    in1_loc_0_we0;
+wire   [31:0] in1_loc_0_q0;
+reg   [5:0] in1_loc_1_address0;
+reg    in1_loc_1_ce0;
+reg    in1_loc_1_we0;
+wire   [31:0] in1_loc_1_q0;
+reg   [5:0] in1_loc_2_address0;
+reg    in1_loc_2_ce0;
+reg    in1_loc_2_we0;
+wire   [31:0] in1_loc_2_q0;
+reg   [5:0] in1_loc_3_address0;
+reg    in1_loc_3_ce0;
+reg    in1_loc_3_we0;
+wire   [31:0] in1_loc_3_q0;
+reg   [5:0] in1_loc_4_address0;
+reg    in1_loc_4_ce0;
+reg    in1_loc_4_we0;
+wire   [31:0] in1_loc_4_q0;
+reg   [5:0] in1_loc_5_address0;
+reg    in1_loc_5_ce0;
+reg    in1_loc_5_we0;
+wire   [31:0] in1_loc_5_q0;
+reg   [5:0] in1_loc_6_address0;
+reg    in1_loc_6_ce0;
+reg    in1_loc_6_we0;
+wire   [31:0] in1_loc_6_q0;
+reg   [5:0] in1_loc_7_address0;
+reg    in1_loc_7_ce0;
+reg    in1_loc_7_we0;
+wire   [31:0] in1_loc_7_q0;
+reg   [5:0] in1_loc_8_address0;
+reg    in1_loc_8_ce0;
+reg    in1_loc_8_we0;
+wire   [31:0] in1_loc_8_q0;
+reg   [5:0] in1_loc_9_address0;
+reg    in1_loc_9_ce0;
+reg    in1_loc_9_we0;
+wire   [31:0] in1_loc_9_q0;
+reg   [5:0] in1_loc_10_address0;
+reg    in1_loc_10_ce0;
+reg    in1_loc_10_we0;
+wire   [31:0] in1_loc_10_q0;
+reg   [5:0] in1_loc_11_address0;
+reg    in1_loc_11_ce0;
+reg    in1_loc_11_we0;
+wire   [31:0] in1_loc_11_q0;
+reg   [5:0] in1_loc_12_address0;
+reg    in1_loc_12_ce0;
+reg    in1_loc_12_we0;
+wire   [31:0] in1_loc_12_q0;
+reg   [5:0] in1_loc_13_address0;
+reg    in1_loc_13_ce0;
+reg    in1_loc_13_we0;
+wire   [31:0] in1_loc_13_q0;
+reg   [5:0] in1_loc_14_address0;
+reg    in1_loc_14_ce0;
+reg    in1_loc_14_we0;
+wire   [31:0] in1_loc_14_q0;
+reg   [5:0] in1_loc_15_address0;
+reg    in1_loc_15_ce0;
+reg    in1_loc_15_we0;
+wire   [31:0] in1_loc_15_q0;
+reg   [5:0] in1_loc_16_address0;
+reg    in1_loc_16_ce0;
+reg    in1_loc_16_we0;
+wire   [31:0] in1_loc_16_q0;
+reg   [5:0] in1_loc_17_address0;
+reg    in1_loc_17_ce0;
+reg    in1_loc_17_we0;
+wire   [31:0] in1_loc_17_q0;
+reg   [5:0] in1_loc_18_address0;
+reg    in1_loc_18_ce0;
+reg    in1_loc_18_we0;
+wire   [31:0] in1_loc_18_q0;
+reg   [5:0] in1_loc_19_address0;
+reg    in1_loc_19_ce0;
+reg    in1_loc_19_we0;
+wire   [31:0] in1_loc_19_q0;
+reg   [5:0] in1_loc_20_address0;
+reg    in1_loc_20_ce0;
+reg    in1_loc_20_we0;
+wire   [31:0] in1_loc_20_q0;
+reg   [5:0] in1_loc_21_address0;
+reg    in1_loc_21_ce0;
+reg    in1_loc_21_we0;
+wire   [31:0] in1_loc_21_q0;
+reg   [5:0] in1_loc_22_address0;
+reg    in1_loc_22_ce0;
+reg    in1_loc_22_we0;
+wire   [31:0] in1_loc_22_q0;
+reg   [5:0] in1_loc_23_address0;
+reg    in1_loc_23_ce0;
+reg    in1_loc_23_we0;
+wire   [31:0] in1_loc_23_q0;
+reg   [5:0] in1_loc_24_address0;
+reg    in1_loc_24_ce0;
+reg    in1_loc_24_we0;
+wire   [31:0] in1_loc_24_q0;
+reg   [5:0] in1_loc_25_address0;
+reg    in1_loc_25_ce0;
+reg    in1_loc_25_we0;
+wire   [31:0] in1_loc_25_q0;
+reg   [5:0] in1_loc_26_address0;
+reg    in1_loc_26_ce0;
+reg    in1_loc_26_we0;
+wire   [31:0] in1_loc_26_q0;
+reg   [5:0] in1_loc_27_address0;
+reg    in1_loc_27_ce0;
+reg    in1_loc_27_we0;
+wire   [31:0] in1_loc_27_q0;
+reg   [5:0] in1_loc_28_address0;
+reg    in1_loc_28_ce0;
+reg    in1_loc_28_we0;
+wire   [31:0] in1_loc_28_q0;
+reg   [5:0] in1_loc_29_address0;
+reg    in1_loc_29_ce0;
+reg    in1_loc_29_we0;
+wire   [31:0] in1_loc_29_q0;
+reg   [5:0] in1_loc_30_address0;
+reg    in1_loc_30_ce0;
+reg    in1_loc_30_we0;
+wire   [31:0] in1_loc_30_q0;
+reg   [5:0] in1_loc_31_address0;
+reg    in1_loc_31_ce0;
+reg    in1_loc_31_we0;
+wire   [31:0] in1_loc_31_q0;
+reg   [5:0] in1_loc_32_address0;
+reg    in1_loc_32_ce0;
+reg    in1_loc_32_we0;
+wire   [31:0] in1_loc_32_q0;
+reg   [5:0] in1_loc_33_address0;
+reg    in1_loc_33_ce0;
+reg    in1_loc_33_we0;
+wire   [31:0] in1_loc_33_q0;
+reg   [5:0] in1_loc_34_address0;
+reg    in1_loc_34_ce0;
+reg    in1_loc_34_we0;
+wire   [31:0] in1_loc_34_q0;
+reg   [5:0] in1_loc_35_address0;
+reg    in1_loc_35_ce0;
+reg    in1_loc_35_we0;
+wire   [31:0] in1_loc_35_q0;
+reg   [5:0] in1_loc_36_address0;
+reg    in1_loc_36_ce0;
+reg    in1_loc_36_we0;
+wire   [31:0] in1_loc_36_q0;
+reg   [5:0] in1_loc_37_address0;
+reg    in1_loc_37_ce0;
+reg    in1_loc_37_we0;
+wire   [31:0] in1_loc_37_q0;
+reg   [5:0] in1_loc_38_address0;
+reg    in1_loc_38_ce0;
+reg    in1_loc_38_we0;
+wire   [31:0] in1_loc_38_q0;
+reg   [5:0] in1_loc_39_address0;
+reg    in1_loc_39_ce0;
+reg    in1_loc_39_we0;
+wire   [31:0] in1_loc_39_q0;
+reg   [5:0] in1_loc_40_address0;
+reg    in1_loc_40_ce0;
+reg    in1_loc_40_we0;
+wire   [31:0] in1_loc_40_q0;
+reg   [5:0] in1_loc_41_address0;
+reg    in1_loc_41_ce0;
+reg    in1_loc_41_we0;
+wire   [31:0] in1_loc_41_q0;
+reg   [5:0] in1_loc_42_address0;
+reg    in1_loc_42_ce0;
+reg    in1_loc_42_we0;
+wire   [31:0] in1_loc_42_q0;
+reg   [5:0] in1_loc_43_address0;
+reg    in1_loc_43_ce0;
+reg    in1_loc_43_we0;
+wire   [31:0] in1_loc_43_q0;
+reg   [5:0] in1_loc_44_address0;
+reg    in1_loc_44_ce0;
+reg    in1_loc_44_we0;
+wire   [31:0] in1_loc_44_q0;
+reg   [5:0] in1_loc_45_address0;
+reg    in1_loc_45_ce0;
+reg    in1_loc_45_we0;
+wire   [31:0] in1_loc_45_q0;
+reg   [5:0] in1_loc_46_address0;
+reg    in1_loc_46_ce0;
+reg    in1_loc_46_we0;
+wire   [31:0] in1_loc_46_q0;
+reg   [5:0] in1_loc_47_address0;
+reg    in1_loc_47_ce0;
+reg    in1_loc_47_we0;
+wire   [31:0] in1_loc_47_q0;
+reg   [5:0] in1_loc_48_address0;
+reg    in1_loc_48_ce0;
+reg    in1_loc_48_we0;
+wire   [31:0] in1_loc_48_q0;
+reg   [5:0] in1_loc_49_address0;
+reg    in1_loc_49_ce0;
+reg    in1_loc_49_we0;
+wire   [31:0] in1_loc_49_q0;
+reg   [5:0] in1_loc_50_address0;
+reg    in1_loc_50_ce0;
+reg    in1_loc_50_we0;
+wire   [31:0] in1_loc_50_q0;
+reg   [5:0] in1_loc_51_address0;
+reg    in1_loc_51_ce0;
+reg    in1_loc_51_we0;
+wire   [31:0] in1_loc_51_q0;
+reg   [5:0] in1_loc_52_address0;
+reg    in1_loc_52_ce0;
+reg    in1_loc_52_we0;
+wire   [31:0] in1_loc_52_q0;
+reg   [5:0] in1_loc_53_address0;
+reg    in1_loc_53_ce0;
+reg    in1_loc_53_we0;
+wire   [31:0] in1_loc_53_q0;
+reg   [5:0] in1_loc_54_address0;
+reg    in1_loc_54_ce0;
+reg    in1_loc_54_we0;
+wire   [31:0] in1_loc_54_q0;
+reg   [5:0] in1_loc_55_address0;
+reg    in1_loc_55_ce0;
+reg    in1_loc_55_we0;
+wire   [31:0] in1_loc_55_q0;
+reg   [5:0] in1_loc_56_address0;
+reg    in1_loc_56_ce0;
+reg    in1_loc_56_we0;
+wire   [31:0] in1_loc_56_q0;
+reg   [5:0] in1_loc_57_address0;
+reg    in1_loc_57_ce0;
+reg    in1_loc_57_we0;
+wire   [31:0] in1_loc_57_q0;
+reg   [5:0] in1_loc_58_address0;
+reg    in1_loc_58_ce0;
+reg    in1_loc_58_we0;
+wire   [31:0] in1_loc_58_q0;
+reg   [5:0] in1_loc_59_address0;
+reg    in1_loc_59_ce0;
+reg    in1_loc_59_we0;
+wire   [31:0] in1_loc_59_q0;
+reg   [5:0] in1_loc_60_address0;
+reg    in1_loc_60_ce0;
+reg    in1_loc_60_we0;
+wire   [31:0] in1_loc_60_q0;
+reg   [5:0] in1_loc_61_address0;
+reg    in1_loc_61_ce0;
+reg    in1_loc_61_we0;
+wire   [31:0] in1_loc_61_q0;
+reg   [5:0] in1_loc_62_address0;
+reg    in1_loc_62_ce0;
+reg    in1_loc_62_we0;
+wire   [31:0] in1_loc_62_q0;
+reg   [5:0] in1_loc_63_address0;
+reg    in1_loc_63_ce0;
+reg    in1_loc_63_we0;
+wire   [31:0] in1_loc_63_q0;
+reg   [5:0] in2_loc_0_address0;
+reg    in2_loc_0_ce0;
+reg    in2_loc_0_we0;
+wire   [31:0] in2_loc_0_q0;
+reg   [5:0] in2_loc_1_address0;
+reg    in2_loc_1_ce0;
+reg    in2_loc_1_we0;
+wire   [31:0] in2_loc_1_q0;
+reg   [5:0] in2_loc_2_address0;
+reg    in2_loc_2_ce0;
+reg    in2_loc_2_we0;
+wire   [31:0] in2_loc_2_q0;
+reg   [5:0] in2_loc_3_address0;
+reg    in2_loc_3_ce0;
+reg    in2_loc_3_we0;
+wire   [31:0] in2_loc_3_q0;
+reg   [5:0] in2_loc_4_address0;
+reg    in2_loc_4_ce0;
+reg    in2_loc_4_we0;
+wire   [31:0] in2_loc_4_q0;
+reg   [5:0] in2_loc_5_address0;
+reg    in2_loc_5_ce0;
+reg    in2_loc_5_we0;
+wire   [31:0] in2_loc_5_q0;
+reg   [5:0] in2_loc_6_address0;
+reg    in2_loc_6_ce0;
+reg    in2_loc_6_we0;
+wire   [31:0] in2_loc_6_q0;
+reg   [5:0] in2_loc_7_address0;
+reg    in2_loc_7_ce0;
+reg    in2_loc_7_we0;
+wire   [31:0] in2_loc_7_q0;
+reg   [5:0] in2_loc_8_address0;
+reg    in2_loc_8_ce0;
+reg    in2_loc_8_we0;
+wire   [31:0] in2_loc_8_q0;
+reg   [5:0] in2_loc_9_address0;
+reg    in2_loc_9_ce0;
+reg    in2_loc_9_we0;
+wire   [31:0] in2_loc_9_q0;
+reg   [5:0] in2_loc_10_address0;
+reg    in2_loc_10_ce0;
+reg    in2_loc_10_we0;
+wire   [31:0] in2_loc_10_q0;
+reg   [5:0] in2_loc_11_address0;
+reg    in2_loc_11_ce0;
+reg    in2_loc_11_we0;
+wire   [31:0] in2_loc_11_q0;
+reg   [5:0] in2_loc_12_address0;
+reg    in2_loc_12_ce0;
+reg    in2_loc_12_we0;
+wire   [31:0] in2_loc_12_q0;
+reg   [5:0] in2_loc_13_address0;
+reg    in2_loc_13_ce0;
+reg    in2_loc_13_we0;
+wire   [31:0] in2_loc_13_q0;
+reg   [5:0] in2_loc_14_address0;
+reg    in2_loc_14_ce0;
+reg    in2_loc_14_we0;
+wire   [31:0] in2_loc_14_q0;
+reg   [5:0] in2_loc_15_address0;
+reg    in2_loc_15_ce0;
+reg    in2_loc_15_we0;
+wire   [31:0] in2_loc_15_q0;
+reg   [5:0] in2_loc_16_address0;
+reg    in2_loc_16_ce0;
+reg    in2_loc_16_we0;
+wire   [31:0] in2_loc_16_q0;
+reg   [5:0] in2_loc_17_address0;
+reg    in2_loc_17_ce0;
+reg    in2_loc_17_we0;
+wire   [31:0] in2_loc_17_q0;
+reg   [5:0] in2_loc_18_address0;
+reg    in2_loc_18_ce0;
+reg    in2_loc_18_we0;
+wire   [31:0] in2_loc_18_q0;
+reg   [5:0] in2_loc_19_address0;
+reg    in2_loc_19_ce0;
+reg    in2_loc_19_we0;
+wire   [31:0] in2_loc_19_q0;
+reg   [5:0] in2_loc_20_address0;
+reg    in2_loc_20_ce0;
+reg    in2_loc_20_we0;
+wire   [31:0] in2_loc_20_q0;
+reg   [5:0] in2_loc_21_address0;
+reg    in2_loc_21_ce0;
+reg    in2_loc_21_we0;
+wire   [31:0] in2_loc_21_q0;
+reg   [5:0] in2_loc_22_address0;
+reg    in2_loc_22_ce0;
+reg    in2_loc_22_we0;
+wire   [31:0] in2_loc_22_q0;
+reg   [5:0] in2_loc_23_address0;
+reg    in2_loc_23_ce0;
+reg    in2_loc_23_we0;
+wire   [31:0] in2_loc_23_q0;
+reg   [5:0] in2_loc_24_address0;
+reg    in2_loc_24_ce0;
+reg    in2_loc_24_we0;
+wire   [31:0] in2_loc_24_q0;
+reg   [5:0] in2_loc_25_address0;
+reg    in2_loc_25_ce0;
+reg    in2_loc_25_we0;
+wire   [31:0] in2_loc_25_q0;
+reg   [5:0] in2_loc_26_address0;
+reg    in2_loc_26_ce0;
+reg    in2_loc_26_we0;
+wire   [31:0] in2_loc_26_q0;
+reg   [5:0] in2_loc_27_address0;
+reg    in2_loc_27_ce0;
+reg    in2_loc_27_we0;
+wire   [31:0] in2_loc_27_q0;
+reg   [5:0] in2_loc_28_address0;
+reg    in2_loc_28_ce0;
+reg    in2_loc_28_we0;
+wire   [31:0] in2_loc_28_q0;
+reg   [5:0] in2_loc_29_address0;
+reg    in2_loc_29_ce0;
+reg    in2_loc_29_we0;
+wire   [31:0] in2_loc_29_q0;
+reg   [5:0] in2_loc_30_address0;
+reg    in2_loc_30_ce0;
+reg    in2_loc_30_we0;
+wire   [31:0] in2_loc_30_q0;
+reg   [5:0] in2_loc_31_address0;
+reg    in2_loc_31_ce0;
+reg    in2_loc_31_we0;
+wire   [31:0] in2_loc_31_q0;
+reg   [5:0] in2_loc_32_address0;
+reg    in2_loc_32_ce0;
+reg    in2_loc_32_we0;
+wire   [31:0] in2_loc_32_q0;
+reg   [5:0] in2_loc_33_address0;
+reg    in2_loc_33_ce0;
+reg    in2_loc_33_we0;
+wire   [31:0] in2_loc_33_q0;
+reg   [5:0] in2_loc_34_address0;
+reg    in2_loc_34_ce0;
+reg    in2_loc_34_we0;
+wire   [31:0] in2_loc_34_q0;
+reg   [5:0] in2_loc_35_address0;
+reg    in2_loc_35_ce0;
+reg    in2_loc_35_we0;
+wire   [31:0] in2_loc_35_q0;
+reg   [5:0] in2_loc_36_address0;
+reg    in2_loc_36_ce0;
+reg    in2_loc_36_we0;
+wire   [31:0] in2_loc_36_q0;
+reg   [5:0] in2_loc_37_address0;
+reg    in2_loc_37_ce0;
+reg    in2_loc_37_we0;
+wire   [31:0] in2_loc_37_q0;
+reg   [5:0] in2_loc_38_address0;
+reg    in2_loc_38_ce0;
+reg    in2_loc_38_we0;
+wire   [31:0] in2_loc_38_q0;
+reg   [5:0] in2_loc_39_address0;
+reg    in2_loc_39_ce0;
+reg    in2_loc_39_we0;
+wire   [31:0] in2_loc_39_q0;
+reg   [5:0] in2_loc_40_address0;
+reg    in2_loc_40_ce0;
+reg    in2_loc_40_we0;
+wire   [31:0] in2_loc_40_q0;
+reg   [5:0] in2_loc_41_address0;
+reg    in2_loc_41_ce0;
+reg    in2_loc_41_we0;
+wire   [31:0] in2_loc_41_q0;
+reg   [5:0] in2_loc_42_address0;
+reg    in2_loc_42_ce0;
+reg    in2_loc_42_we0;
+wire   [31:0] in2_loc_42_q0;
+reg   [5:0] in2_loc_43_address0;
+reg    in2_loc_43_ce0;
+reg    in2_loc_43_we0;
+wire   [31:0] in2_loc_43_q0;
+reg   [5:0] in2_loc_44_address0;
+reg    in2_loc_44_ce0;
+reg    in2_loc_44_we0;
+wire   [31:0] in2_loc_44_q0;
+reg   [5:0] in2_loc_45_address0;
+reg    in2_loc_45_ce0;
+reg    in2_loc_45_we0;
+wire   [31:0] in2_loc_45_q0;
+reg   [5:0] in2_loc_46_address0;
+reg    in2_loc_46_ce0;
+reg    in2_loc_46_we0;
+wire   [31:0] in2_loc_46_q0;
+reg   [5:0] in2_loc_47_address0;
+reg    in2_loc_47_ce0;
+reg    in2_loc_47_we0;
+wire   [31:0] in2_loc_47_q0;
+reg   [5:0] in2_loc_48_address0;
+reg    in2_loc_48_ce0;
+reg    in2_loc_48_we0;
+wire   [31:0] in2_loc_48_q0;
+reg   [5:0] in2_loc_49_address0;
+reg    in2_loc_49_ce0;
+reg    in2_loc_49_we0;
+wire   [31:0] in2_loc_49_q0;
+reg   [5:0] in2_loc_50_address0;
+reg    in2_loc_50_ce0;
+reg    in2_loc_50_we0;
+wire   [31:0] in2_loc_50_q0;
+reg   [5:0] in2_loc_51_address0;
+reg    in2_loc_51_ce0;
+reg    in2_loc_51_we0;
+wire   [31:0] in2_loc_51_q0;
+reg   [5:0] in2_loc_52_address0;
+reg    in2_loc_52_ce0;
+reg    in2_loc_52_we0;
+wire   [31:0] in2_loc_52_q0;
+reg   [5:0] in2_loc_53_address0;
+reg    in2_loc_53_ce0;
+reg    in2_loc_53_we0;
+wire   [31:0] in2_loc_53_q0;
+reg   [5:0] in2_loc_54_address0;
+reg    in2_loc_54_ce0;
+reg    in2_loc_54_we0;
+wire   [31:0] in2_loc_54_q0;
+reg   [5:0] in2_loc_55_address0;
+reg    in2_loc_55_ce0;
+reg    in2_loc_55_we0;
+wire   [31:0] in2_loc_55_q0;
+reg   [5:0] in2_loc_56_address0;
+reg    in2_loc_56_ce0;
+reg    in2_loc_56_we0;
+wire   [31:0] in2_loc_56_q0;
+reg   [5:0] in2_loc_57_address0;
+reg    in2_loc_57_ce0;
+reg    in2_loc_57_we0;
+wire   [31:0] in2_loc_57_q0;
+reg   [5:0] in2_loc_58_address0;
+reg    in2_loc_58_ce0;
+reg    in2_loc_58_we0;
+wire   [31:0] in2_loc_58_q0;
+reg   [5:0] in2_loc_59_address0;
+reg    in2_loc_59_ce0;
+reg    in2_loc_59_we0;
+wire   [31:0] in2_loc_59_q0;
+reg   [5:0] in2_loc_60_address0;
+reg    in2_loc_60_ce0;
+reg    in2_loc_60_we0;
+wire   [31:0] in2_loc_60_q0;
+reg   [5:0] in2_loc_61_address0;
+reg    in2_loc_61_ce0;
+reg    in2_loc_61_we0;
+wire   [31:0] in2_loc_61_q0;
+reg   [5:0] in2_loc_62_address0;
+reg    in2_loc_62_ce0;
+reg    in2_loc_62_we0;
+wire   [31:0] in2_loc_62_q0;
+reg   [5:0] in2_loc_63_address0;
+reg    in2_loc_63_ce0;
+reg    in2_loc_63_we0;
+wire   [31:0] in2_loc_63_q0;
+reg   [11:0] out_loc_address0;
+reg    out_loc_ce0;
+reg    out_loc_ce1;
+reg    out_loc_we1;
+wire   [31:0] out_loc_d1;
+reg   [30:0] ap_phi_mux_i_0_phi_fu_3333_p4;
+wire    ap_block_pp2_stage0;
+wire   [63:0] zext_ln27_fu_3446_p1;
+wire   [63:0] zext_ln28_fu_3539_p1;
+wire   [63:0] zext_ln31_1_fu_3665_p1;
+wire   [63:0] zext_ln38_fu_3811_p1;
+wire  signed [63:0] sext_ln38_fu_3733_p1;
+wire   [63:0] zext_ln42_fu_4588_p1;
+wire   [63:0] empty_8_fu_3392_p1;
+wire   [63:0] empty_fu_3402_p1;
+wire   [63:0] empty_7_fu_3411_p1;
+wire    ap_block_pp3_stage0_01001;
+wire   [31:0] mul_ln31_fu_3609_p0;
+wire   [63:0] zext_ln31_fu_3606_p1;
+wire   [31:0] mul_ln31_fu_3609_p1;
+wire   [0:0] icmp_ln33_fu_3632_p2;
+wire   [30:0] i_fu_3626_p2;
+wire   [7:0] trunc_ln38_fu_3653_p1;
+wire  signed [31:0] select_ln31_fu_3637_p3;
+wire   [13:0] tmp_cast_fu_3657_p3;
+wire   [13:0] trunc_ln38_1_fu_3801_p1;
+wire   [13:0] add_ln38_64_fu_3805_p2;
+wire  signed [31:0] mul_ln38_fu_3822_p0;
+wire  signed [31:0] mul_ln38_fu_3822_p1;
+wire  signed [31:0] mul_ln38_1_fu_3828_p0;
+wire  signed [31:0] mul_ln38_1_fu_3828_p1;
+wire  signed [31:0] mul_ln38_2_fu_3834_p0;
+wire  signed [31:0] mul_ln38_2_fu_3834_p1;
+wire  signed [31:0] mul_ln38_3_fu_3840_p0;
+wire  signed [31:0] mul_ln38_3_fu_3840_p1;
+wire  signed [31:0] mul_ln38_4_fu_3846_p0;
+wire  signed [31:0] mul_ln38_4_fu_3846_p1;
+wire  signed [31:0] mul_ln38_5_fu_3852_p0;
+wire  signed [31:0] mul_ln38_5_fu_3852_p1;
+wire  signed [31:0] mul_ln38_6_fu_3858_p0;
+wire  signed [31:0] mul_ln38_6_fu_3858_p1;
+wire  signed [31:0] mul_ln38_7_fu_3864_p0;
+wire  signed [31:0] mul_ln38_7_fu_3864_p1;
+wire  signed [31:0] mul_ln38_8_fu_3870_p0;
+wire  signed [31:0] mul_ln38_8_fu_3870_p1;
+wire  signed [31:0] mul_ln38_9_fu_3876_p0;
+wire  signed [31:0] mul_ln38_9_fu_3876_p1;
+wire  signed [31:0] mul_ln38_10_fu_3882_p0;
+wire  signed [31:0] mul_ln38_10_fu_3882_p1;
+wire  signed [31:0] mul_ln38_11_fu_3888_p0;
+wire  signed [31:0] mul_ln38_11_fu_3888_p1;
+wire  signed [31:0] mul_ln38_12_fu_3894_p0;
+wire  signed [31:0] mul_ln38_12_fu_3894_p1;
+wire  signed [31:0] mul_ln38_13_fu_3900_p0;
+wire  signed [31:0] mul_ln38_13_fu_3900_p1;
+wire  signed [31:0] mul_ln38_14_fu_3906_p0;
+wire  signed [31:0] mul_ln38_14_fu_3906_p1;
+wire  signed [31:0] mul_ln38_15_fu_3912_p0;
+wire  signed [31:0] mul_ln38_15_fu_3912_p1;
+wire  signed [31:0] mul_ln38_16_fu_3918_p0;
+wire  signed [31:0] mul_ln38_16_fu_3918_p1;
+wire  signed [31:0] mul_ln38_17_fu_3924_p0;
+wire  signed [31:0] mul_ln38_17_fu_3924_p1;
+wire  signed [31:0] mul_ln38_18_fu_3930_p0;
+wire  signed [31:0] mul_ln38_18_fu_3930_p1;
+wire  signed [31:0] mul_ln38_19_fu_3936_p0;
+wire  signed [31:0] mul_ln38_19_fu_3936_p1;
+wire  signed [31:0] mul_ln38_20_fu_3942_p0;
+wire  signed [31:0] mul_ln38_20_fu_3942_p1;
+wire  signed [31:0] mul_ln38_21_fu_3948_p0;
+wire  signed [31:0] mul_ln38_21_fu_3948_p1;
+wire  signed [31:0] mul_ln38_22_fu_3954_p0;
+wire  signed [31:0] mul_ln38_22_fu_3954_p1;
+wire  signed [31:0] mul_ln38_23_fu_3960_p0;
+wire  signed [31:0] mul_ln38_23_fu_3960_p1;
+wire  signed [31:0] mul_ln38_24_fu_3966_p0;
+wire  signed [31:0] mul_ln38_24_fu_3966_p1;
+wire  signed [31:0] mul_ln38_25_fu_3972_p0;
+wire  signed [31:0] mul_ln38_25_fu_3972_p1;
+wire  signed [31:0] mul_ln38_26_fu_3978_p0;
+wire  signed [31:0] mul_ln38_26_fu_3978_p1;
+wire  signed [31:0] mul_ln38_27_fu_3984_p0;
+wire  signed [31:0] mul_ln38_27_fu_3984_p1;
+wire  signed [31:0] mul_ln38_28_fu_3990_p0;
+wire  signed [31:0] mul_ln38_28_fu_3990_p1;
+wire  signed [31:0] mul_ln38_29_fu_3996_p0;
+wire  signed [31:0] mul_ln38_29_fu_3996_p1;
+wire  signed [31:0] mul_ln38_30_fu_4002_p0;
+wire  signed [31:0] mul_ln38_30_fu_4002_p1;
+wire  signed [31:0] mul_ln38_31_fu_4008_p0;
+wire  signed [31:0] mul_ln38_31_fu_4008_p1;
+wire  signed [31:0] mul_ln38_32_fu_4014_p0;
+wire  signed [31:0] mul_ln38_32_fu_4014_p1;
+wire  signed [31:0] mul_ln38_33_fu_4020_p0;
+wire  signed [31:0] mul_ln38_33_fu_4020_p1;
+wire  signed [31:0] mul_ln38_34_fu_4026_p0;
+wire  signed [31:0] mul_ln38_34_fu_4026_p1;
+wire  signed [31:0] mul_ln38_35_fu_4032_p0;
+wire  signed [31:0] mul_ln38_35_fu_4032_p1;
+wire  signed [31:0] mul_ln38_36_fu_4038_p0;
+wire  signed [31:0] mul_ln38_36_fu_4038_p1;
+wire  signed [31:0] mul_ln38_37_fu_4044_p0;
+wire  signed [31:0] mul_ln38_37_fu_4044_p1;
+wire  signed [31:0] mul_ln38_38_fu_4050_p0;
+wire  signed [31:0] mul_ln38_38_fu_4050_p1;
+wire  signed [31:0] mul_ln38_39_fu_4056_p0;
+wire  signed [31:0] mul_ln38_39_fu_4056_p1;
+wire  signed [31:0] mul_ln38_40_fu_4062_p0;
+wire  signed [31:0] mul_ln38_40_fu_4062_p1;
+wire  signed [31:0] mul_ln38_41_fu_4068_p0;
+wire  signed [31:0] mul_ln38_41_fu_4068_p1;
+wire  signed [31:0] mul_ln38_42_fu_4074_p0;
+wire  signed [31:0] mul_ln38_42_fu_4074_p1;
+wire  signed [31:0] mul_ln38_43_fu_4080_p0;
+wire  signed [31:0] mul_ln38_43_fu_4080_p1;
+wire  signed [31:0] mul_ln38_44_fu_4086_p0;
+wire  signed [31:0] mul_ln38_44_fu_4086_p1;
+wire  signed [31:0] mul_ln38_45_fu_4092_p0;
+wire  signed [31:0] mul_ln38_45_fu_4092_p1;
+wire  signed [31:0] mul_ln38_46_fu_4098_p0;
+wire  signed [31:0] mul_ln38_46_fu_4098_p1;
+wire  signed [31:0] mul_ln38_47_fu_4104_p0;
+wire  signed [31:0] mul_ln38_47_fu_4104_p1;
+wire  signed [31:0] mul_ln38_48_fu_4110_p0;
+wire  signed [31:0] mul_ln38_48_fu_4110_p1;
+wire  signed [31:0] mul_ln38_49_fu_4116_p0;
+wire  signed [31:0] mul_ln38_49_fu_4116_p1;
+wire  signed [31:0] mul_ln38_50_fu_4122_p0;
+wire  signed [31:0] mul_ln38_50_fu_4122_p1;
+wire  signed [31:0] mul_ln38_51_fu_4128_p0;
+wire  signed [31:0] mul_ln38_51_fu_4128_p1;
+wire  signed [31:0] mul_ln38_52_fu_4134_p0;
+wire  signed [31:0] mul_ln38_52_fu_4134_p1;
+wire  signed [31:0] mul_ln38_53_fu_4140_p0;
+wire  signed [31:0] mul_ln38_53_fu_4140_p1;
+wire  signed [31:0] mul_ln38_54_fu_4146_p0;
+wire  signed [31:0] mul_ln38_54_fu_4146_p1;
+wire  signed [31:0] mul_ln38_55_fu_4152_p0;
+wire  signed [31:0] mul_ln38_55_fu_4152_p1;
+wire  signed [31:0] mul_ln38_56_fu_4158_p0;
+wire  signed [31:0] mul_ln38_56_fu_4158_p1;
+wire  signed [31:0] mul_ln38_57_fu_4164_p0;
+wire  signed [31:0] mul_ln38_57_fu_4164_p1;
+wire  signed [31:0] mul_ln38_58_fu_4170_p0;
+wire  signed [31:0] mul_ln38_58_fu_4170_p1;
+wire  signed [31:0] mul_ln38_59_fu_4176_p0;
+wire  signed [31:0] mul_ln38_59_fu_4176_p1;
+wire  signed [31:0] mul_ln38_60_fu_4182_p0;
+wire  signed [31:0] mul_ln38_60_fu_4182_p1;
+wire  signed [31:0] mul_ln38_61_fu_4188_p0;
+wire  signed [31:0] mul_ln38_61_fu_4188_p1;
+wire  signed [31:0] mul_ln38_62_fu_4194_p0;
+wire  signed [31:0] mul_ln38_62_fu_4194_p1;
+wire  signed [31:0] mul_ln38_63_fu_4200_p0;
+wire  signed [31:0] mul_ln38_63_fu_4200_p1;
+wire   [31:0] mul_ln38_4_fu_3846_p2;
+wire   [31:0] mul_ln38_3_fu_3840_p2;
+wire   [31:0] mul_ln38_6_fu_3858_p2;
+wire   [31:0] mul_ln38_5_fu_3852_p2;
+wire   [31:0] mul_ln38_8_fu_3870_p2;
+wire   [31:0] mul_ln38_7_fu_3864_p2;
+wire   [31:0] mul_ln38_10_fu_3882_p2;
+wire   [31:0] mul_ln38_9_fu_3876_p2;
+wire   [31:0] add_ln38_7_fu_4218_p2;
+wire   [31:0] add_ln38_8_fu_4224_p2;
+wire   [31:0] mul_ln38_12_fu_3894_p2;
+wire   [31:0] mul_ln38_11_fu_3888_p2;
+wire   [31:0] mul_ln38_14_fu_3906_p2;
+wire   [31:0] mul_ln38_13_fu_3900_p2;
+wire   [31:0] add_ln38_10_fu_4236_p2;
+wire   [31:0] add_ln38_11_fu_4242_p2;
+wire   [31:0] mul_ln38_16_fu_3918_p2;
+wire   [31:0] mul_ln38_15_fu_3912_p2;
+wire   [31:0] mul_ln38_18_fu_3930_p2;
+wire   [31:0] mul_ln38_17_fu_3924_p2;
+wire   [31:0] add_ln38_15_fu_4254_p2;
+wire   [31:0] add_ln38_16_fu_4260_p2;
+wire   [31:0] mul_ln38_20_fu_3942_p2;
+wire   [31:0] mul_ln38_19_fu_3936_p2;
+wire   [31:0] mul_ln38_22_fu_3954_p2;
+wire   [31:0] mul_ln38_21_fu_3948_p2;
+wire   [31:0] add_ln38_18_fu_4272_p2;
+wire   [31:0] add_ln38_19_fu_4278_p2;
+wire   [31:0] add_ln38_17_fu_4266_p2;
+wire   [31:0] add_ln38_20_fu_4284_p2;
+wire   [31:0] mul_ln38_24_fu_3966_p2;
+wire   [31:0] mul_ln38_23_fu_3960_p2;
+wire   [31:0] mul_ln38_26_fu_3978_p2;
+wire   [31:0] mul_ln38_25_fu_3972_p2;
+wire   [31:0] add_ln38_22_fu_4296_p2;
+wire   [31:0] add_ln38_23_fu_4302_p2;
+wire   [31:0] mul_ln38_28_fu_3990_p2;
+wire   [31:0] mul_ln38_27_fu_3984_p2;
+wire   [31:0] mul_ln38_30_fu_4002_p2;
+wire   [31:0] mul_ln38_29_fu_3996_p2;
+wire   [31:0] add_ln38_25_fu_4314_p2;
+wire   [31:0] add_ln38_26_fu_4320_p2;
+wire   [31:0] add_ln38_24_fu_4308_p2;
+wire   [31:0] add_ln38_27_fu_4326_p2;
+wire   [31:0] mul_ln38_32_fu_4014_p2;
+wire   [31:0] mul_ln38_31_fu_4008_p2;
+wire   [31:0] mul_ln38_34_fu_4026_p2;
+wire   [31:0] mul_ln38_33_fu_4020_p2;
+wire   [31:0] add_ln38_31_fu_4338_p2;
+wire   [31:0] add_ln38_32_fu_4344_p2;
+wire   [31:0] mul_ln38_36_fu_4038_p2;
+wire   [31:0] mul_ln38_35_fu_4032_p2;
+wire   [31:0] mul_ln38_38_fu_4050_p2;
+wire   [31:0] mul_ln38_37_fu_4044_p2;
+wire   [31:0] add_ln38_34_fu_4356_p2;
+wire   [31:0] add_ln38_35_fu_4362_p2;
+wire   [31:0] add_ln38_33_fu_4350_p2;
+wire   [31:0] add_ln38_36_fu_4368_p2;
+wire   [31:0] mul_ln38_40_fu_4062_p2;
+wire   [31:0] mul_ln38_39_fu_4056_p2;
+wire   [31:0] mul_ln38_42_fu_4074_p2;
+wire   [31:0] mul_ln38_41_fu_4068_p2;
+wire   [31:0] add_ln38_38_fu_4380_p2;
+wire   [31:0] add_ln38_39_fu_4386_p2;
+wire   [31:0] mul_ln38_44_fu_4086_p2;
+wire   [31:0] mul_ln38_43_fu_4080_p2;
+wire   [31:0] mul_ln38_46_fu_4098_p2;
+wire   [31:0] mul_ln38_45_fu_4092_p2;
+wire   [31:0] add_ln38_41_fu_4398_p2;
+wire   [31:0] add_ln38_42_fu_4404_p2;
+wire   [31:0] mul_ln38_48_fu_4110_p2;
+wire   [31:0] mul_ln38_47_fu_4104_p2;
+wire   [31:0] mul_ln38_50_fu_4122_p2;
+wire   [31:0] mul_ln38_49_fu_4116_p2;
+wire   [31:0] add_ln38_46_fu_4416_p2;
+wire   [31:0] add_ln38_47_fu_4422_p2;
+wire   [31:0] mul_ln38_52_fu_4134_p2;
+wire   [31:0] mul_ln38_51_fu_4128_p2;
+wire   [31:0] mul_ln38_54_fu_4146_p2;
+wire   [31:0] mul_ln38_53_fu_4140_p2;
+wire   [31:0] add_ln38_49_fu_4434_p2;
+wire   [31:0] add_ln38_50_fu_4440_p2;
+wire   [31:0] add_ln38_48_fu_4428_p2;
+wire   [31:0] add_ln38_51_fu_4446_p2;
+wire   [31:0] mul_ln38_56_fu_4158_p2;
+wire   [31:0] mul_ln38_55_fu_4152_p2;
+wire   [31:0] mul_ln38_58_fu_4170_p2;
+wire   [31:0] mul_ln38_57_fu_4164_p2;
+wire   [31:0] add_ln38_53_fu_4458_p2;
+wire   [31:0] add_ln38_54_fu_4464_p2;
+wire   [31:0] mul_ln38_60_fu_4182_p2;
+wire   [31:0] mul_ln38_59_fu_4176_p2;
+wire   [31:0] mul_ln38_63_fu_4200_p2;
+wire   [31:0] mul_ln38_62_fu_4194_p2;
+wire   [31:0] mul_ln38_61_fu_4188_p2;
+wire   [31:0] add_ln38_57_fu_4482_p2;
+wire   [31:0] add_ln38_56_fu_4476_p2;
+wire   [31:0] add_ln38_58_fu_4488_p2;
+wire   [31:0] add_ln38_fu_4500_p2;
+wire   [31:0] add_ln38_1_fu_4505_p2;
+wire   [31:0] add_ln38_2_fu_4509_p2;
+wire   [31:0] add_ln38_5_fu_4515_p2;
+wire   [31:0] add_ln38_6_fu_4519_p2;
+wire   [31:0] add_ln38_13_fu_4525_p2;
+wire   [31:0] add_ln38_14_fu_4529_p2;
+wire   [31:0] add_ln38_29_fu_4535_p2;
+wire   [31:0] add_ln38_44_fu_4545_p2;
+wire   [31:0] add_ln38_60_fu_4554_p2;
+wire   [31:0] add_ln38_45_fu_4549_p2;
+wire   [31:0] add_ln38_61_fu_4558_p2;
+wire   [31:0] add_ln38_30_fu_4539_p2;
+wire   [31:0] add_ln38_62_fu_4563_p2;
+reg   [25:0] ap_NS_fsm;
+reg    ap_idle_pp0;
+wire    ap_enable_pp0;
+reg    ap_idle_pp1;
+wire    ap_enable_pp1;
+reg    ap_idle_pp2;
+wire    ap_enable_pp2;
+reg    ap_idle_pp3;
+wire    ap_enable_pp3;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 26'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp1_iter1 = 1'b0;
+#0 ap_enable_reg_pp3_iter2 = 1'b0;
+#0 ap_enable_reg_pp0_iter0 = 1'b0;
+#0 ap_enable_reg_pp1_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter0 = 1'b0;
+#0 ap_enable_reg_pp3_iter0 = 1'b0;
+#0 ap_enable_reg_pp3_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp1_iter2 = 1'b0;
+#0 ap_enable_reg_pp2_iter1 = 1'b0;
+#0 ap_enable_reg_pp2_iter2 = 1'b0;
+end
+
+mmult_params_s_axi #(
+    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PARAMS_ADDR_WIDTH ),
+    .C_S_AXI_DATA_WIDTH( C_S_AXI_PARAMS_DATA_WIDTH ))
+mmult_params_s_axi_U(
+    .AWVALID(s_axi_params_AWVALID),
+    .AWREADY(s_axi_params_AWREADY),
+    .AWADDR(s_axi_params_AWADDR),
+    .WVALID(s_axi_params_WVALID),
+    .WREADY(s_axi_params_WREADY),
+    .WDATA(s_axi_params_WDATA),
+    .WSTRB(s_axi_params_WSTRB),
+    .ARVALID(s_axi_params_ARVALID),
+    .ARREADY(s_axi_params_ARREADY),
+    .ARADDR(s_axi_params_ARADDR),
+    .RVALID(s_axi_params_RVALID),
+    .RREADY(s_axi_params_RREADY),
+    .RDATA(s_axi_params_RDATA),
+    .RRESP(s_axi_params_RRESP),
+    .BVALID(s_axi_params_BVALID),
+    .BREADY(s_axi_params_BREADY),
+    .BRESP(s_axi_params_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .in1(in1),
+    .in2(in2),
+    .out_r(out_r),
+    .dim(dim)
+);
+
+mmult_in1_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN1_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN1_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN1_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN1_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN1_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN1_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN1_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN1_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN1_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN1_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN1_MEM_CACHE_VALUE ))
+mmult_in1_mem_m_axi_U(
+    .AWVALID(m_axi_in1_mem_AWVALID),
+    .AWREADY(m_axi_in1_mem_AWREADY),
+    .AWADDR(m_axi_in1_mem_AWADDR),
+    .AWID(m_axi_in1_mem_AWID),
+    .AWLEN(m_axi_in1_mem_AWLEN),
+    .AWSIZE(m_axi_in1_mem_AWSIZE),
+    .AWBURST(m_axi_in1_mem_AWBURST),
+    .AWLOCK(m_axi_in1_mem_AWLOCK),
+    .AWCACHE(m_axi_in1_mem_AWCACHE),
+    .AWPROT(m_axi_in1_mem_AWPROT),
+    .AWQOS(m_axi_in1_mem_AWQOS),
+    .AWREGION(m_axi_in1_mem_AWREGION),
+    .AWUSER(m_axi_in1_mem_AWUSER),
+    .WVALID(m_axi_in1_mem_WVALID),
+    .WREADY(m_axi_in1_mem_WREADY),
+    .WDATA(m_axi_in1_mem_WDATA),
+    .WSTRB(m_axi_in1_mem_WSTRB),
+    .WLAST(m_axi_in1_mem_WLAST),
+    .WID(m_axi_in1_mem_WID),
+    .WUSER(m_axi_in1_mem_WUSER),
+    .ARVALID(m_axi_in1_mem_ARVALID),
+    .ARREADY(m_axi_in1_mem_ARREADY),
+    .ARADDR(m_axi_in1_mem_ARADDR),
+    .ARID(m_axi_in1_mem_ARID),
+    .ARLEN(m_axi_in1_mem_ARLEN),
+    .ARSIZE(m_axi_in1_mem_ARSIZE),
+    .ARBURST(m_axi_in1_mem_ARBURST),
+    .ARLOCK(m_axi_in1_mem_ARLOCK),
+    .ARCACHE(m_axi_in1_mem_ARCACHE),
+    .ARPROT(m_axi_in1_mem_ARPROT),
+    .ARQOS(m_axi_in1_mem_ARQOS),
+    .ARREGION(m_axi_in1_mem_ARREGION),
+    .ARUSER(m_axi_in1_mem_ARUSER),
+    .RVALID(m_axi_in1_mem_RVALID),
+    .RREADY(m_axi_in1_mem_RREADY),
+    .RDATA(m_axi_in1_mem_RDATA),
+    .RLAST(m_axi_in1_mem_RLAST),
+    .RID(m_axi_in1_mem_RID),
+    .RUSER(m_axi_in1_mem_RUSER),
+    .RRESP(m_axi_in1_mem_RRESP),
+    .BVALID(m_axi_in1_mem_BVALID),
+    .BREADY(m_axi_in1_mem_BREADY),
+    .BRESP(m_axi_in1_mem_BRESP),
+    .BID(m_axi_in1_mem_BID),
+    .BUSER(m_axi_in1_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in1_mem_ARVALID),
+    .I_ARREADY(in1_mem_ARREADY),
+    .I_ARADDR(in1_mem_ARADDR),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in1_mem_RVALID),
+    .I_RREADY(in1_mem_RREADY),
+    .I_RDATA(in1_mem_RDATA),
+    .I_RID(in1_mem_RID),
+    .I_RUSER(in1_mem_RUSER),
+    .I_RRESP(in1_mem_RRESP),
+    .I_RLAST(in1_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in1_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in1_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in1_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in1_mem_BRESP),
+    .I_BID(in1_mem_BID),
+    .I_BUSER(in1_mem_BUSER)
+);
+
+mmult_in2_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN2_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN2_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN2_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN2_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN2_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN2_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN2_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN2_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN2_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN2_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN2_MEM_CACHE_VALUE ))
+mmult_in2_mem_m_axi_U(
+    .AWVALID(m_axi_in2_mem_AWVALID),
+    .AWREADY(m_axi_in2_mem_AWREADY),
+    .AWADDR(m_axi_in2_mem_AWADDR),
+    .AWID(m_axi_in2_mem_AWID),
+    .AWLEN(m_axi_in2_mem_AWLEN),
+    .AWSIZE(m_axi_in2_mem_AWSIZE),
+    .AWBURST(m_axi_in2_mem_AWBURST),
+    .AWLOCK(m_axi_in2_mem_AWLOCK),
+    .AWCACHE(m_axi_in2_mem_AWCACHE),
+    .AWPROT(m_axi_in2_mem_AWPROT),
+    .AWQOS(m_axi_in2_mem_AWQOS),
+    .AWREGION(m_axi_in2_mem_AWREGION),
+    .AWUSER(m_axi_in2_mem_AWUSER),
+    .WVALID(m_axi_in2_mem_WVALID),
+    .WREADY(m_axi_in2_mem_WREADY),
+    .WDATA(m_axi_in2_mem_WDATA),
+    .WSTRB(m_axi_in2_mem_WSTRB),
+    .WLAST(m_axi_in2_mem_WLAST),
+    .WID(m_axi_in2_mem_WID),
+    .WUSER(m_axi_in2_mem_WUSER),
+    .ARVALID(m_axi_in2_mem_ARVALID),
+    .ARREADY(m_axi_in2_mem_ARREADY),
+    .ARADDR(m_axi_in2_mem_ARADDR),
+    .ARID(m_axi_in2_mem_ARID),
+    .ARLEN(m_axi_in2_mem_ARLEN),
+    .ARSIZE(m_axi_in2_mem_ARSIZE),
+    .ARBURST(m_axi_in2_mem_ARBURST),
+    .ARLOCK(m_axi_in2_mem_ARLOCK),
+    .ARCACHE(m_axi_in2_mem_ARCACHE),
+    .ARPROT(m_axi_in2_mem_ARPROT),
+    .ARQOS(m_axi_in2_mem_ARQOS),
+    .ARREGION(m_axi_in2_mem_ARREGION),
+    .ARUSER(m_axi_in2_mem_ARUSER),
+    .RVALID(m_axi_in2_mem_RVALID),
+    .RREADY(m_axi_in2_mem_RREADY),
+    .RDATA(m_axi_in2_mem_RDATA),
+    .RLAST(m_axi_in2_mem_RLAST),
+    .RID(m_axi_in2_mem_RID),
+    .RUSER(m_axi_in2_mem_RUSER),
+    .RRESP(m_axi_in2_mem_RRESP),
+    .BVALID(m_axi_in2_mem_BVALID),
+    .BREADY(m_axi_in2_mem_BREADY),
+    .BRESP(m_axi_in2_mem_BRESP),
+    .BID(m_axi_in2_mem_BID),
+    .BUSER(m_axi_in2_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in2_mem_ARVALID),
+    .I_ARREADY(in2_mem_ARREADY),
+    .I_ARADDR(in2_mem_addr_reg_4626),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in2_mem_RVALID),
+    .I_RREADY(in2_mem_RREADY),
+    .I_RDATA(in2_mem_RDATA),
+    .I_RID(in2_mem_RID),
+    .I_RUSER(in2_mem_RUSER),
+    .I_RRESP(in2_mem_RRESP),
+    .I_RLAST(in2_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in2_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in2_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in2_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in2_mem_BRESP),
+    .I_BID(in2_mem_BID),
+    .I_BUSER(in2_mem_BUSER)
+);
+
+mmult_out_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_OUT_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_OUT_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_OUT_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_OUT_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_OUT_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_OUT_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_OUT_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_OUT_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_OUT_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_OUT_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_OUT_MEM_CACHE_VALUE ))
+mmult_out_mem_m_axi_U(
+    .AWVALID(m_axi_out_mem_AWVALID),
+    .AWREADY(m_axi_out_mem_AWREADY),
+    .AWADDR(m_axi_out_mem_AWADDR),
+    .AWID(m_axi_out_mem_AWID),
+    .AWLEN(m_axi_out_mem_AWLEN),
+    .AWSIZE(m_axi_out_mem_AWSIZE),
+    .AWBURST(m_axi_out_mem_AWBURST),
+    .AWLOCK(m_axi_out_mem_AWLOCK),
+    .AWCACHE(m_axi_out_mem_AWCACHE),
+    .AWPROT(m_axi_out_mem_AWPROT),
+    .AWQOS(m_axi_out_mem_AWQOS),
+    .AWREGION(m_axi_out_mem_AWREGION),
+    .AWUSER(m_axi_out_mem_AWUSER),
+    .WVALID(m_axi_out_mem_WVALID),
+    .WREADY(m_axi_out_mem_WREADY),
+    .WDATA(m_axi_out_mem_WDATA),
+    .WSTRB(m_axi_out_mem_WSTRB),
+    .WLAST(m_axi_out_mem_WLAST),
+    .WID(m_axi_out_mem_WID),
+    .WUSER(m_axi_out_mem_WUSER),
+    .ARVALID(m_axi_out_mem_ARVALID),
+    .ARREADY(m_axi_out_mem_ARREADY),
+    .ARADDR(m_axi_out_mem_ARADDR),
+    .ARID(m_axi_out_mem_ARID),
+    .ARLEN(m_axi_out_mem_ARLEN),
+    .ARSIZE(m_axi_out_mem_ARSIZE),
+    .ARBURST(m_axi_out_mem_ARBURST),
+    .ARLOCK(m_axi_out_mem_ARLOCK),
+    .ARCACHE(m_axi_out_mem_ARCACHE),
+    .ARPROT(m_axi_out_mem_ARPROT),
+    .ARQOS(m_axi_out_mem_ARQOS),
+    .ARREGION(m_axi_out_mem_ARREGION),
+    .ARUSER(m_axi_out_mem_ARUSER),
+    .RVALID(m_axi_out_mem_RVALID),
+    .RREADY(m_axi_out_mem_RREADY),
+    .RDATA(m_axi_out_mem_RDATA),
+    .RLAST(m_axi_out_mem_RLAST),
+    .RID(m_axi_out_mem_RID),
+    .RUSER(m_axi_out_mem_RUSER),
+    .RRESP(m_axi_out_mem_RRESP),
+    .BVALID(m_axi_out_mem_BVALID),
+    .BREADY(m_axi_out_mem_BREADY),
+    .BRESP(m_axi_out_mem_BRESP),
+    .BID(m_axi_out_mem_BID),
+    .BUSER(m_axi_out_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(1'b0),
+    .I_ARREADY(out_mem_ARREADY),
+    .I_ARADDR(32'd0),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd0),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(out_mem_RVALID),
+    .I_RREADY(1'b0),
+    .I_RDATA(out_mem_RDATA),
+    .I_RID(out_mem_RID),
+    .I_RUSER(out_mem_RUSER),
+    .I_RRESP(out_mem_RRESP),
+    .I_RLAST(out_mem_RLAST),
+    .I_AWVALID(out_mem_AWVALID),
+    .I_AWREADY(out_mem_AWREADY),
+    .I_AWADDR(out_mem_addr_reg_4620),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd4096),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(out_mem_WVALID),
+    .I_WREADY(out_mem_WREADY),
+    .I_WDATA(out_loc_load_reg_5563),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd15),
+    .I_BVALID(out_mem_BVALID),
+    .I_BREADY(out_mem_BREADY),
+    .I_BRESP(out_mem_BRESP),
+    .I_BID(out_mem_BID),
+    .I_BUSER(out_mem_BUSER)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_0_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_0_address0),
+    .ce0(in1_loc_0_ce0),
+    .we0(in1_loc_0_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_0_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_1_address0),
+    .ce0(in1_loc_1_ce0),
+    .we0(in1_loc_1_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_1_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_2_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_2_address0),
+    .ce0(in1_loc_2_ce0),
+    .we0(in1_loc_2_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_2_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_3_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_3_address0),
+    .ce0(in1_loc_3_ce0),
+    .we0(in1_loc_3_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_3_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_4_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_4_address0),
+    .ce0(in1_loc_4_ce0),
+    .we0(in1_loc_4_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_4_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_5_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_5_address0),
+    .ce0(in1_loc_5_ce0),
+    .we0(in1_loc_5_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_5_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_6_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_6_address0),
+    .ce0(in1_loc_6_ce0),
+    .we0(in1_loc_6_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_6_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_7_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_7_address0),
+    .ce0(in1_loc_7_ce0),
+    .we0(in1_loc_7_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_7_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_8_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_8_address0),
+    .ce0(in1_loc_8_ce0),
+    .we0(in1_loc_8_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_8_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_9_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_9_address0),
+    .ce0(in1_loc_9_ce0),
+    .we0(in1_loc_9_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_9_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_10_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_10_address0),
+    .ce0(in1_loc_10_ce0),
+    .we0(in1_loc_10_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_10_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_11_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_11_address0),
+    .ce0(in1_loc_11_ce0),
+    .we0(in1_loc_11_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_11_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_12_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_12_address0),
+    .ce0(in1_loc_12_ce0),
+    .we0(in1_loc_12_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_12_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_13_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_13_address0),
+    .ce0(in1_loc_13_ce0),
+    .we0(in1_loc_13_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_13_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_14_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_14_address0),
+    .ce0(in1_loc_14_ce0),
+    .we0(in1_loc_14_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_14_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_15_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_15_address0),
+    .ce0(in1_loc_15_ce0),
+    .we0(in1_loc_15_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_15_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_16_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_16_address0),
+    .ce0(in1_loc_16_ce0),
+    .we0(in1_loc_16_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_16_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_17_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_17_address0),
+    .ce0(in1_loc_17_ce0),
+    .we0(in1_loc_17_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_17_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_18_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_18_address0),
+    .ce0(in1_loc_18_ce0),
+    .we0(in1_loc_18_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_18_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_19_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_19_address0),
+    .ce0(in1_loc_19_ce0),
+    .we0(in1_loc_19_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_19_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_20_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_20_address0),
+    .ce0(in1_loc_20_ce0),
+    .we0(in1_loc_20_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_20_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_21_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_21_address0),
+    .ce0(in1_loc_21_ce0),
+    .we0(in1_loc_21_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_21_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_22_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_22_address0),
+    .ce0(in1_loc_22_ce0),
+    .we0(in1_loc_22_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_22_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_23_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_23_address0),
+    .ce0(in1_loc_23_ce0),
+    .we0(in1_loc_23_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_23_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_24_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_24_address0),
+    .ce0(in1_loc_24_ce0),
+    .we0(in1_loc_24_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_24_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_25_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_25_address0),
+    .ce0(in1_loc_25_ce0),
+    .we0(in1_loc_25_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_25_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_26_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_26_address0),
+    .ce0(in1_loc_26_ce0),
+    .we0(in1_loc_26_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_26_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_27_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_27_address0),
+    .ce0(in1_loc_27_ce0),
+    .we0(in1_loc_27_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_27_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_28_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_28_address0),
+    .ce0(in1_loc_28_ce0),
+    .we0(in1_loc_28_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_28_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_29_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_29_address0),
+    .ce0(in1_loc_29_ce0),
+    .we0(in1_loc_29_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_29_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_30_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_30_address0),
+    .ce0(in1_loc_30_ce0),
+    .we0(in1_loc_30_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_30_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_31_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_31_address0),
+    .ce0(in1_loc_31_ce0),
+    .we0(in1_loc_31_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_31_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_32_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_32_address0),
+    .ce0(in1_loc_32_ce0),
+    .we0(in1_loc_32_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_32_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_33_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_33_address0),
+    .ce0(in1_loc_33_ce0),
+    .we0(in1_loc_33_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_33_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_34_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_34_address0),
+    .ce0(in1_loc_34_ce0),
+    .we0(in1_loc_34_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_34_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_35_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_35_address0),
+    .ce0(in1_loc_35_ce0),
+    .we0(in1_loc_35_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_35_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_36_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_36_address0),
+    .ce0(in1_loc_36_ce0),
+    .we0(in1_loc_36_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_36_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_37_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_37_address0),
+    .ce0(in1_loc_37_ce0),
+    .we0(in1_loc_37_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_37_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_38_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_38_address0),
+    .ce0(in1_loc_38_ce0),
+    .we0(in1_loc_38_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_38_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_39_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_39_address0),
+    .ce0(in1_loc_39_ce0),
+    .we0(in1_loc_39_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_39_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_40_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_40_address0),
+    .ce0(in1_loc_40_ce0),
+    .we0(in1_loc_40_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_40_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_41_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_41_address0),
+    .ce0(in1_loc_41_ce0),
+    .we0(in1_loc_41_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_41_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_42_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_42_address0),
+    .ce0(in1_loc_42_ce0),
+    .we0(in1_loc_42_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_42_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_43_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_43_address0),
+    .ce0(in1_loc_43_ce0),
+    .we0(in1_loc_43_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_43_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_44_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_44_address0),
+    .ce0(in1_loc_44_ce0),
+    .we0(in1_loc_44_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_44_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_45_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_45_address0),
+    .ce0(in1_loc_45_ce0),
+    .we0(in1_loc_45_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_45_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_46_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_46_address0),
+    .ce0(in1_loc_46_ce0),
+    .we0(in1_loc_46_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_46_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_47_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_47_address0),
+    .ce0(in1_loc_47_ce0),
+    .we0(in1_loc_47_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_47_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_48_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_48_address0),
+    .ce0(in1_loc_48_ce0),
+    .we0(in1_loc_48_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_48_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_49_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_49_address0),
+    .ce0(in1_loc_49_ce0),
+    .we0(in1_loc_49_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_49_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_50_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_50_address0),
+    .ce0(in1_loc_50_ce0),
+    .we0(in1_loc_50_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_50_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_51_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_51_address0),
+    .ce0(in1_loc_51_ce0),
+    .we0(in1_loc_51_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_51_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_52_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_52_address0),
+    .ce0(in1_loc_52_ce0),
+    .we0(in1_loc_52_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_52_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_53_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_53_address0),
+    .ce0(in1_loc_53_ce0),
+    .we0(in1_loc_53_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_53_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_54_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_54_address0),
+    .ce0(in1_loc_54_ce0),
+    .we0(in1_loc_54_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_54_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_55_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_55_address0),
+    .ce0(in1_loc_55_ce0),
+    .we0(in1_loc_55_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_55_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_56_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_56_address0),
+    .ce0(in1_loc_56_ce0),
+    .we0(in1_loc_56_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_56_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_57_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_57_address0),
+    .ce0(in1_loc_57_ce0),
+    .we0(in1_loc_57_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_57_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_58_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_58_address0),
+    .ce0(in1_loc_58_ce0),
+    .we0(in1_loc_58_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_58_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_59_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_59_address0),
+    .ce0(in1_loc_59_ce0),
+    .we0(in1_loc_59_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_59_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_60_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_60_address0),
+    .ce0(in1_loc_60_ce0),
+    .we0(in1_loc_60_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_60_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_61_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_61_address0),
+    .ce0(in1_loc_61_ce0),
+    .we0(in1_loc_61_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_61_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_62_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_62_address0),
+    .ce0(in1_loc_62_ce0),
+    .we0(in1_loc_62_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_62_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_63_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_63_address0),
+    .ce0(in1_loc_63_ce0),
+    .we0(in1_loc_63_we0),
+    .d0(in1_mem_addr_read_reg_4650),
+    .q0(in1_loc_63_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_0_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_0_address0),
+    .ce0(in2_loc_0_ce0),
+    .we0(in2_loc_0_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_0_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_1_address0),
+    .ce0(in2_loc_1_ce0),
+    .we0(in2_loc_1_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_1_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_2_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_2_address0),
+    .ce0(in2_loc_2_ce0),
+    .we0(in2_loc_2_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_2_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_3_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_3_address0),
+    .ce0(in2_loc_3_ce0),
+    .we0(in2_loc_3_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_3_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_4_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_4_address0),
+    .ce0(in2_loc_4_ce0),
+    .we0(in2_loc_4_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_4_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_5_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_5_address0),
+    .ce0(in2_loc_5_ce0),
+    .we0(in2_loc_5_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_5_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_6_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_6_address0),
+    .ce0(in2_loc_6_ce0),
+    .we0(in2_loc_6_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_6_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_7_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_7_address0),
+    .ce0(in2_loc_7_ce0),
+    .we0(in2_loc_7_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_7_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_8_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_8_address0),
+    .ce0(in2_loc_8_ce0),
+    .we0(in2_loc_8_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_8_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_9_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_9_address0),
+    .ce0(in2_loc_9_ce0),
+    .we0(in2_loc_9_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_9_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_10_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_10_address0),
+    .ce0(in2_loc_10_ce0),
+    .we0(in2_loc_10_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_10_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_11_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_11_address0),
+    .ce0(in2_loc_11_ce0),
+    .we0(in2_loc_11_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_11_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_12_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_12_address0),
+    .ce0(in2_loc_12_ce0),
+    .we0(in2_loc_12_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_12_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_13_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_13_address0),
+    .ce0(in2_loc_13_ce0),
+    .we0(in2_loc_13_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_13_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_14_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_14_address0),
+    .ce0(in2_loc_14_ce0),
+    .we0(in2_loc_14_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_14_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_15_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_15_address0),
+    .ce0(in2_loc_15_ce0),
+    .we0(in2_loc_15_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_15_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_16_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_16_address0),
+    .ce0(in2_loc_16_ce0),
+    .we0(in2_loc_16_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_16_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_17_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_17_address0),
+    .ce0(in2_loc_17_ce0),
+    .we0(in2_loc_17_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_17_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_18_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_18_address0),
+    .ce0(in2_loc_18_ce0),
+    .we0(in2_loc_18_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_18_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_19_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_19_address0),
+    .ce0(in2_loc_19_ce0),
+    .we0(in2_loc_19_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_19_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_20_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_20_address0),
+    .ce0(in2_loc_20_ce0),
+    .we0(in2_loc_20_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_20_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_21_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_21_address0),
+    .ce0(in2_loc_21_ce0),
+    .we0(in2_loc_21_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_21_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_22_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_22_address0),
+    .ce0(in2_loc_22_ce0),
+    .we0(in2_loc_22_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_22_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_23_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_23_address0),
+    .ce0(in2_loc_23_ce0),
+    .we0(in2_loc_23_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_23_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_24_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_24_address0),
+    .ce0(in2_loc_24_ce0),
+    .we0(in2_loc_24_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_24_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_25_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_25_address0),
+    .ce0(in2_loc_25_ce0),
+    .we0(in2_loc_25_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_25_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_26_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_26_address0),
+    .ce0(in2_loc_26_ce0),
+    .we0(in2_loc_26_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_26_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_27_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_27_address0),
+    .ce0(in2_loc_27_ce0),
+    .we0(in2_loc_27_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_27_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_28_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_28_address0),
+    .ce0(in2_loc_28_ce0),
+    .we0(in2_loc_28_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_28_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_29_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_29_address0),
+    .ce0(in2_loc_29_ce0),
+    .we0(in2_loc_29_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_29_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_30_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_30_address0),
+    .ce0(in2_loc_30_ce0),
+    .we0(in2_loc_30_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_30_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_31_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_31_address0),
+    .ce0(in2_loc_31_ce0),
+    .we0(in2_loc_31_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_31_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_32_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_32_address0),
+    .ce0(in2_loc_32_ce0),
+    .we0(in2_loc_32_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_32_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_33_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_33_address0),
+    .ce0(in2_loc_33_ce0),
+    .we0(in2_loc_33_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_33_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_34_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_34_address0),
+    .ce0(in2_loc_34_ce0),
+    .we0(in2_loc_34_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_34_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_35_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_35_address0),
+    .ce0(in2_loc_35_ce0),
+    .we0(in2_loc_35_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_35_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_36_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_36_address0),
+    .ce0(in2_loc_36_ce0),
+    .we0(in2_loc_36_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_36_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_37_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_37_address0),
+    .ce0(in2_loc_37_ce0),
+    .we0(in2_loc_37_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_37_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_38_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_38_address0),
+    .ce0(in2_loc_38_ce0),
+    .we0(in2_loc_38_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_38_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_39_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_39_address0),
+    .ce0(in2_loc_39_ce0),
+    .we0(in2_loc_39_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_39_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_40_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_40_address0),
+    .ce0(in2_loc_40_ce0),
+    .we0(in2_loc_40_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_40_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_41_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_41_address0),
+    .ce0(in2_loc_41_ce0),
+    .we0(in2_loc_41_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_41_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_42_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_42_address0),
+    .ce0(in2_loc_42_ce0),
+    .we0(in2_loc_42_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_42_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_43_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_43_address0),
+    .ce0(in2_loc_43_ce0),
+    .we0(in2_loc_43_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_43_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_44_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_44_address0),
+    .ce0(in2_loc_44_ce0),
+    .we0(in2_loc_44_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_44_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_45_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_45_address0),
+    .ce0(in2_loc_45_ce0),
+    .we0(in2_loc_45_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_45_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_46_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_46_address0),
+    .ce0(in2_loc_46_ce0),
+    .we0(in2_loc_46_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_46_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_47_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_47_address0),
+    .ce0(in2_loc_47_ce0),
+    .we0(in2_loc_47_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_47_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_48_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_48_address0),
+    .ce0(in2_loc_48_ce0),
+    .we0(in2_loc_48_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_48_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_49_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_49_address0),
+    .ce0(in2_loc_49_ce0),
+    .we0(in2_loc_49_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_49_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_50_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_50_address0),
+    .ce0(in2_loc_50_ce0),
+    .we0(in2_loc_50_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_50_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_51_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_51_address0),
+    .ce0(in2_loc_51_ce0),
+    .we0(in2_loc_51_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_51_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_52_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_52_address0),
+    .ce0(in2_loc_52_ce0),
+    .we0(in2_loc_52_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_52_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_53_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_53_address0),
+    .ce0(in2_loc_53_ce0),
+    .we0(in2_loc_53_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_53_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_54_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_54_address0),
+    .ce0(in2_loc_54_ce0),
+    .we0(in2_loc_54_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_54_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_55_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_55_address0),
+    .ce0(in2_loc_55_ce0),
+    .we0(in2_loc_55_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_55_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_56_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_56_address0),
+    .ce0(in2_loc_56_ce0),
+    .we0(in2_loc_56_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_56_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_57_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_57_address0),
+    .ce0(in2_loc_57_ce0),
+    .we0(in2_loc_57_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_57_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_58_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_58_address0),
+    .ce0(in2_loc_58_ce0),
+    .we0(in2_loc_58_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_58_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_59_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_59_address0),
+    .ce0(in2_loc_59_ce0),
+    .we0(in2_loc_59_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_59_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_60_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_60_address0),
+    .ce0(in2_loc_60_ce0),
+    .we0(in2_loc_60_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_60_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_61_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_61_address0),
+    .ce0(in2_loc_61_ce0),
+    .we0(in2_loc_61_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_61_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_62_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_62_address0),
+    .ce0(in2_loc_62_ce0),
+    .we0(in2_loc_62_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_62_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_63_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_63_address0),
+    .ce0(in2_loc_63_ce0),
+    .we0(in2_loc_63_we0),
+    .d0(in2_mem_addr_read_reg_4736),
+    .q0(in2_loc_63_q0)
+);
+
+mmult_out_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+out_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(out_loc_address0),
+    .ce0(out_loc_ce0),
+    .q0(out_loc_q0),
+    .address1(out_loc_addr_reg_5143_pp2_iter1_reg),
+    .ce1(out_loc_ce1),
+    .we1(out_loc_we1),
+    .d1(out_loc_d1)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter0 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state9) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_enable_reg_pp0_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp0_exit_iter0_state9)) begin
+                ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state9);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter0 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp1_stage0_subdone) & (1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_condition_pp1_exit_iter0_state19))) begin
+            ap_enable_reg_pp1_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp1_exit_iter0_state19)) begin
+                ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_condition_pp2_exit_iter0_state23) & (1'b0 == ap_block_pp2_stage0_subdone))) begin
+            ap_enable_reg_pp2_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state22)) begin
+            ap_enable_reg_pp2_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp2_exit_iter0_state23)) begin
+                ap_enable_reg_pp2_iter1 <= (1'b1 ^ ap_condition_pp2_exit_iter0_state23);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state22)) begin
+            ap_enable_reg_pp2_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp3_stage0) & (1'b1 == ap_condition_pp3_exit_iter0_state27) & (1'b0 == ap_block_pp3_stage0_subdone))) begin
+            ap_enable_reg_pp3_iter0 <= 1'b0;
+        end else if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state26))) begin
+            ap_enable_reg_pp3_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp3_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp3_exit_iter0_state27)) begin
+                ap_enable_reg_pp3_iter1 <= (1'b1 ^ ap_condition_pp3_exit_iter0_state27);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp3_iter1 <= ap_enable_reg_pp3_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp3_stage0_subdone)) begin
+            ap_enable_reg_pp3_iter2 <= ap_enable_reg_pp3_iter1;
+        end else if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state26))) begin
+            ap_enable_reg_pp3_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4809 == 1'd0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        i_0_reg_3329 <= select_ln31_1_reg_4818;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        i_0_reg_3329 <= 31'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3615_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        indvar_flatten_reg_3318 <= add_ln31_fu_3620_p2;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        indvar_flatten_reg_3318 <= 64'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3615_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        j_0_reg_3340 <= j_fu_3816_p2;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        j_0_reg_3340 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_fu_3420_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        phi_ln27_reg_3296 <= add_ln27_fu_3426_p2;
+    end else if ((1'b1 == ap_CS_fsm_state8)) begin
+        phi_ln27_reg_3296 <= 13'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        phi_ln28_reg_3307 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_fu_3513_p2 == 1'd0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        phi_ln28_reg_3307 <= add_ln28_fu_3519_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state26))) begin
+        phi_ln42_reg_3351 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_fu_4576_p2 == 1'd0) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        phi_ln42_reg_3351 <= add_ln42_fu_4582_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4809 == 1'd0) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        add_ln38_12_reg_5504 <= add_ln38_12_fu_4248_p2;
+        add_ln38_21_reg_5509 <= add_ln38_21_fu_4290_p2;
+        add_ln38_28_reg_5514 <= add_ln38_28_fu_4332_p2;
+        add_ln38_37_reg_5519 <= add_ln38_37_fu_4374_p2;
+        add_ln38_3_reg_5489 <= add_ln38_3_fu_4206_p2;
+        add_ln38_40_reg_5524 <= add_ln38_40_fu_4392_p2;
+        add_ln38_43_reg_5529 <= add_ln38_43_fu_4410_p2;
+        add_ln38_4_reg_5494 <= add_ln38_4_fu_4212_p2;
+        add_ln38_52_reg_5534 <= add_ln38_52_fu_4452_p2;
+        add_ln38_55_reg_5539 <= add_ln38_55_fu_4470_p2;
+        add_ln38_59_reg_5544 <= add_ln38_59_fu_4494_p2;
+        add_ln38_9_reg_5499 <= add_ln38_9_fu_4230_p2;
+        mul_ln38_1_reg_5479 <= mul_ln38_1_fu_3828_p2;
+        mul_ln38_2_reg_5484 <= mul_ln38_2_fu_3834_p2;
+        mul_ln38_reg_5474 <= mul_ln38_fu_3822_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        dim_read_reg_4593 <= dim;
+        in3_reg_4609 <= {{in1[31:2]}};
+        in_reg_4604 <= {{in2[31:2]}};
+        out5_reg_4599 <= {{out_r[31:2]}};
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        icmp_ln31_reg_4809 <= icmp_ln31_fu_3615_p2;
+        icmp_ln31_reg_4809_pp2_iter1_reg <= icmp_ln31_reg_4809;
+        out_loc_addr_reg_5143_pp2_iter1_reg <= out_loc_addr_reg_5143;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp3_stage0_11001) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        icmp_ln42_reg_5549 <= icmp_ln42_fu_4576_p2;
+        icmp_ln42_reg_5549_pp3_iter1_reg <= icmp_ln42_reg_5549;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_addr_read_reg_4650 <= in1_mem_RDATA;
+        lshr_ln_reg_4641_pp0_iter1_reg <= lshr_ln_reg_4641;
+        trunc_ln27_reg_4646_pp0_iter1_reg <= trunc_ln27_reg_4646;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_addr_read_reg_4736 <= in2_mem_RDATA;
+        trunc_ln1_reg_4732_pp1_iter1_reg <= trunc_ln1_reg_4732;
+        trunc_ln28_reg_4727_pp1_iter1_reg <= trunc_ln28_reg_4727;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        in2_mem_addr_reg_4626[29 : 0] <= empty_7_fu_3411_p1[29 : 0];
+        out_mem_addr_reg_4620[29 : 0] <= empty_fu_3402_p1[29 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_fu_3420_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        lshr_ln_reg_4641 <= {{phi_ln27_reg_3296[12:6]}};
+        trunc_ln27_reg_4646 <= trunc_ln27_fu_3442_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state22)) begin
+        mul_ln31_reg_4804 <= mul_ln31_fu_3609_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3615_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        out_loc_addr_reg_5143 <= zext_ln38_fu_3811_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_reg_5549 == 1'd0) & (ap_enable_reg_pp3_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        out_loc_load_reg_5563 <= out_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3615_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        select_ln31_1_reg_4818 <= select_ln31_1_fu_3645_p3;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_fu_3513_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        trunc_ln1_reg_4732 <= {{phi_ln28_reg_3307[11:6]}};
+        trunc_ln28_reg_4727 <= trunc_ln28_fu_3525_p1;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln27_fu_3420_p2 == 1'd1)) begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b1;
+    end else begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln28_fu_3513_p2 == 1'd1)) begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b1;
+    end else begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln31_fu_3615_p2 == 1'd1)) begin
+        ap_condition_pp2_exit_iter0_state23 = 1'b1;
+    end else begin
+        ap_condition_pp2_exit_iter0_state23 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln42_fu_4576_p2 == 1'd1)) begin
+        ap_condition_pp3_exit_iter0_state27 = 1'b1;
+    end else begin
+        ap_condition_pp3_exit_iter0_state27 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b0))) begin
+        ap_idle_pp1 = 1'b1;
+    end else begin
+        ap_idle_pp1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter2 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b0))) begin
+        ap_idle_pp2 = 1'b1;
+    end else begin
+        ap_idle_pp2 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter0 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b0))) begin
+        ap_idle_pp3 = 1'b1;
+    end else begin
+        ap_idle_pp3 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln31_reg_4809 == 1'd0) & (1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        ap_phi_mux_i_0_phi_fu_3333_p4 = select_ln31_1_reg_4818;
+    end else begin
+        ap_phi_mux_i_0_phi_fu_3333_p4 = i_0_reg_3329;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_0_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_0_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_0_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_0_ce0 = 1'b1;
+    end else begin
+        in1_loc_0_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_0_we0 = 1'b1;
+    end else begin
+        in1_loc_0_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_10_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_10_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_10_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_10_ce0 = 1'b1;
+    end else begin
+        in1_loc_10_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd10) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_10_we0 = 1'b1;
+    end else begin
+        in1_loc_10_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_11_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_11_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_11_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_11_ce0 = 1'b1;
+    end else begin
+        in1_loc_11_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd11) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_11_we0 = 1'b1;
+    end else begin
+        in1_loc_11_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_12_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_12_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_12_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_12_ce0 = 1'b1;
+    end else begin
+        in1_loc_12_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd12) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_12_we0 = 1'b1;
+    end else begin
+        in1_loc_12_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_13_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_13_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_13_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_13_ce0 = 1'b1;
+    end else begin
+        in1_loc_13_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd13) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_13_we0 = 1'b1;
+    end else begin
+        in1_loc_13_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_14_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_14_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_14_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_14_ce0 = 1'b1;
+    end else begin
+        in1_loc_14_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd14) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_14_we0 = 1'b1;
+    end else begin
+        in1_loc_14_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_15_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_15_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_15_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_15_ce0 = 1'b1;
+    end else begin
+        in1_loc_15_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd15) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_15_we0 = 1'b1;
+    end else begin
+        in1_loc_15_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_16_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_16_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_16_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_16_ce0 = 1'b1;
+    end else begin
+        in1_loc_16_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd16) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_16_we0 = 1'b1;
+    end else begin
+        in1_loc_16_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_17_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_17_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_17_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_17_ce0 = 1'b1;
+    end else begin
+        in1_loc_17_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd17) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_17_we0 = 1'b1;
+    end else begin
+        in1_loc_17_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_18_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_18_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_18_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_18_ce0 = 1'b1;
+    end else begin
+        in1_loc_18_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd18) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_18_we0 = 1'b1;
+    end else begin
+        in1_loc_18_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_19_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_19_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_19_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_19_ce0 = 1'b1;
+    end else begin
+        in1_loc_19_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd19) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_19_we0 = 1'b1;
+    end else begin
+        in1_loc_19_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_1_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_1_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_1_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_1_ce0 = 1'b1;
+    end else begin
+        in1_loc_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_1_we0 = 1'b1;
+    end else begin
+        in1_loc_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_20_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_20_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_20_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_20_ce0 = 1'b1;
+    end else begin
+        in1_loc_20_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd20) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_20_we0 = 1'b1;
+    end else begin
+        in1_loc_20_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_21_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_21_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_21_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_21_ce0 = 1'b1;
+    end else begin
+        in1_loc_21_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd21) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_21_we0 = 1'b1;
+    end else begin
+        in1_loc_21_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_22_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_22_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_22_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_22_ce0 = 1'b1;
+    end else begin
+        in1_loc_22_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd22) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_22_we0 = 1'b1;
+    end else begin
+        in1_loc_22_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_23_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_23_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_23_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_23_ce0 = 1'b1;
+    end else begin
+        in1_loc_23_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd23) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_23_we0 = 1'b1;
+    end else begin
+        in1_loc_23_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_24_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_24_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_24_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_24_ce0 = 1'b1;
+    end else begin
+        in1_loc_24_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd24) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_24_we0 = 1'b1;
+    end else begin
+        in1_loc_24_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_25_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_25_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_25_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_25_ce0 = 1'b1;
+    end else begin
+        in1_loc_25_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd25) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_25_we0 = 1'b1;
+    end else begin
+        in1_loc_25_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_26_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_26_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_26_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_26_ce0 = 1'b1;
+    end else begin
+        in1_loc_26_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd26) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_26_we0 = 1'b1;
+    end else begin
+        in1_loc_26_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_27_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_27_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_27_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_27_ce0 = 1'b1;
+    end else begin
+        in1_loc_27_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd27) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_27_we0 = 1'b1;
+    end else begin
+        in1_loc_27_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_28_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_28_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_28_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_28_ce0 = 1'b1;
+    end else begin
+        in1_loc_28_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd28) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_28_we0 = 1'b1;
+    end else begin
+        in1_loc_28_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_29_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_29_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_29_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_29_ce0 = 1'b1;
+    end else begin
+        in1_loc_29_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd29) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_29_we0 = 1'b1;
+    end else begin
+        in1_loc_29_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_2_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_2_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_2_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_2_ce0 = 1'b1;
+    end else begin
+        in1_loc_2_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd2) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_2_we0 = 1'b1;
+    end else begin
+        in1_loc_2_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_30_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_30_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_30_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_30_ce0 = 1'b1;
+    end else begin
+        in1_loc_30_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd30) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_30_we0 = 1'b1;
+    end else begin
+        in1_loc_30_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_31_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_31_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_31_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_31_ce0 = 1'b1;
+    end else begin
+        in1_loc_31_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd31) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_31_we0 = 1'b1;
+    end else begin
+        in1_loc_31_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_32_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_32_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_32_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_32_ce0 = 1'b1;
+    end else begin
+        in1_loc_32_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd32) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_32_we0 = 1'b1;
+    end else begin
+        in1_loc_32_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_33_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_33_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_33_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_33_ce0 = 1'b1;
+    end else begin
+        in1_loc_33_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd33) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_33_we0 = 1'b1;
+    end else begin
+        in1_loc_33_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_34_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_34_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_34_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_34_ce0 = 1'b1;
+    end else begin
+        in1_loc_34_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd34) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_34_we0 = 1'b1;
+    end else begin
+        in1_loc_34_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_35_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_35_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_35_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_35_ce0 = 1'b1;
+    end else begin
+        in1_loc_35_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd35) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_35_we0 = 1'b1;
+    end else begin
+        in1_loc_35_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_36_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_36_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_36_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_36_ce0 = 1'b1;
+    end else begin
+        in1_loc_36_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd36) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_36_we0 = 1'b1;
+    end else begin
+        in1_loc_36_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_37_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_37_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_37_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_37_ce0 = 1'b1;
+    end else begin
+        in1_loc_37_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd37) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_37_we0 = 1'b1;
+    end else begin
+        in1_loc_37_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_38_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_38_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_38_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_38_ce0 = 1'b1;
+    end else begin
+        in1_loc_38_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd38) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_38_we0 = 1'b1;
+    end else begin
+        in1_loc_38_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_39_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_39_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_39_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_39_ce0 = 1'b1;
+    end else begin
+        in1_loc_39_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd39) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_39_we0 = 1'b1;
+    end else begin
+        in1_loc_39_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_3_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_3_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_3_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_3_ce0 = 1'b1;
+    end else begin
+        in1_loc_3_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd3) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_3_we0 = 1'b1;
+    end else begin
+        in1_loc_3_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_40_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_40_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_40_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_40_ce0 = 1'b1;
+    end else begin
+        in1_loc_40_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd40) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_40_we0 = 1'b1;
+    end else begin
+        in1_loc_40_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_41_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_41_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_41_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_41_ce0 = 1'b1;
+    end else begin
+        in1_loc_41_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd41) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_41_we0 = 1'b1;
+    end else begin
+        in1_loc_41_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_42_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_42_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_42_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_42_ce0 = 1'b1;
+    end else begin
+        in1_loc_42_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd42) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_42_we0 = 1'b1;
+    end else begin
+        in1_loc_42_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_43_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_43_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_43_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_43_ce0 = 1'b1;
+    end else begin
+        in1_loc_43_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd43) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_43_we0 = 1'b1;
+    end else begin
+        in1_loc_43_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_44_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_44_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_44_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_44_ce0 = 1'b1;
+    end else begin
+        in1_loc_44_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd44) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_44_we0 = 1'b1;
+    end else begin
+        in1_loc_44_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_45_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_45_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_45_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_45_ce0 = 1'b1;
+    end else begin
+        in1_loc_45_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd45) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_45_we0 = 1'b1;
+    end else begin
+        in1_loc_45_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_46_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_46_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_46_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_46_ce0 = 1'b1;
+    end else begin
+        in1_loc_46_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd46) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_46_we0 = 1'b1;
+    end else begin
+        in1_loc_46_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_47_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_47_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_47_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_47_ce0 = 1'b1;
+    end else begin
+        in1_loc_47_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd47) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_47_we0 = 1'b1;
+    end else begin
+        in1_loc_47_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_48_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_48_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_48_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_48_ce0 = 1'b1;
+    end else begin
+        in1_loc_48_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd48) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_48_we0 = 1'b1;
+    end else begin
+        in1_loc_48_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_49_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_49_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_49_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_49_ce0 = 1'b1;
+    end else begin
+        in1_loc_49_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd49) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_49_we0 = 1'b1;
+    end else begin
+        in1_loc_49_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_4_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_4_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_4_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_4_ce0 = 1'b1;
+    end else begin
+        in1_loc_4_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd4) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_4_we0 = 1'b1;
+    end else begin
+        in1_loc_4_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_50_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_50_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_50_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_50_ce0 = 1'b1;
+    end else begin
+        in1_loc_50_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd50) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_50_we0 = 1'b1;
+    end else begin
+        in1_loc_50_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_51_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_51_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_51_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_51_ce0 = 1'b1;
+    end else begin
+        in1_loc_51_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd51) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_51_we0 = 1'b1;
+    end else begin
+        in1_loc_51_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_52_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_52_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_52_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_52_ce0 = 1'b1;
+    end else begin
+        in1_loc_52_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd52) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_52_we0 = 1'b1;
+    end else begin
+        in1_loc_52_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_53_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_53_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_53_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_53_ce0 = 1'b1;
+    end else begin
+        in1_loc_53_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd53) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_53_we0 = 1'b1;
+    end else begin
+        in1_loc_53_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_54_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_54_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_54_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_54_ce0 = 1'b1;
+    end else begin
+        in1_loc_54_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd54) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_54_we0 = 1'b1;
+    end else begin
+        in1_loc_54_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_55_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_55_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_55_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_55_ce0 = 1'b1;
+    end else begin
+        in1_loc_55_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd55) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_55_we0 = 1'b1;
+    end else begin
+        in1_loc_55_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_56_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_56_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_56_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_56_ce0 = 1'b1;
+    end else begin
+        in1_loc_56_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd56) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_56_we0 = 1'b1;
+    end else begin
+        in1_loc_56_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_57_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_57_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_57_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_57_ce0 = 1'b1;
+    end else begin
+        in1_loc_57_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd57) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_57_we0 = 1'b1;
+    end else begin
+        in1_loc_57_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_58_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_58_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_58_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_58_ce0 = 1'b1;
+    end else begin
+        in1_loc_58_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd58) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_58_we0 = 1'b1;
+    end else begin
+        in1_loc_58_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_59_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_59_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_59_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_59_ce0 = 1'b1;
+    end else begin
+        in1_loc_59_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd59) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_59_we0 = 1'b1;
+    end else begin
+        in1_loc_59_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_5_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_5_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_5_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_5_ce0 = 1'b1;
+    end else begin
+        in1_loc_5_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd5) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_5_we0 = 1'b1;
+    end else begin
+        in1_loc_5_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_60_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_60_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_60_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_60_ce0 = 1'b1;
+    end else begin
+        in1_loc_60_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd60) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_60_we0 = 1'b1;
+    end else begin
+        in1_loc_60_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_61_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_61_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_61_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_61_ce0 = 1'b1;
+    end else begin
+        in1_loc_61_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd61) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_61_we0 = 1'b1;
+    end else begin
+        in1_loc_61_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_62_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_62_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_62_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_62_ce0 = 1'b1;
+    end else begin
+        in1_loc_62_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd62) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_62_we0 = 1'b1;
+    end else begin
+        in1_loc_62_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_63_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_63_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_63_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_63_ce0 = 1'b1;
+    end else begin
+        in1_loc_63_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd63) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_63_we0 = 1'b1;
+    end else begin
+        in1_loc_63_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_6_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_6_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_6_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_6_ce0 = 1'b1;
+    end else begin
+        in1_loc_6_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd6) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_6_we0 = 1'b1;
+    end else begin
+        in1_loc_6_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_7_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_7_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_7_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_7_ce0 = 1'b1;
+    end else begin
+        in1_loc_7_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd7) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_7_we0 = 1'b1;
+    end else begin
+        in1_loc_7_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_8_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_8_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_8_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_8_ce0 = 1'b1;
+    end else begin
+        in1_loc_8_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd8) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_8_we0 = 1'b1;
+    end else begin
+        in1_loc_8_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_9_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_9_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_9_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_9_ce0 = 1'b1;
+    end else begin
+        in1_loc_9_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4646_pp0_iter1_reg == 6'd9) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_9_we0 = 1'b1;
+    end else begin
+        in1_loc_9_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        in1_mem_ARVALID = 1'b1;
+    end else begin
+        in1_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_RREADY = 1'b1;
+    end else begin
+        in1_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        in1_mem_blk_n_AR = m_axi_in1_mem_ARREADY;
+    end else begin
+        in1_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_blk_n_R = m_axi_in1_mem_RVALID;
+    end else begin
+        in1_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_0_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_0_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_0_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_0_ce0 = 1'b1;
+    end else begin
+        in2_loc_0_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_0_we0 = 1'b1;
+    end else begin
+        in2_loc_0_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_10_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_10_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_10_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_10_ce0 = 1'b1;
+    end else begin
+        in2_loc_10_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd10) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_10_we0 = 1'b1;
+    end else begin
+        in2_loc_10_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_11_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_11_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_11_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_11_ce0 = 1'b1;
+    end else begin
+        in2_loc_11_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd11) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_11_we0 = 1'b1;
+    end else begin
+        in2_loc_11_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_12_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_12_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_12_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_12_ce0 = 1'b1;
+    end else begin
+        in2_loc_12_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd12) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_12_we0 = 1'b1;
+    end else begin
+        in2_loc_12_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_13_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_13_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_13_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_13_ce0 = 1'b1;
+    end else begin
+        in2_loc_13_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd13) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_13_we0 = 1'b1;
+    end else begin
+        in2_loc_13_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_14_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_14_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_14_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_14_ce0 = 1'b1;
+    end else begin
+        in2_loc_14_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd14) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_14_we0 = 1'b1;
+    end else begin
+        in2_loc_14_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_15_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_15_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_15_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_15_ce0 = 1'b1;
+    end else begin
+        in2_loc_15_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd15) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_15_we0 = 1'b1;
+    end else begin
+        in2_loc_15_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_16_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_16_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_16_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_16_ce0 = 1'b1;
+    end else begin
+        in2_loc_16_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd16) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_16_we0 = 1'b1;
+    end else begin
+        in2_loc_16_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_17_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_17_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_17_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_17_ce0 = 1'b1;
+    end else begin
+        in2_loc_17_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd17) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_17_we0 = 1'b1;
+    end else begin
+        in2_loc_17_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_18_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_18_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_18_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_18_ce0 = 1'b1;
+    end else begin
+        in2_loc_18_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd18) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_18_we0 = 1'b1;
+    end else begin
+        in2_loc_18_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_19_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_19_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_19_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_19_ce0 = 1'b1;
+    end else begin
+        in2_loc_19_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd19) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_19_we0 = 1'b1;
+    end else begin
+        in2_loc_19_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_1_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_1_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_1_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_1_ce0 = 1'b1;
+    end else begin
+        in2_loc_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd1) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_1_we0 = 1'b1;
+    end else begin
+        in2_loc_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_20_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_20_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_20_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_20_ce0 = 1'b1;
+    end else begin
+        in2_loc_20_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd20) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_20_we0 = 1'b1;
+    end else begin
+        in2_loc_20_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_21_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_21_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_21_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_21_ce0 = 1'b1;
+    end else begin
+        in2_loc_21_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd21) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_21_we0 = 1'b1;
+    end else begin
+        in2_loc_21_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_22_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_22_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_22_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_22_ce0 = 1'b1;
+    end else begin
+        in2_loc_22_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd22) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_22_we0 = 1'b1;
+    end else begin
+        in2_loc_22_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_23_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_23_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_23_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_23_ce0 = 1'b1;
+    end else begin
+        in2_loc_23_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd23) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_23_we0 = 1'b1;
+    end else begin
+        in2_loc_23_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_24_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_24_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_24_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_24_ce0 = 1'b1;
+    end else begin
+        in2_loc_24_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd24) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_24_we0 = 1'b1;
+    end else begin
+        in2_loc_24_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_25_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_25_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_25_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_25_ce0 = 1'b1;
+    end else begin
+        in2_loc_25_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd25) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_25_we0 = 1'b1;
+    end else begin
+        in2_loc_25_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_26_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_26_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_26_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_26_ce0 = 1'b1;
+    end else begin
+        in2_loc_26_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd26) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_26_we0 = 1'b1;
+    end else begin
+        in2_loc_26_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_27_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_27_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_27_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_27_ce0 = 1'b1;
+    end else begin
+        in2_loc_27_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd27) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_27_we0 = 1'b1;
+    end else begin
+        in2_loc_27_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_28_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_28_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_28_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_28_ce0 = 1'b1;
+    end else begin
+        in2_loc_28_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd28) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_28_we0 = 1'b1;
+    end else begin
+        in2_loc_28_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_29_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_29_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_29_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_29_ce0 = 1'b1;
+    end else begin
+        in2_loc_29_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd29) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_29_we0 = 1'b1;
+    end else begin
+        in2_loc_29_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_2_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_2_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_2_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_2_ce0 = 1'b1;
+    end else begin
+        in2_loc_2_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd2) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_2_we0 = 1'b1;
+    end else begin
+        in2_loc_2_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_30_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_30_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_30_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_30_ce0 = 1'b1;
+    end else begin
+        in2_loc_30_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd30) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_30_we0 = 1'b1;
+    end else begin
+        in2_loc_30_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_31_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_31_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_31_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_31_ce0 = 1'b1;
+    end else begin
+        in2_loc_31_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd31) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_31_we0 = 1'b1;
+    end else begin
+        in2_loc_31_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_32_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_32_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_32_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_32_ce0 = 1'b1;
+    end else begin
+        in2_loc_32_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd32) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_32_we0 = 1'b1;
+    end else begin
+        in2_loc_32_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_33_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_33_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_33_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_33_ce0 = 1'b1;
+    end else begin
+        in2_loc_33_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd33) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_33_we0 = 1'b1;
+    end else begin
+        in2_loc_33_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_34_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_34_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_34_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_34_ce0 = 1'b1;
+    end else begin
+        in2_loc_34_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd34) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_34_we0 = 1'b1;
+    end else begin
+        in2_loc_34_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_35_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_35_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_35_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_35_ce0 = 1'b1;
+    end else begin
+        in2_loc_35_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd35) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_35_we0 = 1'b1;
+    end else begin
+        in2_loc_35_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_36_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_36_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_36_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_36_ce0 = 1'b1;
+    end else begin
+        in2_loc_36_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd36) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_36_we0 = 1'b1;
+    end else begin
+        in2_loc_36_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_37_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_37_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_37_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_37_ce0 = 1'b1;
+    end else begin
+        in2_loc_37_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd37) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_37_we0 = 1'b1;
+    end else begin
+        in2_loc_37_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_38_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_38_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_38_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_38_ce0 = 1'b1;
+    end else begin
+        in2_loc_38_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd38) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_38_we0 = 1'b1;
+    end else begin
+        in2_loc_38_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_39_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_39_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_39_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_39_ce0 = 1'b1;
+    end else begin
+        in2_loc_39_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd39) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_39_we0 = 1'b1;
+    end else begin
+        in2_loc_39_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_3_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_3_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_3_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_3_ce0 = 1'b1;
+    end else begin
+        in2_loc_3_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd3) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_3_we0 = 1'b1;
+    end else begin
+        in2_loc_3_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_40_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_40_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_40_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_40_ce0 = 1'b1;
+    end else begin
+        in2_loc_40_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd40) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_40_we0 = 1'b1;
+    end else begin
+        in2_loc_40_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_41_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_41_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_41_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_41_ce0 = 1'b1;
+    end else begin
+        in2_loc_41_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd41) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_41_we0 = 1'b1;
+    end else begin
+        in2_loc_41_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_42_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_42_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_42_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_42_ce0 = 1'b1;
+    end else begin
+        in2_loc_42_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd42) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_42_we0 = 1'b1;
+    end else begin
+        in2_loc_42_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_43_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_43_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_43_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_43_ce0 = 1'b1;
+    end else begin
+        in2_loc_43_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd43) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_43_we0 = 1'b1;
+    end else begin
+        in2_loc_43_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_44_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_44_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_44_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_44_ce0 = 1'b1;
+    end else begin
+        in2_loc_44_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd44) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_44_we0 = 1'b1;
+    end else begin
+        in2_loc_44_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_45_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_45_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_45_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_45_ce0 = 1'b1;
+    end else begin
+        in2_loc_45_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd45) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_45_we0 = 1'b1;
+    end else begin
+        in2_loc_45_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_46_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_46_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_46_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_46_ce0 = 1'b1;
+    end else begin
+        in2_loc_46_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd46) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_46_we0 = 1'b1;
+    end else begin
+        in2_loc_46_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_47_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_47_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_47_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_47_ce0 = 1'b1;
+    end else begin
+        in2_loc_47_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd47) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_47_we0 = 1'b1;
+    end else begin
+        in2_loc_47_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_48_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_48_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_48_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_48_ce0 = 1'b1;
+    end else begin
+        in2_loc_48_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd48) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_48_we0 = 1'b1;
+    end else begin
+        in2_loc_48_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_49_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_49_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_49_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_49_ce0 = 1'b1;
+    end else begin
+        in2_loc_49_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd49) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_49_we0 = 1'b1;
+    end else begin
+        in2_loc_49_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_4_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_4_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_4_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_4_ce0 = 1'b1;
+    end else begin
+        in2_loc_4_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd4) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_4_we0 = 1'b1;
+    end else begin
+        in2_loc_4_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_50_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_50_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_50_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_50_ce0 = 1'b1;
+    end else begin
+        in2_loc_50_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd50) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_50_we0 = 1'b1;
+    end else begin
+        in2_loc_50_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_51_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_51_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_51_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_51_ce0 = 1'b1;
+    end else begin
+        in2_loc_51_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd51) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_51_we0 = 1'b1;
+    end else begin
+        in2_loc_51_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_52_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_52_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_52_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_52_ce0 = 1'b1;
+    end else begin
+        in2_loc_52_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd52) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_52_we0 = 1'b1;
+    end else begin
+        in2_loc_52_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_53_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_53_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_53_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_53_ce0 = 1'b1;
+    end else begin
+        in2_loc_53_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd53) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_53_we0 = 1'b1;
+    end else begin
+        in2_loc_53_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_54_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_54_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_54_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_54_ce0 = 1'b1;
+    end else begin
+        in2_loc_54_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd54) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_54_we0 = 1'b1;
+    end else begin
+        in2_loc_54_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_55_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_55_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_55_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_55_ce0 = 1'b1;
+    end else begin
+        in2_loc_55_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd55) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_55_we0 = 1'b1;
+    end else begin
+        in2_loc_55_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_56_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_56_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_56_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_56_ce0 = 1'b1;
+    end else begin
+        in2_loc_56_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd56) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_56_we0 = 1'b1;
+    end else begin
+        in2_loc_56_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_57_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_57_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_57_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_57_ce0 = 1'b1;
+    end else begin
+        in2_loc_57_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd57) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_57_we0 = 1'b1;
+    end else begin
+        in2_loc_57_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_58_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_58_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_58_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_58_ce0 = 1'b1;
+    end else begin
+        in2_loc_58_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd58) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_58_we0 = 1'b1;
+    end else begin
+        in2_loc_58_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_59_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_59_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_59_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_59_ce0 = 1'b1;
+    end else begin
+        in2_loc_59_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd59) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_59_we0 = 1'b1;
+    end else begin
+        in2_loc_59_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_5_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_5_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_5_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_5_ce0 = 1'b1;
+    end else begin
+        in2_loc_5_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd5) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_5_we0 = 1'b1;
+    end else begin
+        in2_loc_5_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_60_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_60_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_60_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_60_ce0 = 1'b1;
+    end else begin
+        in2_loc_60_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd60) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_60_we0 = 1'b1;
+    end else begin
+        in2_loc_60_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_61_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_61_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_61_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_61_ce0 = 1'b1;
+    end else begin
+        in2_loc_61_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd61) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_61_we0 = 1'b1;
+    end else begin
+        in2_loc_61_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_62_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_62_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_62_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_62_ce0 = 1'b1;
+    end else begin
+        in2_loc_62_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd62) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_62_we0 = 1'b1;
+    end else begin
+        in2_loc_62_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_63_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_63_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_63_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_63_ce0 = 1'b1;
+    end else begin
+        in2_loc_63_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd63) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_63_we0 = 1'b1;
+    end else begin
+        in2_loc_63_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_6_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_6_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_6_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_6_ce0 = 1'b1;
+    end else begin
+        in2_loc_6_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd6) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_6_we0 = 1'b1;
+    end else begin
+        in2_loc_6_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_7_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_7_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_7_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_7_ce0 = 1'b1;
+    end else begin
+        in2_loc_7_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd7) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_7_we0 = 1'b1;
+    end else begin
+        in2_loc_7_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_8_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_8_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_8_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_8_ce0 = 1'b1;
+    end else begin
+        in2_loc_8_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd8) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_8_we0 = 1'b1;
+    end else begin
+        in2_loc_8_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_9_address0 = sext_ln38_fu_3733_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_9_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_9_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_9_ce0 = 1'b1;
+    end else begin
+        in2_loc_9_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4732_pp1_iter1_reg == 6'd9) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_9_we0 = 1'b1;
+    end else begin
+        in2_loc_9_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+        in2_mem_ARVALID = 1'b1;
+    end else begin
+        in2_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_RREADY = 1'b1;
+    end else begin
+        in2_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state12)) begin
+        in2_mem_blk_n_AR = m_axi_in2_mem_ARREADY;
+    end else begin
+        in2_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_blk_n_R = m_axi_in2_mem_RVALID;
+    end else begin
+        in2_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp3_stage0) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        out_loc_address0 = zext_ln42_fu_4588_p1;
+    end else if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        out_loc_address0 = out_loc_addr_reg_5143;
+    end else begin
+        out_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp3_stage0_11001) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        out_loc_ce0 = 1'b1;
+    end else begin
+        out_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        out_loc_ce1 = 1'b1;
+    end else begin
+        out_loc_ce1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4809_pp2_iter1_reg == 1'd0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        out_loc_we1 = 1'b1;
+    end else begin
+        out_loc_we1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state26))) begin
+        out_mem_AWVALID = 1'b1;
+    end else begin
+        out_mem_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+        out_mem_BREADY = 1'b1;
+    end else begin
+        out_mem_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_reg_5549_pp3_iter1_reg == 1'd0) & (ap_enable_reg_pp3_iter2 == 1'b1))) begin
+        out_mem_WVALID = 1'b1;
+    end else begin
+        out_mem_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state26)) begin
+        out_mem_blk_n_AW = m_axi_out_mem_AWREADY;
+    end else begin
+        out_mem_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state34)) begin
+        out_mem_blk_n_B = m_axi_out_mem_BVALID;
+    end else begin
+        out_mem_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln42_reg_5549_pp3_iter1_reg == 1'd0) & (1'b0 == ap_block_pp3_stage0) & (ap_enable_reg_pp3_iter2 == 1'b1))) begin
+        out_mem_blk_n_W = m_axi_out_mem_WREADY;
+    end else begin
+        out_mem_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        ap_ST_fsm_pp0_stage0 : begin
+            if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln27_fu_3420_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (icmp_ln27_fu_3420_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end
+        end
+        ap_ST_fsm_state12 : begin
+            if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+                ap_NS_fsm = ap_ST_fsm_state13;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end
+        end
+        ap_ST_fsm_state13 : begin
+            ap_NS_fsm = ap_ST_fsm_state14;
+        end
+        ap_ST_fsm_state14 : begin
+            ap_NS_fsm = ap_ST_fsm_state15;
+        end
+        ap_ST_fsm_state15 : begin
+            ap_NS_fsm = ap_ST_fsm_state16;
+        end
+        ap_ST_fsm_state16 : begin
+            ap_NS_fsm = ap_ST_fsm_state17;
+        end
+        ap_ST_fsm_state17 : begin
+            ap_NS_fsm = ap_ST_fsm_state18;
+        end
+        ap_ST_fsm_state18 : begin
+            ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+        end
+        ap_ST_fsm_pp1_stage0 : begin
+            if ((~((1'b0 == ap_block_pp1_stage0_subdone) & (icmp_ln28_fu_3513_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end else if ((((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp1_stage0_subdone) & (icmp_ln28_fu_3513_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1)))) begin
+                ap_NS_fsm = ap_ST_fsm_state22;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end
+        end
+        ap_ST_fsm_state22 : begin
+            ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+        end
+        ap_ST_fsm_pp2_stage0 : begin
+            if ((~((icmp_ln31_fu_3615_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (ap_enable_reg_pp2_iter1 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)) & ~((ap_enable_reg_pp2_iter2 == 1'b1) & (ap_enable_reg_pp2_iter1 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end else if ((((icmp_ln31_fu_3615_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (ap_enable_reg_pp2_iter1 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)) | ((ap_enable_reg_pp2_iter2 == 1'b1) & (ap_enable_reg_pp2_iter1 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state26;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end
+        end
+        ap_ST_fsm_state26 : begin
+            if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state26))) begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state26;
+            end
+        end
+        ap_ST_fsm_pp3_stage0 : begin
+            if ((~((ap_enable_reg_pp3_iter1 == 1'b0) & (icmp_ln42_fu_4576_p2 == 1'd1) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone)) & ~((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end else if ((((ap_enable_reg_pp3_iter1 == 1'b0) & (icmp_ln42_fu_4576_p2 == 1'd1) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone)) | ((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state30;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end
+        end
+        ap_ST_fsm_state30 : begin
+            ap_NS_fsm = ap_ST_fsm_state31;
+        end
+        ap_ST_fsm_state31 : begin
+            ap_NS_fsm = ap_ST_fsm_state32;
+        end
+        ap_ST_fsm_state32 : begin
+            ap_NS_fsm = ap_ST_fsm_state33;
+        end
+        ap_ST_fsm_state33 : begin
+            ap_NS_fsm = ap_ST_fsm_state34;
+        end
+        ap_ST_fsm_state34 : begin
+            if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state34;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln27_fu_3426_p2 = (phi_ln27_reg_3296 + 13'd1);
+
+assign add_ln28_fu_3519_p2 = (phi_ln28_reg_3307 + 13'd1);
+
+assign add_ln31_fu_3620_p2 = (indvar_flatten_reg_3318 + 64'd1);
+
+assign add_ln38_10_fu_4236_p2 = (mul_ln38_12_fu_3894_p2 + mul_ln38_11_fu_3888_p2);
+
+assign add_ln38_11_fu_4242_p2 = (mul_ln38_14_fu_3906_p2 + mul_ln38_13_fu_3900_p2);
+
+assign add_ln38_12_fu_4248_p2 = (add_ln38_10_fu_4236_p2 + add_ln38_11_fu_4242_p2);
+
+assign add_ln38_13_fu_4525_p2 = (add_ln38_9_reg_5499 + add_ln38_12_reg_5504);
+
+assign add_ln38_14_fu_4529_p2 = (add_ln38_6_fu_4519_p2 + add_ln38_13_fu_4525_p2);
+
+assign add_ln38_15_fu_4254_p2 = (mul_ln38_16_fu_3918_p2 + mul_ln38_15_fu_3912_p2);
+
+assign add_ln38_16_fu_4260_p2 = (mul_ln38_18_fu_3930_p2 + mul_ln38_17_fu_3924_p2);
+
+assign add_ln38_17_fu_4266_p2 = (add_ln38_15_fu_4254_p2 + add_ln38_16_fu_4260_p2);
+
+assign add_ln38_18_fu_4272_p2 = (mul_ln38_20_fu_3942_p2 + mul_ln38_19_fu_3936_p2);
+
+assign add_ln38_19_fu_4278_p2 = (mul_ln38_22_fu_3954_p2 + mul_ln38_21_fu_3948_p2);
+
+assign add_ln38_1_fu_4505_p2 = (mul_ln38_2_reg_5484 + mul_ln38_1_reg_5479);
+
+assign add_ln38_20_fu_4284_p2 = (add_ln38_18_fu_4272_p2 + add_ln38_19_fu_4278_p2);
+
+assign add_ln38_21_fu_4290_p2 = (add_ln38_17_fu_4266_p2 + add_ln38_20_fu_4284_p2);
+
+assign add_ln38_22_fu_4296_p2 = (mul_ln38_24_fu_3966_p2 + mul_ln38_23_fu_3960_p2);
+
+assign add_ln38_23_fu_4302_p2 = (mul_ln38_26_fu_3978_p2 + mul_ln38_25_fu_3972_p2);
+
+assign add_ln38_24_fu_4308_p2 = (add_ln38_22_fu_4296_p2 + add_ln38_23_fu_4302_p2);
+
+assign add_ln38_25_fu_4314_p2 = (mul_ln38_28_fu_3990_p2 + mul_ln38_27_fu_3984_p2);
+
+assign add_ln38_26_fu_4320_p2 = (mul_ln38_30_fu_4002_p2 + mul_ln38_29_fu_3996_p2);
+
+assign add_ln38_27_fu_4326_p2 = (add_ln38_25_fu_4314_p2 + add_ln38_26_fu_4320_p2);
+
+assign add_ln38_28_fu_4332_p2 = (add_ln38_24_fu_4308_p2 + add_ln38_27_fu_4326_p2);
+
+assign add_ln38_29_fu_4535_p2 = (add_ln38_21_reg_5509 + add_ln38_28_reg_5514);
+
+assign add_ln38_2_fu_4509_p2 = (add_ln38_fu_4500_p2 + add_ln38_1_fu_4505_p2);
+
+assign add_ln38_30_fu_4539_p2 = (add_ln38_14_fu_4529_p2 + add_ln38_29_fu_4535_p2);
+
+assign add_ln38_31_fu_4338_p2 = (mul_ln38_32_fu_4014_p2 + mul_ln38_31_fu_4008_p2);
+
+assign add_ln38_32_fu_4344_p2 = (mul_ln38_34_fu_4026_p2 + mul_ln38_33_fu_4020_p2);
+
+assign add_ln38_33_fu_4350_p2 = (add_ln38_31_fu_4338_p2 + add_ln38_32_fu_4344_p2);
+
+assign add_ln38_34_fu_4356_p2 = (mul_ln38_36_fu_4038_p2 + mul_ln38_35_fu_4032_p2);
+
+assign add_ln38_35_fu_4362_p2 = (mul_ln38_38_fu_4050_p2 + mul_ln38_37_fu_4044_p2);
+
+assign add_ln38_36_fu_4368_p2 = (add_ln38_34_fu_4356_p2 + add_ln38_35_fu_4362_p2);
+
+assign add_ln38_37_fu_4374_p2 = (add_ln38_33_fu_4350_p2 + add_ln38_36_fu_4368_p2);
+
+assign add_ln38_38_fu_4380_p2 = (mul_ln38_40_fu_4062_p2 + mul_ln38_39_fu_4056_p2);
+
+assign add_ln38_39_fu_4386_p2 = (mul_ln38_42_fu_4074_p2 + mul_ln38_41_fu_4068_p2);
+
+assign add_ln38_3_fu_4206_p2 = (mul_ln38_4_fu_3846_p2 + mul_ln38_3_fu_3840_p2);
+
+assign add_ln38_40_fu_4392_p2 = (add_ln38_38_fu_4380_p2 + add_ln38_39_fu_4386_p2);
+
+assign add_ln38_41_fu_4398_p2 = (mul_ln38_44_fu_4086_p2 + mul_ln38_43_fu_4080_p2);
+
+assign add_ln38_42_fu_4404_p2 = (mul_ln38_46_fu_4098_p2 + mul_ln38_45_fu_4092_p2);
+
+assign add_ln38_43_fu_4410_p2 = (add_ln38_41_fu_4398_p2 + add_ln38_42_fu_4404_p2);
+
+assign add_ln38_44_fu_4545_p2 = (add_ln38_40_reg_5524 + add_ln38_43_reg_5529);
+
+assign add_ln38_45_fu_4549_p2 = (add_ln38_37_reg_5519 + add_ln38_44_fu_4545_p2);
+
+assign add_ln38_46_fu_4416_p2 = (mul_ln38_48_fu_4110_p2 + mul_ln38_47_fu_4104_p2);
+
+assign add_ln38_47_fu_4422_p2 = (mul_ln38_50_fu_4122_p2 + mul_ln38_49_fu_4116_p2);
+
+assign add_ln38_48_fu_4428_p2 = (add_ln38_46_fu_4416_p2 + add_ln38_47_fu_4422_p2);
+
+assign add_ln38_49_fu_4434_p2 = (mul_ln38_52_fu_4134_p2 + mul_ln38_51_fu_4128_p2);
+
+assign add_ln38_4_fu_4212_p2 = (mul_ln38_6_fu_3858_p2 + mul_ln38_5_fu_3852_p2);
+
+assign add_ln38_50_fu_4440_p2 = (mul_ln38_54_fu_4146_p2 + mul_ln38_53_fu_4140_p2);
+
+assign add_ln38_51_fu_4446_p2 = (add_ln38_49_fu_4434_p2 + add_ln38_50_fu_4440_p2);
+
+assign add_ln38_52_fu_4452_p2 = (add_ln38_48_fu_4428_p2 + add_ln38_51_fu_4446_p2);
+
+assign add_ln38_53_fu_4458_p2 = (mul_ln38_56_fu_4158_p2 + mul_ln38_55_fu_4152_p2);
+
+assign add_ln38_54_fu_4464_p2 = (mul_ln38_58_fu_4170_p2 + mul_ln38_57_fu_4164_p2);
+
+assign add_ln38_55_fu_4470_p2 = (add_ln38_53_fu_4458_p2 + add_ln38_54_fu_4464_p2);
+
+assign add_ln38_56_fu_4476_p2 = (mul_ln38_60_fu_4182_p2 + mul_ln38_59_fu_4176_p2);
+
+assign add_ln38_57_fu_4482_p2 = (mul_ln38_63_fu_4200_p2 + mul_ln38_62_fu_4194_p2);
+
+assign add_ln38_58_fu_4488_p2 = (mul_ln38_61_fu_4188_p2 + add_ln38_57_fu_4482_p2);
+
+assign add_ln38_59_fu_4494_p2 = (add_ln38_56_fu_4476_p2 + add_ln38_58_fu_4488_p2);
+
+assign add_ln38_5_fu_4515_p2 = (add_ln38_3_reg_5489 + add_ln38_4_reg_5494);
+
+assign add_ln38_60_fu_4554_p2 = (add_ln38_55_reg_5539 + add_ln38_59_reg_5544);
+
+assign add_ln38_61_fu_4558_p2 = (add_ln38_52_reg_5534 + add_ln38_60_fu_4554_p2);
+
+assign add_ln38_62_fu_4563_p2 = (add_ln38_45_fu_4549_p2 + add_ln38_61_fu_4558_p2);
+
+assign add_ln38_64_fu_3805_p2 = (tmp_cast_fu_3657_p3 + trunc_ln38_1_fu_3801_p1);
+
+assign add_ln38_6_fu_4519_p2 = (add_ln38_2_fu_4509_p2 + add_ln38_5_fu_4515_p2);
+
+assign add_ln38_7_fu_4218_p2 = (mul_ln38_8_fu_3870_p2 + mul_ln38_7_fu_3864_p2);
+
+assign add_ln38_8_fu_4224_p2 = (mul_ln38_10_fu_3882_p2 + mul_ln38_9_fu_3876_p2);
+
+assign add_ln38_9_fu_4230_p2 = (add_ln38_7_fu_4218_p2 + add_ln38_8_fu_4224_p2);
+
+assign add_ln38_fu_4500_p2 = (mul_ln38_reg_5474 + out_loc_q0);
+
+assign add_ln42_fu_4582_p2 = (phi_ln42_reg_3351 + 13'd1);
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd8];
+
+assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd16];
+
+assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd18];
+
+assign ap_CS_fsm_pp3_stage0 = ap_CS_fsm[32'd20];
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state12 = ap_CS_fsm[32'd9];
+
+assign ap_CS_fsm_state18 = ap_CS_fsm[32'd15];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state22 = ap_CS_fsm[32'd17];
+
+assign ap_CS_fsm_state26 = ap_CS_fsm[32'd19];
+
+assign ap_CS_fsm_state34 = ap_CS_fsm[32'd25];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = ((in1_mem_RVALID == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = ((in1_mem_RVALID == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp1_stage0_11001 = ((in2_mem_RVALID == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp1_stage0_subdone = ((in2_mem_RVALID == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+assign ap_block_pp2_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp2_stage0_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp2_stage0_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp3_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp3_stage0_01001 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp3_stage0_11001 = ((1'b1 == ap_block_state29_io) & (ap_enable_reg_pp3_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp3_stage0_subdone = ((1'b1 == ap_block_state29_io) & (ap_enable_reg_pp3_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state10_pp0_stage0_iter1 = (in1_mem_RVALID == 1'b0);
+end
+
+assign ap_block_state11_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state20_pp1_stage0_iter1 = (in2_mem_RVALID == 1'b0);
+end
+
+assign ap_block_state21_pp1_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state23_pp2_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state24_pp2_stage0_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state25_pp2_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state27_pp3_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state28_pp3_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state29_io = ((out_mem_WREADY == 1'b0) & (icmp_ln42_reg_5549_pp3_iter1_reg == 1'd0));
+end
+
+assign ap_block_state29_pp3_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state9_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
+
+assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);
+
+assign ap_enable_pp3 = (ap_idle_pp3 ^ 1'b1);
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign empty_7_fu_3411_p1 = in_reg_4604;
+
+assign empty_8_fu_3392_p1 = in3_reg_4609;
+
+assign empty_fu_3402_p1 = out5_reg_4599;
+
+assign i_fu_3626_p2 = (31'd1 + ap_phi_mux_i_0_phi_fu_3333_p4);
+
+assign icmp_ln27_fu_3420_p2 = ((phi_ln27_reg_3296 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln28_fu_3513_p2 = ((phi_ln28_reg_3307 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln31_fu_3615_p2 = ((indvar_flatten_reg_3318 == mul_ln31_reg_4804) ? 1'b1 : 1'b0);
+
+assign icmp_ln33_fu_3632_p2 = ((j_0_reg_3340 == dim_read_reg_4593) ? 1'b1 : 1'b0);
+
+assign icmp_ln42_fu_4576_p2 = ((phi_ln42_reg_3351 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign in1_mem_ARADDR = empty_8_fu_3392_p1;
+
+assign j_fu_3816_p2 = ($signed(32'd1) + $signed(select_ln31_fu_3637_p3));
+
+assign mul_ln31_fu_3609_p0 = zext_ln31_fu_3606_p1;
+
+assign mul_ln31_fu_3609_p1 = zext_ln31_fu_3606_p1;
+
+assign mul_ln31_fu_3609_p2 = (mul_ln31_fu_3609_p0 * mul_ln31_fu_3609_p1);
+
+assign mul_ln38_10_fu_3882_p0 = in2_loc_10_q0;
+
+assign mul_ln38_10_fu_3882_p1 = in1_loc_10_q0;
+
+assign mul_ln38_10_fu_3882_p2 = ($signed(mul_ln38_10_fu_3882_p0) * $signed(mul_ln38_10_fu_3882_p1));
+
+assign mul_ln38_11_fu_3888_p0 = in2_loc_11_q0;
+
+assign mul_ln38_11_fu_3888_p1 = in1_loc_11_q0;
+
+assign mul_ln38_11_fu_3888_p2 = ($signed(mul_ln38_11_fu_3888_p0) * $signed(mul_ln38_11_fu_3888_p1));
+
+assign mul_ln38_12_fu_3894_p0 = in2_loc_12_q0;
+
+assign mul_ln38_12_fu_3894_p1 = in1_loc_12_q0;
+
+assign mul_ln38_12_fu_3894_p2 = ($signed(mul_ln38_12_fu_3894_p0) * $signed(mul_ln38_12_fu_3894_p1));
+
+assign mul_ln38_13_fu_3900_p0 = in2_loc_13_q0;
+
+assign mul_ln38_13_fu_3900_p1 = in1_loc_13_q0;
+
+assign mul_ln38_13_fu_3900_p2 = ($signed(mul_ln38_13_fu_3900_p0) * $signed(mul_ln38_13_fu_3900_p1));
+
+assign mul_ln38_14_fu_3906_p0 = in2_loc_14_q0;
+
+assign mul_ln38_14_fu_3906_p1 = in1_loc_14_q0;
+
+assign mul_ln38_14_fu_3906_p2 = ($signed(mul_ln38_14_fu_3906_p0) * $signed(mul_ln38_14_fu_3906_p1));
+
+assign mul_ln38_15_fu_3912_p0 = in2_loc_15_q0;
+
+assign mul_ln38_15_fu_3912_p1 = in1_loc_15_q0;
+
+assign mul_ln38_15_fu_3912_p2 = ($signed(mul_ln38_15_fu_3912_p0) * $signed(mul_ln38_15_fu_3912_p1));
+
+assign mul_ln38_16_fu_3918_p0 = in2_loc_16_q0;
+
+assign mul_ln38_16_fu_3918_p1 = in1_loc_16_q0;
+
+assign mul_ln38_16_fu_3918_p2 = ($signed(mul_ln38_16_fu_3918_p0) * $signed(mul_ln38_16_fu_3918_p1));
+
+assign mul_ln38_17_fu_3924_p0 = in2_loc_17_q0;
+
+assign mul_ln38_17_fu_3924_p1 = in1_loc_17_q0;
+
+assign mul_ln38_17_fu_3924_p2 = ($signed(mul_ln38_17_fu_3924_p0) * $signed(mul_ln38_17_fu_3924_p1));
+
+assign mul_ln38_18_fu_3930_p0 = in2_loc_18_q0;
+
+assign mul_ln38_18_fu_3930_p1 = in1_loc_18_q0;
+
+assign mul_ln38_18_fu_3930_p2 = ($signed(mul_ln38_18_fu_3930_p0) * $signed(mul_ln38_18_fu_3930_p1));
+
+assign mul_ln38_19_fu_3936_p0 = in2_loc_19_q0;
+
+assign mul_ln38_19_fu_3936_p1 = in1_loc_19_q0;
+
+assign mul_ln38_19_fu_3936_p2 = ($signed(mul_ln38_19_fu_3936_p0) * $signed(mul_ln38_19_fu_3936_p1));
+
+assign mul_ln38_1_fu_3828_p0 = in2_loc_1_q0;
+
+assign mul_ln38_1_fu_3828_p1 = in1_loc_1_q0;
+
+assign mul_ln38_1_fu_3828_p2 = ($signed(mul_ln38_1_fu_3828_p0) * $signed(mul_ln38_1_fu_3828_p1));
+
+assign mul_ln38_20_fu_3942_p0 = in2_loc_20_q0;
+
+assign mul_ln38_20_fu_3942_p1 = in1_loc_20_q0;
+
+assign mul_ln38_20_fu_3942_p2 = ($signed(mul_ln38_20_fu_3942_p0) * $signed(mul_ln38_20_fu_3942_p1));
+
+assign mul_ln38_21_fu_3948_p0 = in2_loc_21_q0;
+
+assign mul_ln38_21_fu_3948_p1 = in1_loc_21_q0;
+
+assign mul_ln38_21_fu_3948_p2 = ($signed(mul_ln38_21_fu_3948_p0) * $signed(mul_ln38_21_fu_3948_p1));
+
+assign mul_ln38_22_fu_3954_p0 = in2_loc_22_q0;
+
+assign mul_ln38_22_fu_3954_p1 = in1_loc_22_q0;
+
+assign mul_ln38_22_fu_3954_p2 = ($signed(mul_ln38_22_fu_3954_p0) * $signed(mul_ln38_22_fu_3954_p1));
+
+assign mul_ln38_23_fu_3960_p0 = in2_loc_23_q0;
+
+assign mul_ln38_23_fu_3960_p1 = in1_loc_23_q0;
+
+assign mul_ln38_23_fu_3960_p2 = ($signed(mul_ln38_23_fu_3960_p0) * $signed(mul_ln38_23_fu_3960_p1));
+
+assign mul_ln38_24_fu_3966_p0 = in2_loc_24_q0;
+
+assign mul_ln38_24_fu_3966_p1 = in1_loc_24_q0;
+
+assign mul_ln38_24_fu_3966_p2 = ($signed(mul_ln38_24_fu_3966_p0) * $signed(mul_ln38_24_fu_3966_p1));
+
+assign mul_ln38_25_fu_3972_p0 = in2_loc_25_q0;
+
+assign mul_ln38_25_fu_3972_p1 = in1_loc_25_q0;
+
+assign mul_ln38_25_fu_3972_p2 = ($signed(mul_ln38_25_fu_3972_p0) * $signed(mul_ln38_25_fu_3972_p1));
+
+assign mul_ln38_26_fu_3978_p0 = in2_loc_26_q0;
+
+assign mul_ln38_26_fu_3978_p1 = in1_loc_26_q0;
+
+assign mul_ln38_26_fu_3978_p2 = ($signed(mul_ln38_26_fu_3978_p0) * $signed(mul_ln38_26_fu_3978_p1));
+
+assign mul_ln38_27_fu_3984_p0 = in2_loc_27_q0;
+
+assign mul_ln38_27_fu_3984_p1 = in1_loc_27_q0;
+
+assign mul_ln38_27_fu_3984_p2 = ($signed(mul_ln38_27_fu_3984_p0) * $signed(mul_ln38_27_fu_3984_p1));
+
+assign mul_ln38_28_fu_3990_p0 = in2_loc_28_q0;
+
+assign mul_ln38_28_fu_3990_p1 = in1_loc_28_q0;
+
+assign mul_ln38_28_fu_3990_p2 = ($signed(mul_ln38_28_fu_3990_p0) * $signed(mul_ln38_28_fu_3990_p1));
+
+assign mul_ln38_29_fu_3996_p0 = in2_loc_29_q0;
+
+assign mul_ln38_29_fu_3996_p1 = in1_loc_29_q0;
+
+assign mul_ln38_29_fu_3996_p2 = ($signed(mul_ln38_29_fu_3996_p0) * $signed(mul_ln38_29_fu_3996_p1));
+
+assign mul_ln38_2_fu_3834_p0 = in2_loc_2_q0;
+
+assign mul_ln38_2_fu_3834_p1 = in1_loc_2_q0;
+
+assign mul_ln38_2_fu_3834_p2 = ($signed(mul_ln38_2_fu_3834_p0) * $signed(mul_ln38_2_fu_3834_p1));
+
+assign mul_ln38_30_fu_4002_p0 = in2_loc_30_q0;
+
+assign mul_ln38_30_fu_4002_p1 = in1_loc_30_q0;
+
+assign mul_ln38_30_fu_4002_p2 = ($signed(mul_ln38_30_fu_4002_p0) * $signed(mul_ln38_30_fu_4002_p1));
+
+assign mul_ln38_31_fu_4008_p0 = in2_loc_31_q0;
+
+assign mul_ln38_31_fu_4008_p1 = in1_loc_31_q0;
+
+assign mul_ln38_31_fu_4008_p2 = ($signed(mul_ln38_31_fu_4008_p0) * $signed(mul_ln38_31_fu_4008_p1));
+
+assign mul_ln38_32_fu_4014_p0 = in2_loc_32_q0;
+
+assign mul_ln38_32_fu_4014_p1 = in1_loc_32_q0;
+
+assign mul_ln38_32_fu_4014_p2 = ($signed(mul_ln38_32_fu_4014_p0) * $signed(mul_ln38_32_fu_4014_p1));
+
+assign mul_ln38_33_fu_4020_p0 = in2_loc_33_q0;
+
+assign mul_ln38_33_fu_4020_p1 = in1_loc_33_q0;
+
+assign mul_ln38_33_fu_4020_p2 = ($signed(mul_ln38_33_fu_4020_p0) * $signed(mul_ln38_33_fu_4020_p1));
+
+assign mul_ln38_34_fu_4026_p0 = in2_loc_34_q0;
+
+assign mul_ln38_34_fu_4026_p1 = in1_loc_34_q0;
+
+assign mul_ln38_34_fu_4026_p2 = ($signed(mul_ln38_34_fu_4026_p0) * $signed(mul_ln38_34_fu_4026_p1));
+
+assign mul_ln38_35_fu_4032_p0 = in2_loc_35_q0;
+
+assign mul_ln38_35_fu_4032_p1 = in1_loc_35_q0;
+
+assign mul_ln38_35_fu_4032_p2 = ($signed(mul_ln38_35_fu_4032_p0) * $signed(mul_ln38_35_fu_4032_p1));
+
+assign mul_ln38_36_fu_4038_p0 = in2_loc_36_q0;
+
+assign mul_ln38_36_fu_4038_p1 = in1_loc_36_q0;
+
+assign mul_ln38_36_fu_4038_p2 = ($signed(mul_ln38_36_fu_4038_p0) * $signed(mul_ln38_36_fu_4038_p1));
+
+assign mul_ln38_37_fu_4044_p0 = in2_loc_37_q0;
+
+assign mul_ln38_37_fu_4044_p1 = in1_loc_37_q0;
+
+assign mul_ln38_37_fu_4044_p2 = ($signed(mul_ln38_37_fu_4044_p0) * $signed(mul_ln38_37_fu_4044_p1));
+
+assign mul_ln38_38_fu_4050_p0 = in2_loc_38_q0;
+
+assign mul_ln38_38_fu_4050_p1 = in1_loc_38_q0;
+
+assign mul_ln38_38_fu_4050_p2 = ($signed(mul_ln38_38_fu_4050_p0) * $signed(mul_ln38_38_fu_4050_p1));
+
+assign mul_ln38_39_fu_4056_p0 = in2_loc_39_q0;
+
+assign mul_ln38_39_fu_4056_p1 = in1_loc_39_q0;
+
+assign mul_ln38_39_fu_4056_p2 = ($signed(mul_ln38_39_fu_4056_p0) * $signed(mul_ln38_39_fu_4056_p1));
+
+assign mul_ln38_3_fu_3840_p0 = in2_loc_3_q0;
+
+assign mul_ln38_3_fu_3840_p1 = in1_loc_3_q0;
+
+assign mul_ln38_3_fu_3840_p2 = ($signed(mul_ln38_3_fu_3840_p0) * $signed(mul_ln38_3_fu_3840_p1));
+
+assign mul_ln38_40_fu_4062_p0 = in2_loc_40_q0;
+
+assign mul_ln38_40_fu_4062_p1 = in1_loc_40_q0;
+
+assign mul_ln38_40_fu_4062_p2 = ($signed(mul_ln38_40_fu_4062_p0) * $signed(mul_ln38_40_fu_4062_p1));
+
+assign mul_ln38_41_fu_4068_p0 = in2_loc_41_q0;
+
+assign mul_ln38_41_fu_4068_p1 = in1_loc_41_q0;
+
+assign mul_ln38_41_fu_4068_p2 = ($signed(mul_ln38_41_fu_4068_p0) * $signed(mul_ln38_41_fu_4068_p1));
+
+assign mul_ln38_42_fu_4074_p0 = in2_loc_42_q0;
+
+assign mul_ln38_42_fu_4074_p1 = in1_loc_42_q0;
+
+assign mul_ln38_42_fu_4074_p2 = ($signed(mul_ln38_42_fu_4074_p0) * $signed(mul_ln38_42_fu_4074_p1));
+
+assign mul_ln38_43_fu_4080_p0 = in2_loc_43_q0;
+
+assign mul_ln38_43_fu_4080_p1 = in1_loc_43_q0;
+
+assign mul_ln38_43_fu_4080_p2 = ($signed(mul_ln38_43_fu_4080_p0) * $signed(mul_ln38_43_fu_4080_p1));
+
+assign mul_ln38_44_fu_4086_p0 = in2_loc_44_q0;
+
+assign mul_ln38_44_fu_4086_p1 = in1_loc_44_q0;
+
+assign mul_ln38_44_fu_4086_p2 = ($signed(mul_ln38_44_fu_4086_p0) * $signed(mul_ln38_44_fu_4086_p1));
+
+assign mul_ln38_45_fu_4092_p0 = in2_loc_45_q0;
+
+assign mul_ln38_45_fu_4092_p1 = in1_loc_45_q0;
+
+assign mul_ln38_45_fu_4092_p2 = ($signed(mul_ln38_45_fu_4092_p0) * $signed(mul_ln38_45_fu_4092_p1));
+
+assign mul_ln38_46_fu_4098_p0 = in2_loc_46_q0;
+
+assign mul_ln38_46_fu_4098_p1 = in1_loc_46_q0;
+
+assign mul_ln38_46_fu_4098_p2 = ($signed(mul_ln38_46_fu_4098_p0) * $signed(mul_ln38_46_fu_4098_p1));
+
+assign mul_ln38_47_fu_4104_p0 = in2_loc_47_q0;
+
+assign mul_ln38_47_fu_4104_p1 = in1_loc_47_q0;
+
+assign mul_ln38_47_fu_4104_p2 = ($signed(mul_ln38_47_fu_4104_p0) * $signed(mul_ln38_47_fu_4104_p1));
+
+assign mul_ln38_48_fu_4110_p0 = in2_loc_48_q0;
+
+assign mul_ln38_48_fu_4110_p1 = in1_loc_48_q0;
+
+assign mul_ln38_48_fu_4110_p2 = ($signed(mul_ln38_48_fu_4110_p0) * $signed(mul_ln38_48_fu_4110_p1));
+
+assign mul_ln38_49_fu_4116_p0 = in2_loc_49_q0;
+
+assign mul_ln38_49_fu_4116_p1 = in1_loc_49_q0;
+
+assign mul_ln38_49_fu_4116_p2 = ($signed(mul_ln38_49_fu_4116_p0) * $signed(mul_ln38_49_fu_4116_p1));
+
+assign mul_ln38_4_fu_3846_p0 = in2_loc_4_q0;
+
+assign mul_ln38_4_fu_3846_p1 = in1_loc_4_q0;
+
+assign mul_ln38_4_fu_3846_p2 = ($signed(mul_ln38_4_fu_3846_p0) * $signed(mul_ln38_4_fu_3846_p1));
+
+assign mul_ln38_50_fu_4122_p0 = in2_loc_50_q0;
+
+assign mul_ln38_50_fu_4122_p1 = in1_loc_50_q0;
+
+assign mul_ln38_50_fu_4122_p2 = ($signed(mul_ln38_50_fu_4122_p0) * $signed(mul_ln38_50_fu_4122_p1));
+
+assign mul_ln38_51_fu_4128_p0 = in2_loc_51_q0;
+
+assign mul_ln38_51_fu_4128_p1 = in1_loc_51_q0;
+
+assign mul_ln38_51_fu_4128_p2 = ($signed(mul_ln38_51_fu_4128_p0) * $signed(mul_ln38_51_fu_4128_p1));
+
+assign mul_ln38_52_fu_4134_p0 = in2_loc_52_q0;
+
+assign mul_ln38_52_fu_4134_p1 = in1_loc_52_q0;
+
+assign mul_ln38_52_fu_4134_p2 = ($signed(mul_ln38_52_fu_4134_p0) * $signed(mul_ln38_52_fu_4134_p1));
+
+assign mul_ln38_53_fu_4140_p0 = in2_loc_53_q0;
+
+assign mul_ln38_53_fu_4140_p1 = in1_loc_53_q0;
+
+assign mul_ln38_53_fu_4140_p2 = ($signed(mul_ln38_53_fu_4140_p0) * $signed(mul_ln38_53_fu_4140_p1));
+
+assign mul_ln38_54_fu_4146_p0 = in2_loc_54_q0;
+
+assign mul_ln38_54_fu_4146_p1 = in1_loc_54_q0;
+
+assign mul_ln38_54_fu_4146_p2 = ($signed(mul_ln38_54_fu_4146_p0) * $signed(mul_ln38_54_fu_4146_p1));
+
+assign mul_ln38_55_fu_4152_p0 = in2_loc_55_q0;
+
+assign mul_ln38_55_fu_4152_p1 = in1_loc_55_q0;
+
+assign mul_ln38_55_fu_4152_p2 = ($signed(mul_ln38_55_fu_4152_p0) * $signed(mul_ln38_55_fu_4152_p1));
+
+assign mul_ln38_56_fu_4158_p0 = in2_loc_56_q0;
+
+assign mul_ln38_56_fu_4158_p1 = in1_loc_56_q0;
+
+assign mul_ln38_56_fu_4158_p2 = ($signed(mul_ln38_56_fu_4158_p0) * $signed(mul_ln38_56_fu_4158_p1));
+
+assign mul_ln38_57_fu_4164_p0 = in2_loc_57_q0;
+
+assign mul_ln38_57_fu_4164_p1 = in1_loc_57_q0;
+
+assign mul_ln38_57_fu_4164_p2 = ($signed(mul_ln38_57_fu_4164_p0) * $signed(mul_ln38_57_fu_4164_p1));
+
+assign mul_ln38_58_fu_4170_p0 = in2_loc_58_q0;
+
+assign mul_ln38_58_fu_4170_p1 = in1_loc_58_q0;
+
+assign mul_ln38_58_fu_4170_p2 = ($signed(mul_ln38_58_fu_4170_p0) * $signed(mul_ln38_58_fu_4170_p1));
+
+assign mul_ln38_59_fu_4176_p0 = in2_loc_59_q0;
+
+assign mul_ln38_59_fu_4176_p1 = in1_loc_59_q0;
+
+assign mul_ln38_59_fu_4176_p2 = ($signed(mul_ln38_59_fu_4176_p0) * $signed(mul_ln38_59_fu_4176_p1));
+
+assign mul_ln38_5_fu_3852_p0 = in2_loc_5_q0;
+
+assign mul_ln38_5_fu_3852_p1 = in1_loc_5_q0;
+
+assign mul_ln38_5_fu_3852_p2 = ($signed(mul_ln38_5_fu_3852_p0) * $signed(mul_ln38_5_fu_3852_p1));
+
+assign mul_ln38_60_fu_4182_p0 = in2_loc_60_q0;
+
+assign mul_ln38_60_fu_4182_p1 = in1_loc_60_q0;
+
+assign mul_ln38_60_fu_4182_p2 = ($signed(mul_ln38_60_fu_4182_p0) * $signed(mul_ln38_60_fu_4182_p1));
+
+assign mul_ln38_61_fu_4188_p0 = in2_loc_61_q0;
+
+assign mul_ln38_61_fu_4188_p1 = in1_loc_61_q0;
+
+assign mul_ln38_61_fu_4188_p2 = ($signed(mul_ln38_61_fu_4188_p0) * $signed(mul_ln38_61_fu_4188_p1));
+
+assign mul_ln38_62_fu_4194_p0 = in2_loc_62_q0;
+
+assign mul_ln38_62_fu_4194_p1 = in1_loc_62_q0;
+
+assign mul_ln38_62_fu_4194_p2 = ($signed(mul_ln38_62_fu_4194_p0) * $signed(mul_ln38_62_fu_4194_p1));
+
+assign mul_ln38_63_fu_4200_p0 = in2_loc_63_q0;
+
+assign mul_ln38_63_fu_4200_p1 = in1_loc_63_q0;
+
+assign mul_ln38_63_fu_4200_p2 = ($signed(mul_ln38_63_fu_4200_p0) * $signed(mul_ln38_63_fu_4200_p1));
+
+assign mul_ln38_6_fu_3858_p0 = in2_loc_6_q0;
+
+assign mul_ln38_6_fu_3858_p1 = in1_loc_6_q0;
+
+assign mul_ln38_6_fu_3858_p2 = ($signed(mul_ln38_6_fu_3858_p0) * $signed(mul_ln38_6_fu_3858_p1));
+
+assign mul_ln38_7_fu_3864_p0 = in2_loc_7_q0;
+
+assign mul_ln38_7_fu_3864_p1 = in1_loc_7_q0;
+
+assign mul_ln38_7_fu_3864_p2 = ($signed(mul_ln38_7_fu_3864_p0) * $signed(mul_ln38_7_fu_3864_p1));
+
+assign mul_ln38_8_fu_3870_p0 = in2_loc_8_q0;
+
+assign mul_ln38_8_fu_3870_p1 = in1_loc_8_q0;
+
+assign mul_ln38_8_fu_3870_p2 = ($signed(mul_ln38_8_fu_3870_p0) * $signed(mul_ln38_8_fu_3870_p1));
+
+assign mul_ln38_9_fu_3876_p0 = in2_loc_9_q0;
+
+assign mul_ln38_9_fu_3876_p1 = in1_loc_9_q0;
+
+assign mul_ln38_9_fu_3876_p2 = ($signed(mul_ln38_9_fu_3876_p0) * $signed(mul_ln38_9_fu_3876_p1));
+
+assign mul_ln38_fu_3822_p0 = in2_loc_0_q0;
+
+assign mul_ln38_fu_3822_p1 = in1_loc_0_q0;
+
+assign mul_ln38_fu_3822_p2 = ($signed(mul_ln38_fu_3822_p0) * $signed(mul_ln38_fu_3822_p1));
+
+assign out_loc_d1 = (add_ln38_30_fu_4539_p2 + add_ln38_62_fu_4563_p2);
+
+assign select_ln31_1_fu_3645_p3 = ((icmp_ln33_fu_3632_p2[0:0] === 1'b1) ? i_fu_3626_p2 : ap_phi_mux_i_0_phi_fu_3333_p4);
+
+assign select_ln31_fu_3637_p3 = ((icmp_ln33_fu_3632_p2[0:0] === 1'b1) ? 32'd0 : j_0_reg_3340);
+
+assign sext_ln38_fu_3733_p1 = select_ln31_fu_3637_p3;
+
+assign tmp_cast_fu_3657_p3 = {{trunc_ln38_fu_3653_p1}, {6'd0}};
+
+assign trunc_ln27_fu_3442_p1 = phi_ln27_reg_3296[5:0];
+
+assign trunc_ln28_fu_3525_p1 = phi_ln28_reg_3307[5:0];
+
+assign trunc_ln38_1_fu_3801_p1 = select_ln31_fu_3637_p3[13:0];
+
+assign trunc_ln38_fu_3653_p1 = select_ln31_1_fu_3645_p3[7:0];
+
+assign zext_ln27_fu_3446_p1 = lshr_ln_reg_4641_pp0_iter1_reg;
+
+assign zext_ln28_fu_3539_p1 = trunc_ln28_reg_4727_pp1_iter1_reg;
+
+assign zext_ln31_1_fu_3665_p1 = select_ln31_1_fu_3645_p3;
+
+assign zext_ln31_fu_3606_p1 = dim_read_reg_4593;
+
+assign zext_ln38_fu_3811_p1 = add_ln38_64_fu_3805_p2;
+
+assign zext_ln42_fu_4588_p1 = phi_ln42_reg_3351;
+
+always @ (posedge ap_clk) begin
+    out_mem_addr_reg_4620[31:30] <= 2'b00;
+    in2_mem_addr_reg_4626[31:30] <= 2'b00;
+end
+
+endmodule //mmult
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in1_loc_0.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in1_loc_0.v
new file mode 100755
index 0000000..7a7e881
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in1_loc_0.v
@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_0_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 6;
+parameter MEM_SIZE = 64;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_0(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd64;
+parameter AddressWidth = 32'd6;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_in1_loc_0_ram mmult_in1_loc_0_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in1_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in1_mem_m_axi.v
new file mode 100755
index 0000000..81f7248
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in1_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in1_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in1_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in1_mem_m_axi_write
+mmult_in1_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in1_mem_m_axi_read
+mmult_in1_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in1_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in1_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in1_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in1_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in1_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in2_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in2_mem_m_axi.v
new file mode 100755
index 0000000..a2eab07
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_in2_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in2_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in2_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in2_mem_m_axi_write
+mmult_in2_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in2_mem_m_axi_read
+mmult_in2_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in2_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in2_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in2_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in2_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in2_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_out_loc.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_out_loc.v
new file mode 100755
index 0000000..9acfd8e
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_out_loc.v
@@ -0,0 +1,83 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_out_loc_ram (addr0, ce0, q0, addr1, ce1, d1, we1,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+output reg[DWIDTH-1:0] q0;
+input[AWIDTH-1:0] addr1;
+input ce1;
+input[DWIDTH-1:0] d1;
+input we1;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        q0 <= ram[addr0];
+    end
+end
+
+
+always @(posedge clk)  
+begin 
+    if (ce1) begin
+        if (we1) 
+            ram[addr1] <= d1; 
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_out_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    q0,
+    address1,
+    ce1,
+    we1,
+    d1);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+output[DataWidth - 1:0] q0;
+input[AddressWidth - 1:0] address1;
+input ce1;
+input we1;
+input[DataWidth - 1:0] d1;
+
+
+
+mmult_out_loc_ram mmult_out_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .q0( q0 ),
+    .addr1( address1 ),
+    .ce1( ce1 ),
+    .we1( we1 ),
+    .d1( d1 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_out_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_out_mem_m_axi.v
new file mode 100755
index 0000000..cc472db
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_out_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_out_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_out_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_out_mem_m_axi_write
+mmult_out_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_out_mem_m_axi_read
+mmult_out_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_out_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_out_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_out_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_out_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_out_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_params_s_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_params_s_axi.v
new file mode 100755
index 0000000..d470352
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/verilog/mmult_params_s_axi.v
@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult.vhd
new file mode 100755
index 0000000..18cb8f6
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult.vhd
@@ -0,0 +1,9255 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+-- Version: 2020.1
+-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult is
+generic (
+    C_M_AXI_IN1_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_S_AXI_PARAMS_ADDR_WIDTH : INTEGER := 6;
+    C_S_AXI_PARAMS_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_IN2_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_OUT_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_CACHE_VALUE : INTEGER := 3 );
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    m_axi_in1_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in1_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_WREADY : IN STD_LOGIC;
+    m_axi_in1_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in1_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in1_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in1_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RVALID : IN STD_LOGIC;
+    m_axi_in1_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_RLAST : IN STD_LOGIC;
+    m_axi_in1_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BVALID : IN STD_LOGIC;
+    m_axi_in1_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in2_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_WREADY : IN STD_LOGIC;
+    m_axi_in2_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in2_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in2_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in2_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RVALID : IN STD_LOGIC;
+    m_axi_in2_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_RLAST : IN STD_LOGIC;
+    m_axi_in2_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BVALID : IN STD_LOGIC;
+    m_axi_in2_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_out_mem_AWREADY : IN STD_LOGIC;
+    m_axi_out_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_WVALID : OUT STD_LOGIC;
+    m_axi_out_mem_WREADY : IN STD_LOGIC;
+    m_axi_out_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_out_mem_WLAST : OUT STD_LOGIC;
+    m_axi_out_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_out_mem_ARREADY : IN STD_LOGIC;
+    m_axi_out_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RVALID : IN STD_LOGIC;
+    m_axi_out_mem_RREADY : OUT STD_LOGIC;
+    m_axi_out_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_RLAST : IN STD_LOGIC;
+    m_axi_out_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BVALID : IN STD_LOGIC;
+    m_axi_out_mem_BREADY : OUT STD_LOGIC;
+    m_axi_out_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_BUSER_WIDTH-1 downto 0);
+    s_axi_params_AWVALID : IN STD_LOGIC;
+    s_axi_params_AWREADY : OUT STD_LOGIC;
+    s_axi_params_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_WVALID : IN STD_LOGIC;
+    s_axi_params_WREADY : OUT STD_LOGIC;
+    s_axi_params_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH/8-1 downto 0);
+    s_axi_params_ARVALID : IN STD_LOGIC;
+    s_axi_params_ARREADY : OUT STD_LOGIC;
+    s_axi_params_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_RVALID : OUT STD_LOGIC;
+    s_axi_params_RREADY : IN STD_LOGIC;
+    s_axi_params_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    s_axi_params_BVALID : OUT STD_LOGIC;
+    s_axi_params_BREADY : IN STD_LOGIC;
+    s_axi_params_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    interrupt : OUT STD_LOGIC );
+end;
+
+
+architecture behav of mmult is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=16413,HLS_SYN_TPT=none,HLS_SYN_MEM=142,HLS_SYN_DSP=260,HLS_SYN_FF=2859,HLS_SYN_LUT=8200,HLS_VERSION=2020_1}";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000100";
+    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000001000";
+    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000010000";
+    constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000100000";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000001000000";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000010000000";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000100000000";
+    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000001000000000";
+    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000010000000000";
+    constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000100000000000";
+    constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000001000000000000";
+    constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000010000000000000";
+    constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000100000000000000";
+    constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (25 downto 0) := "00000000001000000000000000";
+    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (25 downto 0) := "00000000010000000000000000";
+    constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (25 downto 0) := "00000000100000000000000000";
+    constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (25 downto 0) := "00000001000000000000000000";
+    constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (25 downto 0) := "00000010000000000000000000";
+    constant ap_ST_fsm_pp3_stage0 : STD_LOGIC_VECTOR (25 downto 0) := "00000100000000000000000000";
+    constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (25 downto 0) := "00001000000000000000000000";
+    constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (25 downto 0) := "00010000000000000000000000";
+    constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (25 downto 0) := "00100000000000000000000000";
+    constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (25 downto 0) := "01000000000000000000000000";
+    constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (25 downto 0) := "10000000000000000000000000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
+    constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
+    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
+    constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
+    constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
+    constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
+    constant ap_const_lv32_1000 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000001000000000000";
+    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
+    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
+    constant ap_const_lv6_3E : STD_LOGIC_VECTOR (5 downto 0) := "111110";
+    constant ap_const_lv6_3D : STD_LOGIC_VECTOR (5 downto 0) := "111101";
+    constant ap_const_lv6_3C : STD_LOGIC_VECTOR (5 downto 0) := "111100";
+    constant ap_const_lv6_3B : STD_LOGIC_VECTOR (5 downto 0) := "111011";
+    constant ap_const_lv6_3A : STD_LOGIC_VECTOR (5 downto 0) := "111010";
+    constant ap_const_lv6_39 : STD_LOGIC_VECTOR (5 downto 0) := "111001";
+    constant ap_const_lv6_38 : STD_LOGIC_VECTOR (5 downto 0) := "111000";
+    constant ap_const_lv6_37 : STD_LOGIC_VECTOR (5 downto 0) := "110111";
+    constant ap_const_lv6_36 : STD_LOGIC_VECTOR (5 downto 0) := "110110";
+    constant ap_const_lv6_35 : STD_LOGIC_VECTOR (5 downto 0) := "110101";
+    constant ap_const_lv6_34 : STD_LOGIC_VECTOR (5 downto 0) := "110100";
+    constant ap_const_lv6_33 : STD_LOGIC_VECTOR (5 downto 0) := "110011";
+    constant ap_const_lv6_32 : STD_LOGIC_VECTOR (5 downto 0) := "110010";
+    constant ap_const_lv6_31 : STD_LOGIC_VECTOR (5 downto 0) := "110001";
+    constant ap_const_lv6_30 : STD_LOGIC_VECTOR (5 downto 0) := "110000";
+    constant ap_const_lv6_2F : STD_LOGIC_VECTOR (5 downto 0) := "101111";
+    constant ap_const_lv6_2E : STD_LOGIC_VECTOR (5 downto 0) := "101110";
+    constant ap_const_lv6_2D : STD_LOGIC_VECTOR (5 downto 0) := "101101";
+    constant ap_const_lv6_2C : STD_LOGIC_VECTOR (5 downto 0) := "101100";
+    constant ap_const_lv6_2B : STD_LOGIC_VECTOR (5 downto 0) := "101011";
+    constant ap_const_lv6_2A : STD_LOGIC_VECTOR (5 downto 0) := "101010";
+    constant ap_const_lv6_29 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
+    constant ap_const_lv6_28 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
+    constant ap_const_lv6_27 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
+    constant ap_const_lv6_26 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
+    constant ap_const_lv6_25 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
+    constant ap_const_lv6_24 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
+    constant ap_const_lv6_23 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
+    constant ap_const_lv6_22 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
+    constant ap_const_lv6_21 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
+    constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
+    constant ap_const_lv6_1F : STD_LOGIC_VECTOR (5 downto 0) := "011111";
+    constant ap_const_lv6_1E : STD_LOGIC_VECTOR (5 downto 0) := "011110";
+    constant ap_const_lv6_1D : STD_LOGIC_VECTOR (5 downto 0) := "011101";
+    constant ap_const_lv6_1C : STD_LOGIC_VECTOR (5 downto 0) := "011100";
+    constant ap_const_lv6_1B : STD_LOGIC_VECTOR (5 downto 0) := "011011";
+    constant ap_const_lv6_1A : STD_LOGIC_VECTOR (5 downto 0) := "011010";
+    constant ap_const_lv6_19 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
+    constant ap_const_lv6_18 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
+    constant ap_const_lv6_17 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
+    constant ap_const_lv6_16 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
+    constant ap_const_lv6_15 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
+    constant ap_const_lv6_14 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
+    constant ap_const_lv6_13 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
+    constant ap_const_lv6_12 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
+    constant ap_const_lv6_11 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
+    constant ap_const_lv6_10 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
+    constant ap_const_lv6_F : STD_LOGIC_VECTOR (5 downto 0) := "001111";
+    constant ap_const_lv6_E : STD_LOGIC_VECTOR (5 downto 0) := "001110";
+    constant ap_const_lv6_D : STD_LOGIC_VECTOR (5 downto 0) := "001101";
+    constant ap_const_lv6_C : STD_LOGIC_VECTOR (5 downto 0) := "001100";
+    constant ap_const_lv6_B : STD_LOGIC_VECTOR (5 downto 0) := "001011";
+    constant ap_const_lv6_A : STD_LOGIC_VECTOR (5 downto 0) := "001010";
+    constant ap_const_lv6_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
+    constant ap_const_lv6_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
+    constant ap_const_lv6_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
+    constant ap_const_lv6_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
+    constant ap_const_lv6_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
+    constant ap_const_lv6_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
+    constant ap_const_lv6_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
+    constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
+    constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
+    constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
+    constant ap_const_lv6_3F : STD_LOGIC_VECTOR (5 downto 0) := "111111";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv13_1000 : STD_LOGIC_VECTOR (12 downto 0) := "1000000000000";
+    constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
+    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
+    constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
+    constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal ap_start : STD_LOGIC;
+    signal ap_done : STD_LOGIC;
+    signal ap_idle : STD_LOGIC;
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal ap_ready : STD_LOGIC;
+    signal in1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_r : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal in1_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal in2_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state12 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
+    signal in2_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
+    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp1_stage0 : BOOLEAN;
+    signal out_mem_blk_n_AW : STD_LOGIC;
+    signal ap_CS_fsm_state26 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
+    signal out_mem_blk_n_W : STD_LOGIC;
+    signal ap_enable_reg_pp3_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp3_stage0 : BOOLEAN;
+    signal icmp_ln42_reg_5549 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln42_reg_5549_pp3_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_B : STD_LOGIC;
+    signal ap_CS_fsm_state34 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state34 : signal is "none";
+    signal in1_mem_AWREADY : STD_LOGIC;
+    signal in1_mem_WREADY : STD_LOGIC;
+    signal in1_mem_ARVALID : STD_LOGIC;
+    signal in1_mem_ARREADY : STD_LOGIC;
+    signal in1_mem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RVALID : STD_LOGIC;
+    signal in1_mem_RREADY : STD_LOGIC;
+    signal in1_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RLAST : STD_LOGIC;
+    signal in1_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BVALID : STD_LOGIC;
+    signal in1_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_AWREADY : STD_LOGIC;
+    signal in2_mem_WREADY : STD_LOGIC;
+    signal in2_mem_ARVALID : STD_LOGIC;
+    signal in2_mem_ARREADY : STD_LOGIC;
+    signal in2_mem_RVALID : STD_LOGIC;
+    signal in2_mem_RREADY : STD_LOGIC;
+    signal in2_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_RLAST : STD_LOGIC;
+    signal in2_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BVALID : STD_LOGIC;
+    signal in2_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_AWVALID : STD_LOGIC;
+    signal out_mem_AWREADY : STD_LOGIC;
+    signal out_mem_WVALID : STD_LOGIC;
+    signal out_mem_WREADY : STD_LOGIC;
+    signal out_mem_ARREADY : STD_LOGIC;
+    signal out_mem_RVALID : STD_LOGIC;
+    signal out_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_RLAST : STD_LOGIC;
+    signal out_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BVALID : STD_LOGIC;
+    signal out_mem_BREADY : STD_LOGIC;
+    signal out_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal phi_ln27_reg_3296 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln28_reg_3307 : STD_LOGIC_VECTOR (12 downto 0);
+    signal indvar_flatten_reg_3318 : STD_LOGIC_VECTOR (63 downto 0);
+    signal i_0_reg_3329 : STD_LOGIC_VECTOR (30 downto 0);
+    signal j_0_reg_3340 : STD_LOGIC_VECTOR (31 downto 0);
+    signal phi_ln42_reg_3351 : STD_LOGIC_VECTOR (12 downto 0);
+    signal dim_read_reg_4593 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out5_reg_4599 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in_reg_4604 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in3_reg_4609 : STD_LOGIC_VECTOR (29 downto 0);
+    signal out_mem_addr_reg_4620 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
+    signal in2_mem_addr_reg_4626 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln27_fu_3420_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state9_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state11_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal add_ln27_fu_3426_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal lshr_ln_reg_4641 : STD_LOGIC_VECTOR (6 downto 0);
+    signal lshr_ln_reg_4641_pp0_iter1_reg : STD_LOGIC_VECTOR (6 downto 0);
+    signal trunc_ln27_fu_3442_p1 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln27_reg_4646 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln27_reg_4646_pp0_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_mem_addr_read_reg_4650 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln28_fu_3513_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state19_pp1_stage0_iter0 : BOOLEAN;
+    signal ap_block_state20_pp1_stage0_iter1 : BOOLEAN;
+    signal ap_block_state21_pp1_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp1_stage0_11001 : BOOLEAN;
+    signal add_ln28_fu_3519_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
+    signal trunc_ln28_fu_3525_p1 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln28_reg_4727 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln28_reg_4727_pp1_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln1_reg_4732 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln1_reg_4732_pp1_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_mem_addr_read_reg_4736 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln31_fu_3609_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal mul_ln31_reg_4804 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_CS_fsm_state22 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
+    signal icmp_ln31_fu_3615_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4809 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
+    signal ap_block_state23_pp2_stage0_iter0 : BOOLEAN;
+    signal ap_block_state24_pp2_stage0_iter1 : BOOLEAN;
+    signal ap_block_state25_pp2_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp2_stage0_11001 : BOOLEAN;
+    signal icmp_ln31_reg_4809_pp2_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln31_fu_3620_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
+    signal select_ln31_1_fu_3645_p3 : STD_LOGIC_VECTOR (30 downto 0);
+    signal select_ln31_1_reg_4818 : STD_LOGIC_VECTOR (30 downto 0);
+    signal out_loc_addr_reg_5143 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_5143_pp2_iter1_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal j_fu_3816_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_fu_3822_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_reg_5474 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_fu_3828_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_reg_5479 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_fu_3834_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_reg_5484 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_3_fu_4206_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_3_reg_5489 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_4_fu_4212_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_4_reg_5494 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_9_fu_4230_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_9_reg_5499 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_12_fu_4248_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_12_reg_5504 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_fu_4290_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_reg_5509 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_28_fu_4332_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_28_reg_5514 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_fu_4374_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_reg_5519 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_40_fu_4392_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_40_reg_5524 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_43_fu_4410_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_43_reg_5529 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_fu_4452_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_reg_5534 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_55_fu_4470_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_55_reg_5539 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_59_fu_4494_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_59_reg_5544 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln42_fu_4576_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp3_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp3_stage0 : signal is "none";
+    signal ap_block_state27_pp3_stage0_iter0 : BOOLEAN;
+    signal ap_block_state28_pp3_stage0_iter1 : BOOLEAN;
+    signal ap_block_state29_pp3_stage0_iter2 : BOOLEAN;
+    signal ap_block_state29_io : BOOLEAN;
+    signal ap_block_pp3_stage0_11001 : BOOLEAN;
+    signal add_ln42_fu_4582_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp3_iter0 : STD_LOGIC := '0';
+    signal out_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_load_reg_5563 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp3_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state9 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_CS_fsm_state18 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
+    signal ap_block_pp1_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp1_exit_iter0_state19 : STD_LOGIC;
+    signal ap_enable_reg_pp1_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp2_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp2_exit_iter0_state23 : STD_LOGIC;
+    signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp2_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp3_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp3_exit_iter0_state27 : STD_LOGIC;
+    signal in1_loc_0_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_0_ce0 : STD_LOGIC;
+    signal in1_loc_0_we0 : STD_LOGIC;
+    signal in1_loc_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_1_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_1_ce0 : STD_LOGIC;
+    signal in1_loc_1_we0 : STD_LOGIC;
+    signal in1_loc_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_2_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_2_ce0 : STD_LOGIC;
+    signal in1_loc_2_we0 : STD_LOGIC;
+    signal in1_loc_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_3_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_3_ce0 : STD_LOGIC;
+    signal in1_loc_3_we0 : STD_LOGIC;
+    signal in1_loc_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_4_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_4_ce0 : STD_LOGIC;
+    signal in1_loc_4_we0 : STD_LOGIC;
+    signal in1_loc_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_5_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_5_ce0 : STD_LOGIC;
+    signal in1_loc_5_we0 : STD_LOGIC;
+    signal in1_loc_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_6_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_6_ce0 : STD_LOGIC;
+    signal in1_loc_6_we0 : STD_LOGIC;
+    signal in1_loc_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_7_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_7_ce0 : STD_LOGIC;
+    signal in1_loc_7_we0 : STD_LOGIC;
+    signal in1_loc_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_8_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_8_ce0 : STD_LOGIC;
+    signal in1_loc_8_we0 : STD_LOGIC;
+    signal in1_loc_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_9_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_9_ce0 : STD_LOGIC;
+    signal in1_loc_9_we0 : STD_LOGIC;
+    signal in1_loc_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_10_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_10_ce0 : STD_LOGIC;
+    signal in1_loc_10_we0 : STD_LOGIC;
+    signal in1_loc_10_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_11_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_11_ce0 : STD_LOGIC;
+    signal in1_loc_11_we0 : STD_LOGIC;
+    signal in1_loc_11_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_12_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_12_ce0 : STD_LOGIC;
+    signal in1_loc_12_we0 : STD_LOGIC;
+    signal in1_loc_12_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_13_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_13_ce0 : STD_LOGIC;
+    signal in1_loc_13_we0 : STD_LOGIC;
+    signal in1_loc_13_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_14_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_14_ce0 : STD_LOGIC;
+    signal in1_loc_14_we0 : STD_LOGIC;
+    signal in1_loc_14_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_15_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_15_ce0 : STD_LOGIC;
+    signal in1_loc_15_we0 : STD_LOGIC;
+    signal in1_loc_15_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_16_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_16_ce0 : STD_LOGIC;
+    signal in1_loc_16_we0 : STD_LOGIC;
+    signal in1_loc_16_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_17_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_17_ce0 : STD_LOGIC;
+    signal in1_loc_17_we0 : STD_LOGIC;
+    signal in1_loc_17_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_18_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_18_ce0 : STD_LOGIC;
+    signal in1_loc_18_we0 : STD_LOGIC;
+    signal in1_loc_18_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_19_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_19_ce0 : STD_LOGIC;
+    signal in1_loc_19_we0 : STD_LOGIC;
+    signal in1_loc_19_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_20_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_20_ce0 : STD_LOGIC;
+    signal in1_loc_20_we0 : STD_LOGIC;
+    signal in1_loc_20_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_21_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_21_ce0 : STD_LOGIC;
+    signal in1_loc_21_we0 : STD_LOGIC;
+    signal in1_loc_21_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_22_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_22_ce0 : STD_LOGIC;
+    signal in1_loc_22_we0 : STD_LOGIC;
+    signal in1_loc_22_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_23_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_23_ce0 : STD_LOGIC;
+    signal in1_loc_23_we0 : STD_LOGIC;
+    signal in1_loc_23_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_24_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_24_ce0 : STD_LOGIC;
+    signal in1_loc_24_we0 : STD_LOGIC;
+    signal in1_loc_24_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_25_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_25_ce0 : STD_LOGIC;
+    signal in1_loc_25_we0 : STD_LOGIC;
+    signal in1_loc_25_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_26_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_26_ce0 : STD_LOGIC;
+    signal in1_loc_26_we0 : STD_LOGIC;
+    signal in1_loc_26_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_27_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_27_ce0 : STD_LOGIC;
+    signal in1_loc_27_we0 : STD_LOGIC;
+    signal in1_loc_27_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_28_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_28_ce0 : STD_LOGIC;
+    signal in1_loc_28_we0 : STD_LOGIC;
+    signal in1_loc_28_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_29_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_29_ce0 : STD_LOGIC;
+    signal in1_loc_29_we0 : STD_LOGIC;
+    signal in1_loc_29_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_30_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_30_ce0 : STD_LOGIC;
+    signal in1_loc_30_we0 : STD_LOGIC;
+    signal in1_loc_30_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_31_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_31_ce0 : STD_LOGIC;
+    signal in1_loc_31_we0 : STD_LOGIC;
+    signal in1_loc_31_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_32_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_32_ce0 : STD_LOGIC;
+    signal in1_loc_32_we0 : STD_LOGIC;
+    signal in1_loc_32_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_33_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_33_ce0 : STD_LOGIC;
+    signal in1_loc_33_we0 : STD_LOGIC;
+    signal in1_loc_33_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_34_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_34_ce0 : STD_LOGIC;
+    signal in1_loc_34_we0 : STD_LOGIC;
+    signal in1_loc_34_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_35_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_35_ce0 : STD_LOGIC;
+    signal in1_loc_35_we0 : STD_LOGIC;
+    signal in1_loc_35_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_36_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_36_ce0 : STD_LOGIC;
+    signal in1_loc_36_we0 : STD_LOGIC;
+    signal in1_loc_36_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_37_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_37_ce0 : STD_LOGIC;
+    signal in1_loc_37_we0 : STD_LOGIC;
+    signal in1_loc_37_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_38_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_38_ce0 : STD_LOGIC;
+    signal in1_loc_38_we0 : STD_LOGIC;
+    signal in1_loc_38_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_39_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_39_ce0 : STD_LOGIC;
+    signal in1_loc_39_we0 : STD_LOGIC;
+    signal in1_loc_39_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_40_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_40_ce0 : STD_LOGIC;
+    signal in1_loc_40_we0 : STD_LOGIC;
+    signal in1_loc_40_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_41_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_41_ce0 : STD_LOGIC;
+    signal in1_loc_41_we0 : STD_LOGIC;
+    signal in1_loc_41_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_42_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_42_ce0 : STD_LOGIC;
+    signal in1_loc_42_we0 : STD_LOGIC;
+    signal in1_loc_42_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_43_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_43_ce0 : STD_LOGIC;
+    signal in1_loc_43_we0 : STD_LOGIC;
+    signal in1_loc_43_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_44_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_44_ce0 : STD_LOGIC;
+    signal in1_loc_44_we0 : STD_LOGIC;
+    signal in1_loc_44_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_45_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_45_ce0 : STD_LOGIC;
+    signal in1_loc_45_we0 : STD_LOGIC;
+    signal in1_loc_45_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_46_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_46_ce0 : STD_LOGIC;
+    signal in1_loc_46_we0 : STD_LOGIC;
+    signal in1_loc_46_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_47_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_47_ce0 : STD_LOGIC;
+    signal in1_loc_47_we0 : STD_LOGIC;
+    signal in1_loc_47_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_48_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_48_ce0 : STD_LOGIC;
+    signal in1_loc_48_we0 : STD_LOGIC;
+    signal in1_loc_48_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_49_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_49_ce0 : STD_LOGIC;
+    signal in1_loc_49_we0 : STD_LOGIC;
+    signal in1_loc_49_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_50_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_50_ce0 : STD_LOGIC;
+    signal in1_loc_50_we0 : STD_LOGIC;
+    signal in1_loc_50_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_51_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_51_ce0 : STD_LOGIC;
+    signal in1_loc_51_we0 : STD_LOGIC;
+    signal in1_loc_51_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_52_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_52_ce0 : STD_LOGIC;
+    signal in1_loc_52_we0 : STD_LOGIC;
+    signal in1_loc_52_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_53_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_53_ce0 : STD_LOGIC;
+    signal in1_loc_53_we0 : STD_LOGIC;
+    signal in1_loc_53_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_54_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_54_ce0 : STD_LOGIC;
+    signal in1_loc_54_we0 : STD_LOGIC;
+    signal in1_loc_54_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_55_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_55_ce0 : STD_LOGIC;
+    signal in1_loc_55_we0 : STD_LOGIC;
+    signal in1_loc_55_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_56_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_56_ce0 : STD_LOGIC;
+    signal in1_loc_56_we0 : STD_LOGIC;
+    signal in1_loc_56_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_57_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_57_ce0 : STD_LOGIC;
+    signal in1_loc_57_we0 : STD_LOGIC;
+    signal in1_loc_57_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_58_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_58_ce0 : STD_LOGIC;
+    signal in1_loc_58_we0 : STD_LOGIC;
+    signal in1_loc_58_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_59_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_59_ce0 : STD_LOGIC;
+    signal in1_loc_59_we0 : STD_LOGIC;
+    signal in1_loc_59_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_60_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_60_ce0 : STD_LOGIC;
+    signal in1_loc_60_we0 : STD_LOGIC;
+    signal in1_loc_60_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_61_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_61_ce0 : STD_LOGIC;
+    signal in1_loc_61_we0 : STD_LOGIC;
+    signal in1_loc_61_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_62_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_62_ce0 : STD_LOGIC;
+    signal in1_loc_62_we0 : STD_LOGIC;
+    signal in1_loc_62_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_63_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_63_ce0 : STD_LOGIC;
+    signal in1_loc_63_we0 : STD_LOGIC;
+    signal in1_loc_63_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_0_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_0_ce0 : STD_LOGIC;
+    signal in2_loc_0_we0 : STD_LOGIC;
+    signal in2_loc_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_1_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_1_ce0 : STD_LOGIC;
+    signal in2_loc_1_we0 : STD_LOGIC;
+    signal in2_loc_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_2_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_2_ce0 : STD_LOGIC;
+    signal in2_loc_2_we0 : STD_LOGIC;
+    signal in2_loc_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_3_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_3_ce0 : STD_LOGIC;
+    signal in2_loc_3_we0 : STD_LOGIC;
+    signal in2_loc_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_4_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_4_ce0 : STD_LOGIC;
+    signal in2_loc_4_we0 : STD_LOGIC;
+    signal in2_loc_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_5_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_5_ce0 : STD_LOGIC;
+    signal in2_loc_5_we0 : STD_LOGIC;
+    signal in2_loc_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_6_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_6_ce0 : STD_LOGIC;
+    signal in2_loc_6_we0 : STD_LOGIC;
+    signal in2_loc_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_7_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_7_ce0 : STD_LOGIC;
+    signal in2_loc_7_we0 : STD_LOGIC;
+    signal in2_loc_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_8_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_8_ce0 : STD_LOGIC;
+    signal in2_loc_8_we0 : STD_LOGIC;
+    signal in2_loc_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_9_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_9_ce0 : STD_LOGIC;
+    signal in2_loc_9_we0 : STD_LOGIC;
+    signal in2_loc_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_10_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_10_ce0 : STD_LOGIC;
+    signal in2_loc_10_we0 : STD_LOGIC;
+    signal in2_loc_10_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_11_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_11_ce0 : STD_LOGIC;
+    signal in2_loc_11_we0 : STD_LOGIC;
+    signal in2_loc_11_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_12_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_12_ce0 : STD_LOGIC;
+    signal in2_loc_12_we0 : STD_LOGIC;
+    signal in2_loc_12_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_13_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_13_ce0 : STD_LOGIC;
+    signal in2_loc_13_we0 : STD_LOGIC;
+    signal in2_loc_13_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_14_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_14_ce0 : STD_LOGIC;
+    signal in2_loc_14_we0 : STD_LOGIC;
+    signal in2_loc_14_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_15_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_15_ce0 : STD_LOGIC;
+    signal in2_loc_15_we0 : STD_LOGIC;
+    signal in2_loc_15_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_16_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_16_ce0 : STD_LOGIC;
+    signal in2_loc_16_we0 : STD_LOGIC;
+    signal in2_loc_16_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_17_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_17_ce0 : STD_LOGIC;
+    signal in2_loc_17_we0 : STD_LOGIC;
+    signal in2_loc_17_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_18_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_18_ce0 : STD_LOGIC;
+    signal in2_loc_18_we0 : STD_LOGIC;
+    signal in2_loc_18_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_19_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_19_ce0 : STD_LOGIC;
+    signal in2_loc_19_we0 : STD_LOGIC;
+    signal in2_loc_19_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_20_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_20_ce0 : STD_LOGIC;
+    signal in2_loc_20_we0 : STD_LOGIC;
+    signal in2_loc_20_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_21_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_21_ce0 : STD_LOGIC;
+    signal in2_loc_21_we0 : STD_LOGIC;
+    signal in2_loc_21_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_22_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_22_ce0 : STD_LOGIC;
+    signal in2_loc_22_we0 : STD_LOGIC;
+    signal in2_loc_22_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_23_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_23_ce0 : STD_LOGIC;
+    signal in2_loc_23_we0 : STD_LOGIC;
+    signal in2_loc_23_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_24_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_24_ce0 : STD_LOGIC;
+    signal in2_loc_24_we0 : STD_LOGIC;
+    signal in2_loc_24_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_25_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_25_ce0 : STD_LOGIC;
+    signal in2_loc_25_we0 : STD_LOGIC;
+    signal in2_loc_25_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_26_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_26_ce0 : STD_LOGIC;
+    signal in2_loc_26_we0 : STD_LOGIC;
+    signal in2_loc_26_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_27_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_27_ce0 : STD_LOGIC;
+    signal in2_loc_27_we0 : STD_LOGIC;
+    signal in2_loc_27_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_28_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_28_ce0 : STD_LOGIC;
+    signal in2_loc_28_we0 : STD_LOGIC;
+    signal in2_loc_28_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_29_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_29_ce0 : STD_LOGIC;
+    signal in2_loc_29_we0 : STD_LOGIC;
+    signal in2_loc_29_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_30_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_30_ce0 : STD_LOGIC;
+    signal in2_loc_30_we0 : STD_LOGIC;
+    signal in2_loc_30_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_31_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_31_ce0 : STD_LOGIC;
+    signal in2_loc_31_we0 : STD_LOGIC;
+    signal in2_loc_31_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_32_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_32_ce0 : STD_LOGIC;
+    signal in2_loc_32_we0 : STD_LOGIC;
+    signal in2_loc_32_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_33_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_33_ce0 : STD_LOGIC;
+    signal in2_loc_33_we0 : STD_LOGIC;
+    signal in2_loc_33_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_34_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_34_ce0 : STD_LOGIC;
+    signal in2_loc_34_we0 : STD_LOGIC;
+    signal in2_loc_34_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_35_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_35_ce0 : STD_LOGIC;
+    signal in2_loc_35_we0 : STD_LOGIC;
+    signal in2_loc_35_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_36_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_36_ce0 : STD_LOGIC;
+    signal in2_loc_36_we0 : STD_LOGIC;
+    signal in2_loc_36_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_37_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_37_ce0 : STD_LOGIC;
+    signal in2_loc_37_we0 : STD_LOGIC;
+    signal in2_loc_37_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_38_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_38_ce0 : STD_LOGIC;
+    signal in2_loc_38_we0 : STD_LOGIC;
+    signal in2_loc_38_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_39_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_39_ce0 : STD_LOGIC;
+    signal in2_loc_39_we0 : STD_LOGIC;
+    signal in2_loc_39_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_40_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_40_ce0 : STD_LOGIC;
+    signal in2_loc_40_we0 : STD_LOGIC;
+    signal in2_loc_40_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_41_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_41_ce0 : STD_LOGIC;
+    signal in2_loc_41_we0 : STD_LOGIC;
+    signal in2_loc_41_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_42_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_42_ce0 : STD_LOGIC;
+    signal in2_loc_42_we0 : STD_LOGIC;
+    signal in2_loc_42_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_43_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_43_ce0 : STD_LOGIC;
+    signal in2_loc_43_we0 : STD_LOGIC;
+    signal in2_loc_43_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_44_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_44_ce0 : STD_LOGIC;
+    signal in2_loc_44_we0 : STD_LOGIC;
+    signal in2_loc_44_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_45_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_45_ce0 : STD_LOGIC;
+    signal in2_loc_45_we0 : STD_LOGIC;
+    signal in2_loc_45_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_46_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_46_ce0 : STD_LOGIC;
+    signal in2_loc_46_we0 : STD_LOGIC;
+    signal in2_loc_46_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_47_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_47_ce0 : STD_LOGIC;
+    signal in2_loc_47_we0 : STD_LOGIC;
+    signal in2_loc_47_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_48_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_48_ce0 : STD_LOGIC;
+    signal in2_loc_48_we0 : STD_LOGIC;
+    signal in2_loc_48_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_49_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_49_ce0 : STD_LOGIC;
+    signal in2_loc_49_we0 : STD_LOGIC;
+    signal in2_loc_49_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_50_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_50_ce0 : STD_LOGIC;
+    signal in2_loc_50_we0 : STD_LOGIC;
+    signal in2_loc_50_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_51_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_51_ce0 : STD_LOGIC;
+    signal in2_loc_51_we0 : STD_LOGIC;
+    signal in2_loc_51_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_52_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_52_ce0 : STD_LOGIC;
+    signal in2_loc_52_we0 : STD_LOGIC;
+    signal in2_loc_52_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_53_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_53_ce0 : STD_LOGIC;
+    signal in2_loc_53_we0 : STD_LOGIC;
+    signal in2_loc_53_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_54_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_54_ce0 : STD_LOGIC;
+    signal in2_loc_54_we0 : STD_LOGIC;
+    signal in2_loc_54_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_55_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_55_ce0 : STD_LOGIC;
+    signal in2_loc_55_we0 : STD_LOGIC;
+    signal in2_loc_55_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_56_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_56_ce0 : STD_LOGIC;
+    signal in2_loc_56_we0 : STD_LOGIC;
+    signal in2_loc_56_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_57_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_57_ce0 : STD_LOGIC;
+    signal in2_loc_57_we0 : STD_LOGIC;
+    signal in2_loc_57_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_58_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_58_ce0 : STD_LOGIC;
+    signal in2_loc_58_we0 : STD_LOGIC;
+    signal in2_loc_58_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_59_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_59_ce0 : STD_LOGIC;
+    signal in2_loc_59_we0 : STD_LOGIC;
+    signal in2_loc_59_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_60_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_60_ce0 : STD_LOGIC;
+    signal in2_loc_60_we0 : STD_LOGIC;
+    signal in2_loc_60_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_61_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_61_ce0 : STD_LOGIC;
+    signal in2_loc_61_we0 : STD_LOGIC;
+    signal in2_loc_61_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_62_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_62_ce0 : STD_LOGIC;
+    signal in2_loc_62_we0 : STD_LOGIC;
+    signal in2_loc_62_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_63_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_63_ce0 : STD_LOGIC;
+    signal in2_loc_63_we0 : STD_LOGIC;
+    signal in2_loc_63_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_ce0 : STD_LOGIC;
+    signal out_loc_ce1 : STD_LOGIC;
+    signal out_loc_we1 : STD_LOGIC;
+    signal out_loc_d1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_phi_mux_i_0_phi_fu_3333_p4 : STD_LOGIC_VECTOR (30 downto 0);
+    signal ap_block_pp2_stage0 : BOOLEAN;
+    signal zext_ln27_fu_3446_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln28_fu_3539_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln31_1_fu_3665_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln38_fu_3811_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_fu_3733_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln42_fu_4588_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_8_fu_3392_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_fu_3402_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_7_fu_3411_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp3_stage0_01001 : BOOLEAN;
+    signal mul_ln31_fu_3609_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal zext_ln31_fu_3606_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal mul_ln31_fu_3609_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln33_fu_3632_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal i_fu_3626_p2 : STD_LOGIC_VECTOR (30 downto 0);
+    signal trunc_ln38_fu_3653_p1 : STD_LOGIC_VECTOR (7 downto 0);
+    signal select_ln31_fu_3637_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_cast_fu_3657_p3 : STD_LOGIC_VECTOR (13 downto 0);
+    signal trunc_ln38_1_fu_3801_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_64_fu_3805_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal mul_ln38_fu_3822_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_fu_3822_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_fu_3828_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_fu_3828_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_fu_3834_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_fu_3834_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_fu_3840_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_fu_3840_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_fu_3846_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_fu_3846_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_fu_3852_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_fu_3852_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_fu_3858_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_fu_3858_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_fu_3864_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_fu_3864_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_fu_3870_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_fu_3870_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_fu_3876_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_fu_3876_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_fu_3882_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_fu_3882_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_fu_3888_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_fu_3888_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_fu_3894_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_fu_3894_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_fu_3900_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_fu_3900_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_fu_3906_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_fu_3906_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_fu_3912_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_fu_3912_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_fu_3918_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_fu_3918_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_fu_3924_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_fu_3924_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_fu_3930_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_fu_3930_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_fu_3936_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_fu_3936_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_fu_3942_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_fu_3942_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_fu_3948_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_fu_3948_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_fu_3954_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_fu_3954_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_fu_3960_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_fu_3960_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_fu_3966_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_fu_3966_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_fu_3972_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_fu_3972_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_fu_3978_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_fu_3978_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_fu_3984_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_fu_3984_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_fu_3990_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_fu_3990_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_fu_3996_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_fu_3996_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_fu_4002_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_fu_4002_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_fu_4008_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_fu_4008_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_fu_4014_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_fu_4014_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_fu_4020_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_fu_4020_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_fu_4026_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_fu_4026_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_fu_4032_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_fu_4032_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_fu_4038_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_fu_4038_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_fu_4044_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_fu_4044_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_fu_4050_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_fu_4050_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_fu_4056_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_fu_4056_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_fu_4062_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_fu_4062_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_fu_4068_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_fu_4068_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_fu_4074_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_fu_4074_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_fu_4080_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_fu_4080_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_fu_4086_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_fu_4086_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_fu_4092_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_fu_4092_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_fu_4098_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_fu_4098_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_fu_4104_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_fu_4104_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_fu_4110_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_fu_4110_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_fu_4116_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_fu_4116_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_fu_4122_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_fu_4122_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_fu_4128_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_fu_4128_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_fu_4134_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_fu_4134_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_fu_4140_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_fu_4140_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_fu_4146_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_fu_4146_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_fu_4152_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_fu_4152_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_fu_4158_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_fu_4158_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_fu_4164_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_fu_4164_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_fu_4170_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_fu_4170_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_fu_4176_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_fu_4176_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_fu_4182_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_fu_4182_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_fu_4188_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_fu_4188_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_fu_4194_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_fu_4194_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_fu_4200_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_fu_4200_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_fu_3846_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_fu_3840_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_fu_3858_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_fu_3852_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_fu_3870_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_fu_3864_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_fu_3882_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_fu_3876_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_7_fu_4218_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_8_fu_4224_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_fu_3894_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_fu_3888_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_fu_3906_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_fu_3900_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_10_fu_4236_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_11_fu_4242_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_fu_3918_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_fu_3912_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_fu_3930_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_fu_3924_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_15_fu_4254_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_16_fu_4260_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_fu_3942_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_fu_3936_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_fu_3954_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_fu_3948_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_18_fu_4272_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_19_fu_4278_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_17_fu_4266_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_20_fu_4284_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_fu_3966_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_fu_3960_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_fu_3978_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_fu_3972_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_22_fu_4296_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_23_fu_4302_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_fu_3990_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_fu_3984_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_fu_4002_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_fu_3996_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_25_fu_4314_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_26_fu_4320_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_24_fu_4308_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_27_fu_4326_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_fu_4014_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_fu_4008_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_fu_4026_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_fu_4020_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_31_fu_4338_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_32_fu_4344_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_fu_4038_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_fu_4032_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_fu_4050_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_fu_4044_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_34_fu_4356_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_35_fu_4362_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_33_fu_4350_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_36_fu_4368_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_fu_4062_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_fu_4056_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_fu_4074_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_fu_4068_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_38_fu_4380_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_39_fu_4386_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_fu_4086_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_fu_4080_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_fu_4098_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_fu_4092_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_41_fu_4398_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_42_fu_4404_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_fu_4110_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_fu_4104_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_fu_4122_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_fu_4116_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_46_fu_4416_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_47_fu_4422_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_fu_4134_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_fu_4128_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_fu_4146_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_fu_4140_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_49_fu_4434_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_50_fu_4440_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_48_fu_4428_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_51_fu_4446_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_fu_4158_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_fu_4152_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_fu_4170_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_fu_4164_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_53_fu_4458_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_54_fu_4464_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_fu_4182_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_fu_4176_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_fu_4200_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_fu_4194_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_fu_4188_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_57_fu_4482_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_56_fu_4476_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_58_fu_4488_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_fu_4500_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_1_fu_4505_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_2_fu_4509_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_5_fu_4515_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_6_fu_4519_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_13_fu_4525_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_14_fu_4529_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_29_fu_4535_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_44_fu_4545_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_60_fu_4554_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_45_fu_4549_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_61_fu_4558_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_30_fu_4539_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_62_fu_4563_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (25 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal ap_idle_pp1 : STD_LOGIC;
+    signal ap_enable_pp1 : STD_LOGIC;
+    signal ap_idle_pp2 : STD_LOGIC;
+    signal ap_enable_pp2 : STD_LOGIC;
+    signal ap_idle_pp3 : STD_LOGIC;
+    signal ap_enable_pp3 : STD_LOGIC;
+
+    component mmult_in1_loc_0 IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (5 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_out_loc IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        address1 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_params_s_axi IS
+    generic (
+        C_S_AXI_ADDR_WIDTH : INTEGER;
+        C_S_AXI_DATA_WIDTH : INTEGER );
+    port (
+        AWVALID : IN STD_LOGIC;
+        AWREADY : OUT STD_LOGIC;
+        AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        WVALID : IN STD_LOGIC;
+        WREADY : OUT STD_LOGIC;
+        WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
+        ARVALID : IN STD_LOGIC;
+        ARREADY : OUT STD_LOGIC;
+        ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        RVALID : OUT STD_LOGIC;
+        RREADY : IN STD_LOGIC;
+        RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : OUT STD_LOGIC;
+        BREADY : IN STD_LOGIC;
+        BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        ap_start : OUT STD_LOGIC;
+        interrupt : OUT STD_LOGIC;
+        ap_ready : IN STD_LOGIC;
+        ap_done : IN STD_LOGIC;
+        ap_idle : IN STD_LOGIC;
+        in1 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        in2 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        out_r : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dim : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_in2_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_out_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+
+begin
+    mmult_params_s_axi_U : component mmult_params_s_axi
+    generic map (
+        C_S_AXI_ADDR_WIDTH => C_S_AXI_PARAMS_ADDR_WIDTH,
+        C_S_AXI_DATA_WIDTH => C_S_AXI_PARAMS_DATA_WIDTH)
+    port map (
+        AWVALID => s_axi_params_AWVALID,
+        AWREADY => s_axi_params_AWREADY,
+        AWADDR => s_axi_params_AWADDR,
+        WVALID => s_axi_params_WVALID,
+        WREADY => s_axi_params_WREADY,
+        WDATA => s_axi_params_WDATA,
+        WSTRB => s_axi_params_WSTRB,
+        ARVALID => s_axi_params_ARVALID,
+        ARREADY => s_axi_params_ARREADY,
+        ARADDR => s_axi_params_ARADDR,
+        RVALID => s_axi_params_RVALID,
+        RREADY => s_axi_params_RREADY,
+        RDATA => s_axi_params_RDATA,
+        RRESP => s_axi_params_RRESP,
+        BVALID => s_axi_params_BVALID,
+        BREADY => s_axi_params_BREADY,
+        BRESP => s_axi_params_BRESP,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        ap_start => ap_start,
+        interrupt => interrupt,
+        ap_ready => ap_ready,
+        ap_done => ap_done,
+        ap_idle => ap_idle,
+        in1 => in1,
+        in2 => in2,
+        out_r => out_r,
+        dim => dim);
+
+    mmult_in1_mem_m_axi_U : component mmult_in1_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN1_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN1_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN1_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN1_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN1_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN1_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN1_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN1_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN1_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN1_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN1_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in1_mem_AWVALID,
+        AWREADY => m_axi_in1_mem_AWREADY,
+        AWADDR => m_axi_in1_mem_AWADDR,
+        AWID => m_axi_in1_mem_AWID,
+        AWLEN => m_axi_in1_mem_AWLEN,
+        AWSIZE => m_axi_in1_mem_AWSIZE,
+        AWBURST => m_axi_in1_mem_AWBURST,
+        AWLOCK => m_axi_in1_mem_AWLOCK,
+        AWCACHE => m_axi_in1_mem_AWCACHE,
+        AWPROT => m_axi_in1_mem_AWPROT,
+        AWQOS => m_axi_in1_mem_AWQOS,
+        AWREGION => m_axi_in1_mem_AWREGION,
+        AWUSER => m_axi_in1_mem_AWUSER,
+        WVALID => m_axi_in1_mem_WVALID,
+        WREADY => m_axi_in1_mem_WREADY,
+        WDATA => m_axi_in1_mem_WDATA,
+        WSTRB => m_axi_in1_mem_WSTRB,
+        WLAST => m_axi_in1_mem_WLAST,
+        WID => m_axi_in1_mem_WID,
+        WUSER => m_axi_in1_mem_WUSER,
+        ARVALID => m_axi_in1_mem_ARVALID,
+        ARREADY => m_axi_in1_mem_ARREADY,
+        ARADDR => m_axi_in1_mem_ARADDR,
+        ARID => m_axi_in1_mem_ARID,
+        ARLEN => m_axi_in1_mem_ARLEN,
+        ARSIZE => m_axi_in1_mem_ARSIZE,
+        ARBURST => m_axi_in1_mem_ARBURST,
+        ARLOCK => m_axi_in1_mem_ARLOCK,
+        ARCACHE => m_axi_in1_mem_ARCACHE,
+        ARPROT => m_axi_in1_mem_ARPROT,
+        ARQOS => m_axi_in1_mem_ARQOS,
+        ARREGION => m_axi_in1_mem_ARREGION,
+        ARUSER => m_axi_in1_mem_ARUSER,
+        RVALID => m_axi_in1_mem_RVALID,
+        RREADY => m_axi_in1_mem_RREADY,
+        RDATA => m_axi_in1_mem_RDATA,
+        RLAST => m_axi_in1_mem_RLAST,
+        RID => m_axi_in1_mem_RID,
+        RUSER => m_axi_in1_mem_RUSER,
+        RRESP => m_axi_in1_mem_RRESP,
+        BVALID => m_axi_in1_mem_BVALID,
+        BREADY => m_axi_in1_mem_BREADY,
+        BRESP => m_axi_in1_mem_BRESP,
+        BID => m_axi_in1_mem_BID,
+        BUSER => m_axi_in1_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in1_mem_ARVALID,
+        I_ARREADY => in1_mem_ARREADY,
+        I_ARADDR => in1_mem_ARADDR,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in1_mem_RVALID,
+        I_RREADY => in1_mem_RREADY,
+        I_RDATA => in1_mem_RDATA,
+        I_RID => in1_mem_RID,
+        I_RUSER => in1_mem_RUSER,
+        I_RRESP => in1_mem_RRESP,
+        I_RLAST => in1_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in1_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in1_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in1_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in1_mem_BRESP,
+        I_BID => in1_mem_BID,
+        I_BUSER => in1_mem_BUSER);
+
+    mmult_in2_mem_m_axi_U : component mmult_in2_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN2_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN2_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN2_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN2_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN2_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN2_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN2_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN2_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN2_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN2_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN2_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in2_mem_AWVALID,
+        AWREADY => m_axi_in2_mem_AWREADY,
+        AWADDR => m_axi_in2_mem_AWADDR,
+        AWID => m_axi_in2_mem_AWID,
+        AWLEN => m_axi_in2_mem_AWLEN,
+        AWSIZE => m_axi_in2_mem_AWSIZE,
+        AWBURST => m_axi_in2_mem_AWBURST,
+        AWLOCK => m_axi_in2_mem_AWLOCK,
+        AWCACHE => m_axi_in2_mem_AWCACHE,
+        AWPROT => m_axi_in2_mem_AWPROT,
+        AWQOS => m_axi_in2_mem_AWQOS,
+        AWREGION => m_axi_in2_mem_AWREGION,
+        AWUSER => m_axi_in2_mem_AWUSER,
+        WVALID => m_axi_in2_mem_WVALID,
+        WREADY => m_axi_in2_mem_WREADY,
+        WDATA => m_axi_in2_mem_WDATA,
+        WSTRB => m_axi_in2_mem_WSTRB,
+        WLAST => m_axi_in2_mem_WLAST,
+        WID => m_axi_in2_mem_WID,
+        WUSER => m_axi_in2_mem_WUSER,
+        ARVALID => m_axi_in2_mem_ARVALID,
+        ARREADY => m_axi_in2_mem_ARREADY,
+        ARADDR => m_axi_in2_mem_ARADDR,
+        ARID => m_axi_in2_mem_ARID,
+        ARLEN => m_axi_in2_mem_ARLEN,
+        ARSIZE => m_axi_in2_mem_ARSIZE,
+        ARBURST => m_axi_in2_mem_ARBURST,
+        ARLOCK => m_axi_in2_mem_ARLOCK,
+        ARCACHE => m_axi_in2_mem_ARCACHE,
+        ARPROT => m_axi_in2_mem_ARPROT,
+        ARQOS => m_axi_in2_mem_ARQOS,
+        ARREGION => m_axi_in2_mem_ARREGION,
+        ARUSER => m_axi_in2_mem_ARUSER,
+        RVALID => m_axi_in2_mem_RVALID,
+        RREADY => m_axi_in2_mem_RREADY,
+        RDATA => m_axi_in2_mem_RDATA,
+        RLAST => m_axi_in2_mem_RLAST,
+        RID => m_axi_in2_mem_RID,
+        RUSER => m_axi_in2_mem_RUSER,
+        RRESP => m_axi_in2_mem_RRESP,
+        BVALID => m_axi_in2_mem_BVALID,
+        BREADY => m_axi_in2_mem_BREADY,
+        BRESP => m_axi_in2_mem_BRESP,
+        BID => m_axi_in2_mem_BID,
+        BUSER => m_axi_in2_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in2_mem_ARVALID,
+        I_ARREADY => in2_mem_ARREADY,
+        I_ARADDR => in2_mem_addr_reg_4626,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in2_mem_RVALID,
+        I_RREADY => in2_mem_RREADY,
+        I_RDATA => in2_mem_RDATA,
+        I_RID => in2_mem_RID,
+        I_RUSER => in2_mem_RUSER,
+        I_RRESP => in2_mem_RRESP,
+        I_RLAST => in2_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in2_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in2_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in2_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in2_mem_BRESP,
+        I_BID => in2_mem_BID,
+        I_BUSER => in2_mem_BUSER);
+
+    mmult_out_mem_m_axi_U : component mmult_out_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_OUT_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_OUT_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_OUT_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_OUT_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_OUT_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_OUT_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_OUT_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_OUT_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_OUT_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_OUT_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_OUT_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_out_mem_AWVALID,
+        AWREADY => m_axi_out_mem_AWREADY,
+        AWADDR => m_axi_out_mem_AWADDR,
+        AWID => m_axi_out_mem_AWID,
+        AWLEN => m_axi_out_mem_AWLEN,
+        AWSIZE => m_axi_out_mem_AWSIZE,
+        AWBURST => m_axi_out_mem_AWBURST,
+        AWLOCK => m_axi_out_mem_AWLOCK,
+        AWCACHE => m_axi_out_mem_AWCACHE,
+        AWPROT => m_axi_out_mem_AWPROT,
+        AWQOS => m_axi_out_mem_AWQOS,
+        AWREGION => m_axi_out_mem_AWREGION,
+        AWUSER => m_axi_out_mem_AWUSER,
+        WVALID => m_axi_out_mem_WVALID,
+        WREADY => m_axi_out_mem_WREADY,
+        WDATA => m_axi_out_mem_WDATA,
+        WSTRB => m_axi_out_mem_WSTRB,
+        WLAST => m_axi_out_mem_WLAST,
+        WID => m_axi_out_mem_WID,
+        WUSER => m_axi_out_mem_WUSER,
+        ARVALID => m_axi_out_mem_ARVALID,
+        ARREADY => m_axi_out_mem_ARREADY,
+        ARADDR => m_axi_out_mem_ARADDR,
+        ARID => m_axi_out_mem_ARID,
+        ARLEN => m_axi_out_mem_ARLEN,
+        ARSIZE => m_axi_out_mem_ARSIZE,
+        ARBURST => m_axi_out_mem_ARBURST,
+        ARLOCK => m_axi_out_mem_ARLOCK,
+        ARCACHE => m_axi_out_mem_ARCACHE,
+        ARPROT => m_axi_out_mem_ARPROT,
+        ARQOS => m_axi_out_mem_ARQOS,
+        ARREGION => m_axi_out_mem_ARREGION,
+        ARUSER => m_axi_out_mem_ARUSER,
+        RVALID => m_axi_out_mem_RVALID,
+        RREADY => m_axi_out_mem_RREADY,
+        RDATA => m_axi_out_mem_RDATA,
+        RLAST => m_axi_out_mem_RLAST,
+        RID => m_axi_out_mem_RID,
+        RUSER => m_axi_out_mem_RUSER,
+        RRESP => m_axi_out_mem_RRESP,
+        BVALID => m_axi_out_mem_BVALID,
+        BREADY => m_axi_out_mem_BREADY,
+        BRESP => m_axi_out_mem_BRESP,
+        BID => m_axi_out_mem_BID,
+        BUSER => m_axi_out_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => ap_const_logic_0,
+        I_ARREADY => out_mem_ARREADY,
+        I_ARADDR => ap_const_lv32_0,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_0,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => out_mem_RVALID,
+        I_RREADY => ap_const_logic_0,
+        I_RDATA => out_mem_RDATA,
+        I_RID => out_mem_RID,
+        I_RUSER => out_mem_RUSER,
+        I_RRESP => out_mem_RRESP,
+        I_RLAST => out_mem_RLAST,
+        I_AWVALID => out_mem_AWVALID,
+        I_AWREADY => out_mem_AWREADY,
+        I_AWADDR => out_mem_addr_reg_4620,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_1000,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => out_mem_WVALID,
+        I_WREADY => out_mem_WREADY,
+        I_WDATA => out_loc_load_reg_5563,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_F,
+        I_BVALID => out_mem_BVALID,
+        I_BREADY => out_mem_BREADY,
+        I_BRESP => out_mem_BRESP,
+        I_BID => out_mem_BID,
+        I_BUSER => out_mem_BUSER);
+
+    in1_loc_0_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_0_address0,
+        ce0 => in1_loc_0_ce0,
+        we0 => in1_loc_0_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_0_q0);
+
+    in1_loc_1_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_1_address0,
+        ce0 => in1_loc_1_ce0,
+        we0 => in1_loc_1_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_1_q0);
+
+    in1_loc_2_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_2_address0,
+        ce0 => in1_loc_2_ce0,
+        we0 => in1_loc_2_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_2_q0);
+
+    in1_loc_3_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_3_address0,
+        ce0 => in1_loc_3_ce0,
+        we0 => in1_loc_3_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_3_q0);
+
+    in1_loc_4_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_4_address0,
+        ce0 => in1_loc_4_ce0,
+        we0 => in1_loc_4_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_4_q0);
+
+    in1_loc_5_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_5_address0,
+        ce0 => in1_loc_5_ce0,
+        we0 => in1_loc_5_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_5_q0);
+
+    in1_loc_6_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_6_address0,
+        ce0 => in1_loc_6_ce0,
+        we0 => in1_loc_6_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_6_q0);
+
+    in1_loc_7_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_7_address0,
+        ce0 => in1_loc_7_ce0,
+        we0 => in1_loc_7_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_7_q0);
+
+    in1_loc_8_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_8_address0,
+        ce0 => in1_loc_8_ce0,
+        we0 => in1_loc_8_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_8_q0);
+
+    in1_loc_9_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_9_address0,
+        ce0 => in1_loc_9_ce0,
+        we0 => in1_loc_9_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_9_q0);
+
+    in1_loc_10_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_10_address0,
+        ce0 => in1_loc_10_ce0,
+        we0 => in1_loc_10_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_10_q0);
+
+    in1_loc_11_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_11_address0,
+        ce0 => in1_loc_11_ce0,
+        we0 => in1_loc_11_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_11_q0);
+
+    in1_loc_12_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_12_address0,
+        ce0 => in1_loc_12_ce0,
+        we0 => in1_loc_12_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_12_q0);
+
+    in1_loc_13_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_13_address0,
+        ce0 => in1_loc_13_ce0,
+        we0 => in1_loc_13_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_13_q0);
+
+    in1_loc_14_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_14_address0,
+        ce0 => in1_loc_14_ce0,
+        we0 => in1_loc_14_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_14_q0);
+
+    in1_loc_15_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_15_address0,
+        ce0 => in1_loc_15_ce0,
+        we0 => in1_loc_15_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_15_q0);
+
+    in1_loc_16_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_16_address0,
+        ce0 => in1_loc_16_ce0,
+        we0 => in1_loc_16_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_16_q0);
+
+    in1_loc_17_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_17_address0,
+        ce0 => in1_loc_17_ce0,
+        we0 => in1_loc_17_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_17_q0);
+
+    in1_loc_18_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_18_address0,
+        ce0 => in1_loc_18_ce0,
+        we0 => in1_loc_18_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_18_q0);
+
+    in1_loc_19_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_19_address0,
+        ce0 => in1_loc_19_ce0,
+        we0 => in1_loc_19_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_19_q0);
+
+    in1_loc_20_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_20_address0,
+        ce0 => in1_loc_20_ce0,
+        we0 => in1_loc_20_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_20_q0);
+
+    in1_loc_21_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_21_address0,
+        ce0 => in1_loc_21_ce0,
+        we0 => in1_loc_21_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_21_q0);
+
+    in1_loc_22_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_22_address0,
+        ce0 => in1_loc_22_ce0,
+        we0 => in1_loc_22_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_22_q0);
+
+    in1_loc_23_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_23_address0,
+        ce0 => in1_loc_23_ce0,
+        we0 => in1_loc_23_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_23_q0);
+
+    in1_loc_24_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_24_address0,
+        ce0 => in1_loc_24_ce0,
+        we0 => in1_loc_24_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_24_q0);
+
+    in1_loc_25_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_25_address0,
+        ce0 => in1_loc_25_ce0,
+        we0 => in1_loc_25_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_25_q0);
+
+    in1_loc_26_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_26_address0,
+        ce0 => in1_loc_26_ce0,
+        we0 => in1_loc_26_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_26_q0);
+
+    in1_loc_27_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_27_address0,
+        ce0 => in1_loc_27_ce0,
+        we0 => in1_loc_27_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_27_q0);
+
+    in1_loc_28_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_28_address0,
+        ce0 => in1_loc_28_ce0,
+        we0 => in1_loc_28_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_28_q0);
+
+    in1_loc_29_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_29_address0,
+        ce0 => in1_loc_29_ce0,
+        we0 => in1_loc_29_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_29_q0);
+
+    in1_loc_30_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_30_address0,
+        ce0 => in1_loc_30_ce0,
+        we0 => in1_loc_30_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_30_q0);
+
+    in1_loc_31_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_31_address0,
+        ce0 => in1_loc_31_ce0,
+        we0 => in1_loc_31_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_31_q0);
+
+    in1_loc_32_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_32_address0,
+        ce0 => in1_loc_32_ce0,
+        we0 => in1_loc_32_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_32_q0);
+
+    in1_loc_33_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_33_address0,
+        ce0 => in1_loc_33_ce0,
+        we0 => in1_loc_33_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_33_q0);
+
+    in1_loc_34_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_34_address0,
+        ce0 => in1_loc_34_ce0,
+        we0 => in1_loc_34_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_34_q0);
+
+    in1_loc_35_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_35_address0,
+        ce0 => in1_loc_35_ce0,
+        we0 => in1_loc_35_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_35_q0);
+
+    in1_loc_36_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_36_address0,
+        ce0 => in1_loc_36_ce0,
+        we0 => in1_loc_36_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_36_q0);
+
+    in1_loc_37_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_37_address0,
+        ce0 => in1_loc_37_ce0,
+        we0 => in1_loc_37_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_37_q0);
+
+    in1_loc_38_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_38_address0,
+        ce0 => in1_loc_38_ce0,
+        we0 => in1_loc_38_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_38_q0);
+
+    in1_loc_39_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_39_address0,
+        ce0 => in1_loc_39_ce0,
+        we0 => in1_loc_39_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_39_q0);
+
+    in1_loc_40_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_40_address0,
+        ce0 => in1_loc_40_ce0,
+        we0 => in1_loc_40_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_40_q0);
+
+    in1_loc_41_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_41_address0,
+        ce0 => in1_loc_41_ce0,
+        we0 => in1_loc_41_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_41_q0);
+
+    in1_loc_42_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_42_address0,
+        ce0 => in1_loc_42_ce0,
+        we0 => in1_loc_42_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_42_q0);
+
+    in1_loc_43_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_43_address0,
+        ce0 => in1_loc_43_ce0,
+        we0 => in1_loc_43_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_43_q0);
+
+    in1_loc_44_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_44_address0,
+        ce0 => in1_loc_44_ce0,
+        we0 => in1_loc_44_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_44_q0);
+
+    in1_loc_45_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_45_address0,
+        ce0 => in1_loc_45_ce0,
+        we0 => in1_loc_45_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_45_q0);
+
+    in1_loc_46_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_46_address0,
+        ce0 => in1_loc_46_ce0,
+        we0 => in1_loc_46_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_46_q0);
+
+    in1_loc_47_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_47_address0,
+        ce0 => in1_loc_47_ce0,
+        we0 => in1_loc_47_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_47_q0);
+
+    in1_loc_48_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_48_address0,
+        ce0 => in1_loc_48_ce0,
+        we0 => in1_loc_48_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_48_q0);
+
+    in1_loc_49_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_49_address0,
+        ce0 => in1_loc_49_ce0,
+        we0 => in1_loc_49_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_49_q0);
+
+    in1_loc_50_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_50_address0,
+        ce0 => in1_loc_50_ce0,
+        we0 => in1_loc_50_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_50_q0);
+
+    in1_loc_51_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_51_address0,
+        ce0 => in1_loc_51_ce0,
+        we0 => in1_loc_51_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_51_q0);
+
+    in1_loc_52_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_52_address0,
+        ce0 => in1_loc_52_ce0,
+        we0 => in1_loc_52_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_52_q0);
+
+    in1_loc_53_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_53_address0,
+        ce0 => in1_loc_53_ce0,
+        we0 => in1_loc_53_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_53_q0);
+
+    in1_loc_54_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_54_address0,
+        ce0 => in1_loc_54_ce0,
+        we0 => in1_loc_54_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_54_q0);
+
+    in1_loc_55_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_55_address0,
+        ce0 => in1_loc_55_ce0,
+        we0 => in1_loc_55_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_55_q0);
+
+    in1_loc_56_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_56_address0,
+        ce0 => in1_loc_56_ce0,
+        we0 => in1_loc_56_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_56_q0);
+
+    in1_loc_57_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_57_address0,
+        ce0 => in1_loc_57_ce0,
+        we0 => in1_loc_57_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_57_q0);
+
+    in1_loc_58_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_58_address0,
+        ce0 => in1_loc_58_ce0,
+        we0 => in1_loc_58_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_58_q0);
+
+    in1_loc_59_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_59_address0,
+        ce0 => in1_loc_59_ce0,
+        we0 => in1_loc_59_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_59_q0);
+
+    in1_loc_60_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_60_address0,
+        ce0 => in1_loc_60_ce0,
+        we0 => in1_loc_60_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_60_q0);
+
+    in1_loc_61_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_61_address0,
+        ce0 => in1_loc_61_ce0,
+        we0 => in1_loc_61_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_61_q0);
+
+    in1_loc_62_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_62_address0,
+        ce0 => in1_loc_62_ce0,
+        we0 => in1_loc_62_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_62_q0);
+
+    in1_loc_63_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_63_address0,
+        ce0 => in1_loc_63_ce0,
+        we0 => in1_loc_63_we0,
+        d0 => in1_mem_addr_read_reg_4650,
+        q0 => in1_loc_63_q0);
+
+    in2_loc_0_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_0_address0,
+        ce0 => in2_loc_0_ce0,
+        we0 => in2_loc_0_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_0_q0);
+
+    in2_loc_1_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_1_address0,
+        ce0 => in2_loc_1_ce0,
+        we0 => in2_loc_1_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_1_q0);
+
+    in2_loc_2_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_2_address0,
+        ce0 => in2_loc_2_ce0,
+        we0 => in2_loc_2_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_2_q0);
+
+    in2_loc_3_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_3_address0,
+        ce0 => in2_loc_3_ce0,
+        we0 => in2_loc_3_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_3_q0);
+
+    in2_loc_4_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_4_address0,
+        ce0 => in2_loc_4_ce0,
+        we0 => in2_loc_4_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_4_q0);
+
+    in2_loc_5_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_5_address0,
+        ce0 => in2_loc_5_ce0,
+        we0 => in2_loc_5_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_5_q0);
+
+    in2_loc_6_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_6_address0,
+        ce0 => in2_loc_6_ce0,
+        we0 => in2_loc_6_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_6_q0);
+
+    in2_loc_7_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_7_address0,
+        ce0 => in2_loc_7_ce0,
+        we0 => in2_loc_7_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_7_q0);
+
+    in2_loc_8_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_8_address0,
+        ce0 => in2_loc_8_ce0,
+        we0 => in2_loc_8_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_8_q0);
+
+    in2_loc_9_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_9_address0,
+        ce0 => in2_loc_9_ce0,
+        we0 => in2_loc_9_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_9_q0);
+
+    in2_loc_10_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_10_address0,
+        ce0 => in2_loc_10_ce0,
+        we0 => in2_loc_10_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_10_q0);
+
+    in2_loc_11_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_11_address0,
+        ce0 => in2_loc_11_ce0,
+        we0 => in2_loc_11_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_11_q0);
+
+    in2_loc_12_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_12_address0,
+        ce0 => in2_loc_12_ce0,
+        we0 => in2_loc_12_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_12_q0);
+
+    in2_loc_13_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_13_address0,
+        ce0 => in2_loc_13_ce0,
+        we0 => in2_loc_13_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_13_q0);
+
+    in2_loc_14_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_14_address0,
+        ce0 => in2_loc_14_ce0,
+        we0 => in2_loc_14_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_14_q0);
+
+    in2_loc_15_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_15_address0,
+        ce0 => in2_loc_15_ce0,
+        we0 => in2_loc_15_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_15_q0);
+
+    in2_loc_16_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_16_address0,
+        ce0 => in2_loc_16_ce0,
+        we0 => in2_loc_16_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_16_q0);
+
+    in2_loc_17_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_17_address0,
+        ce0 => in2_loc_17_ce0,
+        we0 => in2_loc_17_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_17_q0);
+
+    in2_loc_18_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_18_address0,
+        ce0 => in2_loc_18_ce0,
+        we0 => in2_loc_18_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_18_q0);
+
+    in2_loc_19_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_19_address0,
+        ce0 => in2_loc_19_ce0,
+        we0 => in2_loc_19_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_19_q0);
+
+    in2_loc_20_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_20_address0,
+        ce0 => in2_loc_20_ce0,
+        we0 => in2_loc_20_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_20_q0);
+
+    in2_loc_21_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_21_address0,
+        ce0 => in2_loc_21_ce0,
+        we0 => in2_loc_21_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_21_q0);
+
+    in2_loc_22_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_22_address0,
+        ce0 => in2_loc_22_ce0,
+        we0 => in2_loc_22_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_22_q0);
+
+    in2_loc_23_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_23_address0,
+        ce0 => in2_loc_23_ce0,
+        we0 => in2_loc_23_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_23_q0);
+
+    in2_loc_24_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_24_address0,
+        ce0 => in2_loc_24_ce0,
+        we0 => in2_loc_24_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_24_q0);
+
+    in2_loc_25_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_25_address0,
+        ce0 => in2_loc_25_ce0,
+        we0 => in2_loc_25_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_25_q0);
+
+    in2_loc_26_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_26_address0,
+        ce0 => in2_loc_26_ce0,
+        we0 => in2_loc_26_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_26_q0);
+
+    in2_loc_27_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_27_address0,
+        ce0 => in2_loc_27_ce0,
+        we0 => in2_loc_27_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_27_q0);
+
+    in2_loc_28_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_28_address0,
+        ce0 => in2_loc_28_ce0,
+        we0 => in2_loc_28_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_28_q0);
+
+    in2_loc_29_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_29_address0,
+        ce0 => in2_loc_29_ce0,
+        we0 => in2_loc_29_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_29_q0);
+
+    in2_loc_30_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_30_address0,
+        ce0 => in2_loc_30_ce0,
+        we0 => in2_loc_30_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_30_q0);
+
+    in2_loc_31_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_31_address0,
+        ce0 => in2_loc_31_ce0,
+        we0 => in2_loc_31_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_31_q0);
+
+    in2_loc_32_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_32_address0,
+        ce0 => in2_loc_32_ce0,
+        we0 => in2_loc_32_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_32_q0);
+
+    in2_loc_33_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_33_address0,
+        ce0 => in2_loc_33_ce0,
+        we0 => in2_loc_33_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_33_q0);
+
+    in2_loc_34_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_34_address0,
+        ce0 => in2_loc_34_ce0,
+        we0 => in2_loc_34_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_34_q0);
+
+    in2_loc_35_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_35_address0,
+        ce0 => in2_loc_35_ce0,
+        we0 => in2_loc_35_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_35_q0);
+
+    in2_loc_36_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_36_address0,
+        ce0 => in2_loc_36_ce0,
+        we0 => in2_loc_36_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_36_q0);
+
+    in2_loc_37_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_37_address0,
+        ce0 => in2_loc_37_ce0,
+        we0 => in2_loc_37_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_37_q0);
+
+    in2_loc_38_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_38_address0,
+        ce0 => in2_loc_38_ce0,
+        we0 => in2_loc_38_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_38_q0);
+
+    in2_loc_39_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_39_address0,
+        ce0 => in2_loc_39_ce0,
+        we0 => in2_loc_39_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_39_q0);
+
+    in2_loc_40_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_40_address0,
+        ce0 => in2_loc_40_ce0,
+        we0 => in2_loc_40_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_40_q0);
+
+    in2_loc_41_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_41_address0,
+        ce0 => in2_loc_41_ce0,
+        we0 => in2_loc_41_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_41_q0);
+
+    in2_loc_42_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_42_address0,
+        ce0 => in2_loc_42_ce0,
+        we0 => in2_loc_42_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_42_q0);
+
+    in2_loc_43_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_43_address0,
+        ce0 => in2_loc_43_ce0,
+        we0 => in2_loc_43_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_43_q0);
+
+    in2_loc_44_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_44_address0,
+        ce0 => in2_loc_44_ce0,
+        we0 => in2_loc_44_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_44_q0);
+
+    in2_loc_45_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_45_address0,
+        ce0 => in2_loc_45_ce0,
+        we0 => in2_loc_45_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_45_q0);
+
+    in2_loc_46_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_46_address0,
+        ce0 => in2_loc_46_ce0,
+        we0 => in2_loc_46_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_46_q0);
+
+    in2_loc_47_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_47_address0,
+        ce0 => in2_loc_47_ce0,
+        we0 => in2_loc_47_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_47_q0);
+
+    in2_loc_48_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_48_address0,
+        ce0 => in2_loc_48_ce0,
+        we0 => in2_loc_48_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_48_q0);
+
+    in2_loc_49_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_49_address0,
+        ce0 => in2_loc_49_ce0,
+        we0 => in2_loc_49_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_49_q0);
+
+    in2_loc_50_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_50_address0,
+        ce0 => in2_loc_50_ce0,
+        we0 => in2_loc_50_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_50_q0);
+
+    in2_loc_51_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_51_address0,
+        ce0 => in2_loc_51_ce0,
+        we0 => in2_loc_51_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_51_q0);
+
+    in2_loc_52_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_52_address0,
+        ce0 => in2_loc_52_ce0,
+        we0 => in2_loc_52_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_52_q0);
+
+    in2_loc_53_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_53_address0,
+        ce0 => in2_loc_53_ce0,
+        we0 => in2_loc_53_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_53_q0);
+
+    in2_loc_54_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_54_address0,
+        ce0 => in2_loc_54_ce0,
+        we0 => in2_loc_54_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_54_q0);
+
+    in2_loc_55_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_55_address0,
+        ce0 => in2_loc_55_ce0,
+        we0 => in2_loc_55_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_55_q0);
+
+    in2_loc_56_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_56_address0,
+        ce0 => in2_loc_56_ce0,
+        we0 => in2_loc_56_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_56_q0);
+
+    in2_loc_57_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_57_address0,
+        ce0 => in2_loc_57_ce0,
+        we0 => in2_loc_57_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_57_q0);
+
+    in2_loc_58_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_58_address0,
+        ce0 => in2_loc_58_ce0,
+        we0 => in2_loc_58_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_58_q0);
+
+    in2_loc_59_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_59_address0,
+        ce0 => in2_loc_59_ce0,
+        we0 => in2_loc_59_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_59_q0);
+
+    in2_loc_60_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_60_address0,
+        ce0 => in2_loc_60_ce0,
+        we0 => in2_loc_60_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_60_q0);
+
+    in2_loc_61_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_61_address0,
+        ce0 => in2_loc_61_ce0,
+        we0 => in2_loc_61_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_61_q0);
+
+    in2_loc_62_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_62_address0,
+        ce0 => in2_loc_62_ce0,
+        we0 => in2_loc_62_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_62_q0);
+
+    in2_loc_63_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_63_address0,
+        ce0 => in2_loc_63_ce0,
+        we0 => in2_loc_63_we0,
+        d0 => in2_mem_addr_read_reg_4736,
+        q0 => in2_loc_63_q0);
+
+    out_loc_U : component mmult_out_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => out_loc_address0,
+        ce0 => out_loc_ce0,
+        q0 => out_loc_q0,
+        address1 => out_loc_addr_reg_5143_pp2_iter1_reg,
+        ce1 => out_loc_ce1,
+        we1 => out_loc_we1,
+        d1 => out_loc_d1);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state9);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19))) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19)) then 
+                        ap_enable_reg_pp1_iter1 <= (ap_const_logic_1 xor ap_condition_pp1_exit_iter0_state19);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_condition_pp2_exit_iter0_state23) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp2_exit_iter0_state23)) then 
+                        ap_enable_reg_pp2_iter1 <= (ap_const_logic_1 xor ap_condition_pp2_exit_iter0_state23);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                    ap_enable_reg_pp2_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_const_logic_1 = ap_condition_pp3_exit_iter0_state27) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone))) then 
+                    ap_enable_reg_pp3_iter0 <= ap_const_logic_0;
+                elsif (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state26))) then 
+                    ap_enable_reg_pp3_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp3_exit_iter0_state27)) then 
+                        ap_enable_reg_pp3_iter1 <= (ap_const_logic_1 xor ap_condition_pp3_exit_iter0_state27);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp3_iter1 <= ap_enable_reg_pp3_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) then 
+                    ap_enable_reg_pp3_iter2 <= ap_enable_reg_pp3_iter1;
+                elsif (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state26))) then 
+                    ap_enable_reg_pp3_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0_reg_3329_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4809 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+                i_0_reg_3329 <= select_ln31_1_reg_4818;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                i_0_reg_3329 <= ap_const_lv31_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_3318_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+                indvar_flatten_reg_3318 <= add_ln31_fu_3620_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                indvar_flatten_reg_3318 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    j_0_reg_3340_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+                j_0_reg_3340 <= j_fu_3816_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                j_0_reg_3340 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln27_reg_3296_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_fu_3420_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                phi_ln27_reg_3296 <= add_ln27_fu_3426_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                phi_ln27_reg_3296 <= ap_const_lv13_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln28_reg_3307_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                phi_ln28_reg_3307 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_fu_3513_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+                phi_ln28_reg_3307 <= add_ln28_fu_3519_p2;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln42_reg_3351_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state26))) then 
+                phi_ln42_reg_3351 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_fu_4576_p2 = ap_const_lv1_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then 
+                phi_ln42_reg_3351 <= add_ln42_fu_4582_p2;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4809 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                add_ln38_12_reg_5504 <= add_ln38_12_fu_4248_p2;
+                add_ln38_21_reg_5509 <= add_ln38_21_fu_4290_p2;
+                add_ln38_28_reg_5514 <= add_ln38_28_fu_4332_p2;
+                add_ln38_37_reg_5519 <= add_ln38_37_fu_4374_p2;
+                add_ln38_3_reg_5489 <= add_ln38_3_fu_4206_p2;
+                add_ln38_40_reg_5524 <= add_ln38_40_fu_4392_p2;
+                add_ln38_43_reg_5529 <= add_ln38_43_fu_4410_p2;
+                add_ln38_4_reg_5494 <= add_ln38_4_fu_4212_p2;
+                add_ln38_52_reg_5534 <= add_ln38_52_fu_4452_p2;
+                add_ln38_55_reg_5539 <= add_ln38_55_fu_4470_p2;
+                add_ln38_59_reg_5544 <= add_ln38_59_fu_4494_p2;
+                add_ln38_9_reg_5499 <= add_ln38_9_fu_4230_p2;
+                mul_ln38_1_reg_5479 <= mul_ln38_1_fu_3828_p2;
+                mul_ln38_2_reg_5484 <= mul_ln38_2_fu_3834_p2;
+                mul_ln38_reg_5474 <= mul_ln38_fu_3822_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                dim_read_reg_4593 <= dim;
+                in3_reg_4609 <= in1(31 downto 2);
+                in_reg_4604 <= in2(31 downto 2);
+                out5_reg_4599 <= out_r(31 downto 2);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                icmp_ln31_reg_4809 <= icmp_ln31_fu_3615_p2;
+                icmp_ln31_reg_4809_pp2_iter1_reg <= icmp_ln31_reg_4809;
+                out_loc_addr_reg_5143_pp2_iter1_reg <= out_loc_addr_reg_5143;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then
+                icmp_ln42_reg_5549 <= icmp_ln42_fu_4576_p2;
+                icmp_ln42_reg_5549_pp3_iter1_reg <= icmp_ln42_reg_5549;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                in1_mem_addr_read_reg_4650 <= in1_mem_RDATA;
+                lshr_ln_reg_4641_pp0_iter1_reg <= lshr_ln_reg_4641;
+                trunc_ln27_reg_4646_pp0_iter1_reg <= trunc_ln27_reg_4646;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                in2_mem_addr_read_reg_4736 <= in2_mem_RDATA;
+                trunc_ln1_reg_4732_pp1_iter1_reg <= trunc_ln1_reg_4732;
+                trunc_ln28_reg_4727_pp1_iter1_reg <= trunc_ln28_reg_4727;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
+                    in2_mem_addr_reg_4626(29 downto 0) <= empty_7_fu_3411_p1(32 - 1 downto 0)(29 downto 0);
+                    out_mem_addr_reg_4620(29 downto 0) <= empty_fu_3402_p1(32 - 1 downto 0)(29 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_fu_3420_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                lshr_ln_reg_4641 <= phi_ln27_reg_3296(12 downto 6);
+                trunc_ln27_reg_4646 <= trunc_ln27_fu_3442_p1;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state22)) then
+                mul_ln31_reg_4804 <= mul_ln31_fu_3609_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                out_loc_addr_reg_5143 <= zext_ln38_fu_3811_p1(12 - 1 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_reg_5549 = ap_const_lv1_0) and (ap_enable_reg_pp3_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then
+                out_loc_load_reg_5563 <= out_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                select_ln31_1_reg_4818 <= select_ln31_1_fu_3645_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_fu_3513_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                trunc_ln1_reg_4732 <= phi_ln28_reg_3307(11 downto 6);
+                trunc_ln28_reg_4727 <= trunc_ln28_fu_3525_p1;
+            end if;
+        end if;
+    end process;
+    out_mem_addr_reg_4620(31 downto 30) <= "00";
+    in2_mem_addr_reg_4626(31 downto 30) <= "00";
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_enable_reg_pp0_iter1, ap_CS_fsm_state12, ap_enable_reg_pp1_iter1, ap_CS_fsm_state26, ap_enable_reg_pp3_iter2, ap_CS_fsm_state34, in1_mem_ARREADY, in2_mem_ARREADY, out_mem_AWREADY, out_mem_BVALID, icmp_ln27_fu_3420_p2, ap_enable_reg_pp0_iter0, icmp_ln28_fu_3513_p2, ap_enable_reg_pp1_iter0, icmp_ln31_fu_3615_p2, ap_enable_reg_pp2_iter0, icmp_ln42_fu_4576_p2, ap_enable_reg_pp3_iter0, ap_enable_reg_pp3_iter1, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter2, ap_block_pp1_stage0_subdone, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0_subdone, ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter2, ap_block_pp3_stage0_subdone)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when ap_ST_fsm_state3 => 
+                ap_NS_fsm <= ap_ST_fsm_state4;
+            when ap_ST_fsm_state4 => 
+                ap_NS_fsm <= ap_ST_fsm_state5;
+            when ap_ST_fsm_state5 => 
+                ap_NS_fsm <= ap_ST_fsm_state6;
+            when ap_ST_fsm_state6 => 
+                ap_NS_fsm <= ap_ST_fsm_state7;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state8;
+            when ap_ST_fsm_state8 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (icmp_ln27_fu_3420_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (icmp_ln27_fu_3420_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state12 => 
+                if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then
+                    ap_NS_fsm <= ap_ST_fsm_state13;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                end if;
+            when ap_ST_fsm_state13 => 
+                ap_NS_fsm <= ap_ST_fsm_state14;
+            when ap_ST_fsm_state14 => 
+                ap_NS_fsm <= ap_ST_fsm_state15;
+            when ap_ST_fsm_state15 => 
+                ap_NS_fsm <= ap_ST_fsm_state16;
+            when ap_ST_fsm_state16 => 
+                ap_NS_fsm <= ap_ST_fsm_state17;
+            when ap_ST_fsm_state17 => 
+                ap_NS_fsm <= ap_ST_fsm_state18;
+            when ap_ST_fsm_state18 => 
+                ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+            when ap_ST_fsm_pp1_stage0 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (icmp_ln28_fu_3513_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                elsif ((((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (icmp_ln28_fu_3513_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state22;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                end if;
+            when ap_ST_fsm_state22 => 
+                ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+            when ap_ST_fsm_pp2_stage0 => 
+                if ((not(((icmp_ln31_fu_3615_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))) and not(((ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                elsif ((((icmp_ln31_fu_3615_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) or ((ap_enable_reg_pp2_iter2 = ap_const_logic_1) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state26;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                end if;
+            when ap_ST_fsm_state26 => 
+                if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state26))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state26;
+                end if;
+            when ap_ST_fsm_pp3_stage0 => 
+                if ((not(((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (icmp_ln42_fu_4576_p2 = ap_const_lv1_1) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone))) and not(((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                elsif ((((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (icmp_ln42_fu_4576_p2 = ap_const_lv1_1) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) or ((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state30;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                end if;
+            when ap_ST_fsm_state30 => 
+                ap_NS_fsm <= ap_ST_fsm_state31;
+            when ap_ST_fsm_state31 => 
+                ap_NS_fsm <= ap_ST_fsm_state32;
+            when ap_ST_fsm_state32 => 
+                ap_NS_fsm <= ap_ST_fsm_state33;
+            when ap_ST_fsm_state33 => 
+                ap_NS_fsm <= ap_ST_fsm_state34;
+            when ap_ST_fsm_state34 => 
+                if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state34;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXX";
+        end case;
+    end process;
+    add_ln27_fu_3426_p2 <= std_logic_vector(unsigned(phi_ln27_reg_3296) + unsigned(ap_const_lv13_1));
+    add_ln28_fu_3519_p2 <= std_logic_vector(unsigned(phi_ln28_reg_3307) + unsigned(ap_const_lv13_1));
+    add_ln31_fu_3620_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_3318) + unsigned(ap_const_lv64_1));
+    add_ln38_10_fu_4236_p2 <= std_logic_vector(unsigned(mul_ln38_12_fu_3894_p2) + unsigned(mul_ln38_11_fu_3888_p2));
+    add_ln38_11_fu_4242_p2 <= std_logic_vector(unsigned(mul_ln38_14_fu_3906_p2) + unsigned(mul_ln38_13_fu_3900_p2));
+    add_ln38_12_fu_4248_p2 <= std_logic_vector(unsigned(add_ln38_10_fu_4236_p2) + unsigned(add_ln38_11_fu_4242_p2));
+    add_ln38_13_fu_4525_p2 <= std_logic_vector(unsigned(add_ln38_9_reg_5499) + unsigned(add_ln38_12_reg_5504));
+    add_ln38_14_fu_4529_p2 <= std_logic_vector(unsigned(add_ln38_6_fu_4519_p2) + unsigned(add_ln38_13_fu_4525_p2));
+    add_ln38_15_fu_4254_p2 <= std_logic_vector(unsigned(mul_ln38_16_fu_3918_p2) + unsigned(mul_ln38_15_fu_3912_p2));
+    add_ln38_16_fu_4260_p2 <= std_logic_vector(unsigned(mul_ln38_18_fu_3930_p2) + unsigned(mul_ln38_17_fu_3924_p2));
+    add_ln38_17_fu_4266_p2 <= std_logic_vector(unsigned(add_ln38_15_fu_4254_p2) + unsigned(add_ln38_16_fu_4260_p2));
+    add_ln38_18_fu_4272_p2 <= std_logic_vector(unsigned(mul_ln38_20_fu_3942_p2) + unsigned(mul_ln38_19_fu_3936_p2));
+    add_ln38_19_fu_4278_p2 <= std_logic_vector(unsigned(mul_ln38_22_fu_3954_p2) + unsigned(mul_ln38_21_fu_3948_p2));
+    add_ln38_1_fu_4505_p2 <= std_logic_vector(unsigned(mul_ln38_2_reg_5484) + unsigned(mul_ln38_1_reg_5479));
+    add_ln38_20_fu_4284_p2 <= std_logic_vector(unsigned(add_ln38_18_fu_4272_p2) + unsigned(add_ln38_19_fu_4278_p2));
+    add_ln38_21_fu_4290_p2 <= std_logic_vector(unsigned(add_ln38_17_fu_4266_p2) + unsigned(add_ln38_20_fu_4284_p2));
+    add_ln38_22_fu_4296_p2 <= std_logic_vector(unsigned(mul_ln38_24_fu_3966_p2) + unsigned(mul_ln38_23_fu_3960_p2));
+    add_ln38_23_fu_4302_p2 <= std_logic_vector(unsigned(mul_ln38_26_fu_3978_p2) + unsigned(mul_ln38_25_fu_3972_p2));
+    add_ln38_24_fu_4308_p2 <= std_logic_vector(unsigned(add_ln38_22_fu_4296_p2) + unsigned(add_ln38_23_fu_4302_p2));
+    add_ln38_25_fu_4314_p2 <= std_logic_vector(unsigned(mul_ln38_28_fu_3990_p2) + unsigned(mul_ln38_27_fu_3984_p2));
+    add_ln38_26_fu_4320_p2 <= std_logic_vector(unsigned(mul_ln38_30_fu_4002_p2) + unsigned(mul_ln38_29_fu_3996_p2));
+    add_ln38_27_fu_4326_p2 <= std_logic_vector(unsigned(add_ln38_25_fu_4314_p2) + unsigned(add_ln38_26_fu_4320_p2));
+    add_ln38_28_fu_4332_p2 <= std_logic_vector(unsigned(add_ln38_24_fu_4308_p2) + unsigned(add_ln38_27_fu_4326_p2));
+    add_ln38_29_fu_4535_p2 <= std_logic_vector(unsigned(add_ln38_21_reg_5509) + unsigned(add_ln38_28_reg_5514));
+    add_ln38_2_fu_4509_p2 <= std_logic_vector(unsigned(add_ln38_fu_4500_p2) + unsigned(add_ln38_1_fu_4505_p2));
+    add_ln38_30_fu_4539_p2 <= std_logic_vector(unsigned(add_ln38_14_fu_4529_p2) + unsigned(add_ln38_29_fu_4535_p2));
+    add_ln38_31_fu_4338_p2 <= std_logic_vector(unsigned(mul_ln38_32_fu_4014_p2) + unsigned(mul_ln38_31_fu_4008_p2));
+    add_ln38_32_fu_4344_p2 <= std_logic_vector(unsigned(mul_ln38_34_fu_4026_p2) + unsigned(mul_ln38_33_fu_4020_p2));
+    add_ln38_33_fu_4350_p2 <= std_logic_vector(unsigned(add_ln38_31_fu_4338_p2) + unsigned(add_ln38_32_fu_4344_p2));
+    add_ln38_34_fu_4356_p2 <= std_logic_vector(unsigned(mul_ln38_36_fu_4038_p2) + unsigned(mul_ln38_35_fu_4032_p2));
+    add_ln38_35_fu_4362_p2 <= std_logic_vector(unsigned(mul_ln38_38_fu_4050_p2) + unsigned(mul_ln38_37_fu_4044_p2));
+    add_ln38_36_fu_4368_p2 <= std_logic_vector(unsigned(add_ln38_34_fu_4356_p2) + unsigned(add_ln38_35_fu_4362_p2));
+    add_ln38_37_fu_4374_p2 <= std_logic_vector(unsigned(add_ln38_33_fu_4350_p2) + unsigned(add_ln38_36_fu_4368_p2));
+    add_ln38_38_fu_4380_p2 <= std_logic_vector(unsigned(mul_ln38_40_fu_4062_p2) + unsigned(mul_ln38_39_fu_4056_p2));
+    add_ln38_39_fu_4386_p2 <= std_logic_vector(unsigned(mul_ln38_42_fu_4074_p2) + unsigned(mul_ln38_41_fu_4068_p2));
+    add_ln38_3_fu_4206_p2 <= std_logic_vector(unsigned(mul_ln38_4_fu_3846_p2) + unsigned(mul_ln38_3_fu_3840_p2));
+    add_ln38_40_fu_4392_p2 <= std_logic_vector(unsigned(add_ln38_38_fu_4380_p2) + unsigned(add_ln38_39_fu_4386_p2));
+    add_ln38_41_fu_4398_p2 <= std_logic_vector(unsigned(mul_ln38_44_fu_4086_p2) + unsigned(mul_ln38_43_fu_4080_p2));
+    add_ln38_42_fu_4404_p2 <= std_logic_vector(unsigned(mul_ln38_46_fu_4098_p2) + unsigned(mul_ln38_45_fu_4092_p2));
+    add_ln38_43_fu_4410_p2 <= std_logic_vector(unsigned(add_ln38_41_fu_4398_p2) + unsigned(add_ln38_42_fu_4404_p2));
+    add_ln38_44_fu_4545_p2 <= std_logic_vector(unsigned(add_ln38_40_reg_5524) + unsigned(add_ln38_43_reg_5529));
+    add_ln38_45_fu_4549_p2 <= std_logic_vector(unsigned(add_ln38_37_reg_5519) + unsigned(add_ln38_44_fu_4545_p2));
+    add_ln38_46_fu_4416_p2 <= std_logic_vector(unsigned(mul_ln38_48_fu_4110_p2) + unsigned(mul_ln38_47_fu_4104_p2));
+    add_ln38_47_fu_4422_p2 <= std_logic_vector(unsigned(mul_ln38_50_fu_4122_p2) + unsigned(mul_ln38_49_fu_4116_p2));
+    add_ln38_48_fu_4428_p2 <= std_logic_vector(unsigned(add_ln38_46_fu_4416_p2) + unsigned(add_ln38_47_fu_4422_p2));
+    add_ln38_49_fu_4434_p2 <= std_logic_vector(unsigned(mul_ln38_52_fu_4134_p2) + unsigned(mul_ln38_51_fu_4128_p2));
+    add_ln38_4_fu_4212_p2 <= std_logic_vector(unsigned(mul_ln38_6_fu_3858_p2) + unsigned(mul_ln38_5_fu_3852_p2));
+    add_ln38_50_fu_4440_p2 <= std_logic_vector(unsigned(mul_ln38_54_fu_4146_p2) + unsigned(mul_ln38_53_fu_4140_p2));
+    add_ln38_51_fu_4446_p2 <= std_logic_vector(unsigned(add_ln38_49_fu_4434_p2) + unsigned(add_ln38_50_fu_4440_p2));
+    add_ln38_52_fu_4452_p2 <= std_logic_vector(unsigned(add_ln38_48_fu_4428_p2) + unsigned(add_ln38_51_fu_4446_p2));
+    add_ln38_53_fu_4458_p2 <= std_logic_vector(unsigned(mul_ln38_56_fu_4158_p2) + unsigned(mul_ln38_55_fu_4152_p2));
+    add_ln38_54_fu_4464_p2 <= std_logic_vector(unsigned(mul_ln38_58_fu_4170_p2) + unsigned(mul_ln38_57_fu_4164_p2));
+    add_ln38_55_fu_4470_p2 <= std_logic_vector(unsigned(add_ln38_53_fu_4458_p2) + unsigned(add_ln38_54_fu_4464_p2));
+    add_ln38_56_fu_4476_p2 <= std_logic_vector(unsigned(mul_ln38_60_fu_4182_p2) + unsigned(mul_ln38_59_fu_4176_p2));
+    add_ln38_57_fu_4482_p2 <= std_logic_vector(unsigned(mul_ln38_63_fu_4200_p2) + unsigned(mul_ln38_62_fu_4194_p2));
+    add_ln38_58_fu_4488_p2 <= std_logic_vector(unsigned(mul_ln38_61_fu_4188_p2) + unsigned(add_ln38_57_fu_4482_p2));
+    add_ln38_59_fu_4494_p2 <= std_logic_vector(unsigned(add_ln38_56_fu_4476_p2) + unsigned(add_ln38_58_fu_4488_p2));
+    add_ln38_5_fu_4515_p2 <= std_logic_vector(unsigned(add_ln38_3_reg_5489) + unsigned(add_ln38_4_reg_5494));
+    add_ln38_60_fu_4554_p2 <= std_logic_vector(unsigned(add_ln38_55_reg_5539) + unsigned(add_ln38_59_reg_5544));
+    add_ln38_61_fu_4558_p2 <= std_logic_vector(unsigned(add_ln38_52_reg_5534) + unsigned(add_ln38_60_fu_4554_p2));
+    add_ln38_62_fu_4563_p2 <= std_logic_vector(unsigned(add_ln38_45_fu_4549_p2) + unsigned(add_ln38_61_fu_4558_p2));
+    add_ln38_64_fu_3805_p2 <= std_logic_vector(unsigned(tmp_cast_fu_3657_p3) + unsigned(trunc_ln38_1_fu_3801_p1));
+    add_ln38_6_fu_4519_p2 <= std_logic_vector(unsigned(add_ln38_2_fu_4509_p2) + unsigned(add_ln38_5_fu_4515_p2));
+    add_ln38_7_fu_4218_p2 <= std_logic_vector(unsigned(mul_ln38_8_fu_3870_p2) + unsigned(mul_ln38_7_fu_3864_p2));
+    add_ln38_8_fu_4224_p2 <= std_logic_vector(unsigned(mul_ln38_10_fu_3882_p2) + unsigned(mul_ln38_9_fu_3876_p2));
+    add_ln38_9_fu_4230_p2 <= std_logic_vector(unsigned(add_ln38_7_fu_4218_p2) + unsigned(add_ln38_8_fu_4224_p2));
+    add_ln38_fu_4500_p2 <= std_logic_vector(unsigned(mul_ln38_reg_5474) + unsigned(out_loc_q0));
+    add_ln42_fu_4582_p2 <= std_logic_vector(unsigned(phi_ln42_reg_3351) + unsigned(ap_const_lv13_1));
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(8);
+    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(16);
+    ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(18);
+    ap_CS_fsm_pp3_stage0 <= ap_CS_fsm(20);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state12 <= ap_CS_fsm(9);
+    ap_CS_fsm_state18 <= ap_CS_fsm(15);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state22 <= ap_CS_fsm(17);
+    ap_CS_fsm_state26 <= ap_CS_fsm(19);
+    ap_CS_fsm_state34 <= ap_CS_fsm(25);
+    ap_CS_fsm_state8 <= ap_CS_fsm(7);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_11001_assign_proc : process(ap_enable_reg_pp0_iter1, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_11001 <= ((in1_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(ap_enable_reg_pp0_iter1, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_subdone <= ((in1_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp1_stage0_11001_assign_proc : process(ap_enable_reg_pp1_iter1, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_11001 <= ((in2_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp1_stage0_subdone_assign_proc : process(ap_enable_reg_pp1_iter1, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_subdone <= ((in2_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp2_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp2_stage0_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp3_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp3_stage0_01001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp3_stage0_11001_assign_proc : process(ap_enable_reg_pp3_iter2, ap_block_state29_io)
+    begin
+                ap_block_pp3_stage0_11001 <= ((ap_const_boolean_1 = ap_block_state29_io) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp3_stage0_subdone_assign_proc : process(ap_enable_reg_pp3_iter2, ap_block_state29_io)
+    begin
+                ap_block_pp3_stage0_subdone <= ((ap_const_boolean_1 = ap_block_state29_io) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state10_pp0_stage0_iter1_assign_proc : process(in1_mem_RVALID)
+    begin
+                ap_block_state10_pp0_stage0_iter1 <= (in1_mem_RVALID = ap_const_logic_0);
+    end process;
+
+        ap_block_state11_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state19_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state20_pp1_stage0_iter1_assign_proc : process(in2_mem_RVALID)
+    begin
+                ap_block_state20_pp1_stage0_iter1 <= (in2_mem_RVALID = ap_const_logic_0);
+    end process;
+
+        ap_block_state21_pp1_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state23_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state24_pp2_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state25_pp2_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state27_pp3_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state28_pp3_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state29_io_assign_proc : process(icmp_ln42_reg_5549_pp3_iter1_reg, out_mem_WREADY)
+    begin
+                ap_block_state29_io <= ((out_mem_WREADY = ap_const_logic_0) and (icmp_ln42_reg_5549_pp3_iter1_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state29_pp3_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state9_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state9_assign_proc : process(icmp_ln27_fu_3420_p2)
+    begin
+        if ((icmp_ln27_fu_3420_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp1_exit_iter0_state19_assign_proc : process(icmp_ln28_fu_3513_p2)
+    begin
+        if ((icmp_ln28_fu_3513_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_1;
+        else 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp2_exit_iter0_state23_assign_proc : process(icmp_ln31_fu_3615_p2)
+    begin
+        if ((icmp_ln31_fu_3615_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp2_exit_iter0_state23 <= ap_const_logic_1;
+        else 
+            ap_condition_pp2_exit_iter0_state23 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp3_exit_iter0_state27_assign_proc : process(icmp_ln42_fu_4576_p2)
+    begin
+        if ((icmp_ln42_fu_4576_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp3_exit_iter0_state27 <= ap_const_logic_1;
+        else 
+            ap_condition_pp3_exit_iter0_state27 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_CS_fsm_state34, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
+    ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
+    ap_enable_pp3 <= (ap_idle_pp3 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp1 <= ap_const_logic_1;
+        else 
+            ap_idle_pp1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter0, ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter2)
+    begin
+        if (((ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))) then 
+            ap_idle_pp2 <= ap_const_logic_1;
+        else 
+            ap_idle_pp2 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp3_assign_proc : process(ap_enable_reg_pp3_iter2, ap_enable_reg_pp3_iter0, ap_enable_reg_pp3_iter1)
+    begin
+        if (((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp3 <= ap_const_logic_1;
+        else 
+            ap_idle_pp3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_i_0_phi_fu_3333_p4_assign_proc : process(i_0_reg_3329, icmp_ln31_reg_4809, ap_CS_fsm_pp2_stage0, select_ln31_1_reg_4818, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0)
+    begin
+        if (((icmp_ln31_reg_4809 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            ap_phi_mux_i_0_phi_fu_3333_p4 <= select_ln31_1_reg_4818;
+        else 
+            ap_phi_mux_i_0_phi_fu_3333_p4 <= i_0_reg_3329;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state34, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    empty_7_fu_3411_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in_reg_4604),64));
+    empty_8_fu_3392_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in3_reg_4609),64));
+    empty_fu_3402_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(out5_reg_4599),64));
+    i_fu_3626_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(ap_phi_mux_i_0_phi_fu_3333_p4));
+    icmp_ln27_fu_3420_p2 <= "1" when (phi_ln27_reg_3296 = ap_const_lv13_1000) else "0";
+    icmp_ln28_fu_3513_p2 <= "1" when (phi_ln28_reg_3307 = ap_const_lv13_1000) else "0";
+    icmp_ln31_fu_3615_p2 <= "1" when (indvar_flatten_reg_3318 = mul_ln31_reg_4804) else "0";
+    icmp_ln33_fu_3632_p2 <= "1" when (j_0_reg_3340 = dim_read_reg_4593) else "0";
+    icmp_ln42_fu_4576_p2 <= "1" when (phi_ln42_reg_3351 = ap_const_lv13_1000) else "0";
+
+    in1_loc_0_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_0_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_0_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_0_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_0_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_0_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_0_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_0_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_0_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_10_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_10_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_10_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_10_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_10_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_10_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_10_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_10_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_11_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_11_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_11_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_11_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_11_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_11_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_11_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_11_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_11_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_11_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_12_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_12_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_12_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_12_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_12_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_12_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_12_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_12_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_12_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_12_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_13_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_13_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_13_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_13_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_13_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_13_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_13_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_13_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_14_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_14_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_14_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_14_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_14_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_14_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_14_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_14_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_15_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_15_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_15_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_15_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_15_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_15_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_15_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_15_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_15_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_15_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_16_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_16_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_16_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_16_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_16_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_16_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_16_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_16_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_10) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_16_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_16_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_17_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_17_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_17_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_17_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_17_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_17_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_17_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_11) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_17_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_18_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_18_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_18_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_18_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_18_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_18_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_18_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_12) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_18_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_19_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_19_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_19_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_19_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_19_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_19_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_19_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_19_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_13) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_19_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_19_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_1_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_1_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_1_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_1_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_1_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_1_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_1_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_1_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_1_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_20_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_20_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_20_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_20_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_20_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_20_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_20_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_20_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_14) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_20_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_20_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_21_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_21_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_21_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_21_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_21_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_21_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_21_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_21_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_15) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_21_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_21_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_22_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_22_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_22_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_22_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_22_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_22_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_22_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_22_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_16) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_22_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_22_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_23_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_23_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_23_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_23_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_23_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_23_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_23_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_23_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_17) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_23_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_23_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_24_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_24_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_24_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_24_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_24_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_24_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_24_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_24_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_18) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_24_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_24_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_25_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_25_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_25_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_25_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_25_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_25_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_25_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_19) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_25_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_26_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_26_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_26_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_26_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_26_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_26_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_26_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_1A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_26_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_27_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_27_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_27_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_27_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_27_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_27_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_27_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_27_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_1B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_27_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_27_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_28_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_28_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_28_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_28_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_28_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_28_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_28_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_28_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_1C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_28_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_28_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_29_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_29_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_29_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_29_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_29_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_29_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_29_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_29_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_1D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_29_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_29_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_2_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_2_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_2_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_2_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_2_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_2_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_2) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_2_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_2_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_30_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_30_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_30_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_30_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_30_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_30_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_30_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_30_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_1E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_30_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_30_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_31_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_31_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_31_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_31_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_31_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_31_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_31_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_31_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_1F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_31_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_31_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_32_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_32_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_32_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_32_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_32_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_32_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_32_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_32_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_20) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_32_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_32_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_33_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_33_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_33_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_33_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_33_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_33_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_33_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_21) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_33_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_34_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_34_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_34_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_34_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_34_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_34_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_34_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_22) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_34_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_35_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_35_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_35_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_35_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_35_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_35_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_35_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_35_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_23) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_35_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_35_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_36_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_36_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_36_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_36_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_36_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_36_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_36_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_36_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_24) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_36_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_36_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_37_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_37_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_37_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_37_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_37_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_37_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_37_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_37_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_25) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_37_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_37_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_38_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_38_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_38_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_38_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_38_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_38_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_38_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_38_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_26) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_38_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_38_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_39_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_39_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_39_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_39_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_39_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_39_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_39_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_39_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_27) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_39_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_39_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_3_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_3_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_3_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_3_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_3_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_3_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_3_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_3) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_3_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_3_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_40_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_40_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_40_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_40_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_40_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_40_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_40_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_40_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_28) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_40_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_40_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_41_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_41_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_41_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_41_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_41_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_41_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_41_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_29) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_41_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_42_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_42_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_42_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_42_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_42_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_42_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_42_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_2A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_42_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_43_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_43_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_43_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_43_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_43_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_43_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_43_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_43_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_2B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_43_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_43_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_44_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_44_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_44_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_44_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_44_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_44_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_44_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_44_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_2C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_44_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_44_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_45_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_45_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_45_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_45_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_45_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_45_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_45_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_2D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_45_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_46_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_46_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_46_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_46_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_46_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_46_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_46_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_2E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_46_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_47_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_47_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_47_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_47_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_47_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_47_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_47_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_47_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_2F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_47_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_47_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_48_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_48_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_48_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_48_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_48_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_48_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_48_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_48_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_30) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_48_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_48_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_49_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_49_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_49_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_49_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_49_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_49_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_49_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_31) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_49_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_4_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_4_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_4_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_4_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_4_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_4_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_4_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_4) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_4_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_4_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_50_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_50_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_50_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_50_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_50_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_50_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_50_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_32) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_50_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_51_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_51_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_51_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_51_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_51_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_51_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_51_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_51_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_33) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_51_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_51_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_52_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_52_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_52_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_52_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_52_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_52_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_52_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_52_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_34) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_52_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_52_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_53_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_53_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_53_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_53_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_53_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_53_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_53_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_53_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_35) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_53_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_53_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_54_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_54_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_54_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_54_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_54_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_54_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_54_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_54_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_36) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_54_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_54_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_55_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_55_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_55_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_55_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_55_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_55_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_55_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_55_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_37) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_55_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_55_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_56_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_56_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_56_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_56_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_56_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_56_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_56_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_56_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_38) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_56_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_56_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_57_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_57_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_57_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_57_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_57_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_57_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_57_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_39) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_57_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_58_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_58_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_58_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_58_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_58_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_58_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_58_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_3A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_58_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_59_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_59_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_59_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_59_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_59_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_59_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_59_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_59_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_3B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_59_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_59_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_5_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_5_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_5_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_5_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_5_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_5_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_5_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_5) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_5_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_5_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_60_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_60_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_60_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_60_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_60_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_60_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_60_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_60_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_3C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_60_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_60_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_61_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_61_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_61_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_61_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_61_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_61_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_61_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_3D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_61_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_62_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_62_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_62_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_62_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_62_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_62_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_62_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_62_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_3E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_62_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_62_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_63_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_63_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_63_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_63_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_63_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_63_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_63_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_63_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_3F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_63_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_63_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_6_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_6_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_6_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_6_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_6_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_6_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_6_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_6) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_6_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_6_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_7_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_7_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_7_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_7_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_7_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_7_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_7_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_7) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_7_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_7_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_8_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_8_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_8_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_8_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_8_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_8_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_8_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_8) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_8_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_8_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_9_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1, zext_ln31_1_fu_3665_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_9_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_9_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_9_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_9_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_9_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4646_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4646_pp0_iter1_reg = ap_const_lv6_9) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_9_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    in1_mem_ARADDR <= empty_8_fu_3392_p1(32 - 1 downto 0);
+
+    in1_mem_ARVALID_assign_proc : process(ap_CS_fsm_state2, in1_mem_ARREADY)
+    begin
+        if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            in1_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in1_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_RREADY <= ap_const_logic_1;
+        else 
+            in1_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_AR_assign_proc : process(m_axi_in1_mem_ARREADY, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            in1_mem_blk_n_AR <= m_axi_in1_mem_ARREADY;
+        else 
+            in1_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_R_assign_proc : process(m_axi_in1_mem_RVALID, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_blk_n_R <= m_axi_in1_mem_RVALID;
+        else 
+            in1_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_loc_0_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_0_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_0_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_0_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_0_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_0_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_0_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_0_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_0_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_10_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_10_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_10_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_10_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_10_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_10_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_10_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_10_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_11_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_11_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_11_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_11_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_11_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_11_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_11_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_11_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_11_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_11_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_12_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_12_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_12_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_12_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_12_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_12_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_12_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_12_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_12_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_12_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_13_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_13_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_13_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_13_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_13_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_13_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_13_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_13_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_14_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_14_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_14_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_14_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_14_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_14_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_14_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_14_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_15_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_15_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_15_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_15_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_15_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_15_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_15_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_15_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_15_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_15_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_16_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_16_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_16_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_16_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_16_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_16_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_16_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_16_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_10) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_16_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_16_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_17_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_17_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_17_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_17_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_17_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_17_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_17_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_11) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_17_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_18_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_18_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_18_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_18_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_18_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_18_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_18_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_12) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_18_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_19_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_19_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_19_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_19_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_19_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_19_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_19_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_19_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_13) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_19_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_19_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_1_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_1_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_1_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_1_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_1_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_1_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_1_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_1_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_1_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_20_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_20_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_20_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_20_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_20_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_20_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_20_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_20_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_14) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_20_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_20_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_21_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_21_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_21_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_21_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_21_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_21_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_21_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_21_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_15) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_21_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_21_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_22_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_22_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_22_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_22_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_22_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_22_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_22_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_22_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_16) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_22_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_22_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_23_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_23_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_23_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_23_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_23_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_23_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_23_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_23_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_17) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_23_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_23_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_24_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_24_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_24_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_24_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_24_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_24_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_24_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_24_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_18) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_24_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_24_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_25_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_25_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_25_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_25_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_25_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_25_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_25_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_19) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_25_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_26_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_26_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_26_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_26_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_26_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_26_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_26_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_1A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_26_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_27_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_27_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_27_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_27_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_27_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_27_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_27_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_27_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_1B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_27_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_27_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_28_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_28_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_28_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_28_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_28_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_28_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_28_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_28_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_1C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_28_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_28_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_29_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_29_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_29_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_29_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_29_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_29_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_29_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_29_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_1D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_29_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_29_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_2_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_2_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_2_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_2_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_2_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_2_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_2_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_2) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_2_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_2_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_30_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_30_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_30_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_30_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_30_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_30_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_30_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_30_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_1E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_30_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_30_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_31_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_31_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_31_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_31_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_31_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_31_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_31_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_31_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_1F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_31_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_31_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_32_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_32_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_32_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_32_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_32_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_32_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_32_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_32_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_20) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_32_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_32_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_33_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_33_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_33_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_33_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_33_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_33_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_33_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_21) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_33_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_34_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_34_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_34_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_34_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_34_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_34_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_34_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_22) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_34_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_35_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_35_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_35_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_35_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_35_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_35_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_35_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_35_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_23) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_35_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_35_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_36_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_36_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_36_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_36_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_36_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_36_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_36_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_36_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_24) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_36_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_36_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_37_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_37_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_37_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_37_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_37_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_37_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_37_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_37_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_25) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_37_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_37_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_38_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_38_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_38_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_38_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_38_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_38_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_38_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_38_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_26) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_38_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_38_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_39_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_39_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_39_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_39_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_39_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_39_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_39_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_39_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_27) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_39_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_39_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_3_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_3_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_3_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_3_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_3_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_3_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_3_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_3) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_3_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_3_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_40_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_40_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_40_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_40_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_40_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_40_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_40_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_40_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_28) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_40_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_40_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_41_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_41_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_41_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_41_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_41_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_41_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_41_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_29) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_41_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_42_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_42_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_42_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_42_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_42_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_42_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_42_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_2A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_42_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_43_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_43_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_43_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_43_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_43_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_43_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_43_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_43_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_2B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_43_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_43_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_44_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_44_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_44_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_44_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_44_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_44_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_44_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_44_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_2C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_44_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_44_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_45_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_45_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_45_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_45_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_45_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_45_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_45_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_2D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_45_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_46_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_46_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_46_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_46_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_46_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_46_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_46_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_2E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_46_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_47_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_47_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_47_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_47_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_47_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_47_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_47_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_47_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_2F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_47_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_47_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_48_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_48_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_48_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_48_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_48_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_48_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_48_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_48_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_30) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_48_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_48_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_49_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_49_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_49_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_49_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_49_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_49_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_49_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_31) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_49_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_4_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_4_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_4_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_4_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_4_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_4_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_4_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_4) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_4_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_4_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_50_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_50_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_50_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_50_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_50_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_50_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_50_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_32) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_50_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_51_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_51_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_51_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_51_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_51_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_51_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_51_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_51_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_33) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_51_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_51_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_52_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_52_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_52_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_52_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_52_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_52_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_52_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_52_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_34) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_52_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_52_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_53_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_53_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_53_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_53_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_53_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_53_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_53_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_53_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_35) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_53_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_53_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_54_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_54_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_54_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_54_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_54_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_54_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_54_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_54_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_36) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_54_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_54_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_55_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_55_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_55_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_55_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_55_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_55_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_55_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_55_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_37) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_55_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_55_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_56_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_56_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_56_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_56_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_56_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_56_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_56_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_56_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_38) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_56_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_56_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_57_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_57_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_57_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_57_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_57_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_57_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_57_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_39) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_57_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_58_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_58_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_58_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_58_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_58_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_58_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_58_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_3A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_58_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_59_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_59_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_59_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_59_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_59_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_59_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_59_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_59_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_3B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_59_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_59_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_5_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_5_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_5_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_5_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_5_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_5_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_5_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_5) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_5_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_5_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_60_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_60_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_60_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_60_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_60_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_60_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_60_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_60_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_3C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_60_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_60_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_61_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_61_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_61_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_61_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_61_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_61_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_61_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_3D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_61_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_62_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_62_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_62_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_62_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_62_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_62_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_62_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_62_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_3E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_62_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_62_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_63_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_63_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_63_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_63_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_63_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_63_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_63_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_63_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_3F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_63_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_63_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_6_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_6_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_6_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_6_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_6_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_6_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_6_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_6) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_6_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_6_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_7_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_7_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_7_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_7_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_7_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_7_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_7_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_7) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_7_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_7_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_8_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_8_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_8_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_8_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_8_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_8_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_8_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_8) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_8_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_8_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_9_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1, sext_ln38_fu_3733_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_9_address0 <= sext_ln38_fu_3733_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_9_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_9_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_9_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_9_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4732_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4732_pp1_iter1_reg = ap_const_lv6_9) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_9_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_ARVALID_assign_proc : process(ap_CS_fsm_state12, in2_mem_ARREADY)
+    begin
+        if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then 
+            in2_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in2_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_RREADY_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_RREADY <= ap_const_logic_1;
+        else 
+            in2_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_AR_assign_proc : process(m_axi_in2_mem_ARREADY, ap_CS_fsm_state12)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state12)) then 
+            in2_mem_blk_n_AR <= m_axi_in2_mem_ARREADY;
+        else 
+            in2_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_R_assign_proc : process(m_axi_in2_mem_RVALID, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_blk_n_R <= m_axi_in2_mem_RVALID;
+        else 
+            in2_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    j_fu_3816_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(select_ln31_fu_3637_p3));
+    mul_ln31_fu_3609_p0 <= zext_ln31_fu_3606_p1(32 - 1 downto 0);
+    mul_ln31_fu_3609_p1 <= zext_ln31_fu_3606_p1(32 - 1 downto 0);
+    mul_ln31_fu_3609_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(mul_ln31_fu_3609_p0) * unsigned(mul_ln31_fu_3609_p1), 64));
+    mul_ln38_10_fu_3882_p0 <= in2_loc_10_q0;
+    mul_ln38_10_fu_3882_p1 <= in1_loc_10_q0;
+    mul_ln38_10_fu_3882_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_10_fu_3882_p0) * signed(mul_ln38_10_fu_3882_p1))), 32));
+    mul_ln38_11_fu_3888_p0 <= in2_loc_11_q0;
+    mul_ln38_11_fu_3888_p1 <= in1_loc_11_q0;
+    mul_ln38_11_fu_3888_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_11_fu_3888_p0) * signed(mul_ln38_11_fu_3888_p1))), 32));
+    mul_ln38_12_fu_3894_p0 <= in2_loc_12_q0;
+    mul_ln38_12_fu_3894_p1 <= in1_loc_12_q0;
+    mul_ln38_12_fu_3894_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_12_fu_3894_p0) * signed(mul_ln38_12_fu_3894_p1))), 32));
+    mul_ln38_13_fu_3900_p0 <= in2_loc_13_q0;
+    mul_ln38_13_fu_3900_p1 <= in1_loc_13_q0;
+    mul_ln38_13_fu_3900_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_13_fu_3900_p0) * signed(mul_ln38_13_fu_3900_p1))), 32));
+    mul_ln38_14_fu_3906_p0 <= in2_loc_14_q0;
+    mul_ln38_14_fu_3906_p1 <= in1_loc_14_q0;
+    mul_ln38_14_fu_3906_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_14_fu_3906_p0) * signed(mul_ln38_14_fu_3906_p1))), 32));
+    mul_ln38_15_fu_3912_p0 <= in2_loc_15_q0;
+    mul_ln38_15_fu_3912_p1 <= in1_loc_15_q0;
+    mul_ln38_15_fu_3912_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_15_fu_3912_p0) * signed(mul_ln38_15_fu_3912_p1))), 32));
+    mul_ln38_16_fu_3918_p0 <= in2_loc_16_q0;
+    mul_ln38_16_fu_3918_p1 <= in1_loc_16_q0;
+    mul_ln38_16_fu_3918_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_16_fu_3918_p0) * signed(mul_ln38_16_fu_3918_p1))), 32));
+    mul_ln38_17_fu_3924_p0 <= in2_loc_17_q0;
+    mul_ln38_17_fu_3924_p1 <= in1_loc_17_q0;
+    mul_ln38_17_fu_3924_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_17_fu_3924_p0) * signed(mul_ln38_17_fu_3924_p1))), 32));
+    mul_ln38_18_fu_3930_p0 <= in2_loc_18_q0;
+    mul_ln38_18_fu_3930_p1 <= in1_loc_18_q0;
+    mul_ln38_18_fu_3930_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_18_fu_3930_p0) * signed(mul_ln38_18_fu_3930_p1))), 32));
+    mul_ln38_19_fu_3936_p0 <= in2_loc_19_q0;
+    mul_ln38_19_fu_3936_p1 <= in1_loc_19_q0;
+    mul_ln38_19_fu_3936_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_19_fu_3936_p0) * signed(mul_ln38_19_fu_3936_p1))), 32));
+    mul_ln38_1_fu_3828_p0 <= in2_loc_1_q0;
+    mul_ln38_1_fu_3828_p1 <= in1_loc_1_q0;
+    mul_ln38_1_fu_3828_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_1_fu_3828_p0) * signed(mul_ln38_1_fu_3828_p1))), 32));
+    mul_ln38_20_fu_3942_p0 <= in2_loc_20_q0;
+    mul_ln38_20_fu_3942_p1 <= in1_loc_20_q0;
+    mul_ln38_20_fu_3942_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_20_fu_3942_p0) * signed(mul_ln38_20_fu_3942_p1))), 32));
+    mul_ln38_21_fu_3948_p0 <= in2_loc_21_q0;
+    mul_ln38_21_fu_3948_p1 <= in1_loc_21_q0;
+    mul_ln38_21_fu_3948_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_21_fu_3948_p0) * signed(mul_ln38_21_fu_3948_p1))), 32));
+    mul_ln38_22_fu_3954_p0 <= in2_loc_22_q0;
+    mul_ln38_22_fu_3954_p1 <= in1_loc_22_q0;
+    mul_ln38_22_fu_3954_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_22_fu_3954_p0) * signed(mul_ln38_22_fu_3954_p1))), 32));
+    mul_ln38_23_fu_3960_p0 <= in2_loc_23_q0;
+    mul_ln38_23_fu_3960_p1 <= in1_loc_23_q0;
+    mul_ln38_23_fu_3960_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_23_fu_3960_p0) * signed(mul_ln38_23_fu_3960_p1))), 32));
+    mul_ln38_24_fu_3966_p0 <= in2_loc_24_q0;
+    mul_ln38_24_fu_3966_p1 <= in1_loc_24_q0;
+    mul_ln38_24_fu_3966_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_24_fu_3966_p0) * signed(mul_ln38_24_fu_3966_p1))), 32));
+    mul_ln38_25_fu_3972_p0 <= in2_loc_25_q0;
+    mul_ln38_25_fu_3972_p1 <= in1_loc_25_q0;
+    mul_ln38_25_fu_3972_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_25_fu_3972_p0) * signed(mul_ln38_25_fu_3972_p1))), 32));
+    mul_ln38_26_fu_3978_p0 <= in2_loc_26_q0;
+    mul_ln38_26_fu_3978_p1 <= in1_loc_26_q0;
+    mul_ln38_26_fu_3978_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_26_fu_3978_p0) * signed(mul_ln38_26_fu_3978_p1))), 32));
+    mul_ln38_27_fu_3984_p0 <= in2_loc_27_q0;
+    mul_ln38_27_fu_3984_p1 <= in1_loc_27_q0;
+    mul_ln38_27_fu_3984_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_27_fu_3984_p0) * signed(mul_ln38_27_fu_3984_p1))), 32));
+    mul_ln38_28_fu_3990_p0 <= in2_loc_28_q0;
+    mul_ln38_28_fu_3990_p1 <= in1_loc_28_q0;
+    mul_ln38_28_fu_3990_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_28_fu_3990_p0) * signed(mul_ln38_28_fu_3990_p1))), 32));
+    mul_ln38_29_fu_3996_p0 <= in2_loc_29_q0;
+    mul_ln38_29_fu_3996_p1 <= in1_loc_29_q0;
+    mul_ln38_29_fu_3996_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_29_fu_3996_p0) * signed(mul_ln38_29_fu_3996_p1))), 32));
+    mul_ln38_2_fu_3834_p0 <= in2_loc_2_q0;
+    mul_ln38_2_fu_3834_p1 <= in1_loc_2_q0;
+    mul_ln38_2_fu_3834_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_2_fu_3834_p0) * signed(mul_ln38_2_fu_3834_p1))), 32));
+    mul_ln38_30_fu_4002_p0 <= in2_loc_30_q0;
+    mul_ln38_30_fu_4002_p1 <= in1_loc_30_q0;
+    mul_ln38_30_fu_4002_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_30_fu_4002_p0) * signed(mul_ln38_30_fu_4002_p1))), 32));
+    mul_ln38_31_fu_4008_p0 <= in2_loc_31_q0;
+    mul_ln38_31_fu_4008_p1 <= in1_loc_31_q0;
+    mul_ln38_31_fu_4008_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_31_fu_4008_p0) * signed(mul_ln38_31_fu_4008_p1))), 32));
+    mul_ln38_32_fu_4014_p0 <= in2_loc_32_q0;
+    mul_ln38_32_fu_4014_p1 <= in1_loc_32_q0;
+    mul_ln38_32_fu_4014_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_32_fu_4014_p0) * signed(mul_ln38_32_fu_4014_p1))), 32));
+    mul_ln38_33_fu_4020_p0 <= in2_loc_33_q0;
+    mul_ln38_33_fu_4020_p1 <= in1_loc_33_q0;
+    mul_ln38_33_fu_4020_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_33_fu_4020_p0) * signed(mul_ln38_33_fu_4020_p1))), 32));
+    mul_ln38_34_fu_4026_p0 <= in2_loc_34_q0;
+    mul_ln38_34_fu_4026_p1 <= in1_loc_34_q0;
+    mul_ln38_34_fu_4026_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_34_fu_4026_p0) * signed(mul_ln38_34_fu_4026_p1))), 32));
+    mul_ln38_35_fu_4032_p0 <= in2_loc_35_q0;
+    mul_ln38_35_fu_4032_p1 <= in1_loc_35_q0;
+    mul_ln38_35_fu_4032_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_35_fu_4032_p0) * signed(mul_ln38_35_fu_4032_p1))), 32));
+    mul_ln38_36_fu_4038_p0 <= in2_loc_36_q0;
+    mul_ln38_36_fu_4038_p1 <= in1_loc_36_q0;
+    mul_ln38_36_fu_4038_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_36_fu_4038_p0) * signed(mul_ln38_36_fu_4038_p1))), 32));
+    mul_ln38_37_fu_4044_p0 <= in2_loc_37_q0;
+    mul_ln38_37_fu_4044_p1 <= in1_loc_37_q0;
+    mul_ln38_37_fu_4044_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_37_fu_4044_p0) * signed(mul_ln38_37_fu_4044_p1))), 32));
+    mul_ln38_38_fu_4050_p0 <= in2_loc_38_q0;
+    mul_ln38_38_fu_4050_p1 <= in1_loc_38_q0;
+    mul_ln38_38_fu_4050_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_38_fu_4050_p0) * signed(mul_ln38_38_fu_4050_p1))), 32));
+    mul_ln38_39_fu_4056_p0 <= in2_loc_39_q0;
+    mul_ln38_39_fu_4056_p1 <= in1_loc_39_q0;
+    mul_ln38_39_fu_4056_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_39_fu_4056_p0) * signed(mul_ln38_39_fu_4056_p1))), 32));
+    mul_ln38_3_fu_3840_p0 <= in2_loc_3_q0;
+    mul_ln38_3_fu_3840_p1 <= in1_loc_3_q0;
+    mul_ln38_3_fu_3840_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_3_fu_3840_p0) * signed(mul_ln38_3_fu_3840_p1))), 32));
+    mul_ln38_40_fu_4062_p0 <= in2_loc_40_q0;
+    mul_ln38_40_fu_4062_p1 <= in1_loc_40_q0;
+    mul_ln38_40_fu_4062_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_40_fu_4062_p0) * signed(mul_ln38_40_fu_4062_p1))), 32));
+    mul_ln38_41_fu_4068_p0 <= in2_loc_41_q0;
+    mul_ln38_41_fu_4068_p1 <= in1_loc_41_q0;
+    mul_ln38_41_fu_4068_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_41_fu_4068_p0) * signed(mul_ln38_41_fu_4068_p1))), 32));
+    mul_ln38_42_fu_4074_p0 <= in2_loc_42_q0;
+    mul_ln38_42_fu_4074_p1 <= in1_loc_42_q0;
+    mul_ln38_42_fu_4074_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_42_fu_4074_p0) * signed(mul_ln38_42_fu_4074_p1))), 32));
+    mul_ln38_43_fu_4080_p0 <= in2_loc_43_q0;
+    mul_ln38_43_fu_4080_p1 <= in1_loc_43_q0;
+    mul_ln38_43_fu_4080_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_43_fu_4080_p0) * signed(mul_ln38_43_fu_4080_p1))), 32));
+    mul_ln38_44_fu_4086_p0 <= in2_loc_44_q0;
+    mul_ln38_44_fu_4086_p1 <= in1_loc_44_q0;
+    mul_ln38_44_fu_4086_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_44_fu_4086_p0) * signed(mul_ln38_44_fu_4086_p1))), 32));
+    mul_ln38_45_fu_4092_p0 <= in2_loc_45_q0;
+    mul_ln38_45_fu_4092_p1 <= in1_loc_45_q0;
+    mul_ln38_45_fu_4092_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_45_fu_4092_p0) * signed(mul_ln38_45_fu_4092_p1))), 32));
+    mul_ln38_46_fu_4098_p0 <= in2_loc_46_q0;
+    mul_ln38_46_fu_4098_p1 <= in1_loc_46_q0;
+    mul_ln38_46_fu_4098_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_46_fu_4098_p0) * signed(mul_ln38_46_fu_4098_p1))), 32));
+    mul_ln38_47_fu_4104_p0 <= in2_loc_47_q0;
+    mul_ln38_47_fu_4104_p1 <= in1_loc_47_q0;
+    mul_ln38_47_fu_4104_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_47_fu_4104_p0) * signed(mul_ln38_47_fu_4104_p1))), 32));
+    mul_ln38_48_fu_4110_p0 <= in2_loc_48_q0;
+    mul_ln38_48_fu_4110_p1 <= in1_loc_48_q0;
+    mul_ln38_48_fu_4110_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_48_fu_4110_p0) * signed(mul_ln38_48_fu_4110_p1))), 32));
+    mul_ln38_49_fu_4116_p0 <= in2_loc_49_q0;
+    mul_ln38_49_fu_4116_p1 <= in1_loc_49_q0;
+    mul_ln38_49_fu_4116_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_49_fu_4116_p0) * signed(mul_ln38_49_fu_4116_p1))), 32));
+    mul_ln38_4_fu_3846_p0 <= in2_loc_4_q0;
+    mul_ln38_4_fu_3846_p1 <= in1_loc_4_q0;
+    mul_ln38_4_fu_3846_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_4_fu_3846_p0) * signed(mul_ln38_4_fu_3846_p1))), 32));
+    mul_ln38_50_fu_4122_p0 <= in2_loc_50_q0;
+    mul_ln38_50_fu_4122_p1 <= in1_loc_50_q0;
+    mul_ln38_50_fu_4122_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_50_fu_4122_p0) * signed(mul_ln38_50_fu_4122_p1))), 32));
+    mul_ln38_51_fu_4128_p0 <= in2_loc_51_q0;
+    mul_ln38_51_fu_4128_p1 <= in1_loc_51_q0;
+    mul_ln38_51_fu_4128_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_51_fu_4128_p0) * signed(mul_ln38_51_fu_4128_p1))), 32));
+    mul_ln38_52_fu_4134_p0 <= in2_loc_52_q0;
+    mul_ln38_52_fu_4134_p1 <= in1_loc_52_q0;
+    mul_ln38_52_fu_4134_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_52_fu_4134_p0) * signed(mul_ln38_52_fu_4134_p1))), 32));
+    mul_ln38_53_fu_4140_p0 <= in2_loc_53_q0;
+    mul_ln38_53_fu_4140_p1 <= in1_loc_53_q0;
+    mul_ln38_53_fu_4140_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_53_fu_4140_p0) * signed(mul_ln38_53_fu_4140_p1))), 32));
+    mul_ln38_54_fu_4146_p0 <= in2_loc_54_q0;
+    mul_ln38_54_fu_4146_p1 <= in1_loc_54_q0;
+    mul_ln38_54_fu_4146_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_54_fu_4146_p0) * signed(mul_ln38_54_fu_4146_p1))), 32));
+    mul_ln38_55_fu_4152_p0 <= in2_loc_55_q0;
+    mul_ln38_55_fu_4152_p1 <= in1_loc_55_q0;
+    mul_ln38_55_fu_4152_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_55_fu_4152_p0) * signed(mul_ln38_55_fu_4152_p1))), 32));
+    mul_ln38_56_fu_4158_p0 <= in2_loc_56_q0;
+    mul_ln38_56_fu_4158_p1 <= in1_loc_56_q0;
+    mul_ln38_56_fu_4158_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_56_fu_4158_p0) * signed(mul_ln38_56_fu_4158_p1))), 32));
+    mul_ln38_57_fu_4164_p0 <= in2_loc_57_q0;
+    mul_ln38_57_fu_4164_p1 <= in1_loc_57_q0;
+    mul_ln38_57_fu_4164_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_57_fu_4164_p0) * signed(mul_ln38_57_fu_4164_p1))), 32));
+    mul_ln38_58_fu_4170_p0 <= in2_loc_58_q0;
+    mul_ln38_58_fu_4170_p1 <= in1_loc_58_q0;
+    mul_ln38_58_fu_4170_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_58_fu_4170_p0) * signed(mul_ln38_58_fu_4170_p1))), 32));
+    mul_ln38_59_fu_4176_p0 <= in2_loc_59_q0;
+    mul_ln38_59_fu_4176_p1 <= in1_loc_59_q0;
+    mul_ln38_59_fu_4176_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_59_fu_4176_p0) * signed(mul_ln38_59_fu_4176_p1))), 32));
+    mul_ln38_5_fu_3852_p0 <= in2_loc_5_q0;
+    mul_ln38_5_fu_3852_p1 <= in1_loc_5_q0;
+    mul_ln38_5_fu_3852_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_5_fu_3852_p0) * signed(mul_ln38_5_fu_3852_p1))), 32));
+    mul_ln38_60_fu_4182_p0 <= in2_loc_60_q0;
+    mul_ln38_60_fu_4182_p1 <= in1_loc_60_q0;
+    mul_ln38_60_fu_4182_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_60_fu_4182_p0) * signed(mul_ln38_60_fu_4182_p1))), 32));
+    mul_ln38_61_fu_4188_p0 <= in2_loc_61_q0;
+    mul_ln38_61_fu_4188_p1 <= in1_loc_61_q0;
+    mul_ln38_61_fu_4188_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_61_fu_4188_p0) * signed(mul_ln38_61_fu_4188_p1))), 32));
+    mul_ln38_62_fu_4194_p0 <= in2_loc_62_q0;
+    mul_ln38_62_fu_4194_p1 <= in1_loc_62_q0;
+    mul_ln38_62_fu_4194_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_62_fu_4194_p0) * signed(mul_ln38_62_fu_4194_p1))), 32));
+    mul_ln38_63_fu_4200_p0 <= in2_loc_63_q0;
+    mul_ln38_63_fu_4200_p1 <= in1_loc_63_q0;
+    mul_ln38_63_fu_4200_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_63_fu_4200_p0) * signed(mul_ln38_63_fu_4200_p1))), 32));
+    mul_ln38_6_fu_3858_p0 <= in2_loc_6_q0;
+    mul_ln38_6_fu_3858_p1 <= in1_loc_6_q0;
+    mul_ln38_6_fu_3858_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_6_fu_3858_p0) * signed(mul_ln38_6_fu_3858_p1))), 32));
+    mul_ln38_7_fu_3864_p0 <= in2_loc_7_q0;
+    mul_ln38_7_fu_3864_p1 <= in1_loc_7_q0;
+    mul_ln38_7_fu_3864_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_7_fu_3864_p0) * signed(mul_ln38_7_fu_3864_p1))), 32));
+    mul_ln38_8_fu_3870_p0 <= in2_loc_8_q0;
+    mul_ln38_8_fu_3870_p1 <= in1_loc_8_q0;
+    mul_ln38_8_fu_3870_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_8_fu_3870_p0) * signed(mul_ln38_8_fu_3870_p1))), 32));
+    mul_ln38_9_fu_3876_p0 <= in2_loc_9_q0;
+    mul_ln38_9_fu_3876_p1 <= in1_loc_9_q0;
+    mul_ln38_9_fu_3876_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_9_fu_3876_p0) * signed(mul_ln38_9_fu_3876_p1))), 32));
+    mul_ln38_fu_3822_p0 <= in2_loc_0_q0;
+    mul_ln38_fu_3822_p1 <= in1_loc_0_q0;
+    mul_ln38_fu_3822_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(mul_ln38_fu_3822_p0) * signed(mul_ln38_fu_3822_p1))), 32));
+
+    out_loc_address0_assign_proc : process(ap_block_pp3_stage0, ap_CS_fsm_pp2_stage0, out_loc_addr_reg_5143, ap_CS_fsm_pp3_stage0, ap_enable_reg_pp3_iter0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln42_fu_4588_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp3_stage0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then 
+            out_loc_address0 <= zext_ln42_fu_4588_p1(12 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            out_loc_address0 <= out_loc_addr_reg_5143;
+        else 
+            out_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    out_loc_ce0_assign_proc : process(ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_CS_fsm_pp3_stage0, ap_block_pp3_stage0_11001, ap_enable_reg_pp3_iter0, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            out_loc_ce0 <= ap_const_logic_1;
+        else 
+            out_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_loc_ce1_assign_proc : process(ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            out_loc_ce1 <= ap_const_logic_1;
+        else 
+            out_loc_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    out_loc_d1 <= std_logic_vector(unsigned(add_ln38_30_fu_4539_p2) + unsigned(add_ln38_62_fu_4563_p2));
+
+    out_loc_we1_assign_proc : process(ap_block_pp2_stage0_11001, icmp_ln31_reg_4809_pp2_iter1_reg, ap_enable_reg_pp2_iter2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4809_pp2_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            out_loc_we1 <= ap_const_logic_1;
+        else 
+            out_loc_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_AWVALID_assign_proc : process(ap_CS_fsm_state26, out_mem_AWREADY)
+    begin
+        if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state26))) then 
+            out_mem_AWVALID <= ap_const_logic_1;
+        else 
+            out_mem_AWVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_BREADY_assign_proc : process(ap_CS_fsm_state34, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then 
+            out_mem_BREADY <= ap_const_logic_1;
+        else 
+            out_mem_BREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_WVALID_assign_proc : process(ap_enable_reg_pp3_iter2, icmp_ln42_reg_5549_pp3_iter1_reg, ap_block_pp3_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_reg_5549_pp3_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1))) then 
+            out_mem_WVALID <= ap_const_logic_1;
+        else 
+            out_mem_WVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AW_assign_proc : process(m_axi_out_mem_AWREADY, ap_CS_fsm_state26)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state26)) then 
+            out_mem_blk_n_AW <= m_axi_out_mem_AWREADY;
+        else 
+            out_mem_blk_n_AW <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_B_assign_proc : process(m_axi_out_mem_BVALID, ap_CS_fsm_state34)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state34)) then 
+            out_mem_blk_n_B <= m_axi_out_mem_BVALID;
+        else 
+            out_mem_blk_n_B <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_W_assign_proc : process(m_axi_out_mem_WREADY, ap_enable_reg_pp3_iter2, ap_block_pp3_stage0, icmp_ln42_reg_5549_pp3_iter1_reg)
+    begin
+        if (((icmp_ln42_reg_5549_pp3_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp3_stage0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1))) then 
+            out_mem_blk_n_W <= m_axi_out_mem_WREADY;
+        else 
+            out_mem_blk_n_W <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    select_ln31_1_fu_3645_p3 <= 
+        i_fu_3626_p2 when (icmp_ln33_fu_3632_p2(0) = '1') else 
+        ap_phi_mux_i_0_phi_fu_3333_p4;
+    select_ln31_fu_3637_p3 <= 
+        ap_const_lv32_0 when (icmp_ln33_fu_3632_p2(0) = '1') else 
+        j_0_reg_3340;
+        sext_ln38_fu_3733_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(select_ln31_fu_3637_p3),64));
+
+    tmp_cast_fu_3657_p3 <= (trunc_ln38_fu_3653_p1 & ap_const_lv6_0);
+    trunc_ln27_fu_3442_p1 <= phi_ln27_reg_3296(6 - 1 downto 0);
+    trunc_ln28_fu_3525_p1 <= phi_ln28_reg_3307(6 - 1 downto 0);
+    trunc_ln38_1_fu_3801_p1 <= select_ln31_fu_3637_p3(14 - 1 downto 0);
+    trunc_ln38_fu_3653_p1 <= select_ln31_1_fu_3645_p3(8 - 1 downto 0);
+    zext_ln27_fu_3446_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(lshr_ln_reg_4641_pp0_iter1_reg),64));
+    zext_ln28_fu_3539_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(trunc_ln28_reg_4727_pp1_iter1_reg),64));
+    zext_ln31_1_fu_3665_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(select_ln31_1_fu_3645_p3),64));
+    zext_ln31_fu_3606_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(dim_read_reg_4593),64));
+    zext_ln38_fu_3811_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln38_64_fu_3805_p2),64));
+    zext_ln42_fu_4588_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln42_reg_3351),64));
+end behav;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in1_loc_0.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in1_loc_0.vhd
new file mode 100755
index 0000000..609e4b6
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in1_loc_0.vhd
@@ -0,0 +1,112 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_in1_loc_0_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 6; 
+            MEM_SIZE    : integer := 64
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_in1_loc_0_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_in1_loc_0 is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 64;
+        AddressWidth : INTEGER := 6);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_in1_loc_0 is
+    component mmult_in1_loc_0_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_in1_loc_0_ram_U :  component mmult_in1_loc_0_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in1_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in1_mem_m_axi.vhd
new file mode 100755
index 0000000..5d4f5b4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in1_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi;
+
+architecture behave of mmult_in1_mem_m_axi is
+    component mmult_in1_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_write;
+
+    component mmult_in1_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_read;
+
+    component mmult_in1_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in1_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in1_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in1_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in1_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in1_mem_m_axi_fifo;
+
+architecture behave of mmult_in1_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in1_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in1_mem_m_axi_decoder;
+
+architecture behav of mmult_in1_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in1_mem_m_axi_throttl;
+
+architecture behav of mmult_in1_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in1_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in1_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_read;
+
+architecture behave of mmult_in1_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_write;
+
+architecture behave of mmult_in1_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in1_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in1_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in2_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in2_mem_m_axi.vhd
new file mode 100755
index 0000000..84687e2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_in2_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi;
+
+architecture behave of mmult_in2_mem_m_axi is
+    component mmult_in2_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_write;
+
+    component mmult_in2_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_read;
+
+    component mmult_in2_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in2_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in2_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in2_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in2_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in2_mem_m_axi_fifo;
+
+architecture behave of mmult_in2_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in2_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in2_mem_m_axi_decoder;
+
+architecture behav of mmult_in2_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in2_mem_m_axi_throttl;
+
+architecture behav of mmult_in2_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in2_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in2_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_read;
+
+architecture behave of mmult_in2_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_write;
+
+architecture behave of mmult_in2_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in2_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in2_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_out_loc.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_out_loc.vhd
new file mode 100755
index 0000000..ea7bf78
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_out_loc.vhd
@@ -0,0 +1,129 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_out_loc_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 12; 
+            MEM_SIZE    : integer := 4096
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce1       : in std_logic; 
+          d1        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we1       : in std_logic; 
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_out_loc_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+        end if;
+    end if;
+end process;
+
+
+p_memory_access_1: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce1 = '1') then 
+            if (we1 = '1') then 
+                ram(CONV_INTEGER(addr1)) := d1; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_out_loc is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 4096;
+        AddressWidth : INTEGER := 12);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_out_loc is
+    component mmult_out_loc_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            q0 : OUT STD_LOGIC_VECTOR;
+            addr1 : IN STD_LOGIC_VECTOR;
+            ce1 : IN STD_LOGIC;
+            we1 : IN STD_LOGIC;
+            d1 : IN STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_out_loc_ram_U :  component mmult_out_loc_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        q0 => q0,
+        addr1 => address1,
+        ce1 => ce1,
+        we1 => we1,
+        d1 => d1);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_out_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_out_mem_m_axi.vhd
new file mode 100755
index 0000000..f2bd717
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_out_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi;
+
+architecture behave of mmult_out_mem_m_axi is
+    component mmult_out_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_write;
+
+    component mmult_out_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_read;
+
+    component mmult_out_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_out_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_out_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_out_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi_reg_slice;
+
+architecture behave of mmult_out_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_out_mem_m_axi_fifo;
+
+architecture behave of mmult_out_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_out_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_out_mem_m_axi_decoder;
+
+architecture behav of mmult_out_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_out_mem_m_axi_throttl;
+
+architecture behav of mmult_out_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_out_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_out_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_read;
+
+architecture behave of mmult_out_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_write;
+
+architecture behave of mmult_out_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_out_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_out_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_params_s_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_params_s_axi.vhd
new file mode 100755
index 0000000..1f9adde
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/hdl/vhdl/mmult_params_s_axi.vhd
@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/misc/logo.png b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/misc/logo.png
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diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/xgui/mmult_v7_0.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/xgui/mmult_v7_0.tcl
new file mode 100755
index 0000000..0276fbf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_7/xgui/mmult_v7_0.tcl
@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/component.xml b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/component.xml
new file mode 100755
index 0000000..69919dc
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/component.xml
@@ -0,0 +1,5578 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>hls</spirit:library>
+  <spirit:name>mmult</spirit:name>
+  <spirit:version>8.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_params"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.ADDR_WIDTH">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi_params:m_axi_in1_mem:m_axi_in2_mem:m_axi_out_mem</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interrupt</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in1_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in1_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in2_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in2_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_out_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_out_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in1_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in2_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_out_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_BASE_PARAM">C_S_AXI_PARAMS_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_HIGH_PARAM">C_S_AXI_PARAMS_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>CTRL</spirit:name>
+          <spirit:displayName>CTRL</spirit:displayName>
+          <spirit:description>Control signals</spirit:description>
+          <spirit:addressOffset>0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>AP_START</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_start&apos;.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_DONE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_done&apos;.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_IDLE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_idle&apos;.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_READY</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_ready&apos;.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_1</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">3</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AUTO_RESTART</spirit:name>
+            <spirit:description>Control signal Register for &apos;auto_restart&apos;.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_2</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">24</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GIER</spirit:name>
+          <spirit:displayName>GIER</spirit:displayName>
+          <spirit:description>Global Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>4</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Enable</spirit:name>
+            <spirit:description>Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">31</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_IER</spirit:name>
+          <spirit:displayName>IP_IER</spirit:displayName>
+          <spirit:description>IP Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>8</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 0 (ap_done) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 1 (ap_ready) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_ISR</spirit:name>
+          <spirit:displayName>IP_ISR</spirit:displayName>
+          <spirit:description>IP Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>12</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_ST</spirit:name>
+            <spirit:description>Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 input interrupt, 1 = Channel 0 input interrup</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_ST</spirit:name>
+            <spirit:description>Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 input interrupt, 1 = Channel 1 input interrup</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>in1</spirit:name>
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+      </spirit:file>
+      <spirit:file>
+        <spirit:name>drivers/mmult_v8_0/src/xmmult_linux.c</spirit:name>
+        <spirit:userFileType>driver_src</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>drivers/mmult_v8_0/src/xmmult_sinit.c</spirit:name>
+        <spirit:userFileType>driver_src</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_documentation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>doc/ReleaseNotes.txt</spirit:name>
+        <spirit:userFileType>text</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_miscfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>misc/logo.png</spirit:name>
+        <spirit:userFileType>image</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/mmult_v8_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_3f68c42e</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>misc/logo.png</spirit:name>
+        <spirit:userFileType>image</spirit:userFileType>
+        <spirit:userFileType>LOGO</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>An IP generated by Vivado HLS</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" spirit:order="2" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH" spirit:order="3" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="4" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" spirit:order="5" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH" spirit:order="6" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH" spirit:order="7" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
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+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH" spirit:order="8" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH" spirit:order="9" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH" spirit:order="10" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE" spirit:order="11" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE" spirit:order="12" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE" spirit:order="13" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" spirit:order="14" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH" spirit:order="15" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="16" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" spirit:order="17" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH" spirit:order="18" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH" spirit:order="19" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH" spirit:order="20" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH" spirit:order="21" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH" spirit:order="22" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE" spirit:order="23" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE" spirit:order="24" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE" spirit:order="25" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" spirit:order="26" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH" spirit:order="27" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="28" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" spirit:order="29" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH" spirit:order="30" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH" spirit:order="31" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH" spirit:order="32" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH" spirit:order="33" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH" spirit:order="34" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE" spirit:order="35" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE" spirit:order="36" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE" spirit:order="37" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mmult_v8_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>clk_period</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.clk_period" spirit:order="38">5</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>machine</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.machine" spirit:order="39">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>combinational</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.combinational" spirit:order="40">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>latency</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.latency" spirit:order="41">16415</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>II</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.II" spirit:order="42">x</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/VIVADO_HLS_IP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>Mmult</xilinx:displayName>
+      <xilinx:definitionSource>HLS</xilinx:definitionSource>
+      <xilinx:coreRevision>2105141831</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2021-05-14T16:31:31Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b5dd57e8"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="c6fd4807"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5ce530f0"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="748b5175"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="7681d788"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c9a673dd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="49c4139e"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/constraints/mmult_ooc.xdc b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/constraints/mmult_ooc.xdc
new file mode 100755
index 0000000..60a9ff7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/constraints/mmult_ooc.xdc
@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 5.000 [get_ports ap_clk]
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/doc/ReleaseNotes.txt b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/doc/ReleaseNotes.txt
new file mode 100755
index 0000000..a04ae42
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/doc/ReleaseNotes.txt
@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 5.000 ns
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/data/mmult.mdd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/data/mmult.mdd
new file mode 100755
index 0000000..f96920a
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/data/mmult.mdd
@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v8_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 8.0;
+
+END driver
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/data/mmult.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/data/mmult.tcl
new file mode 100755
index 0000000..0de7a9c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/data/mmult.tcl
@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/Makefile b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/Makefile
new file mode 100755
index 0000000..7f76086
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/Makefile
@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult.c
new file mode 100755
index 0000000..fb9a1fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult.c
@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult.h
new file mode 100755
index 0000000..4983669
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult.h
@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_hw.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_hw.h
new file mode 100755
index 0000000..3a0a2a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_hw.h
@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_linux.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_linux.c
new file mode 100755
index 0000000..c8dbb33
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_linux.c
@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_sinit.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_sinit.c
new file mode 100755
index 0000000..f099590
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/drivers/mmult_v8_0/src/xmmult_sinit.c
@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult.v
new file mode 100755
index 0000000..6870150
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult.v
@@ -0,0 +1,8344 @@
+// ==============================================================
+// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+// Version: 2020.1
+// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+// 
+// ===========================================================
+
+`timescale 1 ns / 1 ps 
+
+(* CORE_GENERATION_INFO="mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.375000,HLS_SYN_LAT=16415,HLS_SYN_TPT=none,HLS_SYN_MEM=142,HLS_SYN_DSP=260,HLS_SYN_FF=9119,HLS_SYN_LUT=8264,HLS_VERSION=2020_1}" *)
+
+module mmult (
+        ap_clk,
+        ap_rst_n,
+        m_axi_in1_mem_AWVALID,
+        m_axi_in1_mem_AWREADY,
+        m_axi_in1_mem_AWADDR,
+        m_axi_in1_mem_AWID,
+        m_axi_in1_mem_AWLEN,
+        m_axi_in1_mem_AWSIZE,
+        m_axi_in1_mem_AWBURST,
+        m_axi_in1_mem_AWLOCK,
+        m_axi_in1_mem_AWCACHE,
+        m_axi_in1_mem_AWPROT,
+        m_axi_in1_mem_AWQOS,
+        m_axi_in1_mem_AWREGION,
+        m_axi_in1_mem_AWUSER,
+        m_axi_in1_mem_WVALID,
+        m_axi_in1_mem_WREADY,
+        m_axi_in1_mem_WDATA,
+        m_axi_in1_mem_WSTRB,
+        m_axi_in1_mem_WLAST,
+        m_axi_in1_mem_WID,
+        m_axi_in1_mem_WUSER,
+        m_axi_in1_mem_ARVALID,
+        m_axi_in1_mem_ARREADY,
+        m_axi_in1_mem_ARADDR,
+        m_axi_in1_mem_ARID,
+        m_axi_in1_mem_ARLEN,
+        m_axi_in1_mem_ARSIZE,
+        m_axi_in1_mem_ARBURST,
+        m_axi_in1_mem_ARLOCK,
+        m_axi_in1_mem_ARCACHE,
+        m_axi_in1_mem_ARPROT,
+        m_axi_in1_mem_ARQOS,
+        m_axi_in1_mem_ARREGION,
+        m_axi_in1_mem_ARUSER,
+        m_axi_in1_mem_RVALID,
+        m_axi_in1_mem_RREADY,
+        m_axi_in1_mem_RDATA,
+        m_axi_in1_mem_RLAST,
+        m_axi_in1_mem_RID,
+        m_axi_in1_mem_RUSER,
+        m_axi_in1_mem_RRESP,
+        m_axi_in1_mem_BVALID,
+        m_axi_in1_mem_BREADY,
+        m_axi_in1_mem_BRESP,
+        m_axi_in1_mem_BID,
+        m_axi_in1_mem_BUSER,
+        m_axi_in2_mem_AWVALID,
+        m_axi_in2_mem_AWREADY,
+        m_axi_in2_mem_AWADDR,
+        m_axi_in2_mem_AWID,
+        m_axi_in2_mem_AWLEN,
+        m_axi_in2_mem_AWSIZE,
+        m_axi_in2_mem_AWBURST,
+        m_axi_in2_mem_AWLOCK,
+        m_axi_in2_mem_AWCACHE,
+        m_axi_in2_mem_AWPROT,
+        m_axi_in2_mem_AWQOS,
+        m_axi_in2_mem_AWREGION,
+        m_axi_in2_mem_AWUSER,
+        m_axi_in2_mem_WVALID,
+        m_axi_in2_mem_WREADY,
+        m_axi_in2_mem_WDATA,
+        m_axi_in2_mem_WSTRB,
+        m_axi_in2_mem_WLAST,
+        m_axi_in2_mem_WID,
+        m_axi_in2_mem_WUSER,
+        m_axi_in2_mem_ARVALID,
+        m_axi_in2_mem_ARREADY,
+        m_axi_in2_mem_ARADDR,
+        m_axi_in2_mem_ARID,
+        m_axi_in2_mem_ARLEN,
+        m_axi_in2_mem_ARSIZE,
+        m_axi_in2_mem_ARBURST,
+        m_axi_in2_mem_ARLOCK,
+        m_axi_in2_mem_ARCACHE,
+        m_axi_in2_mem_ARPROT,
+        m_axi_in2_mem_ARQOS,
+        m_axi_in2_mem_ARREGION,
+        m_axi_in2_mem_ARUSER,
+        m_axi_in2_mem_RVALID,
+        m_axi_in2_mem_RREADY,
+        m_axi_in2_mem_RDATA,
+        m_axi_in2_mem_RLAST,
+        m_axi_in2_mem_RID,
+        m_axi_in2_mem_RUSER,
+        m_axi_in2_mem_RRESP,
+        m_axi_in2_mem_BVALID,
+        m_axi_in2_mem_BREADY,
+        m_axi_in2_mem_BRESP,
+        m_axi_in2_mem_BID,
+        m_axi_in2_mem_BUSER,
+        m_axi_out_mem_AWVALID,
+        m_axi_out_mem_AWREADY,
+        m_axi_out_mem_AWADDR,
+        m_axi_out_mem_AWID,
+        m_axi_out_mem_AWLEN,
+        m_axi_out_mem_AWSIZE,
+        m_axi_out_mem_AWBURST,
+        m_axi_out_mem_AWLOCK,
+        m_axi_out_mem_AWCACHE,
+        m_axi_out_mem_AWPROT,
+        m_axi_out_mem_AWQOS,
+        m_axi_out_mem_AWREGION,
+        m_axi_out_mem_AWUSER,
+        m_axi_out_mem_WVALID,
+        m_axi_out_mem_WREADY,
+        m_axi_out_mem_WDATA,
+        m_axi_out_mem_WSTRB,
+        m_axi_out_mem_WLAST,
+        m_axi_out_mem_WID,
+        m_axi_out_mem_WUSER,
+        m_axi_out_mem_ARVALID,
+        m_axi_out_mem_ARREADY,
+        m_axi_out_mem_ARADDR,
+        m_axi_out_mem_ARID,
+        m_axi_out_mem_ARLEN,
+        m_axi_out_mem_ARSIZE,
+        m_axi_out_mem_ARBURST,
+        m_axi_out_mem_ARLOCK,
+        m_axi_out_mem_ARCACHE,
+        m_axi_out_mem_ARPROT,
+        m_axi_out_mem_ARQOS,
+        m_axi_out_mem_ARREGION,
+        m_axi_out_mem_ARUSER,
+        m_axi_out_mem_RVALID,
+        m_axi_out_mem_RREADY,
+        m_axi_out_mem_RDATA,
+        m_axi_out_mem_RLAST,
+        m_axi_out_mem_RID,
+        m_axi_out_mem_RUSER,
+        m_axi_out_mem_RRESP,
+        m_axi_out_mem_BVALID,
+        m_axi_out_mem_BREADY,
+        m_axi_out_mem_BRESP,
+        m_axi_out_mem_BID,
+        m_axi_out_mem_BUSER,
+        s_axi_params_AWVALID,
+        s_axi_params_AWREADY,
+        s_axi_params_AWADDR,
+        s_axi_params_WVALID,
+        s_axi_params_WREADY,
+        s_axi_params_WDATA,
+        s_axi_params_WSTRB,
+        s_axi_params_ARVALID,
+        s_axi_params_ARREADY,
+        s_axi_params_ARADDR,
+        s_axi_params_RVALID,
+        s_axi_params_RREADY,
+        s_axi_params_RDATA,
+        s_axi_params_RRESP,
+        s_axi_params_BVALID,
+        s_axi_params_BREADY,
+        s_axi_params_BRESP,
+        interrupt
+);
+
+parameter    ap_ST_fsm_state1 = 26'd1;
+parameter    ap_ST_fsm_state2 = 26'd2;
+parameter    ap_ST_fsm_state3 = 26'd4;
+parameter    ap_ST_fsm_state4 = 26'd8;
+parameter    ap_ST_fsm_state5 = 26'd16;
+parameter    ap_ST_fsm_state6 = 26'd32;
+parameter    ap_ST_fsm_state7 = 26'd64;
+parameter    ap_ST_fsm_state8 = 26'd128;
+parameter    ap_ST_fsm_pp0_stage0 = 26'd256;
+parameter    ap_ST_fsm_state12 = 26'd512;
+parameter    ap_ST_fsm_state13 = 26'd1024;
+parameter    ap_ST_fsm_state14 = 26'd2048;
+parameter    ap_ST_fsm_state15 = 26'd4096;
+parameter    ap_ST_fsm_state16 = 26'd8192;
+parameter    ap_ST_fsm_state17 = 26'd16384;
+parameter    ap_ST_fsm_state18 = 26'd32768;
+parameter    ap_ST_fsm_pp1_stage0 = 26'd65536;
+parameter    ap_ST_fsm_state22 = 26'd131072;
+parameter    ap_ST_fsm_pp2_stage0 = 26'd262144;
+parameter    ap_ST_fsm_state28 = 26'd524288;
+parameter    ap_ST_fsm_pp3_stage0 = 26'd1048576;
+parameter    ap_ST_fsm_state32 = 26'd2097152;
+parameter    ap_ST_fsm_state33 = 26'd4194304;
+parameter    ap_ST_fsm_state34 = 26'd8388608;
+parameter    ap_ST_fsm_state35 = 26'd16777216;
+parameter    ap_ST_fsm_state36 = 26'd33554432;
+parameter    C_S_AXI_PARAMS_DATA_WIDTH = 32;
+parameter    C_S_AXI_PARAMS_ADDR_WIDTH = 6;
+parameter    C_S_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_OUT_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_CACHE_VALUE = 3;
+
+parameter C_S_AXI_PARAMS_WSTRB_WIDTH = (32 / 8);
+parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN1_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN2_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_OUT_MEM_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+output   m_axi_in1_mem_AWVALID;
+input   m_axi_in1_mem_AWREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_AWADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_AWID;
+output  [7:0] m_axi_in1_mem_AWLEN;
+output  [2:0] m_axi_in1_mem_AWSIZE;
+output  [1:0] m_axi_in1_mem_AWBURST;
+output  [1:0] m_axi_in1_mem_AWLOCK;
+output  [3:0] m_axi_in1_mem_AWCACHE;
+output  [2:0] m_axi_in1_mem_AWPROT;
+output  [3:0] m_axi_in1_mem_AWQOS;
+output  [3:0] m_axi_in1_mem_AWREGION;
+output  [C_M_AXI_IN1_MEM_AWUSER_WIDTH - 1:0] m_axi_in1_mem_AWUSER;
+output   m_axi_in1_mem_WVALID;
+input   m_axi_in1_mem_WREADY;
+output  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_WDATA;
+output  [C_M_AXI_IN1_MEM_WSTRB_WIDTH - 1:0] m_axi_in1_mem_WSTRB;
+output   m_axi_in1_mem_WLAST;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_WID;
+output  [C_M_AXI_IN1_MEM_WUSER_WIDTH - 1:0] m_axi_in1_mem_WUSER;
+output   m_axi_in1_mem_ARVALID;
+input   m_axi_in1_mem_ARREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_ARADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_ARID;
+output  [7:0] m_axi_in1_mem_ARLEN;
+output  [2:0] m_axi_in1_mem_ARSIZE;
+output  [1:0] m_axi_in1_mem_ARBURST;
+output  [1:0] m_axi_in1_mem_ARLOCK;
+output  [3:0] m_axi_in1_mem_ARCACHE;
+output  [2:0] m_axi_in1_mem_ARPROT;
+output  [3:0] m_axi_in1_mem_ARQOS;
+output  [3:0] m_axi_in1_mem_ARREGION;
+output  [C_M_AXI_IN1_MEM_ARUSER_WIDTH - 1:0] m_axi_in1_mem_ARUSER;
+input   m_axi_in1_mem_RVALID;
+output   m_axi_in1_mem_RREADY;
+input  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_RDATA;
+input   m_axi_in1_mem_RLAST;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_RID;
+input  [C_M_AXI_IN1_MEM_RUSER_WIDTH - 1:0] m_axi_in1_mem_RUSER;
+input  [1:0] m_axi_in1_mem_RRESP;
+input   m_axi_in1_mem_BVALID;
+output   m_axi_in1_mem_BREADY;
+input  [1:0] m_axi_in1_mem_BRESP;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_BID;
+input  [C_M_AXI_IN1_MEM_BUSER_WIDTH - 1:0] m_axi_in1_mem_BUSER;
+output   m_axi_in2_mem_AWVALID;
+input   m_axi_in2_mem_AWREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_AWADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_AWID;
+output  [7:0] m_axi_in2_mem_AWLEN;
+output  [2:0] m_axi_in2_mem_AWSIZE;
+output  [1:0] m_axi_in2_mem_AWBURST;
+output  [1:0] m_axi_in2_mem_AWLOCK;
+output  [3:0] m_axi_in2_mem_AWCACHE;
+output  [2:0] m_axi_in2_mem_AWPROT;
+output  [3:0] m_axi_in2_mem_AWQOS;
+output  [3:0] m_axi_in2_mem_AWREGION;
+output  [C_M_AXI_IN2_MEM_AWUSER_WIDTH - 1:0] m_axi_in2_mem_AWUSER;
+output   m_axi_in2_mem_WVALID;
+input   m_axi_in2_mem_WREADY;
+output  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_WDATA;
+output  [C_M_AXI_IN2_MEM_WSTRB_WIDTH - 1:0] m_axi_in2_mem_WSTRB;
+output   m_axi_in2_mem_WLAST;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_WID;
+output  [C_M_AXI_IN2_MEM_WUSER_WIDTH - 1:0] m_axi_in2_mem_WUSER;
+output   m_axi_in2_mem_ARVALID;
+input   m_axi_in2_mem_ARREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_ARADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_ARID;
+output  [7:0] m_axi_in2_mem_ARLEN;
+output  [2:0] m_axi_in2_mem_ARSIZE;
+output  [1:0] m_axi_in2_mem_ARBURST;
+output  [1:0] m_axi_in2_mem_ARLOCK;
+output  [3:0] m_axi_in2_mem_ARCACHE;
+output  [2:0] m_axi_in2_mem_ARPROT;
+output  [3:0] m_axi_in2_mem_ARQOS;
+output  [3:0] m_axi_in2_mem_ARREGION;
+output  [C_M_AXI_IN2_MEM_ARUSER_WIDTH - 1:0] m_axi_in2_mem_ARUSER;
+input   m_axi_in2_mem_RVALID;
+output   m_axi_in2_mem_RREADY;
+input  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_RDATA;
+input   m_axi_in2_mem_RLAST;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_RID;
+input  [C_M_AXI_IN2_MEM_RUSER_WIDTH - 1:0] m_axi_in2_mem_RUSER;
+input  [1:0] m_axi_in2_mem_RRESP;
+input   m_axi_in2_mem_BVALID;
+output   m_axi_in2_mem_BREADY;
+input  [1:0] m_axi_in2_mem_BRESP;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_BID;
+input  [C_M_AXI_IN2_MEM_BUSER_WIDTH - 1:0] m_axi_in2_mem_BUSER;
+output   m_axi_out_mem_AWVALID;
+input   m_axi_out_mem_AWREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_AWADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_AWID;
+output  [7:0] m_axi_out_mem_AWLEN;
+output  [2:0] m_axi_out_mem_AWSIZE;
+output  [1:0] m_axi_out_mem_AWBURST;
+output  [1:0] m_axi_out_mem_AWLOCK;
+output  [3:0] m_axi_out_mem_AWCACHE;
+output  [2:0] m_axi_out_mem_AWPROT;
+output  [3:0] m_axi_out_mem_AWQOS;
+output  [3:0] m_axi_out_mem_AWREGION;
+output  [C_M_AXI_OUT_MEM_AWUSER_WIDTH - 1:0] m_axi_out_mem_AWUSER;
+output   m_axi_out_mem_WVALID;
+input   m_axi_out_mem_WREADY;
+output  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_WDATA;
+output  [C_M_AXI_OUT_MEM_WSTRB_WIDTH - 1:0] m_axi_out_mem_WSTRB;
+output   m_axi_out_mem_WLAST;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_WID;
+output  [C_M_AXI_OUT_MEM_WUSER_WIDTH - 1:0] m_axi_out_mem_WUSER;
+output   m_axi_out_mem_ARVALID;
+input   m_axi_out_mem_ARREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_ARADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_ARID;
+output  [7:0] m_axi_out_mem_ARLEN;
+output  [2:0] m_axi_out_mem_ARSIZE;
+output  [1:0] m_axi_out_mem_ARBURST;
+output  [1:0] m_axi_out_mem_ARLOCK;
+output  [3:0] m_axi_out_mem_ARCACHE;
+output  [2:0] m_axi_out_mem_ARPROT;
+output  [3:0] m_axi_out_mem_ARQOS;
+output  [3:0] m_axi_out_mem_ARREGION;
+output  [C_M_AXI_OUT_MEM_ARUSER_WIDTH - 1:0] m_axi_out_mem_ARUSER;
+input   m_axi_out_mem_RVALID;
+output   m_axi_out_mem_RREADY;
+input  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_RDATA;
+input   m_axi_out_mem_RLAST;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_RID;
+input  [C_M_AXI_OUT_MEM_RUSER_WIDTH - 1:0] m_axi_out_mem_RUSER;
+input  [1:0] m_axi_out_mem_RRESP;
+input   m_axi_out_mem_BVALID;
+output   m_axi_out_mem_BREADY;
+input  [1:0] m_axi_out_mem_BRESP;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_BID;
+input  [C_M_AXI_OUT_MEM_BUSER_WIDTH - 1:0] m_axi_out_mem_BUSER;
+input   s_axi_params_AWVALID;
+output   s_axi_params_AWREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_AWADDR;
+input   s_axi_params_WVALID;
+output   s_axi_params_WREADY;
+input  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_WDATA;
+input  [C_S_AXI_PARAMS_WSTRB_WIDTH - 1:0] s_axi_params_WSTRB;
+input   s_axi_params_ARVALID;
+output   s_axi_params_ARREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_ARADDR;
+output   s_axi_params_RVALID;
+input   s_axi_params_RREADY;
+output  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_RDATA;
+output  [1:0] s_axi_params_RRESP;
+output   s_axi_params_BVALID;
+input   s_axi_params_BREADY;
+output  [1:0] s_axi_params_BRESP;
+output   interrupt;
+
+ reg    ap_rst_n_inv;
+wire    ap_start;
+reg    ap_done;
+reg    ap_idle;
+(* fsm_encoding = "none" *) reg   [25:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    ap_ready;
+wire   [31:0] in1;
+wire   [31:0] in2;
+wire   [31:0] out_r;
+wire   [31:0] dim;
+reg    in1_mem_blk_n_AR;
+wire    ap_CS_fsm_state2;
+reg    in1_mem_blk_n_R;
+wire    ap_CS_fsm_pp0_stage0;
+reg    ap_enable_reg_pp0_iter1;
+wire    ap_block_pp0_stage0;
+reg    in2_mem_blk_n_AR;
+wire    ap_CS_fsm_state12;
+reg    in2_mem_blk_n_R;
+wire    ap_CS_fsm_pp1_stage0;
+reg    ap_enable_reg_pp1_iter1;
+wire    ap_block_pp1_stage0;
+reg    out_mem_blk_n_AW;
+wire    ap_CS_fsm_state28;
+reg    out_mem_blk_n_W;
+reg    ap_enable_reg_pp3_iter2;
+wire    ap_block_pp3_stage0;
+reg   [0:0] icmp_ln42_reg_6313;
+reg   [0:0] icmp_ln42_reg_6313_pp3_iter1_reg;
+reg    out_mem_blk_n_B;
+wire    ap_CS_fsm_state36;
+wire    in1_mem_AWREADY;
+wire    in1_mem_WREADY;
+reg    in1_mem_ARVALID;
+wire    in1_mem_ARREADY;
+wire   [31:0] in1_mem_ARADDR;
+wire    in1_mem_RVALID;
+reg    in1_mem_RREADY;
+wire   [31:0] in1_mem_RDATA;
+wire    in1_mem_RLAST;
+wire   [0:0] in1_mem_RID;
+wire   [0:0] in1_mem_RUSER;
+wire   [1:0] in1_mem_RRESP;
+wire    in1_mem_BVALID;
+wire   [1:0] in1_mem_BRESP;
+wire   [0:0] in1_mem_BID;
+wire   [0:0] in1_mem_BUSER;
+wire    in2_mem_AWREADY;
+wire    in2_mem_WREADY;
+reg    in2_mem_ARVALID;
+wire    in2_mem_ARREADY;
+wire    in2_mem_RVALID;
+reg    in2_mem_RREADY;
+wire   [31:0] in2_mem_RDATA;
+wire    in2_mem_RLAST;
+wire   [0:0] in2_mem_RID;
+wire   [0:0] in2_mem_RUSER;
+wire   [1:0] in2_mem_RRESP;
+wire    in2_mem_BVALID;
+wire   [1:0] in2_mem_BRESP;
+wire   [0:0] in2_mem_BID;
+wire   [0:0] in2_mem_BUSER;
+reg    out_mem_AWVALID;
+wire    out_mem_AWREADY;
+reg    out_mem_WVALID;
+wire    out_mem_WREADY;
+wire    out_mem_ARREADY;
+wire    out_mem_RVALID;
+wire   [31:0] out_mem_RDATA;
+wire    out_mem_RLAST;
+wire   [0:0] out_mem_RID;
+wire   [0:0] out_mem_RUSER;
+wire   [1:0] out_mem_RRESP;
+wire    out_mem_BVALID;
+reg    out_mem_BREADY;
+wire   [1:0] out_mem_BRESP;
+wire   [0:0] out_mem_BID;
+wire   [0:0] out_mem_BUSER;
+reg   [12:0] phi_ln27_reg_3296;
+reg   [12:0] phi_ln28_reg_3307;
+reg   [63:0] indvar_flatten_reg_3318;
+reg   [30:0] i_0_reg_3329;
+reg   [31:0] j_0_reg_3340;
+reg   [12:0] phi_ln42_reg_3351;
+reg   [31:0] dim_read_reg_4390;
+reg   [29:0] out5_reg_4396;
+reg   [29:0] in_reg_4401;
+reg   [29:0] in3_reg_4406;
+reg   [31:0] out_mem_addr_reg_4417;
+wire    ap_CS_fsm_state8;
+reg   [31:0] in2_mem_addr_reg_4423;
+wire   [0:0] icmp_ln27_fu_3420_p2;
+wire    ap_block_state9_pp0_stage0_iter0;
+reg    ap_block_state10_pp0_stage0_iter1;
+wire    ap_block_state11_pp0_stage0_iter2;
+reg    ap_block_pp0_stage0_11001;
+wire   [12:0] add_ln27_fu_3426_p2;
+reg    ap_enable_reg_pp0_iter0;
+reg   [6:0] lshr_ln_reg_4438;
+reg   [6:0] lshr_ln_reg_4438_pp0_iter1_reg;
+wire   [5:0] trunc_ln27_fu_3442_p1;
+reg   [5:0] trunc_ln27_reg_4443;
+reg   [5:0] trunc_ln27_reg_4443_pp0_iter1_reg;
+reg   [31:0] in1_mem_addr_read_reg_4447;
+wire   [0:0] icmp_ln28_fu_3513_p2;
+wire    ap_block_state19_pp1_stage0_iter0;
+reg    ap_block_state20_pp1_stage0_iter1;
+wire    ap_block_state21_pp1_stage0_iter2;
+reg    ap_block_pp1_stage0_11001;
+wire   [12:0] add_ln28_fu_3519_p2;
+reg    ap_enable_reg_pp1_iter0;
+wire   [5:0] trunc_ln28_fu_3525_p1;
+reg   [5:0] trunc_ln28_reg_4524;
+reg   [5:0] trunc_ln28_reg_4524_pp1_iter1_reg;
+reg   [5:0] trunc_ln1_reg_4529;
+reg   [5:0] trunc_ln1_reg_4529_pp1_iter1_reg;
+reg   [31:0] in2_mem_addr_read_reg_4533;
+wire   [63:0] mul_ln31_fu_3609_p2;
+reg   [63:0] mul_ln31_reg_4601;
+wire    ap_CS_fsm_state22;
+wire   [0:0] icmp_ln31_fu_3615_p2;
+reg   [0:0] icmp_ln31_reg_4606;
+wire    ap_CS_fsm_pp2_stage0;
+wire    ap_block_state23_pp2_stage0_iter0;
+wire    ap_block_state24_pp2_stage0_iter1;
+wire    ap_block_state25_pp2_stage0_iter2;
+wire    ap_block_state26_pp2_stage0_iter3;
+wire    ap_block_state27_pp2_stage0_iter4;
+wire    ap_block_pp2_stage0_11001;
+reg   [0:0] icmp_ln31_reg_4606_pp2_iter1_reg;
+reg   [0:0] icmp_ln31_reg_4606_pp2_iter2_reg;
+reg   [0:0] icmp_ln31_reg_4606_pp2_iter3_reg;
+wire   [63:0] add_ln31_fu_3620_p2;
+reg    ap_enable_reg_pp2_iter0;
+wire   [30:0] select_ln31_1_fu_3645_p3;
+reg   [30:0] select_ln31_1_reg_4615;
+wire   [63:0] zext_ln31_1_fu_3665_p1;
+reg   [63:0] zext_ln31_1_reg_4620;
+wire  signed [63:0] sext_ln38_fu_3726_p1;
+reg  signed [63:0] sext_ln38_reg_4916;
+reg   [11:0] out_loc_addr_reg_4927;
+reg   [11:0] out_loc_addr_reg_4927_pp2_iter1_reg;
+reg   [11:0] out_loc_addr_reg_4927_pp2_iter2_reg;
+reg   [11:0] out_loc_addr_reg_4927_pp2_iter3_reg;
+wire   [31:0] j_fu_3802_p2;
+wire   [31:0] in1_loc_0_q0;
+reg  signed [31:0] in1_loc_0_load_reg_5223;
+reg    ap_enable_reg_pp2_iter1;
+wire   [31:0] in1_loc_1_q0;
+reg  signed [31:0] in1_loc_1_load_reg_5228;
+wire   [31:0] in1_loc_2_q0;
+reg  signed [31:0] in1_loc_2_load_reg_5233;
+wire   [31:0] in1_loc_3_q0;
+reg  signed [31:0] in1_loc_3_load_reg_5238;
+wire   [31:0] in1_loc_4_q0;
+reg  signed [31:0] in1_loc_4_load_reg_5243;
+wire   [31:0] in1_loc_5_q0;
+reg  signed [31:0] in1_loc_5_load_reg_5248;
+wire   [31:0] in1_loc_6_q0;
+reg  signed [31:0] in1_loc_6_load_reg_5253;
+wire   [31:0] in1_loc_7_q0;
+reg  signed [31:0] in1_loc_7_load_reg_5258;
+wire   [31:0] in1_loc_8_q0;
+reg  signed [31:0] in1_loc_8_load_reg_5263;
+wire   [31:0] in1_loc_9_q0;
+reg  signed [31:0] in1_loc_9_load_reg_5268;
+wire   [31:0] in1_loc_10_q0;
+reg  signed [31:0] in1_loc_10_load_reg_5273;
+wire   [31:0] in1_loc_11_q0;
+reg  signed [31:0] in1_loc_11_load_reg_5278;
+wire   [31:0] in1_loc_12_q0;
+reg  signed [31:0] in1_loc_12_load_reg_5283;
+wire   [31:0] in1_loc_13_q0;
+reg  signed [31:0] in1_loc_13_load_reg_5288;
+wire   [31:0] in1_loc_14_q0;
+reg  signed [31:0] in1_loc_14_load_reg_5293;
+wire   [31:0] in1_loc_15_q0;
+reg  signed [31:0] in1_loc_15_load_reg_5298;
+wire   [31:0] in1_loc_16_q0;
+reg  signed [31:0] in1_loc_16_load_reg_5303;
+wire   [31:0] in1_loc_17_q0;
+reg  signed [31:0] in1_loc_17_load_reg_5308;
+wire   [31:0] in1_loc_18_q0;
+reg  signed [31:0] in1_loc_18_load_reg_5313;
+wire   [31:0] in1_loc_19_q0;
+reg  signed [31:0] in1_loc_19_load_reg_5318;
+wire   [31:0] in1_loc_20_q0;
+reg  signed [31:0] in1_loc_20_load_reg_5323;
+wire   [31:0] in1_loc_21_q0;
+reg  signed [31:0] in1_loc_21_load_reg_5328;
+wire   [31:0] in1_loc_22_q0;
+reg  signed [31:0] in1_loc_22_load_reg_5333;
+wire   [31:0] in1_loc_23_q0;
+reg  signed [31:0] in1_loc_23_load_reg_5338;
+wire   [31:0] in1_loc_24_q0;
+reg  signed [31:0] in1_loc_24_load_reg_5343;
+wire   [31:0] in1_loc_25_q0;
+reg  signed [31:0] in1_loc_25_load_reg_5348;
+wire   [31:0] in1_loc_26_q0;
+reg  signed [31:0] in1_loc_26_load_reg_5353;
+wire   [31:0] in1_loc_27_q0;
+reg  signed [31:0] in1_loc_27_load_reg_5358;
+wire   [31:0] in1_loc_28_q0;
+reg  signed [31:0] in1_loc_28_load_reg_5363;
+wire   [31:0] in1_loc_29_q0;
+reg  signed [31:0] in1_loc_29_load_reg_5368;
+wire   [31:0] in1_loc_30_q0;
+reg  signed [31:0] in1_loc_30_load_reg_5373;
+wire   [31:0] in1_loc_31_q0;
+reg  signed [31:0] in1_loc_31_load_reg_5378;
+wire   [31:0] in1_loc_32_q0;
+reg  signed [31:0] in1_loc_32_load_reg_5383;
+wire   [31:0] in1_loc_33_q0;
+reg  signed [31:0] in1_loc_33_load_reg_5388;
+wire   [31:0] in1_loc_34_q0;
+reg  signed [31:0] in1_loc_34_load_reg_5393;
+wire   [31:0] in1_loc_35_q0;
+reg  signed [31:0] in1_loc_35_load_reg_5398;
+wire   [31:0] in1_loc_36_q0;
+reg  signed [31:0] in1_loc_36_load_reg_5403;
+wire   [31:0] in1_loc_37_q0;
+reg  signed [31:0] in1_loc_37_load_reg_5408;
+wire   [31:0] in1_loc_38_q0;
+reg  signed [31:0] in1_loc_38_load_reg_5413;
+wire   [31:0] in1_loc_39_q0;
+reg  signed [31:0] in1_loc_39_load_reg_5418;
+wire   [31:0] in1_loc_40_q0;
+reg  signed [31:0] in1_loc_40_load_reg_5423;
+wire   [31:0] in1_loc_43_q0;
+reg  signed [31:0] in1_loc_43_load_reg_5438;
+wire   [31:0] in1_loc_44_q0;
+reg  signed [31:0] in1_loc_44_load_reg_5443;
+wire   [31:0] in1_loc_47_q0;
+reg  signed [31:0] in1_loc_47_load_reg_5458;
+wire   [31:0] in1_loc_48_q0;
+reg  signed [31:0] in1_loc_48_load_reg_5463;
+wire   [31:0] in1_loc_49_q0;
+reg  signed [31:0] in1_loc_49_load_reg_5468;
+wire   [31:0] in1_loc_50_q0;
+reg  signed [31:0] in1_loc_50_load_reg_5473;
+wire   [31:0] in1_loc_51_q0;
+reg  signed [31:0] in1_loc_51_load_reg_5478;
+wire   [31:0] in1_loc_52_q0;
+reg  signed [31:0] in1_loc_52_load_reg_5483;
+wire   [31:0] in1_loc_53_q0;
+reg  signed [31:0] in1_loc_53_load_reg_5488;
+wire   [31:0] in1_loc_54_q0;
+reg  signed [31:0] in1_loc_54_load_reg_5493;
+wire   [31:0] in1_loc_55_q0;
+reg  signed [31:0] in1_loc_55_load_reg_5498;
+wire   [31:0] in1_loc_56_q0;
+reg  signed [31:0] in1_loc_56_load_reg_5503;
+wire   [31:0] in1_loc_59_q0;
+reg  signed [31:0] in1_loc_59_load_reg_5518;
+wire   [31:0] in1_loc_60_q0;
+reg  signed [31:0] in1_loc_60_load_reg_5523;
+wire   [31:0] in1_loc_62_q0;
+reg  signed [31:0] in1_loc_62_load_reg_5533;
+wire   [31:0] in1_loc_63_q0;
+reg  signed [31:0] in1_loc_63_load_reg_5538;
+wire   [31:0] in2_loc_0_q0;
+reg  signed [31:0] in2_loc_0_load_reg_5543;
+wire   [31:0] in2_loc_1_q0;
+reg  signed [31:0] in2_loc_1_load_reg_5548;
+wire   [31:0] in2_loc_2_q0;
+reg  signed [31:0] in2_loc_2_load_reg_5553;
+wire   [31:0] in2_loc_3_q0;
+reg  signed [31:0] in2_loc_3_load_reg_5558;
+wire   [31:0] in2_loc_4_q0;
+reg  signed [31:0] in2_loc_4_load_reg_5563;
+wire   [31:0] in2_loc_5_q0;
+reg  signed [31:0] in2_loc_5_load_reg_5568;
+wire   [31:0] in2_loc_6_q0;
+reg  signed [31:0] in2_loc_6_load_reg_5573;
+wire   [31:0] in2_loc_7_q0;
+reg  signed [31:0] in2_loc_7_load_reg_5578;
+wire   [31:0] in2_loc_8_q0;
+reg  signed [31:0] in2_loc_8_load_reg_5583;
+wire   [31:0] in2_loc_9_q0;
+reg  signed [31:0] in2_loc_9_load_reg_5588;
+wire   [31:0] in2_loc_10_q0;
+reg  signed [31:0] in2_loc_10_load_reg_5593;
+wire   [31:0] in2_loc_11_q0;
+reg  signed [31:0] in2_loc_11_load_reg_5598;
+wire   [31:0] in2_loc_12_q0;
+reg  signed [31:0] in2_loc_12_load_reg_5603;
+wire   [31:0] in2_loc_13_q0;
+reg  signed [31:0] in2_loc_13_load_reg_5608;
+wire   [31:0] in2_loc_14_q0;
+reg  signed [31:0] in2_loc_14_load_reg_5613;
+wire   [31:0] in2_loc_15_q0;
+reg  signed [31:0] in2_loc_15_load_reg_5618;
+wire   [31:0] in2_loc_16_q0;
+reg  signed [31:0] in2_loc_16_load_reg_5623;
+wire   [31:0] in2_loc_17_q0;
+reg  signed [31:0] in2_loc_17_load_reg_5628;
+wire   [31:0] in2_loc_18_q0;
+reg  signed [31:0] in2_loc_18_load_reg_5633;
+wire   [31:0] in2_loc_19_q0;
+reg  signed [31:0] in2_loc_19_load_reg_5638;
+wire   [31:0] in2_loc_20_q0;
+reg  signed [31:0] in2_loc_20_load_reg_5643;
+wire   [31:0] in2_loc_21_q0;
+reg  signed [31:0] in2_loc_21_load_reg_5648;
+wire   [31:0] in2_loc_22_q0;
+reg  signed [31:0] in2_loc_22_load_reg_5653;
+wire   [31:0] in2_loc_23_q0;
+reg  signed [31:0] in2_loc_23_load_reg_5658;
+wire   [31:0] in2_loc_24_q0;
+reg  signed [31:0] in2_loc_24_load_reg_5663;
+wire   [31:0] in2_loc_25_q0;
+reg  signed [31:0] in2_loc_25_load_reg_5668;
+wire   [31:0] in2_loc_26_q0;
+reg  signed [31:0] in2_loc_26_load_reg_5673;
+wire   [31:0] in2_loc_27_q0;
+reg  signed [31:0] in2_loc_27_load_reg_5678;
+wire   [31:0] in2_loc_28_q0;
+reg  signed [31:0] in2_loc_28_load_reg_5683;
+wire   [31:0] in2_loc_29_q0;
+reg  signed [31:0] in2_loc_29_load_reg_5688;
+wire   [31:0] in2_loc_30_q0;
+reg  signed [31:0] in2_loc_30_load_reg_5693;
+wire   [31:0] in2_loc_31_q0;
+reg  signed [31:0] in2_loc_31_load_reg_5698;
+wire   [31:0] in2_loc_32_q0;
+reg  signed [31:0] in2_loc_32_load_reg_5703;
+wire   [31:0] in2_loc_33_q0;
+reg  signed [31:0] in2_loc_33_load_reg_5708;
+wire   [31:0] in2_loc_34_q0;
+reg  signed [31:0] in2_loc_34_load_reg_5713;
+wire   [31:0] in2_loc_35_q0;
+reg  signed [31:0] in2_loc_35_load_reg_5718;
+wire   [31:0] in2_loc_36_q0;
+reg  signed [31:0] in2_loc_36_load_reg_5723;
+wire   [31:0] in2_loc_37_q0;
+reg  signed [31:0] in2_loc_37_load_reg_5728;
+wire   [31:0] in2_loc_38_q0;
+reg  signed [31:0] in2_loc_38_load_reg_5733;
+wire   [31:0] in2_loc_39_q0;
+reg  signed [31:0] in2_loc_39_load_reg_5738;
+wire   [31:0] in2_loc_40_q0;
+reg  signed [31:0] in2_loc_40_load_reg_5743;
+wire   [31:0] in2_loc_43_q0;
+reg  signed [31:0] in2_loc_43_load_reg_5758;
+wire   [31:0] in2_loc_44_q0;
+reg  signed [31:0] in2_loc_44_load_reg_5763;
+wire   [31:0] in2_loc_47_q0;
+reg  signed [31:0] in2_loc_47_load_reg_5778;
+wire   [31:0] in2_loc_48_q0;
+reg  signed [31:0] in2_loc_48_load_reg_5783;
+wire   [31:0] in2_loc_49_q0;
+reg  signed [31:0] in2_loc_49_load_reg_5788;
+wire   [31:0] in2_loc_50_q0;
+reg  signed [31:0] in2_loc_50_load_reg_5793;
+wire   [31:0] in2_loc_51_q0;
+reg  signed [31:0] in2_loc_51_load_reg_5798;
+wire   [31:0] in2_loc_52_q0;
+reg  signed [31:0] in2_loc_52_load_reg_5803;
+wire   [31:0] in2_loc_53_q0;
+reg  signed [31:0] in2_loc_53_load_reg_5808;
+wire   [31:0] in2_loc_54_q0;
+reg  signed [31:0] in2_loc_54_load_reg_5813;
+wire   [31:0] in2_loc_55_q0;
+reg  signed [31:0] in2_loc_55_load_reg_5818;
+wire   [31:0] in2_loc_56_q0;
+reg  signed [31:0] in2_loc_56_load_reg_5823;
+wire   [31:0] in2_loc_59_q0;
+reg  signed [31:0] in2_loc_59_load_reg_5838;
+wire   [31:0] in2_loc_60_q0;
+reg  signed [31:0] in2_loc_60_load_reg_5843;
+wire   [31:0] in2_loc_62_q0;
+reg  signed [31:0] in2_loc_62_load_reg_5853;
+wire   [31:0] in2_loc_63_q0;
+reg  signed [31:0] in2_loc_63_load_reg_5858;
+wire   [31:0] in1_loc_41_q0;
+reg  signed [31:0] in1_loc_41_load_reg_5863;
+reg    ap_enable_reg_pp2_iter2;
+wire   [31:0] in1_loc_42_q0;
+reg  signed [31:0] in1_loc_42_load_reg_5868;
+wire   [31:0] in1_loc_45_q0;
+reg  signed [31:0] in1_loc_45_load_reg_5873;
+wire   [31:0] in1_loc_46_q0;
+reg  signed [31:0] in1_loc_46_load_reg_5878;
+wire   [31:0] in1_loc_57_q0;
+reg  signed [31:0] in1_loc_57_load_reg_5883;
+wire   [31:0] in1_loc_58_q0;
+reg  signed [31:0] in1_loc_58_load_reg_5888;
+wire   [31:0] in1_loc_61_q0;
+reg  signed [31:0] in1_loc_61_load_reg_5893;
+wire   [31:0] mul_ln38_fu_3808_p2;
+reg   [31:0] mul_ln38_reg_5898;
+wire   [31:0] mul_ln38_1_fu_3812_p2;
+reg   [31:0] mul_ln38_1_reg_5903;
+wire   [31:0] mul_ln38_2_fu_3816_p2;
+reg   [31:0] mul_ln38_2_reg_5908;
+wire   [31:0] mul_ln38_3_fu_3820_p2;
+reg   [31:0] mul_ln38_3_reg_5913;
+wire   [31:0] mul_ln38_4_fu_3824_p2;
+reg   [31:0] mul_ln38_4_reg_5918;
+wire   [31:0] mul_ln38_5_fu_3828_p2;
+reg   [31:0] mul_ln38_5_reg_5923;
+wire   [31:0] mul_ln38_6_fu_3832_p2;
+reg   [31:0] mul_ln38_6_reg_5928;
+wire   [31:0] mul_ln38_7_fu_3836_p2;
+reg   [31:0] mul_ln38_7_reg_5933;
+wire   [31:0] mul_ln38_8_fu_3840_p2;
+reg   [31:0] mul_ln38_8_reg_5938;
+wire   [31:0] mul_ln38_9_fu_3844_p2;
+reg   [31:0] mul_ln38_9_reg_5943;
+wire   [31:0] mul_ln38_10_fu_3848_p2;
+reg   [31:0] mul_ln38_10_reg_5948;
+wire   [31:0] mul_ln38_11_fu_3852_p2;
+reg   [31:0] mul_ln38_11_reg_5953;
+wire   [31:0] mul_ln38_12_fu_3856_p2;
+reg   [31:0] mul_ln38_12_reg_5958;
+wire   [31:0] mul_ln38_13_fu_3860_p2;
+reg   [31:0] mul_ln38_13_reg_5963;
+wire   [31:0] mul_ln38_14_fu_3864_p2;
+reg   [31:0] mul_ln38_14_reg_5968;
+wire   [31:0] mul_ln38_15_fu_3868_p2;
+reg   [31:0] mul_ln38_15_reg_5973;
+wire   [31:0] mul_ln38_16_fu_3872_p2;
+reg   [31:0] mul_ln38_16_reg_5978;
+wire   [31:0] mul_ln38_17_fu_3876_p2;
+reg   [31:0] mul_ln38_17_reg_5983;
+wire   [31:0] mul_ln38_18_fu_3880_p2;
+reg   [31:0] mul_ln38_18_reg_5988;
+wire   [31:0] mul_ln38_19_fu_3884_p2;
+reg   [31:0] mul_ln38_19_reg_5993;
+wire   [31:0] mul_ln38_20_fu_3888_p2;
+reg   [31:0] mul_ln38_20_reg_5998;
+wire   [31:0] mul_ln38_21_fu_3892_p2;
+reg   [31:0] mul_ln38_21_reg_6003;
+wire   [31:0] mul_ln38_22_fu_3896_p2;
+reg   [31:0] mul_ln38_22_reg_6008;
+wire   [31:0] mul_ln38_23_fu_3900_p2;
+reg   [31:0] mul_ln38_23_reg_6013;
+wire   [31:0] mul_ln38_24_fu_3904_p2;
+reg   [31:0] mul_ln38_24_reg_6018;
+wire   [31:0] mul_ln38_25_fu_3908_p2;
+reg   [31:0] mul_ln38_25_reg_6023;
+wire   [31:0] mul_ln38_26_fu_3912_p2;
+reg   [31:0] mul_ln38_26_reg_6028;
+wire   [31:0] mul_ln38_27_fu_3916_p2;
+reg   [31:0] mul_ln38_27_reg_6033;
+wire   [31:0] mul_ln38_28_fu_3920_p2;
+reg   [31:0] mul_ln38_28_reg_6038;
+wire   [31:0] mul_ln38_29_fu_3924_p2;
+reg   [31:0] mul_ln38_29_reg_6043;
+wire   [31:0] mul_ln38_30_fu_3928_p2;
+reg   [31:0] mul_ln38_30_reg_6048;
+wire   [31:0] mul_ln38_31_fu_3932_p2;
+reg   [31:0] mul_ln38_31_reg_6053;
+wire   [31:0] mul_ln38_32_fu_3936_p2;
+reg   [31:0] mul_ln38_32_reg_6058;
+wire   [31:0] mul_ln38_33_fu_3940_p2;
+reg   [31:0] mul_ln38_33_reg_6063;
+wire   [31:0] mul_ln38_34_fu_3944_p2;
+reg   [31:0] mul_ln38_34_reg_6068;
+wire   [31:0] mul_ln38_35_fu_3948_p2;
+reg   [31:0] mul_ln38_35_reg_6073;
+wire   [31:0] mul_ln38_36_fu_3952_p2;
+reg   [31:0] mul_ln38_36_reg_6078;
+wire   [31:0] mul_ln38_37_fu_3956_p2;
+reg   [31:0] mul_ln38_37_reg_6083;
+wire   [31:0] mul_ln38_38_fu_3960_p2;
+reg   [31:0] mul_ln38_38_reg_6088;
+wire   [31:0] mul_ln38_39_fu_3964_p2;
+reg   [31:0] mul_ln38_39_reg_6093;
+wire   [31:0] mul_ln38_40_fu_3968_p2;
+reg   [31:0] mul_ln38_40_reg_6098;
+wire   [31:0] in2_loc_41_q0;
+reg  signed [31:0] in2_loc_41_load_reg_6103;
+wire   [31:0] in2_loc_42_q0;
+reg  signed [31:0] in2_loc_42_load_reg_6108;
+wire   [31:0] mul_ln38_43_fu_3972_p2;
+reg   [31:0] mul_ln38_43_reg_6113;
+wire   [31:0] mul_ln38_44_fu_3976_p2;
+reg   [31:0] mul_ln38_44_reg_6118;
+wire   [31:0] in2_loc_45_q0;
+reg  signed [31:0] in2_loc_45_load_reg_6123;
+wire   [31:0] in2_loc_46_q0;
+reg  signed [31:0] in2_loc_46_load_reg_6128;
+wire   [31:0] mul_ln38_47_fu_3980_p2;
+reg   [31:0] mul_ln38_47_reg_6133;
+wire   [31:0] mul_ln38_48_fu_3984_p2;
+reg   [31:0] mul_ln38_48_reg_6138;
+wire   [31:0] mul_ln38_49_fu_3988_p2;
+reg   [31:0] mul_ln38_49_reg_6143;
+wire   [31:0] mul_ln38_50_fu_3992_p2;
+reg   [31:0] mul_ln38_50_reg_6148;
+wire   [31:0] mul_ln38_51_fu_3996_p2;
+reg   [31:0] mul_ln38_51_reg_6153;
+wire   [31:0] mul_ln38_52_fu_4000_p2;
+reg   [31:0] mul_ln38_52_reg_6158;
+wire   [31:0] mul_ln38_53_fu_4004_p2;
+reg   [31:0] mul_ln38_53_reg_6163;
+wire   [31:0] mul_ln38_54_fu_4008_p2;
+reg   [31:0] mul_ln38_54_reg_6168;
+wire   [31:0] mul_ln38_55_fu_4012_p2;
+reg   [31:0] mul_ln38_55_reg_6173;
+wire   [31:0] mul_ln38_56_fu_4016_p2;
+reg   [31:0] mul_ln38_56_reg_6178;
+wire   [31:0] in2_loc_57_q0;
+reg  signed [31:0] in2_loc_57_load_reg_6183;
+wire   [31:0] in2_loc_58_q0;
+reg  signed [31:0] in2_loc_58_load_reg_6188;
+wire   [31:0] mul_ln38_59_fu_4020_p2;
+reg   [31:0] mul_ln38_59_reg_6193;
+wire   [31:0] mul_ln38_60_fu_4024_p2;
+reg   [31:0] mul_ln38_60_reg_6198;
+wire   [31:0] in2_loc_61_q0;
+reg  signed [31:0] in2_loc_61_load_reg_6203;
+wire   [31:0] mul_ln38_62_fu_4028_p2;
+reg   [31:0] mul_ln38_62_reg_6208;
+wire   [31:0] mul_ln38_63_fu_4032_p2;
+reg   [31:0] mul_ln38_63_reg_6213;
+wire   [31:0] mul_ln38_41_fu_4036_p2;
+reg   [31:0] mul_ln38_41_reg_6218;
+wire   [31:0] mul_ln38_42_fu_4040_p2;
+reg   [31:0] mul_ln38_42_reg_6223;
+wire   [31:0] mul_ln38_45_fu_4044_p2;
+reg   [31:0] mul_ln38_45_reg_6228;
+wire   [31:0] mul_ln38_46_fu_4048_p2;
+reg   [31:0] mul_ln38_46_reg_6233;
+wire   [31:0] mul_ln38_57_fu_4052_p2;
+reg   [31:0] mul_ln38_57_reg_6238;
+wire   [31:0] mul_ln38_58_fu_4056_p2;
+reg   [31:0] mul_ln38_58_reg_6243;
+wire   [31:0] mul_ln38_61_fu_4060_p2;
+reg   [31:0] mul_ln38_61_reg_6248;
+wire   [31:0] add_ln38_6_fu_4093_p2;
+reg   [31:0] add_ln38_6_reg_6253;
+wire   [31:0] add_ln38_9_fu_4107_p2;
+reg   [31:0] add_ln38_9_reg_6258;
+wire   [31:0] add_ln38_12_fu_4121_p2;
+reg   [31:0] add_ln38_12_reg_6263;
+wire   [31:0] add_ln38_21_fu_4155_p2;
+reg   [31:0] add_ln38_21_reg_6268;
+wire   [31:0] add_ln38_28_fu_4189_p2;
+reg   [31:0] add_ln38_28_reg_6273;
+wire   [31:0] add_ln38_37_fu_4223_p2;
+reg   [31:0] add_ln38_37_reg_6278;
+wire   [31:0] add_ln38_38_fu_4229_p2;
+reg   [31:0] add_ln38_38_reg_6283;
+wire   [31:0] add_ln38_41_fu_4233_p2;
+reg   [31:0] add_ln38_41_reg_6288;
+wire   [31:0] add_ln38_52_fu_4265_p2;
+reg   [31:0] add_ln38_52_reg_6293;
+wire   [31:0] add_ln38_53_fu_4271_p2;
+reg   [31:0] add_ln38_53_reg_6298;
+wire   [31:0] add_ln38_56_fu_4275_p2;
+reg   [31:0] add_ln38_56_reg_6303;
+wire   [31:0] add_ln38_57_fu_4279_p2;
+reg   [31:0] add_ln38_57_reg_6308;
+wire   [0:0] icmp_ln42_fu_4373_p2;
+wire    ap_CS_fsm_pp3_stage0;
+wire    ap_block_state29_pp3_stage0_iter0;
+wire    ap_block_state30_pp3_stage0_iter1;
+wire    ap_block_state31_pp3_stage0_iter2;
+reg    ap_block_state31_io;
+reg    ap_block_pp3_stage0_11001;
+wire   [12:0] add_ln42_fu_4379_p2;
+reg    ap_enable_reg_pp3_iter0;
+wire   [31:0] out_loc_q0;
+reg   [31:0] out_loc_load_reg_6327;
+reg    ap_enable_reg_pp3_iter1;
+reg    ap_block_pp0_stage0_subdone;
+reg    ap_condition_pp0_exit_iter0_state9;
+reg    ap_enable_reg_pp0_iter2;
+wire    ap_CS_fsm_state18;
+reg    ap_block_pp1_stage0_subdone;
+reg    ap_condition_pp1_exit_iter0_state19;
+reg    ap_enable_reg_pp1_iter2;
+wire    ap_block_pp2_stage0_subdone;
+reg    ap_condition_pp2_exit_iter0_state23;
+reg    ap_enable_reg_pp2_iter3;
+reg    ap_enable_reg_pp2_iter4;
+reg    ap_block_pp3_stage0_subdone;
+reg    ap_condition_pp3_exit_iter0_state29;
+reg   [5:0] in1_loc_0_address0;
+reg    in1_loc_0_ce0;
+reg    in1_loc_0_we0;
+reg   [5:0] in1_loc_1_address0;
+reg    in1_loc_1_ce0;
+reg    in1_loc_1_we0;
+reg   [5:0] in1_loc_2_address0;
+reg    in1_loc_2_ce0;
+reg    in1_loc_2_we0;
+reg   [5:0] in1_loc_3_address0;
+reg    in1_loc_3_ce0;
+reg    in1_loc_3_we0;
+reg   [5:0] in1_loc_4_address0;
+reg    in1_loc_4_ce0;
+reg    in1_loc_4_we0;
+reg   [5:0] in1_loc_5_address0;
+reg    in1_loc_5_ce0;
+reg    in1_loc_5_we0;
+reg   [5:0] in1_loc_6_address0;
+reg    in1_loc_6_ce0;
+reg    in1_loc_6_we0;
+reg   [5:0] in1_loc_7_address0;
+reg    in1_loc_7_ce0;
+reg    in1_loc_7_we0;
+reg   [5:0] in1_loc_8_address0;
+reg    in1_loc_8_ce0;
+reg    in1_loc_8_we0;
+reg   [5:0] in1_loc_9_address0;
+reg    in1_loc_9_ce0;
+reg    in1_loc_9_we0;
+reg   [5:0] in1_loc_10_address0;
+reg    in1_loc_10_ce0;
+reg    in1_loc_10_we0;
+reg   [5:0] in1_loc_11_address0;
+reg    in1_loc_11_ce0;
+reg    in1_loc_11_we0;
+reg   [5:0] in1_loc_12_address0;
+reg    in1_loc_12_ce0;
+reg    in1_loc_12_we0;
+reg   [5:0] in1_loc_13_address0;
+reg    in1_loc_13_ce0;
+reg    in1_loc_13_we0;
+reg   [5:0] in1_loc_14_address0;
+reg    in1_loc_14_ce0;
+reg    in1_loc_14_we0;
+reg   [5:0] in1_loc_15_address0;
+reg    in1_loc_15_ce0;
+reg    in1_loc_15_we0;
+reg   [5:0] in1_loc_16_address0;
+reg    in1_loc_16_ce0;
+reg    in1_loc_16_we0;
+reg   [5:0] in1_loc_17_address0;
+reg    in1_loc_17_ce0;
+reg    in1_loc_17_we0;
+reg   [5:0] in1_loc_18_address0;
+reg    in1_loc_18_ce0;
+reg    in1_loc_18_we0;
+reg   [5:0] in1_loc_19_address0;
+reg    in1_loc_19_ce0;
+reg    in1_loc_19_we0;
+reg   [5:0] in1_loc_20_address0;
+reg    in1_loc_20_ce0;
+reg    in1_loc_20_we0;
+reg   [5:0] in1_loc_21_address0;
+reg    in1_loc_21_ce0;
+reg    in1_loc_21_we0;
+reg   [5:0] in1_loc_22_address0;
+reg    in1_loc_22_ce0;
+reg    in1_loc_22_we0;
+reg   [5:0] in1_loc_23_address0;
+reg    in1_loc_23_ce0;
+reg    in1_loc_23_we0;
+reg   [5:0] in1_loc_24_address0;
+reg    in1_loc_24_ce0;
+reg    in1_loc_24_we0;
+reg   [5:0] in1_loc_25_address0;
+reg    in1_loc_25_ce0;
+reg    in1_loc_25_we0;
+reg   [5:0] in1_loc_26_address0;
+reg    in1_loc_26_ce0;
+reg    in1_loc_26_we0;
+reg   [5:0] in1_loc_27_address0;
+reg    in1_loc_27_ce0;
+reg    in1_loc_27_we0;
+reg   [5:0] in1_loc_28_address0;
+reg    in1_loc_28_ce0;
+reg    in1_loc_28_we0;
+reg   [5:0] in1_loc_29_address0;
+reg    in1_loc_29_ce0;
+reg    in1_loc_29_we0;
+reg   [5:0] in1_loc_30_address0;
+reg    in1_loc_30_ce0;
+reg    in1_loc_30_we0;
+reg   [5:0] in1_loc_31_address0;
+reg    in1_loc_31_ce0;
+reg    in1_loc_31_we0;
+reg   [5:0] in1_loc_32_address0;
+reg    in1_loc_32_ce0;
+reg    in1_loc_32_we0;
+reg   [5:0] in1_loc_33_address0;
+reg    in1_loc_33_ce0;
+reg    in1_loc_33_we0;
+reg   [5:0] in1_loc_34_address0;
+reg    in1_loc_34_ce0;
+reg    in1_loc_34_we0;
+reg   [5:0] in1_loc_35_address0;
+reg    in1_loc_35_ce0;
+reg    in1_loc_35_we0;
+reg   [5:0] in1_loc_36_address0;
+reg    in1_loc_36_ce0;
+reg    in1_loc_36_we0;
+reg   [5:0] in1_loc_37_address0;
+reg    in1_loc_37_ce0;
+reg    in1_loc_37_we0;
+reg   [5:0] in1_loc_38_address0;
+reg    in1_loc_38_ce0;
+reg    in1_loc_38_we0;
+reg   [5:0] in1_loc_39_address0;
+reg    in1_loc_39_ce0;
+reg    in1_loc_39_we0;
+reg   [5:0] in1_loc_40_address0;
+reg    in1_loc_40_ce0;
+reg    in1_loc_40_we0;
+reg   [5:0] in1_loc_41_address0;
+reg    in1_loc_41_ce0;
+reg    in1_loc_41_we0;
+reg   [5:0] in1_loc_42_address0;
+reg    in1_loc_42_ce0;
+reg    in1_loc_42_we0;
+reg   [5:0] in1_loc_43_address0;
+reg    in1_loc_43_ce0;
+reg    in1_loc_43_we0;
+reg   [5:0] in1_loc_44_address0;
+reg    in1_loc_44_ce0;
+reg    in1_loc_44_we0;
+reg   [5:0] in1_loc_45_address0;
+reg    in1_loc_45_ce0;
+reg    in1_loc_45_we0;
+reg   [5:0] in1_loc_46_address0;
+reg    in1_loc_46_ce0;
+reg    in1_loc_46_we0;
+reg   [5:0] in1_loc_47_address0;
+reg    in1_loc_47_ce0;
+reg    in1_loc_47_we0;
+reg   [5:0] in1_loc_48_address0;
+reg    in1_loc_48_ce0;
+reg    in1_loc_48_we0;
+reg   [5:0] in1_loc_49_address0;
+reg    in1_loc_49_ce0;
+reg    in1_loc_49_we0;
+reg   [5:0] in1_loc_50_address0;
+reg    in1_loc_50_ce0;
+reg    in1_loc_50_we0;
+reg   [5:0] in1_loc_51_address0;
+reg    in1_loc_51_ce0;
+reg    in1_loc_51_we0;
+reg   [5:0] in1_loc_52_address0;
+reg    in1_loc_52_ce0;
+reg    in1_loc_52_we0;
+reg   [5:0] in1_loc_53_address0;
+reg    in1_loc_53_ce0;
+reg    in1_loc_53_we0;
+reg   [5:0] in1_loc_54_address0;
+reg    in1_loc_54_ce0;
+reg    in1_loc_54_we0;
+reg   [5:0] in1_loc_55_address0;
+reg    in1_loc_55_ce0;
+reg    in1_loc_55_we0;
+reg   [5:0] in1_loc_56_address0;
+reg    in1_loc_56_ce0;
+reg    in1_loc_56_we0;
+reg   [5:0] in1_loc_57_address0;
+reg    in1_loc_57_ce0;
+reg    in1_loc_57_we0;
+reg   [5:0] in1_loc_58_address0;
+reg    in1_loc_58_ce0;
+reg    in1_loc_58_we0;
+reg   [5:0] in1_loc_59_address0;
+reg    in1_loc_59_ce0;
+reg    in1_loc_59_we0;
+reg   [5:0] in1_loc_60_address0;
+reg    in1_loc_60_ce0;
+reg    in1_loc_60_we0;
+reg   [5:0] in1_loc_61_address0;
+reg    in1_loc_61_ce0;
+reg    in1_loc_61_we0;
+reg   [5:0] in1_loc_62_address0;
+reg    in1_loc_62_ce0;
+reg    in1_loc_62_we0;
+reg   [5:0] in1_loc_63_address0;
+reg    in1_loc_63_ce0;
+reg    in1_loc_63_we0;
+reg   [5:0] in2_loc_0_address0;
+reg    in2_loc_0_ce0;
+reg    in2_loc_0_we0;
+reg   [5:0] in2_loc_1_address0;
+reg    in2_loc_1_ce0;
+reg    in2_loc_1_we0;
+reg   [5:0] in2_loc_2_address0;
+reg    in2_loc_2_ce0;
+reg    in2_loc_2_we0;
+reg   [5:0] in2_loc_3_address0;
+reg    in2_loc_3_ce0;
+reg    in2_loc_3_we0;
+reg   [5:0] in2_loc_4_address0;
+reg    in2_loc_4_ce0;
+reg    in2_loc_4_we0;
+reg   [5:0] in2_loc_5_address0;
+reg    in2_loc_5_ce0;
+reg    in2_loc_5_we0;
+reg   [5:0] in2_loc_6_address0;
+reg    in2_loc_6_ce0;
+reg    in2_loc_6_we0;
+reg   [5:0] in2_loc_7_address0;
+reg    in2_loc_7_ce0;
+reg    in2_loc_7_we0;
+reg   [5:0] in2_loc_8_address0;
+reg    in2_loc_8_ce0;
+reg    in2_loc_8_we0;
+reg   [5:0] in2_loc_9_address0;
+reg    in2_loc_9_ce0;
+reg    in2_loc_9_we0;
+reg   [5:0] in2_loc_10_address0;
+reg    in2_loc_10_ce0;
+reg    in2_loc_10_we0;
+reg   [5:0] in2_loc_11_address0;
+reg    in2_loc_11_ce0;
+reg    in2_loc_11_we0;
+reg   [5:0] in2_loc_12_address0;
+reg    in2_loc_12_ce0;
+reg    in2_loc_12_we0;
+reg   [5:0] in2_loc_13_address0;
+reg    in2_loc_13_ce0;
+reg    in2_loc_13_we0;
+reg   [5:0] in2_loc_14_address0;
+reg    in2_loc_14_ce0;
+reg    in2_loc_14_we0;
+reg   [5:0] in2_loc_15_address0;
+reg    in2_loc_15_ce0;
+reg    in2_loc_15_we0;
+reg   [5:0] in2_loc_16_address0;
+reg    in2_loc_16_ce0;
+reg    in2_loc_16_we0;
+reg   [5:0] in2_loc_17_address0;
+reg    in2_loc_17_ce0;
+reg    in2_loc_17_we0;
+reg   [5:0] in2_loc_18_address0;
+reg    in2_loc_18_ce0;
+reg    in2_loc_18_we0;
+reg   [5:0] in2_loc_19_address0;
+reg    in2_loc_19_ce0;
+reg    in2_loc_19_we0;
+reg   [5:0] in2_loc_20_address0;
+reg    in2_loc_20_ce0;
+reg    in2_loc_20_we0;
+reg   [5:0] in2_loc_21_address0;
+reg    in2_loc_21_ce0;
+reg    in2_loc_21_we0;
+reg   [5:0] in2_loc_22_address0;
+reg    in2_loc_22_ce0;
+reg    in2_loc_22_we0;
+reg   [5:0] in2_loc_23_address0;
+reg    in2_loc_23_ce0;
+reg    in2_loc_23_we0;
+reg   [5:0] in2_loc_24_address0;
+reg    in2_loc_24_ce0;
+reg    in2_loc_24_we0;
+reg   [5:0] in2_loc_25_address0;
+reg    in2_loc_25_ce0;
+reg    in2_loc_25_we0;
+reg   [5:0] in2_loc_26_address0;
+reg    in2_loc_26_ce0;
+reg    in2_loc_26_we0;
+reg   [5:0] in2_loc_27_address0;
+reg    in2_loc_27_ce0;
+reg    in2_loc_27_we0;
+reg   [5:0] in2_loc_28_address0;
+reg    in2_loc_28_ce0;
+reg    in2_loc_28_we0;
+reg   [5:0] in2_loc_29_address0;
+reg    in2_loc_29_ce0;
+reg    in2_loc_29_we0;
+reg   [5:0] in2_loc_30_address0;
+reg    in2_loc_30_ce0;
+reg    in2_loc_30_we0;
+reg   [5:0] in2_loc_31_address0;
+reg    in2_loc_31_ce0;
+reg    in2_loc_31_we0;
+reg   [5:0] in2_loc_32_address0;
+reg    in2_loc_32_ce0;
+reg    in2_loc_32_we0;
+reg   [5:0] in2_loc_33_address0;
+reg    in2_loc_33_ce0;
+reg    in2_loc_33_we0;
+reg   [5:0] in2_loc_34_address0;
+reg    in2_loc_34_ce0;
+reg    in2_loc_34_we0;
+reg   [5:0] in2_loc_35_address0;
+reg    in2_loc_35_ce0;
+reg    in2_loc_35_we0;
+reg   [5:0] in2_loc_36_address0;
+reg    in2_loc_36_ce0;
+reg    in2_loc_36_we0;
+reg   [5:0] in2_loc_37_address0;
+reg    in2_loc_37_ce0;
+reg    in2_loc_37_we0;
+reg   [5:0] in2_loc_38_address0;
+reg    in2_loc_38_ce0;
+reg    in2_loc_38_we0;
+reg   [5:0] in2_loc_39_address0;
+reg    in2_loc_39_ce0;
+reg    in2_loc_39_we0;
+reg   [5:0] in2_loc_40_address0;
+reg    in2_loc_40_ce0;
+reg    in2_loc_40_we0;
+reg   [5:0] in2_loc_41_address0;
+reg    in2_loc_41_ce0;
+reg    in2_loc_41_we0;
+reg   [5:0] in2_loc_42_address0;
+reg    in2_loc_42_ce0;
+reg    in2_loc_42_we0;
+reg   [5:0] in2_loc_43_address0;
+reg    in2_loc_43_ce0;
+reg    in2_loc_43_we0;
+reg   [5:0] in2_loc_44_address0;
+reg    in2_loc_44_ce0;
+reg    in2_loc_44_we0;
+reg   [5:0] in2_loc_45_address0;
+reg    in2_loc_45_ce0;
+reg    in2_loc_45_we0;
+reg   [5:0] in2_loc_46_address0;
+reg    in2_loc_46_ce0;
+reg    in2_loc_46_we0;
+reg   [5:0] in2_loc_47_address0;
+reg    in2_loc_47_ce0;
+reg    in2_loc_47_we0;
+reg   [5:0] in2_loc_48_address0;
+reg    in2_loc_48_ce0;
+reg    in2_loc_48_we0;
+reg   [5:0] in2_loc_49_address0;
+reg    in2_loc_49_ce0;
+reg    in2_loc_49_we0;
+reg   [5:0] in2_loc_50_address0;
+reg    in2_loc_50_ce0;
+reg    in2_loc_50_we0;
+reg   [5:0] in2_loc_51_address0;
+reg    in2_loc_51_ce0;
+reg    in2_loc_51_we0;
+reg   [5:0] in2_loc_52_address0;
+reg    in2_loc_52_ce0;
+reg    in2_loc_52_we0;
+reg   [5:0] in2_loc_53_address0;
+reg    in2_loc_53_ce0;
+reg    in2_loc_53_we0;
+reg   [5:0] in2_loc_54_address0;
+reg    in2_loc_54_ce0;
+reg    in2_loc_54_we0;
+reg   [5:0] in2_loc_55_address0;
+reg    in2_loc_55_ce0;
+reg    in2_loc_55_we0;
+reg   [5:0] in2_loc_56_address0;
+reg    in2_loc_56_ce0;
+reg    in2_loc_56_we0;
+reg   [5:0] in2_loc_57_address0;
+reg    in2_loc_57_ce0;
+reg    in2_loc_57_we0;
+reg   [5:0] in2_loc_58_address0;
+reg    in2_loc_58_ce0;
+reg    in2_loc_58_we0;
+reg   [5:0] in2_loc_59_address0;
+reg    in2_loc_59_ce0;
+reg    in2_loc_59_we0;
+reg   [5:0] in2_loc_60_address0;
+reg    in2_loc_60_ce0;
+reg    in2_loc_60_we0;
+reg   [5:0] in2_loc_61_address0;
+reg    in2_loc_61_ce0;
+reg    in2_loc_61_we0;
+reg   [5:0] in2_loc_62_address0;
+reg    in2_loc_62_ce0;
+reg    in2_loc_62_we0;
+reg   [5:0] in2_loc_63_address0;
+reg    in2_loc_63_ce0;
+reg    in2_loc_63_we0;
+reg   [11:0] out_loc_address0;
+reg    out_loc_ce0;
+reg    out_loc_ce1;
+reg    out_loc_we1;
+wire   [31:0] out_loc_d1;
+reg   [30:0] ap_phi_mux_i_0_phi_fu_3333_p4;
+wire    ap_block_pp2_stage0;
+wire   [63:0] zext_ln27_fu_3446_p1;
+wire   [63:0] zext_ln28_fu_3539_p1;
+wire   [63:0] zext_ln38_fu_3797_p1;
+wire   [63:0] zext_ln42_fu_4385_p1;
+wire   [63:0] empty_8_fu_3392_p1;
+wire   [63:0] empty_fu_3402_p1;
+wire   [63:0] empty_7_fu_3411_p1;
+wire    ap_block_pp3_stage0_01001;
+wire   [31:0] mul_ln31_fu_3609_p0;
+wire   [63:0] zext_ln31_fu_3606_p1;
+wire   [31:0] mul_ln31_fu_3609_p1;
+wire   [0:0] icmp_ln33_fu_3632_p2;
+wire   [30:0] i_fu_3626_p2;
+wire   [7:0] trunc_ln38_fu_3653_p1;
+wire  signed [31:0] select_ln31_fu_3637_p3;
+wire   [13:0] tmp_cast_fu_3657_p3;
+wire   [13:0] trunc_ln38_1_fu_3787_p1;
+wire   [13:0] add_ln38_64_fu_3791_p2;
+wire   [31:0] add_ln38_fu_4064_p2;
+wire   [31:0] add_ln38_1_fu_4069_p2;
+wire   [31:0] add_ln38_3_fu_4079_p2;
+wire   [31:0] add_ln38_4_fu_4083_p2;
+wire   [31:0] add_ln38_2_fu_4073_p2;
+wire   [31:0] add_ln38_5_fu_4087_p2;
+wire   [31:0] add_ln38_7_fu_4099_p2;
+wire   [31:0] add_ln38_8_fu_4103_p2;
+wire   [31:0] add_ln38_10_fu_4113_p2;
+wire   [31:0] add_ln38_11_fu_4117_p2;
+wire   [31:0] add_ln38_15_fu_4127_p2;
+wire   [31:0] add_ln38_16_fu_4131_p2;
+wire   [31:0] add_ln38_18_fu_4141_p2;
+wire   [31:0] add_ln38_19_fu_4145_p2;
+wire   [31:0] add_ln38_17_fu_4135_p2;
+wire   [31:0] add_ln38_20_fu_4149_p2;
+wire   [31:0] add_ln38_22_fu_4161_p2;
+wire   [31:0] add_ln38_23_fu_4165_p2;
+wire   [31:0] add_ln38_25_fu_4175_p2;
+wire   [31:0] add_ln38_26_fu_4179_p2;
+wire   [31:0] add_ln38_24_fu_4169_p2;
+wire   [31:0] add_ln38_27_fu_4183_p2;
+wire   [31:0] add_ln38_31_fu_4195_p2;
+wire   [31:0] add_ln38_32_fu_4199_p2;
+wire   [31:0] add_ln38_34_fu_4209_p2;
+wire   [31:0] add_ln38_35_fu_4213_p2;
+wire   [31:0] add_ln38_33_fu_4203_p2;
+wire   [31:0] add_ln38_36_fu_4217_p2;
+wire   [31:0] add_ln38_46_fu_4237_p2;
+wire   [31:0] add_ln38_47_fu_4241_p2;
+wire   [31:0] add_ln38_49_fu_4251_p2;
+wire   [31:0] add_ln38_50_fu_4255_p2;
+wire   [31:0] add_ln38_48_fu_4245_p2;
+wire   [31:0] add_ln38_51_fu_4259_p2;
+wire   [31:0] add_ln38_13_fu_4283_p2;
+wire   [31:0] add_ln38_14_fu_4287_p2;
+wire   [31:0] add_ln38_29_fu_4292_p2;
+wire   [31:0] add_ln38_39_fu_4302_p2;
+wire   [31:0] add_ln38_42_fu_4311_p2;
+wire   [31:0] add_ln38_40_fu_4306_p2;
+wire   [31:0] add_ln38_43_fu_4315_p2;
+wire   [31:0] add_ln38_44_fu_4320_p2;
+wire   [31:0] add_ln38_54_fu_4331_p2;
+wire   [31:0] add_ln38_58_fu_4340_p2;
+wire   [31:0] add_ln38_55_fu_4335_p2;
+wire   [31:0] add_ln38_59_fu_4344_p2;
+wire   [31:0] add_ln38_60_fu_4349_p2;
+wire   [31:0] add_ln38_45_fu_4326_p2;
+wire   [31:0] add_ln38_61_fu_4355_p2;
+wire   [31:0] add_ln38_30_fu_4296_p2;
+wire   [31:0] add_ln38_62_fu_4360_p2;
+reg   [25:0] ap_NS_fsm;
+reg    ap_idle_pp0;
+wire    ap_enable_pp0;
+reg    ap_idle_pp1;
+wire    ap_enable_pp1;
+reg    ap_idle_pp2;
+wire    ap_enable_pp2;
+reg    ap_idle_pp3;
+wire    ap_enable_pp3;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 26'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp1_iter1 = 1'b0;
+#0 ap_enable_reg_pp3_iter2 = 1'b0;
+#0 ap_enable_reg_pp0_iter0 = 1'b0;
+#0 ap_enable_reg_pp1_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter1 = 1'b0;
+#0 ap_enable_reg_pp2_iter2 = 1'b0;
+#0 ap_enable_reg_pp3_iter0 = 1'b0;
+#0 ap_enable_reg_pp3_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp1_iter2 = 1'b0;
+#0 ap_enable_reg_pp2_iter3 = 1'b0;
+#0 ap_enable_reg_pp2_iter4 = 1'b0;
+end
+
+mmult_params_s_axi #(
+    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PARAMS_ADDR_WIDTH ),
+    .C_S_AXI_DATA_WIDTH( C_S_AXI_PARAMS_DATA_WIDTH ))
+mmult_params_s_axi_U(
+    .AWVALID(s_axi_params_AWVALID),
+    .AWREADY(s_axi_params_AWREADY),
+    .AWADDR(s_axi_params_AWADDR),
+    .WVALID(s_axi_params_WVALID),
+    .WREADY(s_axi_params_WREADY),
+    .WDATA(s_axi_params_WDATA),
+    .WSTRB(s_axi_params_WSTRB),
+    .ARVALID(s_axi_params_ARVALID),
+    .ARREADY(s_axi_params_ARREADY),
+    .ARADDR(s_axi_params_ARADDR),
+    .RVALID(s_axi_params_RVALID),
+    .RREADY(s_axi_params_RREADY),
+    .RDATA(s_axi_params_RDATA),
+    .RRESP(s_axi_params_RRESP),
+    .BVALID(s_axi_params_BVALID),
+    .BREADY(s_axi_params_BREADY),
+    .BRESP(s_axi_params_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .in1(in1),
+    .in2(in2),
+    .out_r(out_r),
+    .dim(dim)
+);
+
+mmult_in1_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN1_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN1_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN1_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN1_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN1_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN1_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN1_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN1_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN1_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN1_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN1_MEM_CACHE_VALUE ))
+mmult_in1_mem_m_axi_U(
+    .AWVALID(m_axi_in1_mem_AWVALID),
+    .AWREADY(m_axi_in1_mem_AWREADY),
+    .AWADDR(m_axi_in1_mem_AWADDR),
+    .AWID(m_axi_in1_mem_AWID),
+    .AWLEN(m_axi_in1_mem_AWLEN),
+    .AWSIZE(m_axi_in1_mem_AWSIZE),
+    .AWBURST(m_axi_in1_mem_AWBURST),
+    .AWLOCK(m_axi_in1_mem_AWLOCK),
+    .AWCACHE(m_axi_in1_mem_AWCACHE),
+    .AWPROT(m_axi_in1_mem_AWPROT),
+    .AWQOS(m_axi_in1_mem_AWQOS),
+    .AWREGION(m_axi_in1_mem_AWREGION),
+    .AWUSER(m_axi_in1_mem_AWUSER),
+    .WVALID(m_axi_in1_mem_WVALID),
+    .WREADY(m_axi_in1_mem_WREADY),
+    .WDATA(m_axi_in1_mem_WDATA),
+    .WSTRB(m_axi_in1_mem_WSTRB),
+    .WLAST(m_axi_in1_mem_WLAST),
+    .WID(m_axi_in1_mem_WID),
+    .WUSER(m_axi_in1_mem_WUSER),
+    .ARVALID(m_axi_in1_mem_ARVALID),
+    .ARREADY(m_axi_in1_mem_ARREADY),
+    .ARADDR(m_axi_in1_mem_ARADDR),
+    .ARID(m_axi_in1_mem_ARID),
+    .ARLEN(m_axi_in1_mem_ARLEN),
+    .ARSIZE(m_axi_in1_mem_ARSIZE),
+    .ARBURST(m_axi_in1_mem_ARBURST),
+    .ARLOCK(m_axi_in1_mem_ARLOCK),
+    .ARCACHE(m_axi_in1_mem_ARCACHE),
+    .ARPROT(m_axi_in1_mem_ARPROT),
+    .ARQOS(m_axi_in1_mem_ARQOS),
+    .ARREGION(m_axi_in1_mem_ARREGION),
+    .ARUSER(m_axi_in1_mem_ARUSER),
+    .RVALID(m_axi_in1_mem_RVALID),
+    .RREADY(m_axi_in1_mem_RREADY),
+    .RDATA(m_axi_in1_mem_RDATA),
+    .RLAST(m_axi_in1_mem_RLAST),
+    .RID(m_axi_in1_mem_RID),
+    .RUSER(m_axi_in1_mem_RUSER),
+    .RRESP(m_axi_in1_mem_RRESP),
+    .BVALID(m_axi_in1_mem_BVALID),
+    .BREADY(m_axi_in1_mem_BREADY),
+    .BRESP(m_axi_in1_mem_BRESP),
+    .BID(m_axi_in1_mem_BID),
+    .BUSER(m_axi_in1_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in1_mem_ARVALID),
+    .I_ARREADY(in1_mem_ARREADY),
+    .I_ARADDR(in1_mem_ARADDR),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in1_mem_RVALID),
+    .I_RREADY(in1_mem_RREADY),
+    .I_RDATA(in1_mem_RDATA),
+    .I_RID(in1_mem_RID),
+    .I_RUSER(in1_mem_RUSER),
+    .I_RRESP(in1_mem_RRESP),
+    .I_RLAST(in1_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in1_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in1_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in1_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in1_mem_BRESP),
+    .I_BID(in1_mem_BID),
+    .I_BUSER(in1_mem_BUSER)
+);
+
+mmult_in2_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN2_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN2_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN2_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN2_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN2_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN2_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN2_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN2_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN2_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN2_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN2_MEM_CACHE_VALUE ))
+mmult_in2_mem_m_axi_U(
+    .AWVALID(m_axi_in2_mem_AWVALID),
+    .AWREADY(m_axi_in2_mem_AWREADY),
+    .AWADDR(m_axi_in2_mem_AWADDR),
+    .AWID(m_axi_in2_mem_AWID),
+    .AWLEN(m_axi_in2_mem_AWLEN),
+    .AWSIZE(m_axi_in2_mem_AWSIZE),
+    .AWBURST(m_axi_in2_mem_AWBURST),
+    .AWLOCK(m_axi_in2_mem_AWLOCK),
+    .AWCACHE(m_axi_in2_mem_AWCACHE),
+    .AWPROT(m_axi_in2_mem_AWPROT),
+    .AWQOS(m_axi_in2_mem_AWQOS),
+    .AWREGION(m_axi_in2_mem_AWREGION),
+    .AWUSER(m_axi_in2_mem_AWUSER),
+    .WVALID(m_axi_in2_mem_WVALID),
+    .WREADY(m_axi_in2_mem_WREADY),
+    .WDATA(m_axi_in2_mem_WDATA),
+    .WSTRB(m_axi_in2_mem_WSTRB),
+    .WLAST(m_axi_in2_mem_WLAST),
+    .WID(m_axi_in2_mem_WID),
+    .WUSER(m_axi_in2_mem_WUSER),
+    .ARVALID(m_axi_in2_mem_ARVALID),
+    .ARREADY(m_axi_in2_mem_ARREADY),
+    .ARADDR(m_axi_in2_mem_ARADDR),
+    .ARID(m_axi_in2_mem_ARID),
+    .ARLEN(m_axi_in2_mem_ARLEN),
+    .ARSIZE(m_axi_in2_mem_ARSIZE),
+    .ARBURST(m_axi_in2_mem_ARBURST),
+    .ARLOCK(m_axi_in2_mem_ARLOCK),
+    .ARCACHE(m_axi_in2_mem_ARCACHE),
+    .ARPROT(m_axi_in2_mem_ARPROT),
+    .ARQOS(m_axi_in2_mem_ARQOS),
+    .ARREGION(m_axi_in2_mem_ARREGION),
+    .ARUSER(m_axi_in2_mem_ARUSER),
+    .RVALID(m_axi_in2_mem_RVALID),
+    .RREADY(m_axi_in2_mem_RREADY),
+    .RDATA(m_axi_in2_mem_RDATA),
+    .RLAST(m_axi_in2_mem_RLAST),
+    .RID(m_axi_in2_mem_RID),
+    .RUSER(m_axi_in2_mem_RUSER),
+    .RRESP(m_axi_in2_mem_RRESP),
+    .BVALID(m_axi_in2_mem_BVALID),
+    .BREADY(m_axi_in2_mem_BREADY),
+    .BRESP(m_axi_in2_mem_BRESP),
+    .BID(m_axi_in2_mem_BID),
+    .BUSER(m_axi_in2_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in2_mem_ARVALID),
+    .I_ARREADY(in2_mem_ARREADY),
+    .I_ARADDR(in2_mem_addr_reg_4423),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in2_mem_RVALID),
+    .I_RREADY(in2_mem_RREADY),
+    .I_RDATA(in2_mem_RDATA),
+    .I_RID(in2_mem_RID),
+    .I_RUSER(in2_mem_RUSER),
+    .I_RRESP(in2_mem_RRESP),
+    .I_RLAST(in2_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in2_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in2_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in2_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in2_mem_BRESP),
+    .I_BID(in2_mem_BID),
+    .I_BUSER(in2_mem_BUSER)
+);
+
+mmult_out_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_OUT_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_OUT_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_OUT_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_OUT_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_OUT_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_OUT_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_OUT_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_OUT_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_OUT_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_OUT_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_OUT_MEM_CACHE_VALUE ))
+mmult_out_mem_m_axi_U(
+    .AWVALID(m_axi_out_mem_AWVALID),
+    .AWREADY(m_axi_out_mem_AWREADY),
+    .AWADDR(m_axi_out_mem_AWADDR),
+    .AWID(m_axi_out_mem_AWID),
+    .AWLEN(m_axi_out_mem_AWLEN),
+    .AWSIZE(m_axi_out_mem_AWSIZE),
+    .AWBURST(m_axi_out_mem_AWBURST),
+    .AWLOCK(m_axi_out_mem_AWLOCK),
+    .AWCACHE(m_axi_out_mem_AWCACHE),
+    .AWPROT(m_axi_out_mem_AWPROT),
+    .AWQOS(m_axi_out_mem_AWQOS),
+    .AWREGION(m_axi_out_mem_AWREGION),
+    .AWUSER(m_axi_out_mem_AWUSER),
+    .WVALID(m_axi_out_mem_WVALID),
+    .WREADY(m_axi_out_mem_WREADY),
+    .WDATA(m_axi_out_mem_WDATA),
+    .WSTRB(m_axi_out_mem_WSTRB),
+    .WLAST(m_axi_out_mem_WLAST),
+    .WID(m_axi_out_mem_WID),
+    .WUSER(m_axi_out_mem_WUSER),
+    .ARVALID(m_axi_out_mem_ARVALID),
+    .ARREADY(m_axi_out_mem_ARREADY),
+    .ARADDR(m_axi_out_mem_ARADDR),
+    .ARID(m_axi_out_mem_ARID),
+    .ARLEN(m_axi_out_mem_ARLEN),
+    .ARSIZE(m_axi_out_mem_ARSIZE),
+    .ARBURST(m_axi_out_mem_ARBURST),
+    .ARLOCK(m_axi_out_mem_ARLOCK),
+    .ARCACHE(m_axi_out_mem_ARCACHE),
+    .ARPROT(m_axi_out_mem_ARPROT),
+    .ARQOS(m_axi_out_mem_ARQOS),
+    .ARREGION(m_axi_out_mem_ARREGION),
+    .ARUSER(m_axi_out_mem_ARUSER),
+    .RVALID(m_axi_out_mem_RVALID),
+    .RREADY(m_axi_out_mem_RREADY),
+    .RDATA(m_axi_out_mem_RDATA),
+    .RLAST(m_axi_out_mem_RLAST),
+    .RID(m_axi_out_mem_RID),
+    .RUSER(m_axi_out_mem_RUSER),
+    .RRESP(m_axi_out_mem_RRESP),
+    .BVALID(m_axi_out_mem_BVALID),
+    .BREADY(m_axi_out_mem_BREADY),
+    .BRESP(m_axi_out_mem_BRESP),
+    .BID(m_axi_out_mem_BID),
+    .BUSER(m_axi_out_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(1'b0),
+    .I_ARREADY(out_mem_ARREADY),
+    .I_ARADDR(32'd0),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd0),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(out_mem_RVALID),
+    .I_RREADY(1'b0),
+    .I_RDATA(out_mem_RDATA),
+    .I_RID(out_mem_RID),
+    .I_RUSER(out_mem_RUSER),
+    .I_RRESP(out_mem_RRESP),
+    .I_RLAST(out_mem_RLAST),
+    .I_AWVALID(out_mem_AWVALID),
+    .I_AWREADY(out_mem_AWREADY),
+    .I_AWADDR(out_mem_addr_reg_4417),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd4096),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(out_mem_WVALID),
+    .I_WREADY(out_mem_WREADY),
+    .I_WDATA(out_loc_load_reg_6327),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd15),
+    .I_BVALID(out_mem_BVALID),
+    .I_BREADY(out_mem_BREADY),
+    .I_BRESP(out_mem_BRESP),
+    .I_BID(out_mem_BID),
+    .I_BUSER(out_mem_BUSER)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_0_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_0_address0),
+    .ce0(in1_loc_0_ce0),
+    .we0(in1_loc_0_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_0_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_1_address0),
+    .ce0(in1_loc_1_ce0),
+    .we0(in1_loc_1_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_1_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_2_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_2_address0),
+    .ce0(in1_loc_2_ce0),
+    .we0(in1_loc_2_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_2_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_3_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_3_address0),
+    .ce0(in1_loc_3_ce0),
+    .we0(in1_loc_3_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_3_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_4_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_4_address0),
+    .ce0(in1_loc_4_ce0),
+    .we0(in1_loc_4_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_4_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_5_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_5_address0),
+    .ce0(in1_loc_5_ce0),
+    .we0(in1_loc_5_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_5_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_6_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_6_address0),
+    .ce0(in1_loc_6_ce0),
+    .we0(in1_loc_6_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_6_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_7_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_7_address0),
+    .ce0(in1_loc_7_ce0),
+    .we0(in1_loc_7_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_7_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_8_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_8_address0),
+    .ce0(in1_loc_8_ce0),
+    .we0(in1_loc_8_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_8_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_9_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_9_address0),
+    .ce0(in1_loc_9_ce0),
+    .we0(in1_loc_9_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_9_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_10_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_10_address0),
+    .ce0(in1_loc_10_ce0),
+    .we0(in1_loc_10_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_10_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_11_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_11_address0),
+    .ce0(in1_loc_11_ce0),
+    .we0(in1_loc_11_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_11_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_12_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_12_address0),
+    .ce0(in1_loc_12_ce0),
+    .we0(in1_loc_12_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_12_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_13_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_13_address0),
+    .ce0(in1_loc_13_ce0),
+    .we0(in1_loc_13_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_13_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_14_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_14_address0),
+    .ce0(in1_loc_14_ce0),
+    .we0(in1_loc_14_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_14_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_15_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_15_address0),
+    .ce0(in1_loc_15_ce0),
+    .we0(in1_loc_15_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_15_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_16_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_16_address0),
+    .ce0(in1_loc_16_ce0),
+    .we0(in1_loc_16_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_16_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_17_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_17_address0),
+    .ce0(in1_loc_17_ce0),
+    .we0(in1_loc_17_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_17_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_18_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_18_address0),
+    .ce0(in1_loc_18_ce0),
+    .we0(in1_loc_18_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_18_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_19_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_19_address0),
+    .ce0(in1_loc_19_ce0),
+    .we0(in1_loc_19_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_19_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_20_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_20_address0),
+    .ce0(in1_loc_20_ce0),
+    .we0(in1_loc_20_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_20_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_21_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_21_address0),
+    .ce0(in1_loc_21_ce0),
+    .we0(in1_loc_21_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_21_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_22_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_22_address0),
+    .ce0(in1_loc_22_ce0),
+    .we0(in1_loc_22_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_22_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_23_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_23_address0),
+    .ce0(in1_loc_23_ce0),
+    .we0(in1_loc_23_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_23_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_24_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_24_address0),
+    .ce0(in1_loc_24_ce0),
+    .we0(in1_loc_24_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_24_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_25_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_25_address0),
+    .ce0(in1_loc_25_ce0),
+    .we0(in1_loc_25_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_25_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_26_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_26_address0),
+    .ce0(in1_loc_26_ce0),
+    .we0(in1_loc_26_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_26_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_27_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_27_address0),
+    .ce0(in1_loc_27_ce0),
+    .we0(in1_loc_27_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_27_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_28_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_28_address0),
+    .ce0(in1_loc_28_ce0),
+    .we0(in1_loc_28_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_28_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_29_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_29_address0),
+    .ce0(in1_loc_29_ce0),
+    .we0(in1_loc_29_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_29_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_30_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_30_address0),
+    .ce0(in1_loc_30_ce0),
+    .we0(in1_loc_30_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_30_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_31_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_31_address0),
+    .ce0(in1_loc_31_ce0),
+    .we0(in1_loc_31_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_31_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_32_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_32_address0),
+    .ce0(in1_loc_32_ce0),
+    .we0(in1_loc_32_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_32_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_33_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_33_address0),
+    .ce0(in1_loc_33_ce0),
+    .we0(in1_loc_33_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_33_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_34_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_34_address0),
+    .ce0(in1_loc_34_ce0),
+    .we0(in1_loc_34_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_34_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_35_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_35_address0),
+    .ce0(in1_loc_35_ce0),
+    .we0(in1_loc_35_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_35_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_36_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_36_address0),
+    .ce0(in1_loc_36_ce0),
+    .we0(in1_loc_36_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_36_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_37_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_37_address0),
+    .ce0(in1_loc_37_ce0),
+    .we0(in1_loc_37_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_37_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_38_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_38_address0),
+    .ce0(in1_loc_38_ce0),
+    .we0(in1_loc_38_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_38_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_39_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_39_address0),
+    .ce0(in1_loc_39_ce0),
+    .we0(in1_loc_39_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_39_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_40_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_40_address0),
+    .ce0(in1_loc_40_ce0),
+    .we0(in1_loc_40_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_40_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_41_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_41_address0),
+    .ce0(in1_loc_41_ce0),
+    .we0(in1_loc_41_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_41_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_42_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_42_address0),
+    .ce0(in1_loc_42_ce0),
+    .we0(in1_loc_42_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_42_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_43_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_43_address0),
+    .ce0(in1_loc_43_ce0),
+    .we0(in1_loc_43_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_43_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_44_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_44_address0),
+    .ce0(in1_loc_44_ce0),
+    .we0(in1_loc_44_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_44_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_45_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_45_address0),
+    .ce0(in1_loc_45_ce0),
+    .we0(in1_loc_45_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_45_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_46_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_46_address0),
+    .ce0(in1_loc_46_ce0),
+    .we0(in1_loc_46_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_46_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_47_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_47_address0),
+    .ce0(in1_loc_47_ce0),
+    .we0(in1_loc_47_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_47_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_48_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_48_address0),
+    .ce0(in1_loc_48_ce0),
+    .we0(in1_loc_48_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_48_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_49_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_49_address0),
+    .ce0(in1_loc_49_ce0),
+    .we0(in1_loc_49_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_49_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_50_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_50_address0),
+    .ce0(in1_loc_50_ce0),
+    .we0(in1_loc_50_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_50_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_51_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_51_address0),
+    .ce0(in1_loc_51_ce0),
+    .we0(in1_loc_51_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_51_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_52_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_52_address0),
+    .ce0(in1_loc_52_ce0),
+    .we0(in1_loc_52_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_52_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_53_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_53_address0),
+    .ce0(in1_loc_53_ce0),
+    .we0(in1_loc_53_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_53_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_54_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_54_address0),
+    .ce0(in1_loc_54_ce0),
+    .we0(in1_loc_54_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_54_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_55_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_55_address0),
+    .ce0(in1_loc_55_ce0),
+    .we0(in1_loc_55_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_55_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_56_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_56_address0),
+    .ce0(in1_loc_56_ce0),
+    .we0(in1_loc_56_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_56_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_57_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_57_address0),
+    .ce0(in1_loc_57_ce0),
+    .we0(in1_loc_57_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_57_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_58_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_58_address0),
+    .ce0(in1_loc_58_ce0),
+    .we0(in1_loc_58_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_58_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_59_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_59_address0),
+    .ce0(in1_loc_59_ce0),
+    .we0(in1_loc_59_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_59_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_60_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_60_address0),
+    .ce0(in1_loc_60_ce0),
+    .we0(in1_loc_60_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_60_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_61_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_61_address0),
+    .ce0(in1_loc_61_ce0),
+    .we0(in1_loc_61_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_61_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_62_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_62_address0),
+    .ce0(in1_loc_62_ce0),
+    .we0(in1_loc_62_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_62_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_63_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_63_address0),
+    .ce0(in1_loc_63_ce0),
+    .we0(in1_loc_63_we0),
+    .d0(in1_mem_addr_read_reg_4447),
+    .q0(in1_loc_63_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_0_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_0_address0),
+    .ce0(in2_loc_0_ce0),
+    .we0(in2_loc_0_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_0_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_1_address0),
+    .ce0(in2_loc_1_ce0),
+    .we0(in2_loc_1_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_1_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_2_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_2_address0),
+    .ce0(in2_loc_2_ce0),
+    .we0(in2_loc_2_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_2_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_3_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_3_address0),
+    .ce0(in2_loc_3_ce0),
+    .we0(in2_loc_3_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_3_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_4_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_4_address0),
+    .ce0(in2_loc_4_ce0),
+    .we0(in2_loc_4_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_4_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_5_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_5_address0),
+    .ce0(in2_loc_5_ce0),
+    .we0(in2_loc_5_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_5_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_6_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_6_address0),
+    .ce0(in2_loc_6_ce0),
+    .we0(in2_loc_6_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_6_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_7_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_7_address0),
+    .ce0(in2_loc_7_ce0),
+    .we0(in2_loc_7_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_7_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_8_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_8_address0),
+    .ce0(in2_loc_8_ce0),
+    .we0(in2_loc_8_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_8_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_9_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_9_address0),
+    .ce0(in2_loc_9_ce0),
+    .we0(in2_loc_9_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_9_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_10_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_10_address0),
+    .ce0(in2_loc_10_ce0),
+    .we0(in2_loc_10_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_10_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_11_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_11_address0),
+    .ce0(in2_loc_11_ce0),
+    .we0(in2_loc_11_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_11_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_12_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_12_address0),
+    .ce0(in2_loc_12_ce0),
+    .we0(in2_loc_12_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_12_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_13_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_13_address0),
+    .ce0(in2_loc_13_ce0),
+    .we0(in2_loc_13_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_13_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_14_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_14_address0),
+    .ce0(in2_loc_14_ce0),
+    .we0(in2_loc_14_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_14_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_15_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_15_address0),
+    .ce0(in2_loc_15_ce0),
+    .we0(in2_loc_15_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_15_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_16_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_16_address0),
+    .ce0(in2_loc_16_ce0),
+    .we0(in2_loc_16_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_16_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_17_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_17_address0),
+    .ce0(in2_loc_17_ce0),
+    .we0(in2_loc_17_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_17_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_18_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_18_address0),
+    .ce0(in2_loc_18_ce0),
+    .we0(in2_loc_18_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_18_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_19_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_19_address0),
+    .ce0(in2_loc_19_ce0),
+    .we0(in2_loc_19_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_19_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_20_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_20_address0),
+    .ce0(in2_loc_20_ce0),
+    .we0(in2_loc_20_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_20_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_21_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_21_address0),
+    .ce0(in2_loc_21_ce0),
+    .we0(in2_loc_21_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_21_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_22_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_22_address0),
+    .ce0(in2_loc_22_ce0),
+    .we0(in2_loc_22_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_22_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_23_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_23_address0),
+    .ce0(in2_loc_23_ce0),
+    .we0(in2_loc_23_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_23_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_24_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_24_address0),
+    .ce0(in2_loc_24_ce0),
+    .we0(in2_loc_24_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_24_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_25_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_25_address0),
+    .ce0(in2_loc_25_ce0),
+    .we0(in2_loc_25_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_25_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_26_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_26_address0),
+    .ce0(in2_loc_26_ce0),
+    .we0(in2_loc_26_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_26_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_27_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_27_address0),
+    .ce0(in2_loc_27_ce0),
+    .we0(in2_loc_27_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_27_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_28_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_28_address0),
+    .ce0(in2_loc_28_ce0),
+    .we0(in2_loc_28_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_28_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_29_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_29_address0),
+    .ce0(in2_loc_29_ce0),
+    .we0(in2_loc_29_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_29_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_30_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_30_address0),
+    .ce0(in2_loc_30_ce0),
+    .we0(in2_loc_30_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_30_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_31_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_31_address0),
+    .ce0(in2_loc_31_ce0),
+    .we0(in2_loc_31_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_31_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_32_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_32_address0),
+    .ce0(in2_loc_32_ce0),
+    .we0(in2_loc_32_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_32_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_33_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_33_address0),
+    .ce0(in2_loc_33_ce0),
+    .we0(in2_loc_33_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_33_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_34_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_34_address0),
+    .ce0(in2_loc_34_ce0),
+    .we0(in2_loc_34_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_34_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_35_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_35_address0),
+    .ce0(in2_loc_35_ce0),
+    .we0(in2_loc_35_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_35_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_36_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_36_address0),
+    .ce0(in2_loc_36_ce0),
+    .we0(in2_loc_36_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_36_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_37_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_37_address0),
+    .ce0(in2_loc_37_ce0),
+    .we0(in2_loc_37_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_37_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_38_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_38_address0),
+    .ce0(in2_loc_38_ce0),
+    .we0(in2_loc_38_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_38_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_39_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_39_address0),
+    .ce0(in2_loc_39_ce0),
+    .we0(in2_loc_39_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_39_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_40_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_40_address0),
+    .ce0(in2_loc_40_ce0),
+    .we0(in2_loc_40_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_40_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_41_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_41_address0),
+    .ce0(in2_loc_41_ce0),
+    .we0(in2_loc_41_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_41_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_42_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_42_address0),
+    .ce0(in2_loc_42_ce0),
+    .we0(in2_loc_42_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_42_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_43_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_43_address0),
+    .ce0(in2_loc_43_ce0),
+    .we0(in2_loc_43_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_43_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_44_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_44_address0),
+    .ce0(in2_loc_44_ce0),
+    .we0(in2_loc_44_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_44_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_45_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_45_address0),
+    .ce0(in2_loc_45_ce0),
+    .we0(in2_loc_45_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_45_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_46_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_46_address0),
+    .ce0(in2_loc_46_ce0),
+    .we0(in2_loc_46_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_46_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_47_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_47_address0),
+    .ce0(in2_loc_47_ce0),
+    .we0(in2_loc_47_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_47_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_48_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_48_address0),
+    .ce0(in2_loc_48_ce0),
+    .we0(in2_loc_48_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_48_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_49_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_49_address0),
+    .ce0(in2_loc_49_ce0),
+    .we0(in2_loc_49_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_49_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_50_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_50_address0),
+    .ce0(in2_loc_50_ce0),
+    .we0(in2_loc_50_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_50_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_51_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_51_address0),
+    .ce0(in2_loc_51_ce0),
+    .we0(in2_loc_51_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_51_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_52_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_52_address0),
+    .ce0(in2_loc_52_ce0),
+    .we0(in2_loc_52_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_52_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_53_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_53_address0),
+    .ce0(in2_loc_53_ce0),
+    .we0(in2_loc_53_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_53_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_54_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_54_address0),
+    .ce0(in2_loc_54_ce0),
+    .we0(in2_loc_54_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_54_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_55_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_55_address0),
+    .ce0(in2_loc_55_ce0),
+    .we0(in2_loc_55_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_55_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_56_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_56_address0),
+    .ce0(in2_loc_56_ce0),
+    .we0(in2_loc_56_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_56_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_57_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_57_address0),
+    .ce0(in2_loc_57_ce0),
+    .we0(in2_loc_57_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_57_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_58_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_58_address0),
+    .ce0(in2_loc_58_ce0),
+    .we0(in2_loc_58_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_58_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_59_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_59_address0),
+    .ce0(in2_loc_59_ce0),
+    .we0(in2_loc_59_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_59_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_60_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_60_address0),
+    .ce0(in2_loc_60_ce0),
+    .we0(in2_loc_60_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_60_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_61_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_61_address0),
+    .ce0(in2_loc_61_ce0),
+    .we0(in2_loc_61_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_61_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_62_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_62_address0),
+    .ce0(in2_loc_62_ce0),
+    .we0(in2_loc_62_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_62_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_63_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_63_address0),
+    .ce0(in2_loc_63_ce0),
+    .we0(in2_loc_63_we0),
+    .d0(in2_mem_addr_read_reg_4533),
+    .q0(in2_loc_63_q0)
+);
+
+mmult_out_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+out_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(out_loc_address0),
+    .ce0(out_loc_ce0),
+    .q0(out_loc_q0),
+    .address1(out_loc_addr_reg_4927_pp2_iter3_reg),
+    .ce1(out_loc_ce1),
+    .we1(out_loc_we1),
+    .d1(out_loc_d1)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state9) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_enable_reg_pp0_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp0_exit_iter0_state9)) begin
+                ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state9);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b0 == ap_block_pp1_stage0_subdone))) begin
+            ap_enable_reg_pp1_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp1_exit_iter0_state19)) begin
+                ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_condition_pp2_exit_iter0_state23) & (1'b0 == ap_block_pp2_stage0_subdone))) begin
+            ap_enable_reg_pp2_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state22)) begin
+            ap_enable_reg_pp2_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp2_exit_iter0_state23)) begin
+                ap_enable_reg_pp2_iter1 <= (1'b1 ^ ap_condition_pp2_exit_iter0_state23);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter3 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter3 <= ap_enable_reg_pp2_iter2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter4 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter4 <= ap_enable_reg_pp2_iter3;
+        end else if ((1'b1 == ap_CS_fsm_state22)) begin
+            ap_enable_reg_pp2_iter4 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_condition_pp3_exit_iter0_state29) & (1'b1 == ap_CS_fsm_pp3_stage0) & (1'b0 == ap_block_pp3_stage0_subdone))) begin
+            ap_enable_reg_pp3_iter0 <= 1'b0;
+        end else if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state28))) begin
+            ap_enable_reg_pp3_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp3_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp3_exit_iter0_state29)) begin
+                ap_enable_reg_pp3_iter1 <= (1'b1 ^ ap_condition_pp3_exit_iter0_state29);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp3_iter1 <= ap_enable_reg_pp3_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp3_stage0_subdone)) begin
+            ap_enable_reg_pp3_iter2 <= ap_enable_reg_pp3_iter1;
+        end else if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state28))) begin
+            ap_enable_reg_pp3_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4606 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        i_0_reg_3329 <= select_ln31_1_reg_4615;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        i_0_reg_3329 <= 31'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3615_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        indvar_flatten_reg_3318 <= add_ln31_fu_3620_p2;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        indvar_flatten_reg_3318 <= 64'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3615_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        j_0_reg_3340 <= j_fu_3802_p2;
+    end else if ((1'b1 == ap_CS_fsm_state22)) begin
+        j_0_reg_3340 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_fu_3420_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        phi_ln27_reg_3296 <= add_ln27_fu_3426_p2;
+    end else if ((1'b1 == ap_CS_fsm_state8)) begin
+        phi_ln27_reg_3296 <= 13'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        phi_ln28_reg_3307 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_fu_3513_p2 == 1'd0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        phi_ln28_reg_3307 <= add_ln28_fu_3519_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state28))) begin
+        phi_ln42_reg_3351 <= 13'd0;
+    end else if (((icmp_ln42_fu_4373_p2 == 1'd0) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0) & (1'b0 == ap_block_pp3_stage0_11001))) begin
+        phi_ln42_reg_3351 <= add_ln42_fu_4379_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4606_pp2_iter2_reg == 1'd0))) begin
+        add_ln38_12_reg_6263 <= add_ln38_12_fu_4121_p2;
+        add_ln38_21_reg_6268 <= add_ln38_21_fu_4155_p2;
+        add_ln38_28_reg_6273 <= add_ln38_28_fu_4189_p2;
+        add_ln38_37_reg_6278 <= add_ln38_37_fu_4223_p2;
+        add_ln38_38_reg_6283 <= add_ln38_38_fu_4229_p2;
+        add_ln38_41_reg_6288 <= add_ln38_41_fu_4233_p2;
+        add_ln38_52_reg_6293 <= add_ln38_52_fu_4265_p2;
+        add_ln38_53_reg_6298 <= add_ln38_53_fu_4271_p2;
+        add_ln38_56_reg_6303 <= add_ln38_56_fu_4275_p2;
+        add_ln38_57_reg_6308 <= add_ln38_57_fu_4279_p2;
+        add_ln38_6_reg_6253 <= add_ln38_6_fu_4093_p2;
+        add_ln38_9_reg_6258 <= add_ln38_9_fu_4107_p2;
+        mul_ln38_41_reg_6218 <= mul_ln38_41_fu_4036_p2;
+        mul_ln38_42_reg_6223 <= mul_ln38_42_fu_4040_p2;
+        mul_ln38_45_reg_6228 <= mul_ln38_45_fu_4044_p2;
+        mul_ln38_46_reg_6233 <= mul_ln38_46_fu_4048_p2;
+        mul_ln38_57_reg_6238 <= mul_ln38_57_fu_4052_p2;
+        mul_ln38_58_reg_6243 <= mul_ln38_58_fu_4056_p2;
+        mul_ln38_61_reg_6248 <= mul_ln38_61_fu_4060_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        dim_read_reg_4390 <= dim;
+        in3_reg_4406 <= {{in1[31:2]}};
+        in_reg_4401 <= {{in2[31:2]}};
+        out5_reg_4396 <= {{out_r[31:2]}};
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        icmp_ln31_reg_4606 <= icmp_ln31_fu_3615_p2;
+        icmp_ln31_reg_4606_pp2_iter1_reg <= icmp_ln31_reg_4606;
+        out_loc_addr_reg_4927_pp2_iter1_reg <= out_loc_addr_reg_4927;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b0 == ap_block_pp2_stage0_11001)) begin
+        icmp_ln31_reg_4606_pp2_iter2_reg <= icmp_ln31_reg_4606_pp2_iter1_reg;
+        icmp_ln31_reg_4606_pp2_iter3_reg <= icmp_ln31_reg_4606_pp2_iter2_reg;
+        out_loc_addr_reg_4927_pp2_iter2_reg <= out_loc_addr_reg_4927_pp2_iter1_reg;
+        out_loc_addr_reg_4927_pp2_iter3_reg <= out_loc_addr_reg_4927_pp2_iter2_reg;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b1 == ap_CS_fsm_pp3_stage0) & (1'b0 == ap_block_pp3_stage0_11001))) begin
+        icmp_ln42_reg_6313 <= icmp_ln42_fu_4373_p2;
+        icmp_ln42_reg_6313_pp3_iter1_reg <= icmp_ln42_reg_6313;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4606 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_0_load_reg_5223 <= in1_loc_0_q0;
+        in1_loc_10_load_reg_5273 <= in1_loc_10_q0;
+        in1_loc_11_load_reg_5278 <= in1_loc_11_q0;
+        in1_loc_12_load_reg_5283 <= in1_loc_12_q0;
+        in1_loc_13_load_reg_5288 <= in1_loc_13_q0;
+        in1_loc_14_load_reg_5293 <= in1_loc_14_q0;
+        in1_loc_15_load_reg_5298 <= in1_loc_15_q0;
+        in1_loc_16_load_reg_5303 <= in1_loc_16_q0;
+        in1_loc_17_load_reg_5308 <= in1_loc_17_q0;
+        in1_loc_18_load_reg_5313 <= in1_loc_18_q0;
+        in1_loc_19_load_reg_5318 <= in1_loc_19_q0;
+        in1_loc_1_load_reg_5228 <= in1_loc_1_q0;
+        in1_loc_20_load_reg_5323 <= in1_loc_20_q0;
+        in1_loc_21_load_reg_5328 <= in1_loc_21_q0;
+        in1_loc_22_load_reg_5333 <= in1_loc_22_q0;
+        in1_loc_23_load_reg_5338 <= in1_loc_23_q0;
+        in1_loc_24_load_reg_5343 <= in1_loc_24_q0;
+        in1_loc_25_load_reg_5348 <= in1_loc_25_q0;
+        in1_loc_26_load_reg_5353 <= in1_loc_26_q0;
+        in1_loc_27_load_reg_5358 <= in1_loc_27_q0;
+        in1_loc_28_load_reg_5363 <= in1_loc_28_q0;
+        in1_loc_29_load_reg_5368 <= in1_loc_29_q0;
+        in1_loc_2_load_reg_5233 <= in1_loc_2_q0;
+        in1_loc_30_load_reg_5373 <= in1_loc_30_q0;
+        in1_loc_31_load_reg_5378 <= in1_loc_31_q0;
+        in1_loc_32_load_reg_5383 <= in1_loc_32_q0;
+        in1_loc_33_load_reg_5388 <= in1_loc_33_q0;
+        in1_loc_34_load_reg_5393 <= in1_loc_34_q0;
+        in1_loc_35_load_reg_5398 <= in1_loc_35_q0;
+        in1_loc_36_load_reg_5403 <= in1_loc_36_q0;
+        in1_loc_37_load_reg_5408 <= in1_loc_37_q0;
+        in1_loc_38_load_reg_5413 <= in1_loc_38_q0;
+        in1_loc_39_load_reg_5418 <= in1_loc_39_q0;
+        in1_loc_3_load_reg_5238 <= in1_loc_3_q0;
+        in1_loc_40_load_reg_5423 <= in1_loc_40_q0;
+        in1_loc_43_load_reg_5438 <= in1_loc_43_q0;
+        in1_loc_44_load_reg_5443 <= in1_loc_44_q0;
+        in1_loc_47_load_reg_5458 <= in1_loc_47_q0;
+        in1_loc_48_load_reg_5463 <= in1_loc_48_q0;
+        in1_loc_49_load_reg_5468 <= in1_loc_49_q0;
+        in1_loc_4_load_reg_5243 <= in1_loc_4_q0;
+        in1_loc_50_load_reg_5473 <= in1_loc_50_q0;
+        in1_loc_51_load_reg_5478 <= in1_loc_51_q0;
+        in1_loc_52_load_reg_5483 <= in1_loc_52_q0;
+        in1_loc_53_load_reg_5488 <= in1_loc_53_q0;
+        in1_loc_54_load_reg_5493 <= in1_loc_54_q0;
+        in1_loc_55_load_reg_5498 <= in1_loc_55_q0;
+        in1_loc_56_load_reg_5503 <= in1_loc_56_q0;
+        in1_loc_59_load_reg_5518 <= in1_loc_59_q0;
+        in1_loc_5_load_reg_5248 <= in1_loc_5_q0;
+        in1_loc_60_load_reg_5523 <= in1_loc_60_q0;
+        in1_loc_62_load_reg_5533 <= in1_loc_62_q0;
+        in1_loc_63_load_reg_5538 <= in1_loc_63_q0;
+        in1_loc_6_load_reg_5253 <= in1_loc_6_q0;
+        in1_loc_7_load_reg_5258 <= in1_loc_7_q0;
+        in1_loc_8_load_reg_5263 <= in1_loc_8_q0;
+        in1_loc_9_load_reg_5268 <= in1_loc_9_q0;
+        in2_loc_0_load_reg_5543 <= in2_loc_0_q0;
+        in2_loc_10_load_reg_5593 <= in2_loc_10_q0;
+        in2_loc_11_load_reg_5598 <= in2_loc_11_q0;
+        in2_loc_12_load_reg_5603 <= in2_loc_12_q0;
+        in2_loc_13_load_reg_5608 <= in2_loc_13_q0;
+        in2_loc_14_load_reg_5613 <= in2_loc_14_q0;
+        in2_loc_15_load_reg_5618 <= in2_loc_15_q0;
+        in2_loc_16_load_reg_5623 <= in2_loc_16_q0;
+        in2_loc_17_load_reg_5628 <= in2_loc_17_q0;
+        in2_loc_18_load_reg_5633 <= in2_loc_18_q0;
+        in2_loc_19_load_reg_5638 <= in2_loc_19_q0;
+        in2_loc_1_load_reg_5548 <= in2_loc_1_q0;
+        in2_loc_20_load_reg_5643 <= in2_loc_20_q0;
+        in2_loc_21_load_reg_5648 <= in2_loc_21_q0;
+        in2_loc_22_load_reg_5653 <= in2_loc_22_q0;
+        in2_loc_23_load_reg_5658 <= in2_loc_23_q0;
+        in2_loc_24_load_reg_5663 <= in2_loc_24_q0;
+        in2_loc_25_load_reg_5668 <= in2_loc_25_q0;
+        in2_loc_26_load_reg_5673 <= in2_loc_26_q0;
+        in2_loc_27_load_reg_5678 <= in2_loc_27_q0;
+        in2_loc_28_load_reg_5683 <= in2_loc_28_q0;
+        in2_loc_29_load_reg_5688 <= in2_loc_29_q0;
+        in2_loc_2_load_reg_5553 <= in2_loc_2_q0;
+        in2_loc_30_load_reg_5693 <= in2_loc_30_q0;
+        in2_loc_31_load_reg_5698 <= in2_loc_31_q0;
+        in2_loc_32_load_reg_5703 <= in2_loc_32_q0;
+        in2_loc_33_load_reg_5708 <= in2_loc_33_q0;
+        in2_loc_34_load_reg_5713 <= in2_loc_34_q0;
+        in2_loc_35_load_reg_5718 <= in2_loc_35_q0;
+        in2_loc_36_load_reg_5723 <= in2_loc_36_q0;
+        in2_loc_37_load_reg_5728 <= in2_loc_37_q0;
+        in2_loc_38_load_reg_5733 <= in2_loc_38_q0;
+        in2_loc_39_load_reg_5738 <= in2_loc_39_q0;
+        in2_loc_3_load_reg_5558 <= in2_loc_3_q0;
+        in2_loc_40_load_reg_5743 <= in2_loc_40_q0;
+        in2_loc_43_load_reg_5758 <= in2_loc_43_q0;
+        in2_loc_44_load_reg_5763 <= in2_loc_44_q0;
+        in2_loc_47_load_reg_5778 <= in2_loc_47_q0;
+        in2_loc_48_load_reg_5783 <= in2_loc_48_q0;
+        in2_loc_49_load_reg_5788 <= in2_loc_49_q0;
+        in2_loc_4_load_reg_5563 <= in2_loc_4_q0;
+        in2_loc_50_load_reg_5793 <= in2_loc_50_q0;
+        in2_loc_51_load_reg_5798 <= in2_loc_51_q0;
+        in2_loc_52_load_reg_5803 <= in2_loc_52_q0;
+        in2_loc_53_load_reg_5808 <= in2_loc_53_q0;
+        in2_loc_54_load_reg_5813 <= in2_loc_54_q0;
+        in2_loc_55_load_reg_5818 <= in2_loc_55_q0;
+        in2_loc_56_load_reg_5823 <= in2_loc_56_q0;
+        in2_loc_59_load_reg_5838 <= in2_loc_59_q0;
+        in2_loc_5_load_reg_5568 <= in2_loc_5_q0;
+        in2_loc_60_load_reg_5843 <= in2_loc_60_q0;
+        in2_loc_62_load_reg_5853 <= in2_loc_62_q0;
+        in2_loc_63_load_reg_5858 <= in2_loc_63_q0;
+        in2_loc_6_load_reg_5573 <= in2_loc_6_q0;
+        in2_loc_7_load_reg_5578 <= in2_loc_7_q0;
+        in2_loc_8_load_reg_5583 <= in2_loc_8_q0;
+        in2_loc_9_load_reg_5588 <= in2_loc_9_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4606_pp2_iter1_reg == 1'd0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_41_load_reg_5863 <= in1_loc_41_q0;
+        in1_loc_42_load_reg_5868 <= in1_loc_42_q0;
+        in1_loc_45_load_reg_5873 <= in1_loc_45_q0;
+        in1_loc_46_load_reg_5878 <= in1_loc_46_q0;
+        in1_loc_57_load_reg_5883 <= in1_loc_57_q0;
+        in1_loc_58_load_reg_5888 <= in1_loc_58_q0;
+        in1_loc_61_load_reg_5893 <= in1_loc_61_q0;
+        in2_loc_41_load_reg_6103 <= in2_loc_41_q0;
+        in2_loc_42_load_reg_6108 <= in2_loc_42_q0;
+        in2_loc_45_load_reg_6123 <= in2_loc_45_q0;
+        in2_loc_46_load_reg_6128 <= in2_loc_46_q0;
+        in2_loc_57_load_reg_6183 <= in2_loc_57_q0;
+        in2_loc_58_load_reg_6188 <= in2_loc_58_q0;
+        in2_loc_61_load_reg_6203 <= in2_loc_61_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_addr_read_reg_4447 <= in1_mem_RDATA;
+        lshr_ln_reg_4438_pp0_iter1_reg <= lshr_ln_reg_4438;
+        trunc_ln27_reg_4443_pp0_iter1_reg <= trunc_ln27_reg_4443;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_addr_read_reg_4533 <= in2_mem_RDATA;
+        trunc_ln1_reg_4529_pp1_iter1_reg <= trunc_ln1_reg_4529;
+        trunc_ln28_reg_4524_pp1_iter1_reg <= trunc_ln28_reg_4524;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        in2_mem_addr_reg_4423[29 : 0] <= empty_7_fu_3411_p1[29 : 0];
+        out_mem_addr_reg_4417[29 : 0] <= empty_fu_3402_p1[29 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_fu_3420_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        lshr_ln_reg_4438 <= {{phi_ln27_reg_3296[12:6]}};
+        trunc_ln27_reg_4443 <= trunc_ln27_fu_3442_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state22)) begin
+        mul_ln31_reg_4601 <= mul_ln31_fu_3609_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4606_pp2_iter1_reg == 1'd0))) begin
+        mul_ln38_10_reg_5948 <= mul_ln38_10_fu_3848_p2;
+        mul_ln38_11_reg_5953 <= mul_ln38_11_fu_3852_p2;
+        mul_ln38_12_reg_5958 <= mul_ln38_12_fu_3856_p2;
+        mul_ln38_13_reg_5963 <= mul_ln38_13_fu_3860_p2;
+        mul_ln38_14_reg_5968 <= mul_ln38_14_fu_3864_p2;
+        mul_ln38_15_reg_5973 <= mul_ln38_15_fu_3868_p2;
+        mul_ln38_16_reg_5978 <= mul_ln38_16_fu_3872_p2;
+        mul_ln38_17_reg_5983 <= mul_ln38_17_fu_3876_p2;
+        mul_ln38_18_reg_5988 <= mul_ln38_18_fu_3880_p2;
+        mul_ln38_19_reg_5993 <= mul_ln38_19_fu_3884_p2;
+        mul_ln38_1_reg_5903 <= mul_ln38_1_fu_3812_p2;
+        mul_ln38_20_reg_5998 <= mul_ln38_20_fu_3888_p2;
+        mul_ln38_21_reg_6003 <= mul_ln38_21_fu_3892_p2;
+        mul_ln38_22_reg_6008 <= mul_ln38_22_fu_3896_p2;
+        mul_ln38_23_reg_6013 <= mul_ln38_23_fu_3900_p2;
+        mul_ln38_24_reg_6018 <= mul_ln38_24_fu_3904_p2;
+        mul_ln38_25_reg_6023 <= mul_ln38_25_fu_3908_p2;
+        mul_ln38_26_reg_6028 <= mul_ln38_26_fu_3912_p2;
+        mul_ln38_27_reg_6033 <= mul_ln38_27_fu_3916_p2;
+        mul_ln38_28_reg_6038 <= mul_ln38_28_fu_3920_p2;
+        mul_ln38_29_reg_6043 <= mul_ln38_29_fu_3924_p2;
+        mul_ln38_2_reg_5908 <= mul_ln38_2_fu_3816_p2;
+        mul_ln38_30_reg_6048 <= mul_ln38_30_fu_3928_p2;
+        mul_ln38_31_reg_6053 <= mul_ln38_31_fu_3932_p2;
+        mul_ln38_32_reg_6058 <= mul_ln38_32_fu_3936_p2;
+        mul_ln38_33_reg_6063 <= mul_ln38_33_fu_3940_p2;
+        mul_ln38_34_reg_6068 <= mul_ln38_34_fu_3944_p2;
+        mul_ln38_35_reg_6073 <= mul_ln38_35_fu_3948_p2;
+        mul_ln38_36_reg_6078 <= mul_ln38_36_fu_3952_p2;
+        mul_ln38_37_reg_6083 <= mul_ln38_37_fu_3956_p2;
+        mul_ln38_38_reg_6088 <= mul_ln38_38_fu_3960_p2;
+        mul_ln38_39_reg_6093 <= mul_ln38_39_fu_3964_p2;
+        mul_ln38_3_reg_5913 <= mul_ln38_3_fu_3820_p2;
+        mul_ln38_40_reg_6098 <= mul_ln38_40_fu_3968_p2;
+        mul_ln38_43_reg_6113 <= mul_ln38_43_fu_3972_p2;
+        mul_ln38_44_reg_6118 <= mul_ln38_44_fu_3976_p2;
+        mul_ln38_47_reg_6133 <= mul_ln38_47_fu_3980_p2;
+        mul_ln38_48_reg_6138 <= mul_ln38_48_fu_3984_p2;
+        mul_ln38_49_reg_6143 <= mul_ln38_49_fu_3988_p2;
+        mul_ln38_4_reg_5918 <= mul_ln38_4_fu_3824_p2;
+        mul_ln38_50_reg_6148 <= mul_ln38_50_fu_3992_p2;
+        mul_ln38_51_reg_6153 <= mul_ln38_51_fu_3996_p2;
+        mul_ln38_52_reg_6158 <= mul_ln38_52_fu_4000_p2;
+        mul_ln38_53_reg_6163 <= mul_ln38_53_fu_4004_p2;
+        mul_ln38_54_reg_6168 <= mul_ln38_54_fu_4008_p2;
+        mul_ln38_55_reg_6173 <= mul_ln38_55_fu_4012_p2;
+        mul_ln38_56_reg_6178 <= mul_ln38_56_fu_4016_p2;
+        mul_ln38_59_reg_6193 <= mul_ln38_59_fu_4020_p2;
+        mul_ln38_5_reg_5923 <= mul_ln38_5_fu_3828_p2;
+        mul_ln38_60_reg_6198 <= mul_ln38_60_fu_4024_p2;
+        mul_ln38_62_reg_6208 <= mul_ln38_62_fu_4028_p2;
+        mul_ln38_63_reg_6213 <= mul_ln38_63_fu_4032_p2;
+        mul_ln38_6_reg_5928 <= mul_ln38_6_fu_3832_p2;
+        mul_ln38_7_reg_5933 <= mul_ln38_7_fu_3836_p2;
+        mul_ln38_8_reg_5938 <= mul_ln38_8_fu_3840_p2;
+        mul_ln38_9_reg_5943 <= mul_ln38_9_fu_3844_p2;
+        mul_ln38_reg_5898 <= mul_ln38_fu_3808_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3615_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        out_loc_addr_reg_4927 <= zext_ln38_fu_3797_p1;
+        sext_ln38_reg_4916 <= sext_ln38_fu_3726_p1;
+        zext_ln31_1_reg_4620[30 : 0] <= zext_ln31_1_fu_3665_p1[30 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((icmp_ln42_reg_6313 == 1'd0) & (ap_enable_reg_pp3_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0) & (1'b0 == ap_block_pp3_stage0_11001))) begin
+        out_loc_load_reg_6327 <= out_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3615_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        select_ln31_1_reg_4615 <= select_ln31_1_fu_3645_p3;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_fu_3513_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        trunc_ln1_reg_4529 <= {{phi_ln28_reg_3307[11:6]}};
+        trunc_ln28_reg_4524 <= trunc_ln28_fu_3525_p1;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln27_fu_3420_p2 == 1'd1)) begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b1;
+    end else begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln28_fu_3513_p2 == 1'd1)) begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b1;
+    end else begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln31_fu_3615_p2 == 1'd1)) begin
+        ap_condition_pp2_exit_iter0_state23 = 1'b1;
+    end else begin
+        ap_condition_pp2_exit_iter0_state23 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln42_fu_4373_p2 == 1'd1)) begin
+        ap_condition_pp3_exit_iter0_state29 = 1'b1;
+    end else begin
+        ap_condition_pp3_exit_iter0_state29 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state36))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b0))) begin
+        ap_idle_pp1 = 1'b1;
+    end else begin
+        ap_idle_pp1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp2_iter1 == 1'b0) & (ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter4 == 1'b0) & (ap_enable_reg_pp2_iter3 == 1'b0) & (ap_enable_reg_pp2_iter2 == 1'b0))) begin
+        ap_idle_pp2 = 1'b1;
+    end else begin
+        ap_idle_pp2 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp3_iter2 == 1'b0) & (ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter0 == 1'b0))) begin
+        ap_idle_pp3 = 1'b1;
+    end else begin
+        ap_idle_pp3 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln31_reg_4606 == 1'd0) & (1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        ap_phi_mux_i_0_phi_fu_3333_p4 = select_ln31_1_reg_4615;
+    end else begin
+        ap_phi_mux_i_0_phi_fu_3333_p4 = i_0_reg_3329;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state36))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_0_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_0_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_0_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_0_ce0 = 1'b1;
+    end else begin
+        in1_loc_0_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_0_we0 = 1'b1;
+    end else begin
+        in1_loc_0_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_10_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_10_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_10_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_10_ce0 = 1'b1;
+    end else begin
+        in1_loc_10_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd10) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_10_we0 = 1'b1;
+    end else begin
+        in1_loc_10_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_11_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_11_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_11_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_11_ce0 = 1'b1;
+    end else begin
+        in1_loc_11_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd11) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_11_we0 = 1'b1;
+    end else begin
+        in1_loc_11_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_12_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_12_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_12_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_12_ce0 = 1'b1;
+    end else begin
+        in1_loc_12_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd12) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_12_we0 = 1'b1;
+    end else begin
+        in1_loc_12_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_13_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_13_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_13_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_13_ce0 = 1'b1;
+    end else begin
+        in1_loc_13_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd13) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_13_we0 = 1'b1;
+    end else begin
+        in1_loc_13_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_14_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_14_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_14_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_14_ce0 = 1'b1;
+    end else begin
+        in1_loc_14_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd14) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_14_we0 = 1'b1;
+    end else begin
+        in1_loc_14_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_15_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_15_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_15_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_15_ce0 = 1'b1;
+    end else begin
+        in1_loc_15_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd15) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_15_we0 = 1'b1;
+    end else begin
+        in1_loc_15_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_16_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_16_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_16_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_16_ce0 = 1'b1;
+    end else begin
+        in1_loc_16_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd16) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_16_we0 = 1'b1;
+    end else begin
+        in1_loc_16_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_17_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_17_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_17_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_17_ce0 = 1'b1;
+    end else begin
+        in1_loc_17_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd17) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_17_we0 = 1'b1;
+    end else begin
+        in1_loc_17_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_18_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_18_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_18_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_18_ce0 = 1'b1;
+    end else begin
+        in1_loc_18_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd18) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_18_we0 = 1'b1;
+    end else begin
+        in1_loc_18_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_19_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_19_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_19_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_19_ce0 = 1'b1;
+    end else begin
+        in1_loc_19_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd19) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_19_we0 = 1'b1;
+    end else begin
+        in1_loc_19_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_1_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_1_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_1_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_1_ce0 = 1'b1;
+    end else begin
+        in1_loc_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_1_we0 = 1'b1;
+    end else begin
+        in1_loc_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_20_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_20_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_20_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_20_ce0 = 1'b1;
+    end else begin
+        in1_loc_20_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd20) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_20_we0 = 1'b1;
+    end else begin
+        in1_loc_20_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_21_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_21_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_21_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_21_ce0 = 1'b1;
+    end else begin
+        in1_loc_21_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd21) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_21_we0 = 1'b1;
+    end else begin
+        in1_loc_21_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_22_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_22_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_22_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_22_ce0 = 1'b1;
+    end else begin
+        in1_loc_22_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd22) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_22_we0 = 1'b1;
+    end else begin
+        in1_loc_22_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_23_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_23_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_23_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_23_ce0 = 1'b1;
+    end else begin
+        in1_loc_23_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd23) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_23_we0 = 1'b1;
+    end else begin
+        in1_loc_23_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_24_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_24_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_24_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_24_ce0 = 1'b1;
+    end else begin
+        in1_loc_24_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd24) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_24_we0 = 1'b1;
+    end else begin
+        in1_loc_24_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_25_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_25_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_25_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_25_ce0 = 1'b1;
+    end else begin
+        in1_loc_25_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd25) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_25_we0 = 1'b1;
+    end else begin
+        in1_loc_25_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_26_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_26_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_26_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_26_ce0 = 1'b1;
+    end else begin
+        in1_loc_26_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd26) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_26_we0 = 1'b1;
+    end else begin
+        in1_loc_26_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_27_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_27_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_27_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_27_ce0 = 1'b1;
+    end else begin
+        in1_loc_27_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd27) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_27_we0 = 1'b1;
+    end else begin
+        in1_loc_27_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_28_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_28_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_28_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_28_ce0 = 1'b1;
+    end else begin
+        in1_loc_28_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd28) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_28_we0 = 1'b1;
+    end else begin
+        in1_loc_28_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_29_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_29_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_29_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_29_ce0 = 1'b1;
+    end else begin
+        in1_loc_29_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd29) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_29_we0 = 1'b1;
+    end else begin
+        in1_loc_29_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_2_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_2_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_2_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_2_ce0 = 1'b1;
+    end else begin
+        in1_loc_2_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd2) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_2_we0 = 1'b1;
+    end else begin
+        in1_loc_2_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_30_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_30_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_30_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_30_ce0 = 1'b1;
+    end else begin
+        in1_loc_30_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd30) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_30_we0 = 1'b1;
+    end else begin
+        in1_loc_30_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_31_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_31_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_31_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_31_ce0 = 1'b1;
+    end else begin
+        in1_loc_31_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd31) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_31_we0 = 1'b1;
+    end else begin
+        in1_loc_31_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_32_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_32_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_32_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_32_ce0 = 1'b1;
+    end else begin
+        in1_loc_32_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd32) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_32_we0 = 1'b1;
+    end else begin
+        in1_loc_32_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_33_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_33_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_33_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_33_ce0 = 1'b1;
+    end else begin
+        in1_loc_33_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd33) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_33_we0 = 1'b1;
+    end else begin
+        in1_loc_33_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_34_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_34_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_34_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_34_ce0 = 1'b1;
+    end else begin
+        in1_loc_34_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd34) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_34_we0 = 1'b1;
+    end else begin
+        in1_loc_34_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_35_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_35_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_35_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_35_ce0 = 1'b1;
+    end else begin
+        in1_loc_35_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd35) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_35_we0 = 1'b1;
+    end else begin
+        in1_loc_35_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_36_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_36_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_36_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_36_ce0 = 1'b1;
+    end else begin
+        in1_loc_36_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd36) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_36_we0 = 1'b1;
+    end else begin
+        in1_loc_36_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_37_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_37_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_37_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_37_ce0 = 1'b1;
+    end else begin
+        in1_loc_37_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd37) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_37_we0 = 1'b1;
+    end else begin
+        in1_loc_37_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_38_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_38_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_38_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_38_ce0 = 1'b1;
+    end else begin
+        in1_loc_38_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd38) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_38_we0 = 1'b1;
+    end else begin
+        in1_loc_38_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_39_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_39_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_39_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_39_ce0 = 1'b1;
+    end else begin
+        in1_loc_39_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd39) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_39_we0 = 1'b1;
+    end else begin
+        in1_loc_39_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_3_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_3_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_3_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_3_ce0 = 1'b1;
+    end else begin
+        in1_loc_3_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd3) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_3_we0 = 1'b1;
+    end else begin
+        in1_loc_3_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_40_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_40_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_40_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_40_ce0 = 1'b1;
+    end else begin
+        in1_loc_40_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd40) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_40_we0 = 1'b1;
+    end else begin
+        in1_loc_40_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_41_address0 = zext_ln31_1_reg_4620;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_41_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_41_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_41_ce0 = 1'b1;
+    end else begin
+        in1_loc_41_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd41) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_41_we0 = 1'b1;
+    end else begin
+        in1_loc_41_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_42_address0 = zext_ln31_1_reg_4620;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_42_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_42_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_42_ce0 = 1'b1;
+    end else begin
+        in1_loc_42_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd42) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_42_we0 = 1'b1;
+    end else begin
+        in1_loc_42_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_43_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_43_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_43_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_43_ce0 = 1'b1;
+    end else begin
+        in1_loc_43_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd43) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_43_we0 = 1'b1;
+    end else begin
+        in1_loc_43_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_44_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_44_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_44_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_44_ce0 = 1'b1;
+    end else begin
+        in1_loc_44_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd44) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_44_we0 = 1'b1;
+    end else begin
+        in1_loc_44_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_45_address0 = zext_ln31_1_reg_4620;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_45_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_45_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_45_ce0 = 1'b1;
+    end else begin
+        in1_loc_45_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd45) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_45_we0 = 1'b1;
+    end else begin
+        in1_loc_45_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_46_address0 = zext_ln31_1_reg_4620;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_46_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_46_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_46_ce0 = 1'b1;
+    end else begin
+        in1_loc_46_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd46) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_46_we0 = 1'b1;
+    end else begin
+        in1_loc_46_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_47_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_47_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_47_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_47_ce0 = 1'b1;
+    end else begin
+        in1_loc_47_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd47) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_47_we0 = 1'b1;
+    end else begin
+        in1_loc_47_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_48_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_48_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_48_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_48_ce0 = 1'b1;
+    end else begin
+        in1_loc_48_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd48) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_48_we0 = 1'b1;
+    end else begin
+        in1_loc_48_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_49_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_49_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_49_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_49_ce0 = 1'b1;
+    end else begin
+        in1_loc_49_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd49) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_49_we0 = 1'b1;
+    end else begin
+        in1_loc_49_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_4_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_4_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_4_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_4_ce0 = 1'b1;
+    end else begin
+        in1_loc_4_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd4) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_4_we0 = 1'b1;
+    end else begin
+        in1_loc_4_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_50_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_50_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_50_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_50_ce0 = 1'b1;
+    end else begin
+        in1_loc_50_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd50) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_50_we0 = 1'b1;
+    end else begin
+        in1_loc_50_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_51_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_51_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_51_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_51_ce0 = 1'b1;
+    end else begin
+        in1_loc_51_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd51) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_51_we0 = 1'b1;
+    end else begin
+        in1_loc_51_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_52_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_52_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_52_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_52_ce0 = 1'b1;
+    end else begin
+        in1_loc_52_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd52) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_52_we0 = 1'b1;
+    end else begin
+        in1_loc_52_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_53_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_53_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_53_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_53_ce0 = 1'b1;
+    end else begin
+        in1_loc_53_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd53) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_53_we0 = 1'b1;
+    end else begin
+        in1_loc_53_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_54_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_54_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_54_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_54_ce0 = 1'b1;
+    end else begin
+        in1_loc_54_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd54) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_54_we0 = 1'b1;
+    end else begin
+        in1_loc_54_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_55_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_55_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_55_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_55_ce0 = 1'b1;
+    end else begin
+        in1_loc_55_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd55) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_55_we0 = 1'b1;
+    end else begin
+        in1_loc_55_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_56_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_56_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_56_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_56_ce0 = 1'b1;
+    end else begin
+        in1_loc_56_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd56) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_56_we0 = 1'b1;
+    end else begin
+        in1_loc_56_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_57_address0 = zext_ln31_1_reg_4620;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_57_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_57_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_57_ce0 = 1'b1;
+    end else begin
+        in1_loc_57_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd57) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_57_we0 = 1'b1;
+    end else begin
+        in1_loc_57_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_58_address0 = zext_ln31_1_reg_4620;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_58_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_58_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_58_ce0 = 1'b1;
+    end else begin
+        in1_loc_58_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd58) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_58_we0 = 1'b1;
+    end else begin
+        in1_loc_58_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_59_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_59_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_59_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_59_ce0 = 1'b1;
+    end else begin
+        in1_loc_59_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd59) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_59_we0 = 1'b1;
+    end else begin
+        in1_loc_59_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_5_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_5_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_5_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_5_ce0 = 1'b1;
+    end else begin
+        in1_loc_5_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd5) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_5_we0 = 1'b1;
+    end else begin
+        in1_loc_5_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_60_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_60_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_60_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_60_ce0 = 1'b1;
+    end else begin
+        in1_loc_60_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd60) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_60_we0 = 1'b1;
+    end else begin
+        in1_loc_60_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_61_address0 = zext_ln31_1_reg_4620;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_61_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_61_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_61_ce0 = 1'b1;
+    end else begin
+        in1_loc_61_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd61) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_61_we0 = 1'b1;
+    end else begin
+        in1_loc_61_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_62_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_62_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_62_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_62_ce0 = 1'b1;
+    end else begin
+        in1_loc_62_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd62) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_62_we0 = 1'b1;
+    end else begin
+        in1_loc_62_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_63_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_63_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_63_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_63_ce0 = 1'b1;
+    end else begin
+        in1_loc_63_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd63) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_63_we0 = 1'b1;
+    end else begin
+        in1_loc_63_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_6_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_6_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_6_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_6_ce0 = 1'b1;
+    end else begin
+        in1_loc_6_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd6) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_6_we0 = 1'b1;
+    end else begin
+        in1_loc_6_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_7_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_7_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_7_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_7_ce0 = 1'b1;
+    end else begin
+        in1_loc_7_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd7) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_7_we0 = 1'b1;
+    end else begin
+        in1_loc_7_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_8_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_8_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_8_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_8_ce0 = 1'b1;
+    end else begin
+        in1_loc_8_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd8) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_8_we0 = 1'b1;
+    end else begin
+        in1_loc_8_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in1_loc_9_address0 = zext_ln31_1_fu_3665_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_9_address0 = zext_ln27_fu_3446_p1;
+    end else begin
+        in1_loc_9_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)))) begin
+        in1_loc_9_ce0 = 1'b1;
+    end else begin
+        in1_loc_9_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4443_pp0_iter1_reg == 6'd9) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_9_we0 = 1'b1;
+    end else begin
+        in1_loc_9_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        in1_mem_ARVALID = 1'b1;
+    end else begin
+        in1_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_RREADY = 1'b1;
+    end else begin
+        in1_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        in1_mem_blk_n_AR = m_axi_in1_mem_ARREADY;
+    end else begin
+        in1_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_blk_n_R = m_axi_in1_mem_RVALID;
+    end else begin
+        in1_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_0_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_0_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_0_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_0_ce0 = 1'b1;
+    end else begin
+        in2_loc_0_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_0_we0 = 1'b1;
+    end else begin
+        in2_loc_0_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_10_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_10_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_10_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_10_ce0 = 1'b1;
+    end else begin
+        in2_loc_10_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd10) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_10_we0 = 1'b1;
+    end else begin
+        in2_loc_10_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_11_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_11_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_11_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_11_ce0 = 1'b1;
+    end else begin
+        in2_loc_11_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd11) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_11_we0 = 1'b1;
+    end else begin
+        in2_loc_11_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_12_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_12_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_12_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_12_ce0 = 1'b1;
+    end else begin
+        in2_loc_12_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd12) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_12_we0 = 1'b1;
+    end else begin
+        in2_loc_12_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_13_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_13_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_13_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_13_ce0 = 1'b1;
+    end else begin
+        in2_loc_13_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd13) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_13_we0 = 1'b1;
+    end else begin
+        in2_loc_13_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_14_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_14_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_14_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_14_ce0 = 1'b1;
+    end else begin
+        in2_loc_14_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd14) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_14_we0 = 1'b1;
+    end else begin
+        in2_loc_14_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_15_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_15_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_15_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_15_ce0 = 1'b1;
+    end else begin
+        in2_loc_15_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd15) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_15_we0 = 1'b1;
+    end else begin
+        in2_loc_15_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_16_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_16_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_16_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_16_ce0 = 1'b1;
+    end else begin
+        in2_loc_16_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd16) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_16_we0 = 1'b1;
+    end else begin
+        in2_loc_16_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_17_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_17_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_17_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_17_ce0 = 1'b1;
+    end else begin
+        in2_loc_17_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd17) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_17_we0 = 1'b1;
+    end else begin
+        in2_loc_17_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_18_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_18_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_18_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_18_ce0 = 1'b1;
+    end else begin
+        in2_loc_18_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd18) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_18_we0 = 1'b1;
+    end else begin
+        in2_loc_18_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_19_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_19_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_19_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_19_ce0 = 1'b1;
+    end else begin
+        in2_loc_19_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd19) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_19_we0 = 1'b1;
+    end else begin
+        in2_loc_19_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_1_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_1_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_1_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_1_ce0 = 1'b1;
+    end else begin
+        in2_loc_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd1) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_1_we0 = 1'b1;
+    end else begin
+        in2_loc_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_20_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_20_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_20_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_20_ce0 = 1'b1;
+    end else begin
+        in2_loc_20_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd20) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_20_we0 = 1'b1;
+    end else begin
+        in2_loc_20_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_21_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_21_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_21_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_21_ce0 = 1'b1;
+    end else begin
+        in2_loc_21_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd21) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_21_we0 = 1'b1;
+    end else begin
+        in2_loc_21_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_22_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_22_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_22_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_22_ce0 = 1'b1;
+    end else begin
+        in2_loc_22_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd22) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_22_we0 = 1'b1;
+    end else begin
+        in2_loc_22_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_23_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_23_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_23_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_23_ce0 = 1'b1;
+    end else begin
+        in2_loc_23_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd23) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_23_we0 = 1'b1;
+    end else begin
+        in2_loc_23_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_24_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_24_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_24_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_24_ce0 = 1'b1;
+    end else begin
+        in2_loc_24_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd24) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_24_we0 = 1'b1;
+    end else begin
+        in2_loc_24_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_25_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_25_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_25_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_25_ce0 = 1'b1;
+    end else begin
+        in2_loc_25_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd25) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_25_we0 = 1'b1;
+    end else begin
+        in2_loc_25_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_26_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_26_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_26_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_26_ce0 = 1'b1;
+    end else begin
+        in2_loc_26_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd26) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_26_we0 = 1'b1;
+    end else begin
+        in2_loc_26_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_27_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_27_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_27_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_27_ce0 = 1'b1;
+    end else begin
+        in2_loc_27_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd27) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_27_we0 = 1'b1;
+    end else begin
+        in2_loc_27_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_28_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_28_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_28_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_28_ce0 = 1'b1;
+    end else begin
+        in2_loc_28_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd28) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_28_we0 = 1'b1;
+    end else begin
+        in2_loc_28_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_29_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_29_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_29_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_29_ce0 = 1'b1;
+    end else begin
+        in2_loc_29_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd29) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_29_we0 = 1'b1;
+    end else begin
+        in2_loc_29_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_2_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_2_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_2_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_2_ce0 = 1'b1;
+    end else begin
+        in2_loc_2_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd2) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_2_we0 = 1'b1;
+    end else begin
+        in2_loc_2_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_30_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_30_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_30_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_30_ce0 = 1'b1;
+    end else begin
+        in2_loc_30_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd30) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_30_we0 = 1'b1;
+    end else begin
+        in2_loc_30_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_31_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_31_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_31_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_31_ce0 = 1'b1;
+    end else begin
+        in2_loc_31_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd31) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_31_we0 = 1'b1;
+    end else begin
+        in2_loc_31_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_32_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_32_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_32_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_32_ce0 = 1'b1;
+    end else begin
+        in2_loc_32_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd32) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_32_we0 = 1'b1;
+    end else begin
+        in2_loc_32_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_33_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_33_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_33_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_33_ce0 = 1'b1;
+    end else begin
+        in2_loc_33_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd33) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_33_we0 = 1'b1;
+    end else begin
+        in2_loc_33_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_34_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_34_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_34_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_34_ce0 = 1'b1;
+    end else begin
+        in2_loc_34_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd34) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_34_we0 = 1'b1;
+    end else begin
+        in2_loc_34_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_35_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_35_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_35_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_35_ce0 = 1'b1;
+    end else begin
+        in2_loc_35_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd35) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_35_we0 = 1'b1;
+    end else begin
+        in2_loc_35_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_36_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_36_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_36_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_36_ce0 = 1'b1;
+    end else begin
+        in2_loc_36_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd36) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_36_we0 = 1'b1;
+    end else begin
+        in2_loc_36_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_37_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_37_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_37_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_37_ce0 = 1'b1;
+    end else begin
+        in2_loc_37_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd37) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_37_we0 = 1'b1;
+    end else begin
+        in2_loc_37_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_38_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_38_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_38_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_38_ce0 = 1'b1;
+    end else begin
+        in2_loc_38_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd38) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_38_we0 = 1'b1;
+    end else begin
+        in2_loc_38_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_39_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_39_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_39_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_39_ce0 = 1'b1;
+    end else begin
+        in2_loc_39_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd39) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_39_we0 = 1'b1;
+    end else begin
+        in2_loc_39_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_3_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_3_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_3_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_3_ce0 = 1'b1;
+    end else begin
+        in2_loc_3_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd3) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_3_we0 = 1'b1;
+    end else begin
+        in2_loc_3_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_40_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_40_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_40_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_40_ce0 = 1'b1;
+    end else begin
+        in2_loc_40_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd40) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_40_we0 = 1'b1;
+    end else begin
+        in2_loc_40_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_41_address0 = sext_ln38_reg_4916;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_41_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_41_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_41_ce0 = 1'b1;
+    end else begin
+        in2_loc_41_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd41) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_41_we0 = 1'b1;
+    end else begin
+        in2_loc_41_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_42_address0 = sext_ln38_reg_4916;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_42_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_42_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_42_ce0 = 1'b1;
+    end else begin
+        in2_loc_42_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd42) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_42_we0 = 1'b1;
+    end else begin
+        in2_loc_42_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_43_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_43_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_43_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_43_ce0 = 1'b1;
+    end else begin
+        in2_loc_43_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd43) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_43_we0 = 1'b1;
+    end else begin
+        in2_loc_43_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_44_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_44_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_44_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_44_ce0 = 1'b1;
+    end else begin
+        in2_loc_44_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd44) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_44_we0 = 1'b1;
+    end else begin
+        in2_loc_44_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_45_address0 = sext_ln38_reg_4916;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_45_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_45_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_45_ce0 = 1'b1;
+    end else begin
+        in2_loc_45_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd45) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_45_we0 = 1'b1;
+    end else begin
+        in2_loc_45_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_46_address0 = sext_ln38_reg_4916;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_46_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_46_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_46_ce0 = 1'b1;
+    end else begin
+        in2_loc_46_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd46) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_46_we0 = 1'b1;
+    end else begin
+        in2_loc_46_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_47_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_47_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_47_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_47_ce0 = 1'b1;
+    end else begin
+        in2_loc_47_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd47) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_47_we0 = 1'b1;
+    end else begin
+        in2_loc_47_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_48_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_48_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_48_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_48_ce0 = 1'b1;
+    end else begin
+        in2_loc_48_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd48) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_48_we0 = 1'b1;
+    end else begin
+        in2_loc_48_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_49_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_49_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_49_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_49_ce0 = 1'b1;
+    end else begin
+        in2_loc_49_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd49) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_49_we0 = 1'b1;
+    end else begin
+        in2_loc_49_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_4_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_4_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_4_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_4_ce0 = 1'b1;
+    end else begin
+        in2_loc_4_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd4) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_4_we0 = 1'b1;
+    end else begin
+        in2_loc_4_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_50_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_50_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_50_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_50_ce0 = 1'b1;
+    end else begin
+        in2_loc_50_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd50) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_50_we0 = 1'b1;
+    end else begin
+        in2_loc_50_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_51_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_51_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_51_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_51_ce0 = 1'b1;
+    end else begin
+        in2_loc_51_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd51) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_51_we0 = 1'b1;
+    end else begin
+        in2_loc_51_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_52_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_52_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_52_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_52_ce0 = 1'b1;
+    end else begin
+        in2_loc_52_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd52) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_52_we0 = 1'b1;
+    end else begin
+        in2_loc_52_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_53_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_53_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_53_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_53_ce0 = 1'b1;
+    end else begin
+        in2_loc_53_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd53) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_53_we0 = 1'b1;
+    end else begin
+        in2_loc_53_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_54_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_54_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_54_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_54_ce0 = 1'b1;
+    end else begin
+        in2_loc_54_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd54) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_54_we0 = 1'b1;
+    end else begin
+        in2_loc_54_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_55_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_55_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_55_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_55_ce0 = 1'b1;
+    end else begin
+        in2_loc_55_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd55) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_55_we0 = 1'b1;
+    end else begin
+        in2_loc_55_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_56_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_56_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_56_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_56_ce0 = 1'b1;
+    end else begin
+        in2_loc_56_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd56) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_56_we0 = 1'b1;
+    end else begin
+        in2_loc_56_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_57_address0 = sext_ln38_reg_4916;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_57_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_57_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_57_ce0 = 1'b1;
+    end else begin
+        in2_loc_57_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd57) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_57_we0 = 1'b1;
+    end else begin
+        in2_loc_57_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_58_address0 = sext_ln38_reg_4916;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_58_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_58_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_58_ce0 = 1'b1;
+    end else begin
+        in2_loc_58_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd58) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_58_we0 = 1'b1;
+    end else begin
+        in2_loc_58_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_59_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_59_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_59_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_59_ce0 = 1'b1;
+    end else begin
+        in2_loc_59_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd59) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_59_we0 = 1'b1;
+    end else begin
+        in2_loc_59_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_5_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_5_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_5_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_5_ce0 = 1'b1;
+    end else begin
+        in2_loc_5_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd5) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_5_we0 = 1'b1;
+    end else begin
+        in2_loc_5_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_60_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_60_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_60_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_60_ce0 = 1'b1;
+    end else begin
+        in2_loc_60_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd60) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_60_we0 = 1'b1;
+    end else begin
+        in2_loc_60_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_61_address0 = sext_ln38_reg_4916;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_61_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_61_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_61_ce0 = 1'b1;
+    end else begin
+        in2_loc_61_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd61) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_61_we0 = 1'b1;
+    end else begin
+        in2_loc_61_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_62_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_62_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_62_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_62_ce0 = 1'b1;
+    end else begin
+        in2_loc_62_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd62) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_62_we0 = 1'b1;
+    end else begin
+        in2_loc_62_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_63_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_63_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_63_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_63_ce0 = 1'b1;
+    end else begin
+        in2_loc_63_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd63) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_63_we0 = 1'b1;
+    end else begin
+        in2_loc_63_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_6_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_6_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_6_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_6_ce0 = 1'b1;
+    end else begin
+        in2_loc_6_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd6) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_6_we0 = 1'b1;
+    end else begin
+        in2_loc_6_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_7_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_7_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_7_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_7_ce0 = 1'b1;
+    end else begin
+        in2_loc_7_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd7) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_7_we0 = 1'b1;
+    end else begin
+        in2_loc_7_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_8_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_8_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_8_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_8_ce0 = 1'b1;
+    end else begin
+        in2_loc_8_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd8) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_8_we0 = 1'b1;
+    end else begin
+        in2_loc_8_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        in2_loc_9_address0 = sext_ln38_fu_3726_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_9_address0 = zext_ln28_fu_3539_p1;
+    end else begin
+        in2_loc_9_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)))) begin
+        in2_loc_9_ce0 = 1'b1;
+    end else begin
+        in2_loc_9_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4529_pp1_iter1_reg == 6'd9) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_9_we0 = 1'b1;
+    end else begin
+        in2_loc_9_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+        in2_mem_ARVALID = 1'b1;
+    end else begin
+        in2_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_RREADY = 1'b1;
+    end else begin
+        in2_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state12)) begin
+        in2_mem_blk_n_AR = m_axi_in2_mem_ARREADY;
+    end else begin
+        in2_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_blk_n_R = m_axi_in2_mem_RVALID;
+    end else begin
+        in2_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp3_stage0) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        out_loc_address0 = zext_ln42_fu_4385_p1;
+    end else if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        out_loc_address0 = out_loc_addr_reg_4927_pp2_iter1_reg;
+    end else begin
+        out_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)) | ((ap_enable_reg_pp3_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0) & (1'b0 == ap_block_pp3_stage0_11001)))) begin
+        out_loc_ce0 = 1'b1;
+    end else begin
+        out_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter4 == 1'b1))) begin
+        out_loc_ce1 = 1'b1;
+    end else begin
+        out_loc_ce1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4606_pp2_iter3_reg == 1'd0) & (ap_enable_reg_pp2_iter4 == 1'b1))) begin
+        out_loc_we1 = 1'b1;
+    end else begin
+        out_loc_we1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state28))) begin
+        out_mem_AWVALID = 1'b1;
+    end else begin
+        out_mem_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state36))) begin
+        out_mem_BREADY = 1'b1;
+    end else begin
+        out_mem_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln42_reg_6313_pp3_iter1_reg == 1'd0) & (ap_enable_reg_pp3_iter2 == 1'b1) & (1'b0 == ap_block_pp3_stage0_11001))) begin
+        out_mem_WVALID = 1'b1;
+    end else begin
+        out_mem_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state28)) begin
+        out_mem_blk_n_AW = m_axi_out_mem_AWREADY;
+    end else begin
+        out_mem_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state36)) begin
+        out_mem_blk_n_B = m_axi_out_mem_BVALID;
+    end else begin
+        out_mem_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln42_reg_6313_pp3_iter1_reg == 1'd0) & (1'b0 == ap_block_pp3_stage0) & (ap_enable_reg_pp3_iter2 == 1'b1))) begin
+        out_mem_blk_n_W = m_axi_out_mem_WREADY;
+    end else begin
+        out_mem_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        ap_ST_fsm_pp0_stage0 : begin
+            if ((~((icmp_ln27_fu_3420_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end else if ((((icmp_ln27_fu_3420_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end
+        end
+        ap_ST_fsm_state12 : begin
+            if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+                ap_NS_fsm = ap_ST_fsm_state13;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end
+        end
+        ap_ST_fsm_state13 : begin
+            ap_NS_fsm = ap_ST_fsm_state14;
+        end
+        ap_ST_fsm_state14 : begin
+            ap_NS_fsm = ap_ST_fsm_state15;
+        end
+        ap_ST_fsm_state15 : begin
+            ap_NS_fsm = ap_ST_fsm_state16;
+        end
+        ap_ST_fsm_state16 : begin
+            ap_NS_fsm = ap_ST_fsm_state17;
+        end
+        ap_ST_fsm_state17 : begin
+            ap_NS_fsm = ap_ST_fsm_state18;
+        end
+        ap_ST_fsm_state18 : begin
+            ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+        end
+        ap_ST_fsm_pp1_stage0 : begin
+            if ((~((icmp_ln28_fu_3513_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)) & ~((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end else if ((((icmp_ln28_fu_3513_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)) | ((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state22;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end
+        end
+        ap_ST_fsm_state22 : begin
+            ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+        end
+        ap_ST_fsm_pp2_stage0 : begin
+            if ((~((ap_enable_reg_pp2_iter1 == 1'b0) & (icmp_ln31_fu_3615_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone)) & ~((ap_enable_reg_pp2_iter4 == 1'b1) & (ap_enable_reg_pp2_iter3 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end else if ((((ap_enable_reg_pp2_iter1 == 1'b0) & (icmp_ln31_fu_3615_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b0 == ap_block_pp2_stage0_subdone)) | ((ap_enable_reg_pp2_iter4 == 1'b1) & (ap_enable_reg_pp2_iter3 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state28;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end
+        end
+        ap_ST_fsm_state28 : begin
+            if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state28))) begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state28;
+            end
+        end
+        ap_ST_fsm_pp3_stage0 : begin
+            if ((~((ap_enable_reg_pp3_iter0 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone) & (ap_enable_reg_pp3_iter1 == 1'b0) & (icmp_ln42_fu_4373_p2 == 1'd1)) & ~((ap_enable_reg_pp3_iter2 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone) & (ap_enable_reg_pp3_iter1 == 1'b0)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end else if ((((ap_enable_reg_pp3_iter2 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone) & (ap_enable_reg_pp3_iter1 == 1'b0)) | ((ap_enable_reg_pp3_iter0 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone) & (ap_enable_reg_pp3_iter1 == 1'b0) & (icmp_ln42_fu_4373_p2 == 1'd1)))) begin
+                ap_NS_fsm = ap_ST_fsm_state32;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end
+        end
+        ap_ST_fsm_state32 : begin
+            ap_NS_fsm = ap_ST_fsm_state33;
+        end
+        ap_ST_fsm_state33 : begin
+            ap_NS_fsm = ap_ST_fsm_state34;
+        end
+        ap_ST_fsm_state34 : begin
+            ap_NS_fsm = ap_ST_fsm_state35;
+        end
+        ap_ST_fsm_state35 : begin
+            ap_NS_fsm = ap_ST_fsm_state36;
+        end
+        ap_ST_fsm_state36 : begin
+            if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state36))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state36;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln27_fu_3426_p2 = (phi_ln27_reg_3296 + 13'd1);
+
+assign add_ln28_fu_3519_p2 = (phi_ln28_reg_3307 + 13'd1);
+
+assign add_ln31_fu_3620_p2 = (indvar_flatten_reg_3318 + 64'd1);
+
+assign add_ln38_10_fu_4113_p2 = (mul_ln38_12_reg_5958 + mul_ln38_11_reg_5953);
+
+assign add_ln38_11_fu_4117_p2 = (mul_ln38_14_reg_5968 + mul_ln38_13_reg_5963);
+
+assign add_ln38_12_fu_4121_p2 = (add_ln38_10_fu_4113_p2 + add_ln38_11_fu_4117_p2);
+
+assign add_ln38_13_fu_4283_p2 = (add_ln38_9_reg_6258 + add_ln38_12_reg_6263);
+
+assign add_ln38_14_fu_4287_p2 = (add_ln38_6_reg_6253 + add_ln38_13_fu_4283_p2);
+
+assign add_ln38_15_fu_4127_p2 = (mul_ln38_16_reg_5978 + mul_ln38_15_reg_5973);
+
+assign add_ln38_16_fu_4131_p2 = (mul_ln38_18_reg_5988 + mul_ln38_17_reg_5983);
+
+assign add_ln38_17_fu_4135_p2 = (add_ln38_15_fu_4127_p2 + add_ln38_16_fu_4131_p2);
+
+assign add_ln38_18_fu_4141_p2 = (mul_ln38_20_reg_5998 + mul_ln38_19_reg_5993);
+
+assign add_ln38_19_fu_4145_p2 = (mul_ln38_22_reg_6008 + mul_ln38_21_reg_6003);
+
+assign add_ln38_1_fu_4069_p2 = (mul_ln38_2_reg_5908 + mul_ln38_1_reg_5903);
+
+assign add_ln38_20_fu_4149_p2 = (add_ln38_18_fu_4141_p2 + add_ln38_19_fu_4145_p2);
+
+assign add_ln38_21_fu_4155_p2 = (add_ln38_17_fu_4135_p2 + add_ln38_20_fu_4149_p2);
+
+assign add_ln38_22_fu_4161_p2 = (mul_ln38_24_reg_6018 + mul_ln38_23_reg_6013);
+
+assign add_ln38_23_fu_4165_p2 = (mul_ln38_26_reg_6028 + mul_ln38_25_reg_6023);
+
+assign add_ln38_24_fu_4169_p2 = (add_ln38_22_fu_4161_p2 + add_ln38_23_fu_4165_p2);
+
+assign add_ln38_25_fu_4175_p2 = (mul_ln38_28_reg_6038 + mul_ln38_27_reg_6033);
+
+assign add_ln38_26_fu_4179_p2 = (mul_ln38_30_reg_6048 + mul_ln38_29_reg_6043);
+
+assign add_ln38_27_fu_4183_p2 = (add_ln38_25_fu_4175_p2 + add_ln38_26_fu_4179_p2);
+
+assign add_ln38_28_fu_4189_p2 = (add_ln38_24_fu_4169_p2 + add_ln38_27_fu_4183_p2);
+
+assign add_ln38_29_fu_4292_p2 = (add_ln38_21_reg_6268 + add_ln38_28_reg_6273);
+
+assign add_ln38_2_fu_4073_p2 = (add_ln38_fu_4064_p2 + add_ln38_1_fu_4069_p2);
+
+assign add_ln38_30_fu_4296_p2 = (add_ln38_14_fu_4287_p2 + add_ln38_29_fu_4292_p2);
+
+assign add_ln38_31_fu_4195_p2 = (mul_ln38_32_reg_6058 + mul_ln38_31_reg_6053);
+
+assign add_ln38_32_fu_4199_p2 = (mul_ln38_34_reg_6068 + mul_ln38_33_reg_6063);
+
+assign add_ln38_33_fu_4203_p2 = (add_ln38_31_fu_4195_p2 + add_ln38_32_fu_4199_p2);
+
+assign add_ln38_34_fu_4209_p2 = (mul_ln38_36_reg_6078 + mul_ln38_35_reg_6073);
+
+assign add_ln38_35_fu_4213_p2 = (mul_ln38_38_reg_6088 + mul_ln38_37_reg_6083);
+
+assign add_ln38_36_fu_4217_p2 = (add_ln38_34_fu_4209_p2 + add_ln38_35_fu_4213_p2);
+
+assign add_ln38_37_fu_4223_p2 = (add_ln38_33_fu_4203_p2 + add_ln38_36_fu_4217_p2);
+
+assign add_ln38_38_fu_4229_p2 = (mul_ln38_40_reg_6098 + mul_ln38_39_reg_6093);
+
+assign add_ln38_39_fu_4302_p2 = (mul_ln38_42_reg_6223 + mul_ln38_41_reg_6218);
+
+assign add_ln38_3_fu_4079_p2 = (mul_ln38_4_reg_5918 + mul_ln38_3_reg_5913);
+
+assign add_ln38_40_fu_4306_p2 = (add_ln38_38_reg_6283 + add_ln38_39_fu_4302_p2);
+
+assign add_ln38_41_fu_4233_p2 = (mul_ln38_44_reg_6118 + mul_ln38_43_reg_6113);
+
+assign add_ln38_42_fu_4311_p2 = (mul_ln38_46_reg_6233 + mul_ln38_45_reg_6228);
+
+assign add_ln38_43_fu_4315_p2 = (add_ln38_41_reg_6288 + add_ln38_42_fu_4311_p2);
+
+assign add_ln38_44_fu_4320_p2 = (add_ln38_40_fu_4306_p2 + add_ln38_43_fu_4315_p2);
+
+assign add_ln38_45_fu_4326_p2 = (add_ln38_37_reg_6278 + add_ln38_44_fu_4320_p2);
+
+assign add_ln38_46_fu_4237_p2 = (mul_ln38_48_reg_6138 + mul_ln38_47_reg_6133);
+
+assign add_ln38_47_fu_4241_p2 = (mul_ln38_50_reg_6148 + mul_ln38_49_reg_6143);
+
+assign add_ln38_48_fu_4245_p2 = (add_ln38_46_fu_4237_p2 + add_ln38_47_fu_4241_p2);
+
+assign add_ln38_49_fu_4251_p2 = (mul_ln38_52_reg_6158 + mul_ln38_51_reg_6153);
+
+assign add_ln38_4_fu_4083_p2 = (mul_ln38_6_reg_5928 + mul_ln38_5_reg_5923);
+
+assign add_ln38_50_fu_4255_p2 = (mul_ln38_54_reg_6168 + mul_ln38_53_reg_6163);
+
+assign add_ln38_51_fu_4259_p2 = (add_ln38_49_fu_4251_p2 + add_ln38_50_fu_4255_p2);
+
+assign add_ln38_52_fu_4265_p2 = (add_ln38_48_fu_4245_p2 + add_ln38_51_fu_4259_p2);
+
+assign add_ln38_53_fu_4271_p2 = (mul_ln38_56_reg_6178 + mul_ln38_55_reg_6173);
+
+assign add_ln38_54_fu_4331_p2 = (mul_ln38_58_reg_6243 + mul_ln38_57_reg_6238);
+
+assign add_ln38_55_fu_4335_p2 = (add_ln38_53_reg_6298 + add_ln38_54_fu_4331_p2);
+
+assign add_ln38_56_fu_4275_p2 = (mul_ln38_60_reg_6198 + mul_ln38_59_reg_6193);
+
+assign add_ln38_57_fu_4279_p2 = (mul_ln38_63_reg_6213 + mul_ln38_62_reg_6208);
+
+assign add_ln38_58_fu_4340_p2 = (mul_ln38_61_reg_6248 + add_ln38_57_reg_6308);
+
+assign add_ln38_59_fu_4344_p2 = (add_ln38_56_reg_6303 + add_ln38_58_fu_4340_p2);
+
+assign add_ln38_5_fu_4087_p2 = (add_ln38_3_fu_4079_p2 + add_ln38_4_fu_4083_p2);
+
+assign add_ln38_60_fu_4349_p2 = (add_ln38_55_fu_4335_p2 + add_ln38_59_fu_4344_p2);
+
+assign add_ln38_61_fu_4355_p2 = (add_ln38_52_reg_6293 + add_ln38_60_fu_4349_p2);
+
+assign add_ln38_62_fu_4360_p2 = (add_ln38_45_fu_4326_p2 + add_ln38_61_fu_4355_p2);
+
+assign add_ln38_64_fu_3791_p2 = (tmp_cast_fu_3657_p3 + trunc_ln38_1_fu_3787_p1);
+
+assign add_ln38_6_fu_4093_p2 = (add_ln38_2_fu_4073_p2 + add_ln38_5_fu_4087_p2);
+
+assign add_ln38_7_fu_4099_p2 = (mul_ln38_8_reg_5938 + mul_ln38_7_reg_5933);
+
+assign add_ln38_8_fu_4103_p2 = (mul_ln38_10_reg_5948 + mul_ln38_9_reg_5943);
+
+assign add_ln38_9_fu_4107_p2 = (add_ln38_7_fu_4099_p2 + add_ln38_8_fu_4103_p2);
+
+assign add_ln38_fu_4064_p2 = (mul_ln38_reg_5898 + out_loc_q0);
+
+assign add_ln42_fu_4379_p2 = (phi_ln42_reg_3351 + 13'd1);
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd8];
+
+assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd16];
+
+assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd18];
+
+assign ap_CS_fsm_pp3_stage0 = ap_CS_fsm[32'd20];
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state12 = ap_CS_fsm[32'd9];
+
+assign ap_CS_fsm_state18 = ap_CS_fsm[32'd15];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state22 = ap_CS_fsm[32'd17];
+
+assign ap_CS_fsm_state28 = ap_CS_fsm[32'd19];
+
+assign ap_CS_fsm_state36 = ap_CS_fsm[32'd25];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = ((in1_mem_RVALID == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = ((in1_mem_RVALID == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp1_stage0_11001 = ((in2_mem_RVALID == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp1_stage0_subdone = ((in2_mem_RVALID == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+assign ap_block_pp2_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp2_stage0_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp2_stage0_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp3_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp3_stage0_01001 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp3_stage0_11001 = ((1'b1 == ap_block_state31_io) & (ap_enable_reg_pp3_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp3_stage0_subdone = ((1'b1 == ap_block_state31_io) & (ap_enable_reg_pp3_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state10_pp0_stage0_iter1 = (in1_mem_RVALID == 1'b0);
+end
+
+assign ap_block_state11_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state20_pp1_stage0_iter1 = (in2_mem_RVALID == 1'b0);
+end
+
+assign ap_block_state21_pp1_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state23_pp2_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state24_pp2_stage0_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state25_pp2_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state26_pp2_stage0_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state27_pp2_stage0_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state29_pp3_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state30_pp3_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state31_io = ((out_mem_WREADY == 1'b0) & (icmp_ln42_reg_6313_pp3_iter1_reg == 1'd0));
+end
+
+assign ap_block_state31_pp3_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state9_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
+
+assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);
+
+assign ap_enable_pp3 = (ap_idle_pp3 ^ 1'b1);
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign empty_7_fu_3411_p1 = in_reg_4401;
+
+assign empty_8_fu_3392_p1 = in3_reg_4406;
+
+assign empty_fu_3402_p1 = out5_reg_4396;
+
+assign i_fu_3626_p2 = (31'd1 + ap_phi_mux_i_0_phi_fu_3333_p4);
+
+assign icmp_ln27_fu_3420_p2 = ((phi_ln27_reg_3296 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln28_fu_3513_p2 = ((phi_ln28_reg_3307 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln31_fu_3615_p2 = ((indvar_flatten_reg_3318 == mul_ln31_reg_4601) ? 1'b1 : 1'b0);
+
+assign icmp_ln33_fu_3632_p2 = ((j_0_reg_3340 == dim_read_reg_4390) ? 1'b1 : 1'b0);
+
+assign icmp_ln42_fu_4373_p2 = ((phi_ln42_reg_3351 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign in1_mem_ARADDR = empty_8_fu_3392_p1;
+
+assign j_fu_3802_p2 = ($signed(32'd1) + $signed(select_ln31_fu_3637_p3));
+
+assign mul_ln31_fu_3609_p0 = zext_ln31_fu_3606_p1;
+
+assign mul_ln31_fu_3609_p1 = zext_ln31_fu_3606_p1;
+
+assign mul_ln31_fu_3609_p2 = (mul_ln31_fu_3609_p0 * mul_ln31_fu_3609_p1);
+
+assign mul_ln38_10_fu_3848_p2 = ($signed(in2_loc_10_load_reg_5593) * $signed(in1_loc_10_load_reg_5273));
+
+assign mul_ln38_11_fu_3852_p2 = ($signed(in2_loc_11_load_reg_5598) * $signed(in1_loc_11_load_reg_5278));
+
+assign mul_ln38_12_fu_3856_p2 = ($signed(in2_loc_12_load_reg_5603) * $signed(in1_loc_12_load_reg_5283));
+
+assign mul_ln38_13_fu_3860_p2 = ($signed(in2_loc_13_load_reg_5608) * $signed(in1_loc_13_load_reg_5288));
+
+assign mul_ln38_14_fu_3864_p2 = ($signed(in2_loc_14_load_reg_5613) * $signed(in1_loc_14_load_reg_5293));
+
+assign mul_ln38_15_fu_3868_p2 = ($signed(in2_loc_15_load_reg_5618) * $signed(in1_loc_15_load_reg_5298));
+
+assign mul_ln38_16_fu_3872_p2 = ($signed(in2_loc_16_load_reg_5623) * $signed(in1_loc_16_load_reg_5303));
+
+assign mul_ln38_17_fu_3876_p2 = ($signed(in2_loc_17_load_reg_5628) * $signed(in1_loc_17_load_reg_5308));
+
+assign mul_ln38_18_fu_3880_p2 = ($signed(in2_loc_18_load_reg_5633) * $signed(in1_loc_18_load_reg_5313));
+
+assign mul_ln38_19_fu_3884_p2 = ($signed(in2_loc_19_load_reg_5638) * $signed(in1_loc_19_load_reg_5318));
+
+assign mul_ln38_1_fu_3812_p2 = ($signed(in2_loc_1_load_reg_5548) * $signed(in1_loc_1_load_reg_5228));
+
+assign mul_ln38_20_fu_3888_p2 = ($signed(in2_loc_20_load_reg_5643) * $signed(in1_loc_20_load_reg_5323));
+
+assign mul_ln38_21_fu_3892_p2 = ($signed(in2_loc_21_load_reg_5648) * $signed(in1_loc_21_load_reg_5328));
+
+assign mul_ln38_22_fu_3896_p2 = ($signed(in2_loc_22_load_reg_5653) * $signed(in1_loc_22_load_reg_5333));
+
+assign mul_ln38_23_fu_3900_p2 = ($signed(in2_loc_23_load_reg_5658) * $signed(in1_loc_23_load_reg_5338));
+
+assign mul_ln38_24_fu_3904_p2 = ($signed(in2_loc_24_load_reg_5663) * $signed(in1_loc_24_load_reg_5343));
+
+assign mul_ln38_25_fu_3908_p2 = ($signed(in2_loc_25_load_reg_5668) * $signed(in1_loc_25_load_reg_5348));
+
+assign mul_ln38_26_fu_3912_p2 = ($signed(in2_loc_26_load_reg_5673) * $signed(in1_loc_26_load_reg_5353));
+
+assign mul_ln38_27_fu_3916_p2 = ($signed(in2_loc_27_load_reg_5678) * $signed(in1_loc_27_load_reg_5358));
+
+assign mul_ln38_28_fu_3920_p2 = ($signed(in2_loc_28_load_reg_5683) * $signed(in1_loc_28_load_reg_5363));
+
+assign mul_ln38_29_fu_3924_p2 = ($signed(in2_loc_29_load_reg_5688) * $signed(in1_loc_29_load_reg_5368));
+
+assign mul_ln38_2_fu_3816_p2 = ($signed(in2_loc_2_load_reg_5553) * $signed(in1_loc_2_load_reg_5233));
+
+assign mul_ln38_30_fu_3928_p2 = ($signed(in2_loc_30_load_reg_5693) * $signed(in1_loc_30_load_reg_5373));
+
+assign mul_ln38_31_fu_3932_p2 = ($signed(in2_loc_31_load_reg_5698) * $signed(in1_loc_31_load_reg_5378));
+
+assign mul_ln38_32_fu_3936_p2 = ($signed(in2_loc_32_load_reg_5703) * $signed(in1_loc_32_load_reg_5383));
+
+assign mul_ln38_33_fu_3940_p2 = ($signed(in2_loc_33_load_reg_5708) * $signed(in1_loc_33_load_reg_5388));
+
+assign mul_ln38_34_fu_3944_p2 = ($signed(in2_loc_34_load_reg_5713) * $signed(in1_loc_34_load_reg_5393));
+
+assign mul_ln38_35_fu_3948_p2 = ($signed(in2_loc_35_load_reg_5718) * $signed(in1_loc_35_load_reg_5398));
+
+assign mul_ln38_36_fu_3952_p2 = ($signed(in2_loc_36_load_reg_5723) * $signed(in1_loc_36_load_reg_5403));
+
+assign mul_ln38_37_fu_3956_p2 = ($signed(in2_loc_37_load_reg_5728) * $signed(in1_loc_37_load_reg_5408));
+
+assign mul_ln38_38_fu_3960_p2 = ($signed(in2_loc_38_load_reg_5733) * $signed(in1_loc_38_load_reg_5413));
+
+assign mul_ln38_39_fu_3964_p2 = ($signed(in2_loc_39_load_reg_5738) * $signed(in1_loc_39_load_reg_5418));
+
+assign mul_ln38_3_fu_3820_p2 = ($signed(in2_loc_3_load_reg_5558) * $signed(in1_loc_3_load_reg_5238));
+
+assign mul_ln38_40_fu_3968_p2 = ($signed(in2_loc_40_load_reg_5743) * $signed(in1_loc_40_load_reg_5423));
+
+assign mul_ln38_41_fu_4036_p2 = ($signed(in2_loc_41_load_reg_6103) * $signed(in1_loc_41_load_reg_5863));
+
+assign mul_ln38_42_fu_4040_p2 = ($signed(in2_loc_42_load_reg_6108) * $signed(in1_loc_42_load_reg_5868));
+
+assign mul_ln38_43_fu_3972_p2 = ($signed(in2_loc_43_load_reg_5758) * $signed(in1_loc_43_load_reg_5438));
+
+assign mul_ln38_44_fu_3976_p2 = ($signed(in2_loc_44_load_reg_5763) * $signed(in1_loc_44_load_reg_5443));
+
+assign mul_ln38_45_fu_4044_p2 = ($signed(in2_loc_45_load_reg_6123) * $signed(in1_loc_45_load_reg_5873));
+
+assign mul_ln38_46_fu_4048_p2 = ($signed(in2_loc_46_load_reg_6128) * $signed(in1_loc_46_load_reg_5878));
+
+assign mul_ln38_47_fu_3980_p2 = ($signed(in2_loc_47_load_reg_5778) * $signed(in1_loc_47_load_reg_5458));
+
+assign mul_ln38_48_fu_3984_p2 = ($signed(in2_loc_48_load_reg_5783) * $signed(in1_loc_48_load_reg_5463));
+
+assign mul_ln38_49_fu_3988_p2 = ($signed(in2_loc_49_load_reg_5788) * $signed(in1_loc_49_load_reg_5468));
+
+assign mul_ln38_4_fu_3824_p2 = ($signed(in2_loc_4_load_reg_5563) * $signed(in1_loc_4_load_reg_5243));
+
+assign mul_ln38_50_fu_3992_p2 = ($signed(in2_loc_50_load_reg_5793) * $signed(in1_loc_50_load_reg_5473));
+
+assign mul_ln38_51_fu_3996_p2 = ($signed(in2_loc_51_load_reg_5798) * $signed(in1_loc_51_load_reg_5478));
+
+assign mul_ln38_52_fu_4000_p2 = ($signed(in2_loc_52_load_reg_5803) * $signed(in1_loc_52_load_reg_5483));
+
+assign mul_ln38_53_fu_4004_p2 = ($signed(in2_loc_53_load_reg_5808) * $signed(in1_loc_53_load_reg_5488));
+
+assign mul_ln38_54_fu_4008_p2 = ($signed(in2_loc_54_load_reg_5813) * $signed(in1_loc_54_load_reg_5493));
+
+assign mul_ln38_55_fu_4012_p2 = ($signed(in2_loc_55_load_reg_5818) * $signed(in1_loc_55_load_reg_5498));
+
+assign mul_ln38_56_fu_4016_p2 = ($signed(in2_loc_56_load_reg_5823) * $signed(in1_loc_56_load_reg_5503));
+
+assign mul_ln38_57_fu_4052_p2 = ($signed(in2_loc_57_load_reg_6183) * $signed(in1_loc_57_load_reg_5883));
+
+assign mul_ln38_58_fu_4056_p2 = ($signed(in2_loc_58_load_reg_6188) * $signed(in1_loc_58_load_reg_5888));
+
+assign mul_ln38_59_fu_4020_p2 = ($signed(in2_loc_59_load_reg_5838) * $signed(in1_loc_59_load_reg_5518));
+
+assign mul_ln38_5_fu_3828_p2 = ($signed(in2_loc_5_load_reg_5568) * $signed(in1_loc_5_load_reg_5248));
+
+assign mul_ln38_60_fu_4024_p2 = ($signed(in2_loc_60_load_reg_5843) * $signed(in1_loc_60_load_reg_5523));
+
+assign mul_ln38_61_fu_4060_p2 = ($signed(in2_loc_61_load_reg_6203) * $signed(in1_loc_61_load_reg_5893));
+
+assign mul_ln38_62_fu_4028_p2 = ($signed(in2_loc_62_load_reg_5853) * $signed(in1_loc_62_load_reg_5533));
+
+assign mul_ln38_63_fu_4032_p2 = ($signed(in2_loc_63_load_reg_5858) * $signed(in1_loc_63_load_reg_5538));
+
+assign mul_ln38_6_fu_3832_p2 = ($signed(in2_loc_6_load_reg_5573) * $signed(in1_loc_6_load_reg_5253));
+
+assign mul_ln38_7_fu_3836_p2 = ($signed(in2_loc_7_load_reg_5578) * $signed(in1_loc_7_load_reg_5258));
+
+assign mul_ln38_8_fu_3840_p2 = ($signed(in2_loc_8_load_reg_5583) * $signed(in1_loc_8_load_reg_5263));
+
+assign mul_ln38_9_fu_3844_p2 = ($signed(in2_loc_9_load_reg_5588) * $signed(in1_loc_9_load_reg_5268));
+
+assign mul_ln38_fu_3808_p2 = ($signed(in2_loc_0_load_reg_5543) * $signed(in1_loc_0_load_reg_5223));
+
+assign out_loc_d1 = (add_ln38_30_fu_4296_p2 + add_ln38_62_fu_4360_p2);
+
+assign select_ln31_1_fu_3645_p3 = ((icmp_ln33_fu_3632_p2[0:0] === 1'b1) ? i_fu_3626_p2 : ap_phi_mux_i_0_phi_fu_3333_p4);
+
+assign select_ln31_fu_3637_p3 = ((icmp_ln33_fu_3632_p2[0:0] === 1'b1) ? 32'd0 : j_0_reg_3340);
+
+assign sext_ln38_fu_3726_p1 = select_ln31_fu_3637_p3;
+
+assign tmp_cast_fu_3657_p3 = {{trunc_ln38_fu_3653_p1}, {6'd0}};
+
+assign trunc_ln27_fu_3442_p1 = phi_ln27_reg_3296[5:0];
+
+assign trunc_ln28_fu_3525_p1 = phi_ln28_reg_3307[5:0];
+
+assign trunc_ln38_1_fu_3787_p1 = select_ln31_fu_3637_p3[13:0];
+
+assign trunc_ln38_fu_3653_p1 = select_ln31_1_fu_3645_p3[7:0];
+
+assign zext_ln27_fu_3446_p1 = lshr_ln_reg_4438_pp0_iter1_reg;
+
+assign zext_ln28_fu_3539_p1 = trunc_ln28_reg_4524_pp1_iter1_reg;
+
+assign zext_ln31_1_fu_3665_p1 = select_ln31_1_fu_3645_p3;
+
+assign zext_ln31_fu_3606_p1 = dim_read_reg_4390;
+
+assign zext_ln38_fu_3797_p1 = add_ln38_64_fu_3791_p2;
+
+assign zext_ln42_fu_4385_p1 = phi_ln42_reg_3351;
+
+always @ (posedge ap_clk) begin
+    out_mem_addr_reg_4417[31:30] <= 2'b00;
+    in2_mem_addr_reg_4423[31:30] <= 2'b00;
+    zext_ln31_1_reg_4620[63:31] <= 33'b000000000000000000000000000000000;
+end
+
+endmodule //mmult
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in1_loc_0.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in1_loc_0.v
new file mode 100755
index 0000000..7a7e881
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in1_loc_0.v
@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_0_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 6;
+parameter MEM_SIZE = 64;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_0(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd64;
+parameter AddressWidth = 32'd6;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_in1_loc_0_ram mmult_in1_loc_0_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in1_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in1_mem_m_axi.v
new file mode 100755
index 0000000..81f7248
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in1_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in1_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in1_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in1_mem_m_axi_write
+mmult_in1_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in1_mem_m_axi_read
+mmult_in1_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in1_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in1_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in1_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in1_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in1_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in2_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in2_mem_m_axi.v
new file mode 100755
index 0000000..a2eab07
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_in2_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in2_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in2_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in2_mem_m_axi_write
+mmult_in2_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in2_mem_m_axi_read
+mmult_in2_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in2_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in2_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in2_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in2_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in2_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_out_loc.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_out_loc.v
new file mode 100755
index 0000000..9acfd8e
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_out_loc.v
@@ -0,0 +1,83 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_out_loc_ram (addr0, ce0, q0, addr1, ce1, d1, we1,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+output reg[DWIDTH-1:0] q0;
+input[AWIDTH-1:0] addr1;
+input ce1;
+input[DWIDTH-1:0] d1;
+input we1;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        q0 <= ram[addr0];
+    end
+end
+
+
+always @(posedge clk)  
+begin 
+    if (ce1) begin
+        if (we1) 
+            ram[addr1] <= d1; 
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_out_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    q0,
+    address1,
+    ce1,
+    we1,
+    d1);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+output[DataWidth - 1:0] q0;
+input[AddressWidth - 1:0] address1;
+input ce1;
+input we1;
+input[DataWidth - 1:0] d1;
+
+
+
+mmult_out_loc_ram mmult_out_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .q0( q0 ),
+    .addr1( address1 ),
+    .ce1( ce1 ),
+    .we1( we1 ),
+    .d1( d1 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_out_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_out_mem_m_axi.v
new file mode 100755
index 0000000..cc472db
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_out_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_out_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_out_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_out_mem_m_axi_write
+mmult_out_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_out_mem_m_axi_read
+mmult_out_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_out_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_out_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_out_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_out_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_out_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_params_s_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_params_s_axi.v
new file mode 100755
index 0000000..d470352
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/verilog/mmult_params_s_axi.v
@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult.vhd
new file mode 100755
index 0000000..fcade3c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult.vhd
@@ -0,0 +1,9452 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+-- Version: 2020.1
+-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult is
+generic (
+    C_M_AXI_IN1_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_S_AXI_PARAMS_ADDR_WIDTH : INTEGER := 6;
+    C_S_AXI_PARAMS_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_IN2_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_OUT_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_CACHE_VALUE : INTEGER := 3 );
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    m_axi_in1_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in1_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_WREADY : IN STD_LOGIC;
+    m_axi_in1_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in1_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in1_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in1_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RVALID : IN STD_LOGIC;
+    m_axi_in1_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_RLAST : IN STD_LOGIC;
+    m_axi_in1_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BVALID : IN STD_LOGIC;
+    m_axi_in1_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in2_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_WREADY : IN STD_LOGIC;
+    m_axi_in2_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in2_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in2_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in2_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RVALID : IN STD_LOGIC;
+    m_axi_in2_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_RLAST : IN STD_LOGIC;
+    m_axi_in2_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BVALID : IN STD_LOGIC;
+    m_axi_in2_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_out_mem_AWREADY : IN STD_LOGIC;
+    m_axi_out_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_WVALID : OUT STD_LOGIC;
+    m_axi_out_mem_WREADY : IN STD_LOGIC;
+    m_axi_out_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_out_mem_WLAST : OUT STD_LOGIC;
+    m_axi_out_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_out_mem_ARREADY : IN STD_LOGIC;
+    m_axi_out_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RVALID : IN STD_LOGIC;
+    m_axi_out_mem_RREADY : OUT STD_LOGIC;
+    m_axi_out_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_RLAST : IN STD_LOGIC;
+    m_axi_out_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BVALID : IN STD_LOGIC;
+    m_axi_out_mem_BREADY : OUT STD_LOGIC;
+    m_axi_out_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_BUSER_WIDTH-1 downto 0);
+    s_axi_params_AWVALID : IN STD_LOGIC;
+    s_axi_params_AWREADY : OUT STD_LOGIC;
+    s_axi_params_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_WVALID : IN STD_LOGIC;
+    s_axi_params_WREADY : OUT STD_LOGIC;
+    s_axi_params_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH/8-1 downto 0);
+    s_axi_params_ARVALID : IN STD_LOGIC;
+    s_axi_params_ARREADY : OUT STD_LOGIC;
+    s_axi_params_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_RVALID : OUT STD_LOGIC;
+    s_axi_params_RREADY : IN STD_LOGIC;
+    s_axi_params_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    s_axi_params_BVALID : OUT STD_LOGIC;
+    s_axi_params_BREADY : IN STD_LOGIC;
+    s_axi_params_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    interrupt : OUT STD_LOGIC );
+end;
+
+
+architecture behav of mmult is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.375000,HLS_SYN_LAT=16415,HLS_SYN_TPT=none,HLS_SYN_MEM=142,HLS_SYN_DSP=260,HLS_SYN_FF=9119,HLS_SYN_LUT=8264,HLS_VERSION=2020_1}";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000100";
+    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000001000";
+    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000010000";
+    constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000100000";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000001000000";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000010000000";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000100000000";
+    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000001000000000";
+    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000010000000000";
+    constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000100000000000";
+    constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000001000000000000";
+    constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000010000000000000";
+    constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000100000000000000";
+    constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (25 downto 0) := "00000000001000000000000000";
+    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (25 downto 0) := "00000000010000000000000000";
+    constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (25 downto 0) := "00000000100000000000000000";
+    constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (25 downto 0) := "00000001000000000000000000";
+    constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (25 downto 0) := "00000010000000000000000000";
+    constant ap_ST_fsm_pp3_stage0 : STD_LOGIC_VECTOR (25 downto 0) := "00000100000000000000000000";
+    constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (25 downto 0) := "00001000000000000000000000";
+    constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (25 downto 0) := "00010000000000000000000000";
+    constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (25 downto 0) := "00100000000000000000000000";
+    constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (25 downto 0) := "01000000000000000000000000";
+    constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (25 downto 0) := "10000000000000000000000000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
+    constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
+    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
+    constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
+    constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
+    constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
+    constant ap_const_lv32_1000 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000001000000000000";
+    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
+    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
+    constant ap_const_lv6_3E : STD_LOGIC_VECTOR (5 downto 0) := "111110";
+    constant ap_const_lv6_3D : STD_LOGIC_VECTOR (5 downto 0) := "111101";
+    constant ap_const_lv6_3C : STD_LOGIC_VECTOR (5 downto 0) := "111100";
+    constant ap_const_lv6_3B : STD_LOGIC_VECTOR (5 downto 0) := "111011";
+    constant ap_const_lv6_3A : STD_LOGIC_VECTOR (5 downto 0) := "111010";
+    constant ap_const_lv6_39 : STD_LOGIC_VECTOR (5 downto 0) := "111001";
+    constant ap_const_lv6_38 : STD_LOGIC_VECTOR (5 downto 0) := "111000";
+    constant ap_const_lv6_37 : STD_LOGIC_VECTOR (5 downto 0) := "110111";
+    constant ap_const_lv6_36 : STD_LOGIC_VECTOR (5 downto 0) := "110110";
+    constant ap_const_lv6_35 : STD_LOGIC_VECTOR (5 downto 0) := "110101";
+    constant ap_const_lv6_34 : STD_LOGIC_VECTOR (5 downto 0) := "110100";
+    constant ap_const_lv6_33 : STD_LOGIC_VECTOR (5 downto 0) := "110011";
+    constant ap_const_lv6_32 : STD_LOGIC_VECTOR (5 downto 0) := "110010";
+    constant ap_const_lv6_31 : STD_LOGIC_VECTOR (5 downto 0) := "110001";
+    constant ap_const_lv6_30 : STD_LOGIC_VECTOR (5 downto 0) := "110000";
+    constant ap_const_lv6_2F : STD_LOGIC_VECTOR (5 downto 0) := "101111";
+    constant ap_const_lv6_2E : STD_LOGIC_VECTOR (5 downto 0) := "101110";
+    constant ap_const_lv6_2D : STD_LOGIC_VECTOR (5 downto 0) := "101101";
+    constant ap_const_lv6_2C : STD_LOGIC_VECTOR (5 downto 0) := "101100";
+    constant ap_const_lv6_2B : STD_LOGIC_VECTOR (5 downto 0) := "101011";
+    constant ap_const_lv6_2A : STD_LOGIC_VECTOR (5 downto 0) := "101010";
+    constant ap_const_lv6_29 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
+    constant ap_const_lv6_28 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
+    constant ap_const_lv6_27 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
+    constant ap_const_lv6_26 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
+    constant ap_const_lv6_25 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
+    constant ap_const_lv6_24 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
+    constant ap_const_lv6_23 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
+    constant ap_const_lv6_22 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
+    constant ap_const_lv6_21 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
+    constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
+    constant ap_const_lv6_1F : STD_LOGIC_VECTOR (5 downto 0) := "011111";
+    constant ap_const_lv6_1E : STD_LOGIC_VECTOR (5 downto 0) := "011110";
+    constant ap_const_lv6_1D : STD_LOGIC_VECTOR (5 downto 0) := "011101";
+    constant ap_const_lv6_1C : STD_LOGIC_VECTOR (5 downto 0) := "011100";
+    constant ap_const_lv6_1B : STD_LOGIC_VECTOR (5 downto 0) := "011011";
+    constant ap_const_lv6_1A : STD_LOGIC_VECTOR (5 downto 0) := "011010";
+    constant ap_const_lv6_19 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
+    constant ap_const_lv6_18 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
+    constant ap_const_lv6_17 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
+    constant ap_const_lv6_16 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
+    constant ap_const_lv6_15 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
+    constant ap_const_lv6_14 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
+    constant ap_const_lv6_13 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
+    constant ap_const_lv6_12 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
+    constant ap_const_lv6_11 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
+    constant ap_const_lv6_10 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
+    constant ap_const_lv6_F : STD_LOGIC_VECTOR (5 downto 0) := "001111";
+    constant ap_const_lv6_E : STD_LOGIC_VECTOR (5 downto 0) := "001110";
+    constant ap_const_lv6_D : STD_LOGIC_VECTOR (5 downto 0) := "001101";
+    constant ap_const_lv6_C : STD_LOGIC_VECTOR (5 downto 0) := "001100";
+    constant ap_const_lv6_B : STD_LOGIC_VECTOR (5 downto 0) := "001011";
+    constant ap_const_lv6_A : STD_LOGIC_VECTOR (5 downto 0) := "001010";
+    constant ap_const_lv6_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
+    constant ap_const_lv6_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
+    constant ap_const_lv6_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
+    constant ap_const_lv6_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
+    constant ap_const_lv6_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
+    constant ap_const_lv6_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
+    constant ap_const_lv6_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
+    constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
+    constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
+    constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
+    constant ap_const_lv6_3F : STD_LOGIC_VECTOR (5 downto 0) := "111111";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv13_1000 : STD_LOGIC_VECTOR (12 downto 0) := "1000000000000";
+    constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
+    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
+    constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
+    constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal ap_start : STD_LOGIC;
+    signal ap_done : STD_LOGIC;
+    signal ap_idle : STD_LOGIC;
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal ap_ready : STD_LOGIC;
+    signal in1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_r : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal in1_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal in2_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state12 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
+    signal in2_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
+    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp1_stage0 : BOOLEAN;
+    signal out_mem_blk_n_AW : STD_LOGIC;
+    signal ap_CS_fsm_state28 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state28 : signal is "none";
+    signal out_mem_blk_n_W : STD_LOGIC;
+    signal ap_enable_reg_pp3_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp3_stage0 : BOOLEAN;
+    signal icmp_ln42_reg_6313 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln42_reg_6313_pp3_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_B : STD_LOGIC;
+    signal ap_CS_fsm_state36 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state36 : signal is "none";
+    signal in1_mem_AWREADY : STD_LOGIC;
+    signal in1_mem_WREADY : STD_LOGIC;
+    signal in1_mem_ARVALID : STD_LOGIC;
+    signal in1_mem_ARREADY : STD_LOGIC;
+    signal in1_mem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RVALID : STD_LOGIC;
+    signal in1_mem_RREADY : STD_LOGIC;
+    signal in1_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RLAST : STD_LOGIC;
+    signal in1_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BVALID : STD_LOGIC;
+    signal in1_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_AWREADY : STD_LOGIC;
+    signal in2_mem_WREADY : STD_LOGIC;
+    signal in2_mem_ARVALID : STD_LOGIC;
+    signal in2_mem_ARREADY : STD_LOGIC;
+    signal in2_mem_RVALID : STD_LOGIC;
+    signal in2_mem_RREADY : STD_LOGIC;
+    signal in2_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_RLAST : STD_LOGIC;
+    signal in2_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BVALID : STD_LOGIC;
+    signal in2_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_AWVALID : STD_LOGIC;
+    signal out_mem_AWREADY : STD_LOGIC;
+    signal out_mem_WVALID : STD_LOGIC;
+    signal out_mem_WREADY : STD_LOGIC;
+    signal out_mem_ARREADY : STD_LOGIC;
+    signal out_mem_RVALID : STD_LOGIC;
+    signal out_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_RLAST : STD_LOGIC;
+    signal out_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BVALID : STD_LOGIC;
+    signal out_mem_BREADY : STD_LOGIC;
+    signal out_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal phi_ln27_reg_3296 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln28_reg_3307 : STD_LOGIC_VECTOR (12 downto 0);
+    signal indvar_flatten_reg_3318 : STD_LOGIC_VECTOR (63 downto 0);
+    signal i_0_reg_3329 : STD_LOGIC_VECTOR (30 downto 0);
+    signal j_0_reg_3340 : STD_LOGIC_VECTOR (31 downto 0);
+    signal phi_ln42_reg_3351 : STD_LOGIC_VECTOR (12 downto 0);
+    signal dim_read_reg_4390 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out5_reg_4396 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in_reg_4401 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in3_reg_4406 : STD_LOGIC_VECTOR (29 downto 0);
+    signal out_mem_addr_reg_4417 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
+    signal in2_mem_addr_reg_4423 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln27_fu_3420_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state9_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state11_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal add_ln27_fu_3426_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal lshr_ln_reg_4438 : STD_LOGIC_VECTOR (6 downto 0);
+    signal lshr_ln_reg_4438_pp0_iter1_reg : STD_LOGIC_VECTOR (6 downto 0);
+    signal trunc_ln27_fu_3442_p1 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln27_reg_4443 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln27_reg_4443_pp0_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_mem_addr_read_reg_4447 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln28_fu_3513_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state19_pp1_stage0_iter0 : BOOLEAN;
+    signal ap_block_state20_pp1_stage0_iter1 : BOOLEAN;
+    signal ap_block_state21_pp1_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp1_stage0_11001 : BOOLEAN;
+    signal add_ln28_fu_3519_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
+    signal trunc_ln28_fu_3525_p1 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln28_reg_4524 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln28_reg_4524_pp1_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln1_reg_4529 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln1_reg_4529_pp1_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_mem_addr_read_reg_4533 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln31_fu_3609_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal mul_ln31_reg_4601 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_CS_fsm_state22 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
+    signal icmp_ln31_fu_3615_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4606 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
+    signal ap_block_state23_pp2_stage0_iter0 : BOOLEAN;
+    signal ap_block_state24_pp2_stage0_iter1 : BOOLEAN;
+    signal ap_block_state25_pp2_stage0_iter2 : BOOLEAN;
+    signal ap_block_state26_pp2_stage0_iter3 : BOOLEAN;
+    signal ap_block_state27_pp2_stage0_iter4 : BOOLEAN;
+    signal ap_block_pp2_stage0_11001 : BOOLEAN;
+    signal icmp_ln31_reg_4606_pp2_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4606_pp2_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4606_pp2_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln31_fu_3620_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
+    signal select_ln31_1_fu_3645_p3 : STD_LOGIC_VECTOR (30 downto 0);
+    signal select_ln31_1_reg_4615 : STD_LOGIC_VECTOR (30 downto 0);
+    signal zext_ln31_1_fu_3665_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln31_1_reg_4620 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_fu_3726_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_reg_4916 : STD_LOGIC_VECTOR (63 downto 0);
+    signal out_loc_addr_reg_4927 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4927_pp2_iter1_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4927_pp2_iter2_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4927_pp2_iter3_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal j_fu_3802_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_0_load_reg_5223 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
+    signal in1_loc_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_1_load_reg_5228 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_2_load_reg_5233 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_3_load_reg_5238 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_4_load_reg_5243 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_5_load_reg_5248 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_6_load_reg_5253 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_7_load_reg_5258 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_8_load_reg_5263 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_9_load_reg_5268 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_10_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_10_load_reg_5273 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_11_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_11_load_reg_5278 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_12_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_12_load_reg_5283 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_13_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_13_load_reg_5288 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_14_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_14_load_reg_5293 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_15_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_15_load_reg_5298 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_16_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_16_load_reg_5303 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_17_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_17_load_reg_5308 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_18_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_18_load_reg_5313 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_19_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_19_load_reg_5318 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_20_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_20_load_reg_5323 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_21_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_21_load_reg_5328 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_22_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_22_load_reg_5333 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_23_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_23_load_reg_5338 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_24_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_24_load_reg_5343 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_25_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_25_load_reg_5348 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_26_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_26_load_reg_5353 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_27_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_27_load_reg_5358 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_28_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_28_load_reg_5363 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_29_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_29_load_reg_5368 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_30_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_30_load_reg_5373 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_31_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_31_load_reg_5378 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_32_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_32_load_reg_5383 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_33_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_33_load_reg_5388 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_34_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_34_load_reg_5393 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_35_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_35_load_reg_5398 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_36_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_36_load_reg_5403 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_37_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_37_load_reg_5408 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_38_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_38_load_reg_5413 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_39_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_39_load_reg_5418 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_40_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_40_load_reg_5423 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_43_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_43_load_reg_5438 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_44_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_44_load_reg_5443 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_47_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_47_load_reg_5458 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_48_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_48_load_reg_5463 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_49_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_49_load_reg_5468 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_50_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_50_load_reg_5473 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_51_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_51_load_reg_5478 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_52_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_52_load_reg_5483 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_53_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_53_load_reg_5488 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_54_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_54_load_reg_5493 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_55_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_55_load_reg_5498 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_56_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_56_load_reg_5503 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_59_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_59_load_reg_5518 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_60_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_60_load_reg_5523 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_62_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_62_load_reg_5533 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_63_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_63_load_reg_5538 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_0_load_reg_5543 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_1_load_reg_5548 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_2_load_reg_5553 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_3_load_reg_5558 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_4_load_reg_5563 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_5_load_reg_5568 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_6_load_reg_5573 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_7_load_reg_5578 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_8_load_reg_5583 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_9_load_reg_5588 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_10_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_10_load_reg_5593 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_11_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_11_load_reg_5598 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_12_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_12_load_reg_5603 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_13_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_13_load_reg_5608 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_14_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_14_load_reg_5613 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_15_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_15_load_reg_5618 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_16_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_16_load_reg_5623 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_17_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_17_load_reg_5628 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_18_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_18_load_reg_5633 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_19_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_19_load_reg_5638 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_20_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_20_load_reg_5643 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_21_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_21_load_reg_5648 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_22_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_22_load_reg_5653 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_23_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_23_load_reg_5658 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_24_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_24_load_reg_5663 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_25_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_25_load_reg_5668 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_26_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_26_load_reg_5673 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_27_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_27_load_reg_5678 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_28_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_28_load_reg_5683 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_29_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_29_load_reg_5688 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_30_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_30_load_reg_5693 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_31_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_31_load_reg_5698 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_32_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_32_load_reg_5703 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_33_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_33_load_reg_5708 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_34_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_34_load_reg_5713 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_35_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_35_load_reg_5718 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_36_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_36_load_reg_5723 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_37_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_37_load_reg_5728 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_38_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_38_load_reg_5733 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_39_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_39_load_reg_5738 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_40_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_40_load_reg_5743 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_43_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_43_load_reg_5758 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_44_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_44_load_reg_5763 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_47_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_47_load_reg_5778 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_48_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_48_load_reg_5783 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_49_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_49_load_reg_5788 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_50_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_50_load_reg_5793 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_51_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_51_load_reg_5798 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_52_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_52_load_reg_5803 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_53_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_53_load_reg_5808 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_54_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_54_load_reg_5813 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_55_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_55_load_reg_5818 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_56_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_56_load_reg_5823 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_59_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_59_load_reg_5838 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_60_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_60_load_reg_5843 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_62_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_62_load_reg_5853 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_63_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_63_load_reg_5858 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_41_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_41_load_reg_5863 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp2_iter2 : STD_LOGIC := '0';
+    signal in1_loc_42_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_42_load_reg_5868 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_45_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_45_load_reg_5873 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_46_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_46_load_reg_5878 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_57_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_57_load_reg_5883 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_58_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_58_load_reg_5888 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_61_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_61_load_reg_5893 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_fu_3808_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_reg_5898 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_fu_3812_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_reg_5903 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_fu_3816_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_reg_5908 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_fu_3820_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_reg_5913 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_fu_3824_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_reg_5918 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_fu_3828_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_reg_5923 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_fu_3832_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_reg_5928 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_fu_3836_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_reg_5933 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_fu_3840_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_reg_5938 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_fu_3844_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_reg_5943 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_fu_3848_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_reg_5948 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_fu_3852_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_reg_5953 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_fu_3856_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_reg_5958 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_fu_3860_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_reg_5963 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_fu_3864_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_reg_5968 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_fu_3868_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_reg_5973 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_fu_3872_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_reg_5978 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_fu_3876_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_reg_5983 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_fu_3880_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_reg_5988 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_fu_3884_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_reg_5993 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_fu_3888_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_reg_5998 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_fu_3892_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_reg_6003 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_fu_3896_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_reg_6008 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_fu_3900_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_reg_6013 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_fu_3904_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_reg_6018 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_fu_3908_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_reg_6023 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_fu_3912_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_reg_6028 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_fu_3916_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_reg_6033 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_fu_3920_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_reg_6038 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_fu_3924_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_reg_6043 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_fu_3928_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_reg_6048 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_fu_3932_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_reg_6053 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_fu_3936_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_reg_6058 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_fu_3940_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_reg_6063 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_fu_3944_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_reg_6068 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_fu_3948_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_reg_6073 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_fu_3952_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_reg_6078 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_fu_3956_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_reg_6083 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_fu_3960_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_reg_6088 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_fu_3964_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_reg_6093 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_fu_3968_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_reg_6098 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_41_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_41_load_reg_6103 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_42_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_42_load_reg_6108 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_fu_3972_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_reg_6113 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_fu_3976_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_reg_6118 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_45_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_45_load_reg_6123 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_46_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_46_load_reg_6128 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_fu_3980_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_reg_6133 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_fu_3984_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_reg_6138 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_fu_3988_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_reg_6143 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_fu_3992_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_reg_6148 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_fu_3996_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_reg_6153 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_fu_4000_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_reg_6158 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_fu_4004_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_reg_6163 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_fu_4008_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_reg_6168 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_fu_4012_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_reg_6173 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_fu_4016_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_reg_6178 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_57_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_57_load_reg_6183 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_58_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_58_load_reg_6188 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_fu_4020_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_reg_6193 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_fu_4024_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_reg_6198 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_61_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_61_load_reg_6203 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_fu_4028_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_reg_6208 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_fu_4032_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_reg_6213 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_fu_4036_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_reg_6218 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_fu_4040_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_reg_6223 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_fu_4044_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_reg_6228 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_fu_4048_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_reg_6233 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_fu_4052_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_reg_6238 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_fu_4056_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_reg_6243 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_fu_4060_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_reg_6248 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_6_fu_4093_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_6_reg_6253 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_9_fu_4107_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_9_reg_6258 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_12_fu_4121_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_12_reg_6263 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_fu_4155_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_reg_6268 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_28_fu_4189_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_28_reg_6273 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_fu_4223_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_reg_6278 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_38_fu_4229_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_38_reg_6283 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_41_fu_4233_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_41_reg_6288 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_fu_4265_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_reg_6293 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_53_fu_4271_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_53_reg_6298 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_56_fu_4275_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_56_reg_6303 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_57_fu_4279_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_57_reg_6308 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln42_fu_4373_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp3_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp3_stage0 : signal is "none";
+    signal ap_block_state29_pp3_stage0_iter0 : BOOLEAN;
+    signal ap_block_state30_pp3_stage0_iter1 : BOOLEAN;
+    signal ap_block_state31_pp3_stage0_iter2 : BOOLEAN;
+    signal ap_block_state31_io : BOOLEAN;
+    signal ap_block_pp3_stage0_11001 : BOOLEAN;
+    signal add_ln42_fu_4379_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp3_iter0 : STD_LOGIC := '0';
+    signal out_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_loc_load_reg_6327 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp3_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state9 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_CS_fsm_state18 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
+    signal ap_block_pp1_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp1_exit_iter0_state19 : STD_LOGIC;
+    signal ap_enable_reg_pp1_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp2_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp2_exit_iter0_state23 : STD_LOGIC;
+    signal ap_enable_reg_pp2_iter3 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp2_iter4 : STD_LOGIC := '0';
+    signal ap_block_pp3_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp3_exit_iter0_state29 : STD_LOGIC;
+    signal in1_loc_0_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_0_ce0 : STD_LOGIC;
+    signal in1_loc_0_we0 : STD_LOGIC;
+    signal in1_loc_1_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_1_ce0 : STD_LOGIC;
+    signal in1_loc_1_we0 : STD_LOGIC;
+    signal in1_loc_2_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_2_ce0 : STD_LOGIC;
+    signal in1_loc_2_we0 : STD_LOGIC;
+    signal in1_loc_3_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_3_ce0 : STD_LOGIC;
+    signal in1_loc_3_we0 : STD_LOGIC;
+    signal in1_loc_4_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_4_ce0 : STD_LOGIC;
+    signal in1_loc_4_we0 : STD_LOGIC;
+    signal in1_loc_5_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_5_ce0 : STD_LOGIC;
+    signal in1_loc_5_we0 : STD_LOGIC;
+    signal in1_loc_6_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_6_ce0 : STD_LOGIC;
+    signal in1_loc_6_we0 : STD_LOGIC;
+    signal in1_loc_7_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_7_ce0 : STD_LOGIC;
+    signal in1_loc_7_we0 : STD_LOGIC;
+    signal in1_loc_8_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_8_ce0 : STD_LOGIC;
+    signal in1_loc_8_we0 : STD_LOGIC;
+    signal in1_loc_9_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_9_ce0 : STD_LOGIC;
+    signal in1_loc_9_we0 : STD_LOGIC;
+    signal in1_loc_10_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_10_ce0 : STD_LOGIC;
+    signal in1_loc_10_we0 : STD_LOGIC;
+    signal in1_loc_11_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_11_ce0 : STD_LOGIC;
+    signal in1_loc_11_we0 : STD_LOGIC;
+    signal in1_loc_12_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_12_ce0 : STD_LOGIC;
+    signal in1_loc_12_we0 : STD_LOGIC;
+    signal in1_loc_13_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_13_ce0 : STD_LOGIC;
+    signal in1_loc_13_we0 : STD_LOGIC;
+    signal in1_loc_14_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_14_ce0 : STD_LOGIC;
+    signal in1_loc_14_we0 : STD_LOGIC;
+    signal in1_loc_15_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_15_ce0 : STD_LOGIC;
+    signal in1_loc_15_we0 : STD_LOGIC;
+    signal in1_loc_16_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_16_ce0 : STD_LOGIC;
+    signal in1_loc_16_we0 : STD_LOGIC;
+    signal in1_loc_17_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_17_ce0 : STD_LOGIC;
+    signal in1_loc_17_we0 : STD_LOGIC;
+    signal in1_loc_18_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_18_ce0 : STD_LOGIC;
+    signal in1_loc_18_we0 : STD_LOGIC;
+    signal in1_loc_19_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_19_ce0 : STD_LOGIC;
+    signal in1_loc_19_we0 : STD_LOGIC;
+    signal in1_loc_20_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_20_ce0 : STD_LOGIC;
+    signal in1_loc_20_we0 : STD_LOGIC;
+    signal in1_loc_21_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_21_ce0 : STD_LOGIC;
+    signal in1_loc_21_we0 : STD_LOGIC;
+    signal in1_loc_22_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_22_ce0 : STD_LOGIC;
+    signal in1_loc_22_we0 : STD_LOGIC;
+    signal in1_loc_23_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_23_ce0 : STD_LOGIC;
+    signal in1_loc_23_we0 : STD_LOGIC;
+    signal in1_loc_24_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_24_ce0 : STD_LOGIC;
+    signal in1_loc_24_we0 : STD_LOGIC;
+    signal in1_loc_25_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_25_ce0 : STD_LOGIC;
+    signal in1_loc_25_we0 : STD_LOGIC;
+    signal in1_loc_26_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_26_ce0 : STD_LOGIC;
+    signal in1_loc_26_we0 : STD_LOGIC;
+    signal in1_loc_27_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_27_ce0 : STD_LOGIC;
+    signal in1_loc_27_we0 : STD_LOGIC;
+    signal in1_loc_28_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_28_ce0 : STD_LOGIC;
+    signal in1_loc_28_we0 : STD_LOGIC;
+    signal in1_loc_29_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_29_ce0 : STD_LOGIC;
+    signal in1_loc_29_we0 : STD_LOGIC;
+    signal in1_loc_30_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_30_ce0 : STD_LOGIC;
+    signal in1_loc_30_we0 : STD_LOGIC;
+    signal in1_loc_31_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_31_ce0 : STD_LOGIC;
+    signal in1_loc_31_we0 : STD_LOGIC;
+    signal in1_loc_32_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_32_ce0 : STD_LOGIC;
+    signal in1_loc_32_we0 : STD_LOGIC;
+    signal in1_loc_33_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_33_ce0 : STD_LOGIC;
+    signal in1_loc_33_we0 : STD_LOGIC;
+    signal in1_loc_34_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_34_ce0 : STD_LOGIC;
+    signal in1_loc_34_we0 : STD_LOGIC;
+    signal in1_loc_35_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_35_ce0 : STD_LOGIC;
+    signal in1_loc_35_we0 : STD_LOGIC;
+    signal in1_loc_36_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_36_ce0 : STD_LOGIC;
+    signal in1_loc_36_we0 : STD_LOGIC;
+    signal in1_loc_37_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_37_ce0 : STD_LOGIC;
+    signal in1_loc_37_we0 : STD_LOGIC;
+    signal in1_loc_38_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_38_ce0 : STD_LOGIC;
+    signal in1_loc_38_we0 : STD_LOGIC;
+    signal in1_loc_39_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_39_ce0 : STD_LOGIC;
+    signal in1_loc_39_we0 : STD_LOGIC;
+    signal in1_loc_40_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_40_ce0 : STD_LOGIC;
+    signal in1_loc_40_we0 : STD_LOGIC;
+    signal in1_loc_41_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_41_ce0 : STD_LOGIC;
+    signal in1_loc_41_we0 : STD_LOGIC;
+    signal in1_loc_42_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_42_ce0 : STD_LOGIC;
+    signal in1_loc_42_we0 : STD_LOGIC;
+    signal in1_loc_43_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_43_ce0 : STD_LOGIC;
+    signal in1_loc_43_we0 : STD_LOGIC;
+    signal in1_loc_44_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_44_ce0 : STD_LOGIC;
+    signal in1_loc_44_we0 : STD_LOGIC;
+    signal in1_loc_45_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_45_ce0 : STD_LOGIC;
+    signal in1_loc_45_we0 : STD_LOGIC;
+    signal in1_loc_46_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_46_ce0 : STD_LOGIC;
+    signal in1_loc_46_we0 : STD_LOGIC;
+    signal in1_loc_47_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_47_ce0 : STD_LOGIC;
+    signal in1_loc_47_we0 : STD_LOGIC;
+    signal in1_loc_48_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_48_ce0 : STD_LOGIC;
+    signal in1_loc_48_we0 : STD_LOGIC;
+    signal in1_loc_49_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_49_ce0 : STD_LOGIC;
+    signal in1_loc_49_we0 : STD_LOGIC;
+    signal in1_loc_50_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_50_ce0 : STD_LOGIC;
+    signal in1_loc_50_we0 : STD_LOGIC;
+    signal in1_loc_51_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_51_ce0 : STD_LOGIC;
+    signal in1_loc_51_we0 : STD_LOGIC;
+    signal in1_loc_52_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_52_ce0 : STD_LOGIC;
+    signal in1_loc_52_we0 : STD_LOGIC;
+    signal in1_loc_53_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_53_ce0 : STD_LOGIC;
+    signal in1_loc_53_we0 : STD_LOGIC;
+    signal in1_loc_54_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_54_ce0 : STD_LOGIC;
+    signal in1_loc_54_we0 : STD_LOGIC;
+    signal in1_loc_55_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_55_ce0 : STD_LOGIC;
+    signal in1_loc_55_we0 : STD_LOGIC;
+    signal in1_loc_56_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_56_ce0 : STD_LOGIC;
+    signal in1_loc_56_we0 : STD_LOGIC;
+    signal in1_loc_57_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_57_ce0 : STD_LOGIC;
+    signal in1_loc_57_we0 : STD_LOGIC;
+    signal in1_loc_58_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_58_ce0 : STD_LOGIC;
+    signal in1_loc_58_we0 : STD_LOGIC;
+    signal in1_loc_59_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_59_ce0 : STD_LOGIC;
+    signal in1_loc_59_we0 : STD_LOGIC;
+    signal in1_loc_60_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_60_ce0 : STD_LOGIC;
+    signal in1_loc_60_we0 : STD_LOGIC;
+    signal in1_loc_61_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_61_ce0 : STD_LOGIC;
+    signal in1_loc_61_we0 : STD_LOGIC;
+    signal in1_loc_62_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_62_ce0 : STD_LOGIC;
+    signal in1_loc_62_we0 : STD_LOGIC;
+    signal in1_loc_63_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_63_ce0 : STD_LOGIC;
+    signal in1_loc_63_we0 : STD_LOGIC;
+    signal in2_loc_0_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_0_ce0 : STD_LOGIC;
+    signal in2_loc_0_we0 : STD_LOGIC;
+    signal in2_loc_1_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_1_ce0 : STD_LOGIC;
+    signal in2_loc_1_we0 : STD_LOGIC;
+    signal in2_loc_2_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_2_ce0 : STD_LOGIC;
+    signal in2_loc_2_we0 : STD_LOGIC;
+    signal in2_loc_3_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_3_ce0 : STD_LOGIC;
+    signal in2_loc_3_we0 : STD_LOGIC;
+    signal in2_loc_4_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_4_ce0 : STD_LOGIC;
+    signal in2_loc_4_we0 : STD_LOGIC;
+    signal in2_loc_5_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_5_ce0 : STD_LOGIC;
+    signal in2_loc_5_we0 : STD_LOGIC;
+    signal in2_loc_6_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_6_ce0 : STD_LOGIC;
+    signal in2_loc_6_we0 : STD_LOGIC;
+    signal in2_loc_7_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_7_ce0 : STD_LOGIC;
+    signal in2_loc_7_we0 : STD_LOGIC;
+    signal in2_loc_8_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_8_ce0 : STD_LOGIC;
+    signal in2_loc_8_we0 : STD_LOGIC;
+    signal in2_loc_9_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_9_ce0 : STD_LOGIC;
+    signal in2_loc_9_we0 : STD_LOGIC;
+    signal in2_loc_10_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_10_ce0 : STD_LOGIC;
+    signal in2_loc_10_we0 : STD_LOGIC;
+    signal in2_loc_11_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_11_ce0 : STD_LOGIC;
+    signal in2_loc_11_we0 : STD_LOGIC;
+    signal in2_loc_12_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_12_ce0 : STD_LOGIC;
+    signal in2_loc_12_we0 : STD_LOGIC;
+    signal in2_loc_13_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_13_ce0 : STD_LOGIC;
+    signal in2_loc_13_we0 : STD_LOGIC;
+    signal in2_loc_14_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_14_ce0 : STD_LOGIC;
+    signal in2_loc_14_we0 : STD_LOGIC;
+    signal in2_loc_15_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_15_ce0 : STD_LOGIC;
+    signal in2_loc_15_we0 : STD_LOGIC;
+    signal in2_loc_16_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_16_ce0 : STD_LOGIC;
+    signal in2_loc_16_we0 : STD_LOGIC;
+    signal in2_loc_17_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_17_ce0 : STD_LOGIC;
+    signal in2_loc_17_we0 : STD_LOGIC;
+    signal in2_loc_18_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_18_ce0 : STD_LOGIC;
+    signal in2_loc_18_we0 : STD_LOGIC;
+    signal in2_loc_19_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_19_ce0 : STD_LOGIC;
+    signal in2_loc_19_we0 : STD_LOGIC;
+    signal in2_loc_20_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_20_ce0 : STD_LOGIC;
+    signal in2_loc_20_we0 : STD_LOGIC;
+    signal in2_loc_21_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_21_ce0 : STD_LOGIC;
+    signal in2_loc_21_we0 : STD_LOGIC;
+    signal in2_loc_22_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_22_ce0 : STD_LOGIC;
+    signal in2_loc_22_we0 : STD_LOGIC;
+    signal in2_loc_23_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_23_ce0 : STD_LOGIC;
+    signal in2_loc_23_we0 : STD_LOGIC;
+    signal in2_loc_24_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_24_ce0 : STD_LOGIC;
+    signal in2_loc_24_we0 : STD_LOGIC;
+    signal in2_loc_25_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_25_ce0 : STD_LOGIC;
+    signal in2_loc_25_we0 : STD_LOGIC;
+    signal in2_loc_26_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_26_ce0 : STD_LOGIC;
+    signal in2_loc_26_we0 : STD_LOGIC;
+    signal in2_loc_27_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_27_ce0 : STD_LOGIC;
+    signal in2_loc_27_we0 : STD_LOGIC;
+    signal in2_loc_28_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_28_ce0 : STD_LOGIC;
+    signal in2_loc_28_we0 : STD_LOGIC;
+    signal in2_loc_29_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_29_ce0 : STD_LOGIC;
+    signal in2_loc_29_we0 : STD_LOGIC;
+    signal in2_loc_30_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_30_ce0 : STD_LOGIC;
+    signal in2_loc_30_we0 : STD_LOGIC;
+    signal in2_loc_31_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_31_ce0 : STD_LOGIC;
+    signal in2_loc_31_we0 : STD_LOGIC;
+    signal in2_loc_32_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_32_ce0 : STD_LOGIC;
+    signal in2_loc_32_we0 : STD_LOGIC;
+    signal in2_loc_33_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_33_ce0 : STD_LOGIC;
+    signal in2_loc_33_we0 : STD_LOGIC;
+    signal in2_loc_34_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_34_ce0 : STD_LOGIC;
+    signal in2_loc_34_we0 : STD_LOGIC;
+    signal in2_loc_35_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_35_ce0 : STD_LOGIC;
+    signal in2_loc_35_we0 : STD_LOGIC;
+    signal in2_loc_36_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_36_ce0 : STD_LOGIC;
+    signal in2_loc_36_we0 : STD_LOGIC;
+    signal in2_loc_37_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_37_ce0 : STD_LOGIC;
+    signal in2_loc_37_we0 : STD_LOGIC;
+    signal in2_loc_38_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_38_ce0 : STD_LOGIC;
+    signal in2_loc_38_we0 : STD_LOGIC;
+    signal in2_loc_39_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_39_ce0 : STD_LOGIC;
+    signal in2_loc_39_we0 : STD_LOGIC;
+    signal in2_loc_40_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_40_ce0 : STD_LOGIC;
+    signal in2_loc_40_we0 : STD_LOGIC;
+    signal in2_loc_41_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_41_ce0 : STD_LOGIC;
+    signal in2_loc_41_we0 : STD_LOGIC;
+    signal in2_loc_42_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_42_ce0 : STD_LOGIC;
+    signal in2_loc_42_we0 : STD_LOGIC;
+    signal in2_loc_43_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_43_ce0 : STD_LOGIC;
+    signal in2_loc_43_we0 : STD_LOGIC;
+    signal in2_loc_44_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_44_ce0 : STD_LOGIC;
+    signal in2_loc_44_we0 : STD_LOGIC;
+    signal in2_loc_45_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_45_ce0 : STD_LOGIC;
+    signal in2_loc_45_we0 : STD_LOGIC;
+    signal in2_loc_46_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_46_ce0 : STD_LOGIC;
+    signal in2_loc_46_we0 : STD_LOGIC;
+    signal in2_loc_47_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_47_ce0 : STD_LOGIC;
+    signal in2_loc_47_we0 : STD_LOGIC;
+    signal in2_loc_48_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_48_ce0 : STD_LOGIC;
+    signal in2_loc_48_we0 : STD_LOGIC;
+    signal in2_loc_49_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_49_ce0 : STD_LOGIC;
+    signal in2_loc_49_we0 : STD_LOGIC;
+    signal in2_loc_50_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_50_ce0 : STD_LOGIC;
+    signal in2_loc_50_we0 : STD_LOGIC;
+    signal in2_loc_51_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_51_ce0 : STD_LOGIC;
+    signal in2_loc_51_we0 : STD_LOGIC;
+    signal in2_loc_52_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_52_ce0 : STD_LOGIC;
+    signal in2_loc_52_we0 : STD_LOGIC;
+    signal in2_loc_53_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_53_ce0 : STD_LOGIC;
+    signal in2_loc_53_we0 : STD_LOGIC;
+    signal in2_loc_54_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_54_ce0 : STD_LOGIC;
+    signal in2_loc_54_we0 : STD_LOGIC;
+    signal in2_loc_55_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_55_ce0 : STD_LOGIC;
+    signal in2_loc_55_we0 : STD_LOGIC;
+    signal in2_loc_56_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_56_ce0 : STD_LOGIC;
+    signal in2_loc_56_we0 : STD_LOGIC;
+    signal in2_loc_57_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_57_ce0 : STD_LOGIC;
+    signal in2_loc_57_we0 : STD_LOGIC;
+    signal in2_loc_58_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_58_ce0 : STD_LOGIC;
+    signal in2_loc_58_we0 : STD_LOGIC;
+    signal in2_loc_59_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_59_ce0 : STD_LOGIC;
+    signal in2_loc_59_we0 : STD_LOGIC;
+    signal in2_loc_60_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_60_ce0 : STD_LOGIC;
+    signal in2_loc_60_we0 : STD_LOGIC;
+    signal in2_loc_61_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_61_ce0 : STD_LOGIC;
+    signal in2_loc_61_we0 : STD_LOGIC;
+    signal in2_loc_62_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_62_ce0 : STD_LOGIC;
+    signal in2_loc_62_we0 : STD_LOGIC;
+    signal in2_loc_63_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_63_ce0 : STD_LOGIC;
+    signal in2_loc_63_we0 : STD_LOGIC;
+    signal out_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_ce0 : STD_LOGIC;
+    signal out_loc_ce1 : STD_LOGIC;
+    signal out_loc_we1 : STD_LOGIC;
+    signal out_loc_d1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_phi_mux_i_0_phi_fu_3333_p4 : STD_LOGIC_VECTOR (30 downto 0);
+    signal ap_block_pp2_stage0 : BOOLEAN;
+    signal zext_ln27_fu_3446_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln28_fu_3539_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln38_fu_3797_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln42_fu_4385_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_8_fu_3392_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_fu_3402_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_7_fu_3411_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp3_stage0_01001 : BOOLEAN;
+    signal mul_ln31_fu_3609_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal zext_ln31_fu_3606_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal mul_ln31_fu_3609_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln33_fu_3632_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal i_fu_3626_p2 : STD_LOGIC_VECTOR (30 downto 0);
+    signal trunc_ln38_fu_3653_p1 : STD_LOGIC_VECTOR (7 downto 0);
+    signal select_ln31_fu_3637_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_cast_fu_3657_p3 : STD_LOGIC_VECTOR (13 downto 0);
+    signal trunc_ln38_1_fu_3787_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_64_fu_3791_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_fu_4064_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_1_fu_4069_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_3_fu_4079_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_4_fu_4083_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_2_fu_4073_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_5_fu_4087_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_7_fu_4099_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_8_fu_4103_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_10_fu_4113_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_11_fu_4117_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_15_fu_4127_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_16_fu_4131_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_18_fu_4141_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_19_fu_4145_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_17_fu_4135_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_20_fu_4149_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_22_fu_4161_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_23_fu_4165_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_25_fu_4175_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_26_fu_4179_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_24_fu_4169_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_27_fu_4183_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_31_fu_4195_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_32_fu_4199_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_34_fu_4209_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_35_fu_4213_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_33_fu_4203_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_36_fu_4217_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_46_fu_4237_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_47_fu_4241_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_49_fu_4251_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_50_fu_4255_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_48_fu_4245_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_51_fu_4259_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_13_fu_4283_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_14_fu_4287_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_29_fu_4292_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_39_fu_4302_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_42_fu_4311_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_40_fu_4306_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_43_fu_4315_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_44_fu_4320_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_54_fu_4331_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_58_fu_4340_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_55_fu_4335_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_59_fu_4344_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_60_fu_4349_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_45_fu_4326_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_61_fu_4355_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_30_fu_4296_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_62_fu_4360_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (25 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal ap_idle_pp1 : STD_LOGIC;
+    signal ap_enable_pp1 : STD_LOGIC;
+    signal ap_idle_pp2 : STD_LOGIC;
+    signal ap_enable_pp2 : STD_LOGIC;
+    signal ap_idle_pp3 : STD_LOGIC;
+    signal ap_enable_pp3 : STD_LOGIC;
+
+    component mmult_in1_loc_0 IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (5 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_out_loc IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        address1 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_params_s_axi IS
+    generic (
+        C_S_AXI_ADDR_WIDTH : INTEGER;
+        C_S_AXI_DATA_WIDTH : INTEGER );
+    port (
+        AWVALID : IN STD_LOGIC;
+        AWREADY : OUT STD_LOGIC;
+        AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        WVALID : IN STD_LOGIC;
+        WREADY : OUT STD_LOGIC;
+        WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
+        ARVALID : IN STD_LOGIC;
+        ARREADY : OUT STD_LOGIC;
+        ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        RVALID : OUT STD_LOGIC;
+        RREADY : IN STD_LOGIC;
+        RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : OUT STD_LOGIC;
+        BREADY : IN STD_LOGIC;
+        BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        ap_start : OUT STD_LOGIC;
+        interrupt : OUT STD_LOGIC;
+        ap_ready : IN STD_LOGIC;
+        ap_done : IN STD_LOGIC;
+        ap_idle : IN STD_LOGIC;
+        in1 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        in2 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        out_r : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dim : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_in2_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_out_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+
+begin
+    mmult_params_s_axi_U : component mmult_params_s_axi
+    generic map (
+        C_S_AXI_ADDR_WIDTH => C_S_AXI_PARAMS_ADDR_WIDTH,
+        C_S_AXI_DATA_WIDTH => C_S_AXI_PARAMS_DATA_WIDTH)
+    port map (
+        AWVALID => s_axi_params_AWVALID,
+        AWREADY => s_axi_params_AWREADY,
+        AWADDR => s_axi_params_AWADDR,
+        WVALID => s_axi_params_WVALID,
+        WREADY => s_axi_params_WREADY,
+        WDATA => s_axi_params_WDATA,
+        WSTRB => s_axi_params_WSTRB,
+        ARVALID => s_axi_params_ARVALID,
+        ARREADY => s_axi_params_ARREADY,
+        ARADDR => s_axi_params_ARADDR,
+        RVALID => s_axi_params_RVALID,
+        RREADY => s_axi_params_RREADY,
+        RDATA => s_axi_params_RDATA,
+        RRESP => s_axi_params_RRESP,
+        BVALID => s_axi_params_BVALID,
+        BREADY => s_axi_params_BREADY,
+        BRESP => s_axi_params_BRESP,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        ap_start => ap_start,
+        interrupt => interrupt,
+        ap_ready => ap_ready,
+        ap_done => ap_done,
+        ap_idle => ap_idle,
+        in1 => in1,
+        in2 => in2,
+        out_r => out_r,
+        dim => dim);
+
+    mmult_in1_mem_m_axi_U : component mmult_in1_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN1_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN1_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN1_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN1_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN1_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN1_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN1_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN1_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN1_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN1_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN1_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in1_mem_AWVALID,
+        AWREADY => m_axi_in1_mem_AWREADY,
+        AWADDR => m_axi_in1_mem_AWADDR,
+        AWID => m_axi_in1_mem_AWID,
+        AWLEN => m_axi_in1_mem_AWLEN,
+        AWSIZE => m_axi_in1_mem_AWSIZE,
+        AWBURST => m_axi_in1_mem_AWBURST,
+        AWLOCK => m_axi_in1_mem_AWLOCK,
+        AWCACHE => m_axi_in1_mem_AWCACHE,
+        AWPROT => m_axi_in1_mem_AWPROT,
+        AWQOS => m_axi_in1_mem_AWQOS,
+        AWREGION => m_axi_in1_mem_AWREGION,
+        AWUSER => m_axi_in1_mem_AWUSER,
+        WVALID => m_axi_in1_mem_WVALID,
+        WREADY => m_axi_in1_mem_WREADY,
+        WDATA => m_axi_in1_mem_WDATA,
+        WSTRB => m_axi_in1_mem_WSTRB,
+        WLAST => m_axi_in1_mem_WLAST,
+        WID => m_axi_in1_mem_WID,
+        WUSER => m_axi_in1_mem_WUSER,
+        ARVALID => m_axi_in1_mem_ARVALID,
+        ARREADY => m_axi_in1_mem_ARREADY,
+        ARADDR => m_axi_in1_mem_ARADDR,
+        ARID => m_axi_in1_mem_ARID,
+        ARLEN => m_axi_in1_mem_ARLEN,
+        ARSIZE => m_axi_in1_mem_ARSIZE,
+        ARBURST => m_axi_in1_mem_ARBURST,
+        ARLOCK => m_axi_in1_mem_ARLOCK,
+        ARCACHE => m_axi_in1_mem_ARCACHE,
+        ARPROT => m_axi_in1_mem_ARPROT,
+        ARQOS => m_axi_in1_mem_ARQOS,
+        ARREGION => m_axi_in1_mem_ARREGION,
+        ARUSER => m_axi_in1_mem_ARUSER,
+        RVALID => m_axi_in1_mem_RVALID,
+        RREADY => m_axi_in1_mem_RREADY,
+        RDATA => m_axi_in1_mem_RDATA,
+        RLAST => m_axi_in1_mem_RLAST,
+        RID => m_axi_in1_mem_RID,
+        RUSER => m_axi_in1_mem_RUSER,
+        RRESP => m_axi_in1_mem_RRESP,
+        BVALID => m_axi_in1_mem_BVALID,
+        BREADY => m_axi_in1_mem_BREADY,
+        BRESP => m_axi_in1_mem_BRESP,
+        BID => m_axi_in1_mem_BID,
+        BUSER => m_axi_in1_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in1_mem_ARVALID,
+        I_ARREADY => in1_mem_ARREADY,
+        I_ARADDR => in1_mem_ARADDR,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in1_mem_RVALID,
+        I_RREADY => in1_mem_RREADY,
+        I_RDATA => in1_mem_RDATA,
+        I_RID => in1_mem_RID,
+        I_RUSER => in1_mem_RUSER,
+        I_RRESP => in1_mem_RRESP,
+        I_RLAST => in1_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in1_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in1_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in1_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in1_mem_BRESP,
+        I_BID => in1_mem_BID,
+        I_BUSER => in1_mem_BUSER);
+
+    mmult_in2_mem_m_axi_U : component mmult_in2_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN2_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN2_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN2_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN2_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN2_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN2_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN2_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN2_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN2_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN2_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN2_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in2_mem_AWVALID,
+        AWREADY => m_axi_in2_mem_AWREADY,
+        AWADDR => m_axi_in2_mem_AWADDR,
+        AWID => m_axi_in2_mem_AWID,
+        AWLEN => m_axi_in2_mem_AWLEN,
+        AWSIZE => m_axi_in2_mem_AWSIZE,
+        AWBURST => m_axi_in2_mem_AWBURST,
+        AWLOCK => m_axi_in2_mem_AWLOCK,
+        AWCACHE => m_axi_in2_mem_AWCACHE,
+        AWPROT => m_axi_in2_mem_AWPROT,
+        AWQOS => m_axi_in2_mem_AWQOS,
+        AWREGION => m_axi_in2_mem_AWREGION,
+        AWUSER => m_axi_in2_mem_AWUSER,
+        WVALID => m_axi_in2_mem_WVALID,
+        WREADY => m_axi_in2_mem_WREADY,
+        WDATA => m_axi_in2_mem_WDATA,
+        WSTRB => m_axi_in2_mem_WSTRB,
+        WLAST => m_axi_in2_mem_WLAST,
+        WID => m_axi_in2_mem_WID,
+        WUSER => m_axi_in2_mem_WUSER,
+        ARVALID => m_axi_in2_mem_ARVALID,
+        ARREADY => m_axi_in2_mem_ARREADY,
+        ARADDR => m_axi_in2_mem_ARADDR,
+        ARID => m_axi_in2_mem_ARID,
+        ARLEN => m_axi_in2_mem_ARLEN,
+        ARSIZE => m_axi_in2_mem_ARSIZE,
+        ARBURST => m_axi_in2_mem_ARBURST,
+        ARLOCK => m_axi_in2_mem_ARLOCK,
+        ARCACHE => m_axi_in2_mem_ARCACHE,
+        ARPROT => m_axi_in2_mem_ARPROT,
+        ARQOS => m_axi_in2_mem_ARQOS,
+        ARREGION => m_axi_in2_mem_ARREGION,
+        ARUSER => m_axi_in2_mem_ARUSER,
+        RVALID => m_axi_in2_mem_RVALID,
+        RREADY => m_axi_in2_mem_RREADY,
+        RDATA => m_axi_in2_mem_RDATA,
+        RLAST => m_axi_in2_mem_RLAST,
+        RID => m_axi_in2_mem_RID,
+        RUSER => m_axi_in2_mem_RUSER,
+        RRESP => m_axi_in2_mem_RRESP,
+        BVALID => m_axi_in2_mem_BVALID,
+        BREADY => m_axi_in2_mem_BREADY,
+        BRESP => m_axi_in2_mem_BRESP,
+        BID => m_axi_in2_mem_BID,
+        BUSER => m_axi_in2_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in2_mem_ARVALID,
+        I_ARREADY => in2_mem_ARREADY,
+        I_ARADDR => in2_mem_addr_reg_4423,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in2_mem_RVALID,
+        I_RREADY => in2_mem_RREADY,
+        I_RDATA => in2_mem_RDATA,
+        I_RID => in2_mem_RID,
+        I_RUSER => in2_mem_RUSER,
+        I_RRESP => in2_mem_RRESP,
+        I_RLAST => in2_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in2_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in2_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in2_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in2_mem_BRESP,
+        I_BID => in2_mem_BID,
+        I_BUSER => in2_mem_BUSER);
+
+    mmult_out_mem_m_axi_U : component mmult_out_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_OUT_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_OUT_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_OUT_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_OUT_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_OUT_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_OUT_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_OUT_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_OUT_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_OUT_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_OUT_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_OUT_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_out_mem_AWVALID,
+        AWREADY => m_axi_out_mem_AWREADY,
+        AWADDR => m_axi_out_mem_AWADDR,
+        AWID => m_axi_out_mem_AWID,
+        AWLEN => m_axi_out_mem_AWLEN,
+        AWSIZE => m_axi_out_mem_AWSIZE,
+        AWBURST => m_axi_out_mem_AWBURST,
+        AWLOCK => m_axi_out_mem_AWLOCK,
+        AWCACHE => m_axi_out_mem_AWCACHE,
+        AWPROT => m_axi_out_mem_AWPROT,
+        AWQOS => m_axi_out_mem_AWQOS,
+        AWREGION => m_axi_out_mem_AWREGION,
+        AWUSER => m_axi_out_mem_AWUSER,
+        WVALID => m_axi_out_mem_WVALID,
+        WREADY => m_axi_out_mem_WREADY,
+        WDATA => m_axi_out_mem_WDATA,
+        WSTRB => m_axi_out_mem_WSTRB,
+        WLAST => m_axi_out_mem_WLAST,
+        WID => m_axi_out_mem_WID,
+        WUSER => m_axi_out_mem_WUSER,
+        ARVALID => m_axi_out_mem_ARVALID,
+        ARREADY => m_axi_out_mem_ARREADY,
+        ARADDR => m_axi_out_mem_ARADDR,
+        ARID => m_axi_out_mem_ARID,
+        ARLEN => m_axi_out_mem_ARLEN,
+        ARSIZE => m_axi_out_mem_ARSIZE,
+        ARBURST => m_axi_out_mem_ARBURST,
+        ARLOCK => m_axi_out_mem_ARLOCK,
+        ARCACHE => m_axi_out_mem_ARCACHE,
+        ARPROT => m_axi_out_mem_ARPROT,
+        ARQOS => m_axi_out_mem_ARQOS,
+        ARREGION => m_axi_out_mem_ARREGION,
+        ARUSER => m_axi_out_mem_ARUSER,
+        RVALID => m_axi_out_mem_RVALID,
+        RREADY => m_axi_out_mem_RREADY,
+        RDATA => m_axi_out_mem_RDATA,
+        RLAST => m_axi_out_mem_RLAST,
+        RID => m_axi_out_mem_RID,
+        RUSER => m_axi_out_mem_RUSER,
+        RRESP => m_axi_out_mem_RRESP,
+        BVALID => m_axi_out_mem_BVALID,
+        BREADY => m_axi_out_mem_BREADY,
+        BRESP => m_axi_out_mem_BRESP,
+        BID => m_axi_out_mem_BID,
+        BUSER => m_axi_out_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => ap_const_logic_0,
+        I_ARREADY => out_mem_ARREADY,
+        I_ARADDR => ap_const_lv32_0,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_0,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => out_mem_RVALID,
+        I_RREADY => ap_const_logic_0,
+        I_RDATA => out_mem_RDATA,
+        I_RID => out_mem_RID,
+        I_RUSER => out_mem_RUSER,
+        I_RRESP => out_mem_RRESP,
+        I_RLAST => out_mem_RLAST,
+        I_AWVALID => out_mem_AWVALID,
+        I_AWREADY => out_mem_AWREADY,
+        I_AWADDR => out_mem_addr_reg_4417,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_1000,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => out_mem_WVALID,
+        I_WREADY => out_mem_WREADY,
+        I_WDATA => out_loc_load_reg_6327,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_F,
+        I_BVALID => out_mem_BVALID,
+        I_BREADY => out_mem_BREADY,
+        I_BRESP => out_mem_BRESP,
+        I_BID => out_mem_BID,
+        I_BUSER => out_mem_BUSER);
+
+    in1_loc_0_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_0_address0,
+        ce0 => in1_loc_0_ce0,
+        we0 => in1_loc_0_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_0_q0);
+
+    in1_loc_1_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_1_address0,
+        ce0 => in1_loc_1_ce0,
+        we0 => in1_loc_1_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_1_q0);
+
+    in1_loc_2_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_2_address0,
+        ce0 => in1_loc_2_ce0,
+        we0 => in1_loc_2_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_2_q0);
+
+    in1_loc_3_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_3_address0,
+        ce0 => in1_loc_3_ce0,
+        we0 => in1_loc_3_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_3_q0);
+
+    in1_loc_4_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_4_address0,
+        ce0 => in1_loc_4_ce0,
+        we0 => in1_loc_4_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_4_q0);
+
+    in1_loc_5_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_5_address0,
+        ce0 => in1_loc_5_ce0,
+        we0 => in1_loc_5_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_5_q0);
+
+    in1_loc_6_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_6_address0,
+        ce0 => in1_loc_6_ce0,
+        we0 => in1_loc_6_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_6_q0);
+
+    in1_loc_7_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_7_address0,
+        ce0 => in1_loc_7_ce0,
+        we0 => in1_loc_7_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_7_q0);
+
+    in1_loc_8_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_8_address0,
+        ce0 => in1_loc_8_ce0,
+        we0 => in1_loc_8_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_8_q0);
+
+    in1_loc_9_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_9_address0,
+        ce0 => in1_loc_9_ce0,
+        we0 => in1_loc_9_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_9_q0);
+
+    in1_loc_10_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_10_address0,
+        ce0 => in1_loc_10_ce0,
+        we0 => in1_loc_10_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_10_q0);
+
+    in1_loc_11_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_11_address0,
+        ce0 => in1_loc_11_ce0,
+        we0 => in1_loc_11_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_11_q0);
+
+    in1_loc_12_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_12_address0,
+        ce0 => in1_loc_12_ce0,
+        we0 => in1_loc_12_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_12_q0);
+
+    in1_loc_13_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_13_address0,
+        ce0 => in1_loc_13_ce0,
+        we0 => in1_loc_13_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_13_q0);
+
+    in1_loc_14_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_14_address0,
+        ce0 => in1_loc_14_ce0,
+        we0 => in1_loc_14_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_14_q0);
+
+    in1_loc_15_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_15_address0,
+        ce0 => in1_loc_15_ce0,
+        we0 => in1_loc_15_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_15_q0);
+
+    in1_loc_16_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_16_address0,
+        ce0 => in1_loc_16_ce0,
+        we0 => in1_loc_16_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_16_q0);
+
+    in1_loc_17_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_17_address0,
+        ce0 => in1_loc_17_ce0,
+        we0 => in1_loc_17_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_17_q0);
+
+    in1_loc_18_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_18_address0,
+        ce0 => in1_loc_18_ce0,
+        we0 => in1_loc_18_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_18_q0);
+
+    in1_loc_19_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_19_address0,
+        ce0 => in1_loc_19_ce0,
+        we0 => in1_loc_19_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_19_q0);
+
+    in1_loc_20_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_20_address0,
+        ce0 => in1_loc_20_ce0,
+        we0 => in1_loc_20_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_20_q0);
+
+    in1_loc_21_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_21_address0,
+        ce0 => in1_loc_21_ce0,
+        we0 => in1_loc_21_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_21_q0);
+
+    in1_loc_22_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_22_address0,
+        ce0 => in1_loc_22_ce0,
+        we0 => in1_loc_22_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_22_q0);
+
+    in1_loc_23_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_23_address0,
+        ce0 => in1_loc_23_ce0,
+        we0 => in1_loc_23_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_23_q0);
+
+    in1_loc_24_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_24_address0,
+        ce0 => in1_loc_24_ce0,
+        we0 => in1_loc_24_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_24_q0);
+
+    in1_loc_25_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_25_address0,
+        ce0 => in1_loc_25_ce0,
+        we0 => in1_loc_25_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_25_q0);
+
+    in1_loc_26_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_26_address0,
+        ce0 => in1_loc_26_ce0,
+        we0 => in1_loc_26_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_26_q0);
+
+    in1_loc_27_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_27_address0,
+        ce0 => in1_loc_27_ce0,
+        we0 => in1_loc_27_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_27_q0);
+
+    in1_loc_28_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_28_address0,
+        ce0 => in1_loc_28_ce0,
+        we0 => in1_loc_28_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_28_q0);
+
+    in1_loc_29_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_29_address0,
+        ce0 => in1_loc_29_ce0,
+        we0 => in1_loc_29_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_29_q0);
+
+    in1_loc_30_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_30_address0,
+        ce0 => in1_loc_30_ce0,
+        we0 => in1_loc_30_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_30_q0);
+
+    in1_loc_31_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_31_address0,
+        ce0 => in1_loc_31_ce0,
+        we0 => in1_loc_31_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_31_q0);
+
+    in1_loc_32_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_32_address0,
+        ce0 => in1_loc_32_ce0,
+        we0 => in1_loc_32_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_32_q0);
+
+    in1_loc_33_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_33_address0,
+        ce0 => in1_loc_33_ce0,
+        we0 => in1_loc_33_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_33_q0);
+
+    in1_loc_34_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_34_address0,
+        ce0 => in1_loc_34_ce0,
+        we0 => in1_loc_34_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_34_q0);
+
+    in1_loc_35_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_35_address0,
+        ce0 => in1_loc_35_ce0,
+        we0 => in1_loc_35_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_35_q0);
+
+    in1_loc_36_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_36_address0,
+        ce0 => in1_loc_36_ce0,
+        we0 => in1_loc_36_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_36_q0);
+
+    in1_loc_37_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_37_address0,
+        ce0 => in1_loc_37_ce0,
+        we0 => in1_loc_37_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_37_q0);
+
+    in1_loc_38_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_38_address0,
+        ce0 => in1_loc_38_ce0,
+        we0 => in1_loc_38_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_38_q0);
+
+    in1_loc_39_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_39_address0,
+        ce0 => in1_loc_39_ce0,
+        we0 => in1_loc_39_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_39_q0);
+
+    in1_loc_40_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_40_address0,
+        ce0 => in1_loc_40_ce0,
+        we0 => in1_loc_40_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_40_q0);
+
+    in1_loc_41_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_41_address0,
+        ce0 => in1_loc_41_ce0,
+        we0 => in1_loc_41_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_41_q0);
+
+    in1_loc_42_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_42_address0,
+        ce0 => in1_loc_42_ce0,
+        we0 => in1_loc_42_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_42_q0);
+
+    in1_loc_43_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_43_address0,
+        ce0 => in1_loc_43_ce0,
+        we0 => in1_loc_43_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_43_q0);
+
+    in1_loc_44_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_44_address0,
+        ce0 => in1_loc_44_ce0,
+        we0 => in1_loc_44_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_44_q0);
+
+    in1_loc_45_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_45_address0,
+        ce0 => in1_loc_45_ce0,
+        we0 => in1_loc_45_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_45_q0);
+
+    in1_loc_46_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_46_address0,
+        ce0 => in1_loc_46_ce0,
+        we0 => in1_loc_46_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_46_q0);
+
+    in1_loc_47_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_47_address0,
+        ce0 => in1_loc_47_ce0,
+        we0 => in1_loc_47_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_47_q0);
+
+    in1_loc_48_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_48_address0,
+        ce0 => in1_loc_48_ce0,
+        we0 => in1_loc_48_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_48_q0);
+
+    in1_loc_49_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_49_address0,
+        ce0 => in1_loc_49_ce0,
+        we0 => in1_loc_49_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_49_q0);
+
+    in1_loc_50_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_50_address0,
+        ce0 => in1_loc_50_ce0,
+        we0 => in1_loc_50_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_50_q0);
+
+    in1_loc_51_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_51_address0,
+        ce0 => in1_loc_51_ce0,
+        we0 => in1_loc_51_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_51_q0);
+
+    in1_loc_52_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_52_address0,
+        ce0 => in1_loc_52_ce0,
+        we0 => in1_loc_52_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_52_q0);
+
+    in1_loc_53_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_53_address0,
+        ce0 => in1_loc_53_ce0,
+        we0 => in1_loc_53_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_53_q0);
+
+    in1_loc_54_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_54_address0,
+        ce0 => in1_loc_54_ce0,
+        we0 => in1_loc_54_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_54_q0);
+
+    in1_loc_55_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_55_address0,
+        ce0 => in1_loc_55_ce0,
+        we0 => in1_loc_55_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_55_q0);
+
+    in1_loc_56_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_56_address0,
+        ce0 => in1_loc_56_ce0,
+        we0 => in1_loc_56_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_56_q0);
+
+    in1_loc_57_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_57_address0,
+        ce0 => in1_loc_57_ce0,
+        we0 => in1_loc_57_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_57_q0);
+
+    in1_loc_58_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_58_address0,
+        ce0 => in1_loc_58_ce0,
+        we0 => in1_loc_58_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_58_q0);
+
+    in1_loc_59_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_59_address0,
+        ce0 => in1_loc_59_ce0,
+        we0 => in1_loc_59_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_59_q0);
+
+    in1_loc_60_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_60_address0,
+        ce0 => in1_loc_60_ce0,
+        we0 => in1_loc_60_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_60_q0);
+
+    in1_loc_61_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_61_address0,
+        ce0 => in1_loc_61_ce0,
+        we0 => in1_loc_61_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_61_q0);
+
+    in1_loc_62_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_62_address0,
+        ce0 => in1_loc_62_ce0,
+        we0 => in1_loc_62_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_62_q0);
+
+    in1_loc_63_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_63_address0,
+        ce0 => in1_loc_63_ce0,
+        we0 => in1_loc_63_we0,
+        d0 => in1_mem_addr_read_reg_4447,
+        q0 => in1_loc_63_q0);
+
+    in2_loc_0_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_0_address0,
+        ce0 => in2_loc_0_ce0,
+        we0 => in2_loc_0_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_0_q0);
+
+    in2_loc_1_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_1_address0,
+        ce0 => in2_loc_1_ce0,
+        we0 => in2_loc_1_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_1_q0);
+
+    in2_loc_2_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_2_address0,
+        ce0 => in2_loc_2_ce0,
+        we0 => in2_loc_2_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_2_q0);
+
+    in2_loc_3_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_3_address0,
+        ce0 => in2_loc_3_ce0,
+        we0 => in2_loc_3_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_3_q0);
+
+    in2_loc_4_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_4_address0,
+        ce0 => in2_loc_4_ce0,
+        we0 => in2_loc_4_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_4_q0);
+
+    in2_loc_5_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_5_address0,
+        ce0 => in2_loc_5_ce0,
+        we0 => in2_loc_5_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_5_q0);
+
+    in2_loc_6_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_6_address0,
+        ce0 => in2_loc_6_ce0,
+        we0 => in2_loc_6_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_6_q0);
+
+    in2_loc_7_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_7_address0,
+        ce0 => in2_loc_7_ce0,
+        we0 => in2_loc_7_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_7_q0);
+
+    in2_loc_8_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_8_address0,
+        ce0 => in2_loc_8_ce0,
+        we0 => in2_loc_8_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_8_q0);
+
+    in2_loc_9_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_9_address0,
+        ce0 => in2_loc_9_ce0,
+        we0 => in2_loc_9_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_9_q0);
+
+    in2_loc_10_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_10_address0,
+        ce0 => in2_loc_10_ce0,
+        we0 => in2_loc_10_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_10_q0);
+
+    in2_loc_11_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_11_address0,
+        ce0 => in2_loc_11_ce0,
+        we0 => in2_loc_11_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_11_q0);
+
+    in2_loc_12_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_12_address0,
+        ce0 => in2_loc_12_ce0,
+        we0 => in2_loc_12_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_12_q0);
+
+    in2_loc_13_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_13_address0,
+        ce0 => in2_loc_13_ce0,
+        we0 => in2_loc_13_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_13_q0);
+
+    in2_loc_14_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_14_address0,
+        ce0 => in2_loc_14_ce0,
+        we0 => in2_loc_14_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_14_q0);
+
+    in2_loc_15_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_15_address0,
+        ce0 => in2_loc_15_ce0,
+        we0 => in2_loc_15_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_15_q0);
+
+    in2_loc_16_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_16_address0,
+        ce0 => in2_loc_16_ce0,
+        we0 => in2_loc_16_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_16_q0);
+
+    in2_loc_17_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_17_address0,
+        ce0 => in2_loc_17_ce0,
+        we0 => in2_loc_17_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_17_q0);
+
+    in2_loc_18_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_18_address0,
+        ce0 => in2_loc_18_ce0,
+        we0 => in2_loc_18_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_18_q0);
+
+    in2_loc_19_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_19_address0,
+        ce0 => in2_loc_19_ce0,
+        we0 => in2_loc_19_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_19_q0);
+
+    in2_loc_20_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_20_address0,
+        ce0 => in2_loc_20_ce0,
+        we0 => in2_loc_20_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_20_q0);
+
+    in2_loc_21_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_21_address0,
+        ce0 => in2_loc_21_ce0,
+        we0 => in2_loc_21_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_21_q0);
+
+    in2_loc_22_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_22_address0,
+        ce0 => in2_loc_22_ce0,
+        we0 => in2_loc_22_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_22_q0);
+
+    in2_loc_23_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_23_address0,
+        ce0 => in2_loc_23_ce0,
+        we0 => in2_loc_23_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_23_q0);
+
+    in2_loc_24_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_24_address0,
+        ce0 => in2_loc_24_ce0,
+        we0 => in2_loc_24_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_24_q0);
+
+    in2_loc_25_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_25_address0,
+        ce0 => in2_loc_25_ce0,
+        we0 => in2_loc_25_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_25_q0);
+
+    in2_loc_26_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_26_address0,
+        ce0 => in2_loc_26_ce0,
+        we0 => in2_loc_26_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_26_q0);
+
+    in2_loc_27_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_27_address0,
+        ce0 => in2_loc_27_ce0,
+        we0 => in2_loc_27_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_27_q0);
+
+    in2_loc_28_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_28_address0,
+        ce0 => in2_loc_28_ce0,
+        we0 => in2_loc_28_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_28_q0);
+
+    in2_loc_29_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_29_address0,
+        ce0 => in2_loc_29_ce0,
+        we0 => in2_loc_29_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_29_q0);
+
+    in2_loc_30_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_30_address0,
+        ce0 => in2_loc_30_ce0,
+        we0 => in2_loc_30_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_30_q0);
+
+    in2_loc_31_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_31_address0,
+        ce0 => in2_loc_31_ce0,
+        we0 => in2_loc_31_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_31_q0);
+
+    in2_loc_32_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_32_address0,
+        ce0 => in2_loc_32_ce0,
+        we0 => in2_loc_32_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_32_q0);
+
+    in2_loc_33_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_33_address0,
+        ce0 => in2_loc_33_ce0,
+        we0 => in2_loc_33_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_33_q0);
+
+    in2_loc_34_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_34_address0,
+        ce0 => in2_loc_34_ce0,
+        we0 => in2_loc_34_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_34_q0);
+
+    in2_loc_35_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_35_address0,
+        ce0 => in2_loc_35_ce0,
+        we0 => in2_loc_35_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_35_q0);
+
+    in2_loc_36_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_36_address0,
+        ce0 => in2_loc_36_ce0,
+        we0 => in2_loc_36_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_36_q0);
+
+    in2_loc_37_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_37_address0,
+        ce0 => in2_loc_37_ce0,
+        we0 => in2_loc_37_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_37_q0);
+
+    in2_loc_38_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_38_address0,
+        ce0 => in2_loc_38_ce0,
+        we0 => in2_loc_38_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_38_q0);
+
+    in2_loc_39_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_39_address0,
+        ce0 => in2_loc_39_ce0,
+        we0 => in2_loc_39_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_39_q0);
+
+    in2_loc_40_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_40_address0,
+        ce0 => in2_loc_40_ce0,
+        we0 => in2_loc_40_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_40_q0);
+
+    in2_loc_41_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_41_address0,
+        ce0 => in2_loc_41_ce0,
+        we0 => in2_loc_41_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_41_q0);
+
+    in2_loc_42_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_42_address0,
+        ce0 => in2_loc_42_ce0,
+        we0 => in2_loc_42_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_42_q0);
+
+    in2_loc_43_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_43_address0,
+        ce0 => in2_loc_43_ce0,
+        we0 => in2_loc_43_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_43_q0);
+
+    in2_loc_44_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_44_address0,
+        ce0 => in2_loc_44_ce0,
+        we0 => in2_loc_44_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_44_q0);
+
+    in2_loc_45_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_45_address0,
+        ce0 => in2_loc_45_ce0,
+        we0 => in2_loc_45_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_45_q0);
+
+    in2_loc_46_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_46_address0,
+        ce0 => in2_loc_46_ce0,
+        we0 => in2_loc_46_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_46_q0);
+
+    in2_loc_47_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_47_address0,
+        ce0 => in2_loc_47_ce0,
+        we0 => in2_loc_47_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_47_q0);
+
+    in2_loc_48_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_48_address0,
+        ce0 => in2_loc_48_ce0,
+        we0 => in2_loc_48_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_48_q0);
+
+    in2_loc_49_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_49_address0,
+        ce0 => in2_loc_49_ce0,
+        we0 => in2_loc_49_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_49_q0);
+
+    in2_loc_50_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_50_address0,
+        ce0 => in2_loc_50_ce0,
+        we0 => in2_loc_50_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_50_q0);
+
+    in2_loc_51_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_51_address0,
+        ce0 => in2_loc_51_ce0,
+        we0 => in2_loc_51_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_51_q0);
+
+    in2_loc_52_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_52_address0,
+        ce0 => in2_loc_52_ce0,
+        we0 => in2_loc_52_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_52_q0);
+
+    in2_loc_53_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_53_address0,
+        ce0 => in2_loc_53_ce0,
+        we0 => in2_loc_53_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_53_q0);
+
+    in2_loc_54_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_54_address0,
+        ce0 => in2_loc_54_ce0,
+        we0 => in2_loc_54_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_54_q0);
+
+    in2_loc_55_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_55_address0,
+        ce0 => in2_loc_55_ce0,
+        we0 => in2_loc_55_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_55_q0);
+
+    in2_loc_56_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_56_address0,
+        ce0 => in2_loc_56_ce0,
+        we0 => in2_loc_56_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_56_q0);
+
+    in2_loc_57_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_57_address0,
+        ce0 => in2_loc_57_ce0,
+        we0 => in2_loc_57_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_57_q0);
+
+    in2_loc_58_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_58_address0,
+        ce0 => in2_loc_58_ce0,
+        we0 => in2_loc_58_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_58_q0);
+
+    in2_loc_59_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_59_address0,
+        ce0 => in2_loc_59_ce0,
+        we0 => in2_loc_59_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_59_q0);
+
+    in2_loc_60_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_60_address0,
+        ce0 => in2_loc_60_ce0,
+        we0 => in2_loc_60_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_60_q0);
+
+    in2_loc_61_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_61_address0,
+        ce0 => in2_loc_61_ce0,
+        we0 => in2_loc_61_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_61_q0);
+
+    in2_loc_62_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_62_address0,
+        ce0 => in2_loc_62_ce0,
+        we0 => in2_loc_62_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_62_q0);
+
+    in2_loc_63_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_63_address0,
+        ce0 => in2_loc_63_ce0,
+        we0 => in2_loc_63_we0,
+        d0 => in2_mem_addr_read_reg_4533,
+        q0 => in2_loc_63_q0);
+
+    out_loc_U : component mmult_out_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => out_loc_address0,
+        ce0 => out_loc_ce0,
+        q0 => out_loc_q0,
+        address1 => out_loc_addr_reg_4927_pp2_iter3_reg,
+        ce1 => out_loc_ce1,
+        we1 => out_loc_we1,
+        d1 => out_loc_d1);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state9);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19)) then 
+                        ap_enable_reg_pp1_iter1 <= (ap_const_logic_1 xor ap_condition_pp1_exit_iter0_state19);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_condition_pp2_exit_iter0_state23) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp2_exit_iter0_state23)) then 
+                        ap_enable_reg_pp2_iter1 <= (ap_const_logic_1 xor ap_condition_pp2_exit_iter0_state23);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter3 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter3 <= ap_enable_reg_pp2_iter2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter4_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter4 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter4 <= ap_enable_reg_pp2_iter3;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                    ap_enable_reg_pp2_iter4 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_condition_pp3_exit_iter0_state29) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone))) then 
+                    ap_enable_reg_pp3_iter0 <= ap_const_logic_0;
+                elsif (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state28))) then 
+                    ap_enable_reg_pp3_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp3_exit_iter0_state29)) then 
+                        ap_enable_reg_pp3_iter1 <= (ap_const_logic_1 xor ap_condition_pp3_exit_iter0_state29);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp3_iter1 <= ap_enable_reg_pp3_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) then 
+                    ap_enable_reg_pp3_iter2 <= ap_enable_reg_pp3_iter1;
+                elsif (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state28))) then 
+                    ap_enable_reg_pp3_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0_reg_3329_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4606 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+                i_0_reg_3329 <= select_ln31_1_reg_4615;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                i_0_reg_3329 <= ap_const_lv31_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_3318_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+                indvar_flatten_reg_3318 <= add_ln31_fu_3620_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                indvar_flatten_reg_3318 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    j_0_reg_3340_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+                j_0_reg_3340 <= j_fu_3802_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state22)) then 
+                j_0_reg_3340 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln27_reg_3296_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_fu_3420_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                phi_ln27_reg_3296 <= add_ln27_fu_3426_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                phi_ln27_reg_3296 <= ap_const_lv13_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln28_reg_3307_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                phi_ln28_reg_3307 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_fu_3513_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+                phi_ln28_reg_3307 <= add_ln28_fu_3519_p2;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln42_reg_3351_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state28))) then 
+                phi_ln42_reg_3351 <= ap_const_lv13_0;
+            elsif (((icmp_ln42_fu_4373_p2 = ap_const_lv1_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_const_boolean_0 = ap_block_pp3_stage0_11001))) then 
+                phi_ln42_reg_3351 <= add_ln42_fu_4379_p2;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4606_pp2_iter2_reg = ap_const_lv1_0))) then
+                add_ln38_12_reg_6263 <= add_ln38_12_fu_4121_p2;
+                add_ln38_21_reg_6268 <= add_ln38_21_fu_4155_p2;
+                add_ln38_28_reg_6273 <= add_ln38_28_fu_4189_p2;
+                add_ln38_37_reg_6278 <= add_ln38_37_fu_4223_p2;
+                add_ln38_38_reg_6283 <= add_ln38_38_fu_4229_p2;
+                add_ln38_41_reg_6288 <= add_ln38_41_fu_4233_p2;
+                add_ln38_52_reg_6293 <= add_ln38_52_fu_4265_p2;
+                add_ln38_53_reg_6298 <= add_ln38_53_fu_4271_p2;
+                add_ln38_56_reg_6303 <= add_ln38_56_fu_4275_p2;
+                add_ln38_57_reg_6308 <= add_ln38_57_fu_4279_p2;
+                add_ln38_6_reg_6253 <= add_ln38_6_fu_4093_p2;
+                add_ln38_9_reg_6258 <= add_ln38_9_fu_4107_p2;
+                mul_ln38_41_reg_6218 <= mul_ln38_41_fu_4036_p2;
+                mul_ln38_42_reg_6223 <= mul_ln38_42_fu_4040_p2;
+                mul_ln38_45_reg_6228 <= mul_ln38_45_fu_4044_p2;
+                mul_ln38_46_reg_6233 <= mul_ln38_46_fu_4048_p2;
+                mul_ln38_57_reg_6238 <= mul_ln38_57_fu_4052_p2;
+                mul_ln38_58_reg_6243 <= mul_ln38_58_fu_4056_p2;
+                mul_ln38_61_reg_6248 <= mul_ln38_61_fu_4060_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                dim_read_reg_4390 <= dim;
+                in3_reg_4406 <= in1(31 downto 2);
+                in_reg_4401 <= in2(31 downto 2);
+                out5_reg_4396 <= out_r(31 downto 2);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                icmp_ln31_reg_4606 <= icmp_ln31_fu_3615_p2;
+                icmp_ln31_reg_4606_pp2_iter1_reg <= icmp_ln31_reg_4606;
+                out_loc_addr_reg_4927_pp2_iter1_reg <= out_loc_addr_reg_4927;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_boolean_0 = ap_block_pp2_stage0_11001)) then
+                icmp_ln31_reg_4606_pp2_iter2_reg <= icmp_ln31_reg_4606_pp2_iter1_reg;
+                icmp_ln31_reg_4606_pp2_iter3_reg <= icmp_ln31_reg_4606_pp2_iter2_reg;
+                out_loc_addr_reg_4927_pp2_iter2_reg <= out_loc_addr_reg_4927_pp2_iter1_reg;
+                out_loc_addr_reg_4927_pp2_iter3_reg <= out_loc_addr_reg_4927_pp2_iter2_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_const_boolean_0 = ap_block_pp3_stage0_11001))) then
+                icmp_ln42_reg_6313 <= icmp_ln42_fu_4373_p2;
+                icmp_ln42_reg_6313_pp3_iter1_reg <= icmp_ln42_reg_6313;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4606 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                in1_loc_0_load_reg_5223 <= in1_loc_0_q0;
+                in1_loc_10_load_reg_5273 <= in1_loc_10_q0;
+                in1_loc_11_load_reg_5278 <= in1_loc_11_q0;
+                in1_loc_12_load_reg_5283 <= in1_loc_12_q0;
+                in1_loc_13_load_reg_5288 <= in1_loc_13_q0;
+                in1_loc_14_load_reg_5293 <= in1_loc_14_q0;
+                in1_loc_15_load_reg_5298 <= in1_loc_15_q0;
+                in1_loc_16_load_reg_5303 <= in1_loc_16_q0;
+                in1_loc_17_load_reg_5308 <= in1_loc_17_q0;
+                in1_loc_18_load_reg_5313 <= in1_loc_18_q0;
+                in1_loc_19_load_reg_5318 <= in1_loc_19_q0;
+                in1_loc_1_load_reg_5228 <= in1_loc_1_q0;
+                in1_loc_20_load_reg_5323 <= in1_loc_20_q0;
+                in1_loc_21_load_reg_5328 <= in1_loc_21_q0;
+                in1_loc_22_load_reg_5333 <= in1_loc_22_q0;
+                in1_loc_23_load_reg_5338 <= in1_loc_23_q0;
+                in1_loc_24_load_reg_5343 <= in1_loc_24_q0;
+                in1_loc_25_load_reg_5348 <= in1_loc_25_q0;
+                in1_loc_26_load_reg_5353 <= in1_loc_26_q0;
+                in1_loc_27_load_reg_5358 <= in1_loc_27_q0;
+                in1_loc_28_load_reg_5363 <= in1_loc_28_q0;
+                in1_loc_29_load_reg_5368 <= in1_loc_29_q0;
+                in1_loc_2_load_reg_5233 <= in1_loc_2_q0;
+                in1_loc_30_load_reg_5373 <= in1_loc_30_q0;
+                in1_loc_31_load_reg_5378 <= in1_loc_31_q0;
+                in1_loc_32_load_reg_5383 <= in1_loc_32_q0;
+                in1_loc_33_load_reg_5388 <= in1_loc_33_q0;
+                in1_loc_34_load_reg_5393 <= in1_loc_34_q0;
+                in1_loc_35_load_reg_5398 <= in1_loc_35_q0;
+                in1_loc_36_load_reg_5403 <= in1_loc_36_q0;
+                in1_loc_37_load_reg_5408 <= in1_loc_37_q0;
+                in1_loc_38_load_reg_5413 <= in1_loc_38_q0;
+                in1_loc_39_load_reg_5418 <= in1_loc_39_q0;
+                in1_loc_3_load_reg_5238 <= in1_loc_3_q0;
+                in1_loc_40_load_reg_5423 <= in1_loc_40_q0;
+                in1_loc_43_load_reg_5438 <= in1_loc_43_q0;
+                in1_loc_44_load_reg_5443 <= in1_loc_44_q0;
+                in1_loc_47_load_reg_5458 <= in1_loc_47_q0;
+                in1_loc_48_load_reg_5463 <= in1_loc_48_q0;
+                in1_loc_49_load_reg_5468 <= in1_loc_49_q0;
+                in1_loc_4_load_reg_5243 <= in1_loc_4_q0;
+                in1_loc_50_load_reg_5473 <= in1_loc_50_q0;
+                in1_loc_51_load_reg_5478 <= in1_loc_51_q0;
+                in1_loc_52_load_reg_5483 <= in1_loc_52_q0;
+                in1_loc_53_load_reg_5488 <= in1_loc_53_q0;
+                in1_loc_54_load_reg_5493 <= in1_loc_54_q0;
+                in1_loc_55_load_reg_5498 <= in1_loc_55_q0;
+                in1_loc_56_load_reg_5503 <= in1_loc_56_q0;
+                in1_loc_59_load_reg_5518 <= in1_loc_59_q0;
+                in1_loc_5_load_reg_5248 <= in1_loc_5_q0;
+                in1_loc_60_load_reg_5523 <= in1_loc_60_q0;
+                in1_loc_62_load_reg_5533 <= in1_loc_62_q0;
+                in1_loc_63_load_reg_5538 <= in1_loc_63_q0;
+                in1_loc_6_load_reg_5253 <= in1_loc_6_q0;
+                in1_loc_7_load_reg_5258 <= in1_loc_7_q0;
+                in1_loc_8_load_reg_5263 <= in1_loc_8_q0;
+                in1_loc_9_load_reg_5268 <= in1_loc_9_q0;
+                in2_loc_0_load_reg_5543 <= in2_loc_0_q0;
+                in2_loc_10_load_reg_5593 <= in2_loc_10_q0;
+                in2_loc_11_load_reg_5598 <= in2_loc_11_q0;
+                in2_loc_12_load_reg_5603 <= in2_loc_12_q0;
+                in2_loc_13_load_reg_5608 <= in2_loc_13_q0;
+                in2_loc_14_load_reg_5613 <= in2_loc_14_q0;
+                in2_loc_15_load_reg_5618 <= in2_loc_15_q0;
+                in2_loc_16_load_reg_5623 <= in2_loc_16_q0;
+                in2_loc_17_load_reg_5628 <= in2_loc_17_q0;
+                in2_loc_18_load_reg_5633 <= in2_loc_18_q0;
+                in2_loc_19_load_reg_5638 <= in2_loc_19_q0;
+                in2_loc_1_load_reg_5548 <= in2_loc_1_q0;
+                in2_loc_20_load_reg_5643 <= in2_loc_20_q0;
+                in2_loc_21_load_reg_5648 <= in2_loc_21_q0;
+                in2_loc_22_load_reg_5653 <= in2_loc_22_q0;
+                in2_loc_23_load_reg_5658 <= in2_loc_23_q0;
+                in2_loc_24_load_reg_5663 <= in2_loc_24_q0;
+                in2_loc_25_load_reg_5668 <= in2_loc_25_q0;
+                in2_loc_26_load_reg_5673 <= in2_loc_26_q0;
+                in2_loc_27_load_reg_5678 <= in2_loc_27_q0;
+                in2_loc_28_load_reg_5683 <= in2_loc_28_q0;
+                in2_loc_29_load_reg_5688 <= in2_loc_29_q0;
+                in2_loc_2_load_reg_5553 <= in2_loc_2_q0;
+                in2_loc_30_load_reg_5693 <= in2_loc_30_q0;
+                in2_loc_31_load_reg_5698 <= in2_loc_31_q0;
+                in2_loc_32_load_reg_5703 <= in2_loc_32_q0;
+                in2_loc_33_load_reg_5708 <= in2_loc_33_q0;
+                in2_loc_34_load_reg_5713 <= in2_loc_34_q0;
+                in2_loc_35_load_reg_5718 <= in2_loc_35_q0;
+                in2_loc_36_load_reg_5723 <= in2_loc_36_q0;
+                in2_loc_37_load_reg_5728 <= in2_loc_37_q0;
+                in2_loc_38_load_reg_5733 <= in2_loc_38_q0;
+                in2_loc_39_load_reg_5738 <= in2_loc_39_q0;
+                in2_loc_3_load_reg_5558 <= in2_loc_3_q0;
+                in2_loc_40_load_reg_5743 <= in2_loc_40_q0;
+                in2_loc_43_load_reg_5758 <= in2_loc_43_q0;
+                in2_loc_44_load_reg_5763 <= in2_loc_44_q0;
+                in2_loc_47_load_reg_5778 <= in2_loc_47_q0;
+                in2_loc_48_load_reg_5783 <= in2_loc_48_q0;
+                in2_loc_49_load_reg_5788 <= in2_loc_49_q0;
+                in2_loc_4_load_reg_5563 <= in2_loc_4_q0;
+                in2_loc_50_load_reg_5793 <= in2_loc_50_q0;
+                in2_loc_51_load_reg_5798 <= in2_loc_51_q0;
+                in2_loc_52_load_reg_5803 <= in2_loc_52_q0;
+                in2_loc_53_load_reg_5808 <= in2_loc_53_q0;
+                in2_loc_54_load_reg_5813 <= in2_loc_54_q0;
+                in2_loc_55_load_reg_5818 <= in2_loc_55_q0;
+                in2_loc_56_load_reg_5823 <= in2_loc_56_q0;
+                in2_loc_59_load_reg_5838 <= in2_loc_59_q0;
+                in2_loc_5_load_reg_5568 <= in2_loc_5_q0;
+                in2_loc_60_load_reg_5843 <= in2_loc_60_q0;
+                in2_loc_62_load_reg_5853 <= in2_loc_62_q0;
+                in2_loc_63_load_reg_5858 <= in2_loc_63_q0;
+                in2_loc_6_load_reg_5573 <= in2_loc_6_q0;
+                in2_loc_7_load_reg_5578 <= in2_loc_7_q0;
+                in2_loc_8_load_reg_5583 <= in2_loc_8_q0;
+                in2_loc_9_load_reg_5588 <= in2_loc_9_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4606_pp2_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then
+                in1_loc_41_load_reg_5863 <= in1_loc_41_q0;
+                in1_loc_42_load_reg_5868 <= in1_loc_42_q0;
+                in1_loc_45_load_reg_5873 <= in1_loc_45_q0;
+                in1_loc_46_load_reg_5878 <= in1_loc_46_q0;
+                in1_loc_57_load_reg_5883 <= in1_loc_57_q0;
+                in1_loc_58_load_reg_5888 <= in1_loc_58_q0;
+                in1_loc_61_load_reg_5893 <= in1_loc_61_q0;
+                in2_loc_41_load_reg_6103 <= in2_loc_41_q0;
+                in2_loc_42_load_reg_6108 <= in2_loc_42_q0;
+                in2_loc_45_load_reg_6123 <= in2_loc_45_q0;
+                in2_loc_46_load_reg_6128 <= in2_loc_46_q0;
+                in2_loc_57_load_reg_6183 <= in2_loc_57_q0;
+                in2_loc_58_load_reg_6188 <= in2_loc_58_q0;
+                in2_loc_61_load_reg_6203 <= in2_loc_61_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                in1_mem_addr_read_reg_4447 <= in1_mem_RDATA;
+                lshr_ln_reg_4438_pp0_iter1_reg <= lshr_ln_reg_4438;
+                trunc_ln27_reg_4443_pp0_iter1_reg <= trunc_ln27_reg_4443;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                in2_mem_addr_read_reg_4533 <= in2_mem_RDATA;
+                trunc_ln1_reg_4529_pp1_iter1_reg <= trunc_ln1_reg_4529;
+                trunc_ln28_reg_4524_pp1_iter1_reg <= trunc_ln28_reg_4524;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
+                    in2_mem_addr_reg_4423(29 downto 0) <= empty_7_fu_3411_p1(32 - 1 downto 0)(29 downto 0);
+                    out_mem_addr_reg_4417(29 downto 0) <= empty_fu_3402_p1(32 - 1 downto 0)(29 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_fu_3420_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                lshr_ln_reg_4438 <= phi_ln27_reg_3296(12 downto 6);
+                trunc_ln27_reg_4443 <= trunc_ln27_fu_3442_p1;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state22)) then
+                mul_ln31_reg_4601 <= mul_ln31_fu_3609_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4606_pp2_iter1_reg = ap_const_lv1_0))) then
+                mul_ln38_10_reg_5948 <= mul_ln38_10_fu_3848_p2;
+                mul_ln38_11_reg_5953 <= mul_ln38_11_fu_3852_p2;
+                mul_ln38_12_reg_5958 <= mul_ln38_12_fu_3856_p2;
+                mul_ln38_13_reg_5963 <= mul_ln38_13_fu_3860_p2;
+                mul_ln38_14_reg_5968 <= mul_ln38_14_fu_3864_p2;
+                mul_ln38_15_reg_5973 <= mul_ln38_15_fu_3868_p2;
+                mul_ln38_16_reg_5978 <= mul_ln38_16_fu_3872_p2;
+                mul_ln38_17_reg_5983 <= mul_ln38_17_fu_3876_p2;
+                mul_ln38_18_reg_5988 <= mul_ln38_18_fu_3880_p2;
+                mul_ln38_19_reg_5993 <= mul_ln38_19_fu_3884_p2;
+                mul_ln38_1_reg_5903 <= mul_ln38_1_fu_3812_p2;
+                mul_ln38_20_reg_5998 <= mul_ln38_20_fu_3888_p2;
+                mul_ln38_21_reg_6003 <= mul_ln38_21_fu_3892_p2;
+                mul_ln38_22_reg_6008 <= mul_ln38_22_fu_3896_p2;
+                mul_ln38_23_reg_6013 <= mul_ln38_23_fu_3900_p2;
+                mul_ln38_24_reg_6018 <= mul_ln38_24_fu_3904_p2;
+                mul_ln38_25_reg_6023 <= mul_ln38_25_fu_3908_p2;
+                mul_ln38_26_reg_6028 <= mul_ln38_26_fu_3912_p2;
+                mul_ln38_27_reg_6033 <= mul_ln38_27_fu_3916_p2;
+                mul_ln38_28_reg_6038 <= mul_ln38_28_fu_3920_p2;
+                mul_ln38_29_reg_6043 <= mul_ln38_29_fu_3924_p2;
+                mul_ln38_2_reg_5908 <= mul_ln38_2_fu_3816_p2;
+                mul_ln38_30_reg_6048 <= mul_ln38_30_fu_3928_p2;
+                mul_ln38_31_reg_6053 <= mul_ln38_31_fu_3932_p2;
+                mul_ln38_32_reg_6058 <= mul_ln38_32_fu_3936_p2;
+                mul_ln38_33_reg_6063 <= mul_ln38_33_fu_3940_p2;
+                mul_ln38_34_reg_6068 <= mul_ln38_34_fu_3944_p2;
+                mul_ln38_35_reg_6073 <= mul_ln38_35_fu_3948_p2;
+                mul_ln38_36_reg_6078 <= mul_ln38_36_fu_3952_p2;
+                mul_ln38_37_reg_6083 <= mul_ln38_37_fu_3956_p2;
+                mul_ln38_38_reg_6088 <= mul_ln38_38_fu_3960_p2;
+                mul_ln38_39_reg_6093 <= mul_ln38_39_fu_3964_p2;
+                mul_ln38_3_reg_5913 <= mul_ln38_3_fu_3820_p2;
+                mul_ln38_40_reg_6098 <= mul_ln38_40_fu_3968_p2;
+                mul_ln38_43_reg_6113 <= mul_ln38_43_fu_3972_p2;
+                mul_ln38_44_reg_6118 <= mul_ln38_44_fu_3976_p2;
+                mul_ln38_47_reg_6133 <= mul_ln38_47_fu_3980_p2;
+                mul_ln38_48_reg_6138 <= mul_ln38_48_fu_3984_p2;
+                mul_ln38_49_reg_6143 <= mul_ln38_49_fu_3988_p2;
+                mul_ln38_4_reg_5918 <= mul_ln38_4_fu_3824_p2;
+                mul_ln38_50_reg_6148 <= mul_ln38_50_fu_3992_p2;
+                mul_ln38_51_reg_6153 <= mul_ln38_51_fu_3996_p2;
+                mul_ln38_52_reg_6158 <= mul_ln38_52_fu_4000_p2;
+                mul_ln38_53_reg_6163 <= mul_ln38_53_fu_4004_p2;
+                mul_ln38_54_reg_6168 <= mul_ln38_54_fu_4008_p2;
+                mul_ln38_55_reg_6173 <= mul_ln38_55_fu_4012_p2;
+                mul_ln38_56_reg_6178 <= mul_ln38_56_fu_4016_p2;
+                mul_ln38_59_reg_6193 <= mul_ln38_59_fu_4020_p2;
+                mul_ln38_5_reg_5923 <= mul_ln38_5_fu_3828_p2;
+                mul_ln38_60_reg_6198 <= mul_ln38_60_fu_4024_p2;
+                mul_ln38_62_reg_6208 <= mul_ln38_62_fu_4028_p2;
+                mul_ln38_63_reg_6213 <= mul_ln38_63_fu_4032_p2;
+                mul_ln38_6_reg_5928 <= mul_ln38_6_fu_3832_p2;
+                mul_ln38_7_reg_5933 <= mul_ln38_7_fu_3836_p2;
+                mul_ln38_8_reg_5938 <= mul_ln38_8_fu_3840_p2;
+                mul_ln38_9_reg_5943 <= mul_ln38_9_fu_3844_p2;
+                mul_ln38_reg_5898 <= mul_ln38_fu_3808_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                out_loc_addr_reg_4927 <= zext_ln38_fu_3797_p1(12 - 1 downto 0);
+                sext_ln38_reg_4916 <= sext_ln38_fu_3726_p1;
+                    zext_ln31_1_reg_4620(30 downto 0) <= zext_ln31_1_fu_3665_p1(30 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((icmp_ln42_reg_6313 = ap_const_lv1_0) and (ap_enable_reg_pp3_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_const_boolean_0 = ap_block_pp3_stage0_11001))) then
+                out_loc_load_reg_6327 <= out_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                select_ln31_1_reg_4615 <= select_ln31_1_fu_3645_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_fu_3513_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                trunc_ln1_reg_4529 <= phi_ln28_reg_3307(11 downto 6);
+                trunc_ln28_reg_4524 <= trunc_ln28_fu_3525_p1;
+            end if;
+        end if;
+    end process;
+    out_mem_addr_reg_4417(31 downto 30) <= "00";
+    in2_mem_addr_reg_4423(31 downto 30) <= "00";
+    zext_ln31_1_reg_4620(63 downto 31) <= "000000000000000000000000000000000";
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_enable_reg_pp0_iter1, ap_CS_fsm_state12, ap_enable_reg_pp1_iter1, ap_CS_fsm_state28, ap_enable_reg_pp3_iter2, ap_CS_fsm_state36, in1_mem_ARREADY, in2_mem_ARREADY, out_mem_AWREADY, out_mem_BVALID, icmp_ln27_fu_3420_p2, ap_enable_reg_pp0_iter0, icmp_ln28_fu_3513_p2, ap_enable_reg_pp1_iter0, icmp_ln31_fu_3615_p2, ap_enable_reg_pp2_iter0, ap_enable_reg_pp2_iter1, icmp_ln42_fu_4373_p2, ap_enable_reg_pp3_iter0, ap_enable_reg_pp3_iter1, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter2, ap_block_pp1_stage0_subdone, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0_subdone, ap_enable_reg_pp2_iter3, ap_enable_reg_pp2_iter4, ap_block_pp3_stage0_subdone)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when ap_ST_fsm_state3 => 
+                ap_NS_fsm <= ap_ST_fsm_state4;
+            when ap_ST_fsm_state4 => 
+                ap_NS_fsm <= ap_ST_fsm_state5;
+            when ap_ST_fsm_state5 => 
+                ap_NS_fsm <= ap_ST_fsm_state6;
+            when ap_ST_fsm_state6 => 
+                ap_NS_fsm <= ap_ST_fsm_state7;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state8;
+            when ap_ST_fsm_state8 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((icmp_ln27_fu_3420_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) and not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((icmp_ln27_fu_3420_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state12 => 
+                if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then
+                    ap_NS_fsm <= ap_ST_fsm_state13;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                end if;
+            when ap_ST_fsm_state13 => 
+                ap_NS_fsm <= ap_ST_fsm_state14;
+            when ap_ST_fsm_state14 => 
+                ap_NS_fsm <= ap_ST_fsm_state15;
+            when ap_ST_fsm_state15 => 
+                ap_NS_fsm <= ap_ST_fsm_state16;
+            when ap_ST_fsm_state16 => 
+                ap_NS_fsm <= ap_ST_fsm_state17;
+            when ap_ST_fsm_state17 => 
+                ap_NS_fsm <= ap_ST_fsm_state18;
+            when ap_ST_fsm_state18 => 
+                ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+            when ap_ST_fsm_pp1_stage0 => 
+                if ((not(((icmp_ln28_fu_3513_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) and not(((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                elsif ((((icmp_ln28_fu_3513_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) or ((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state22;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                end if;
+            when ap_ST_fsm_state22 => 
+                ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+            when ap_ST_fsm_pp2_stage0 => 
+                if ((not(((ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))) and not(((ap_enable_reg_pp2_iter4 = ap_const_logic_1) and (ap_enable_reg_pp2_iter3 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                elsif ((((ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (icmp_ln31_fu_3615_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) or ((ap_enable_reg_pp2_iter4 = ap_const_logic_1) and (ap_enable_reg_pp2_iter3 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state28;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                end if;
+            when ap_ST_fsm_state28 => 
+                if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state28))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state28;
+                end if;
+            when ap_ST_fsm_pp3_stage0 => 
+                if ((not(((ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (icmp_ln42_fu_4373_p2 = ap_const_lv1_1))) and not(((ap_enable_reg_pp3_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                elsif ((((ap_enable_reg_pp3_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0)) or ((ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (icmp_ln42_fu_4373_p2 = ap_const_lv1_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state32;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                end if;
+            when ap_ST_fsm_state32 => 
+                ap_NS_fsm <= ap_ST_fsm_state33;
+            when ap_ST_fsm_state33 => 
+                ap_NS_fsm <= ap_ST_fsm_state34;
+            when ap_ST_fsm_state34 => 
+                ap_NS_fsm <= ap_ST_fsm_state35;
+            when ap_ST_fsm_state35 => 
+                ap_NS_fsm <= ap_ST_fsm_state36;
+            when ap_ST_fsm_state36 => 
+                if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state36))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state36;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXX";
+        end case;
+    end process;
+    add_ln27_fu_3426_p2 <= std_logic_vector(unsigned(phi_ln27_reg_3296) + unsigned(ap_const_lv13_1));
+    add_ln28_fu_3519_p2 <= std_logic_vector(unsigned(phi_ln28_reg_3307) + unsigned(ap_const_lv13_1));
+    add_ln31_fu_3620_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_3318) + unsigned(ap_const_lv64_1));
+    add_ln38_10_fu_4113_p2 <= std_logic_vector(unsigned(mul_ln38_12_reg_5958) + unsigned(mul_ln38_11_reg_5953));
+    add_ln38_11_fu_4117_p2 <= std_logic_vector(unsigned(mul_ln38_14_reg_5968) + unsigned(mul_ln38_13_reg_5963));
+    add_ln38_12_fu_4121_p2 <= std_logic_vector(unsigned(add_ln38_10_fu_4113_p2) + unsigned(add_ln38_11_fu_4117_p2));
+    add_ln38_13_fu_4283_p2 <= std_logic_vector(unsigned(add_ln38_9_reg_6258) + unsigned(add_ln38_12_reg_6263));
+    add_ln38_14_fu_4287_p2 <= std_logic_vector(unsigned(add_ln38_6_reg_6253) + unsigned(add_ln38_13_fu_4283_p2));
+    add_ln38_15_fu_4127_p2 <= std_logic_vector(unsigned(mul_ln38_16_reg_5978) + unsigned(mul_ln38_15_reg_5973));
+    add_ln38_16_fu_4131_p2 <= std_logic_vector(unsigned(mul_ln38_18_reg_5988) + unsigned(mul_ln38_17_reg_5983));
+    add_ln38_17_fu_4135_p2 <= std_logic_vector(unsigned(add_ln38_15_fu_4127_p2) + unsigned(add_ln38_16_fu_4131_p2));
+    add_ln38_18_fu_4141_p2 <= std_logic_vector(unsigned(mul_ln38_20_reg_5998) + unsigned(mul_ln38_19_reg_5993));
+    add_ln38_19_fu_4145_p2 <= std_logic_vector(unsigned(mul_ln38_22_reg_6008) + unsigned(mul_ln38_21_reg_6003));
+    add_ln38_1_fu_4069_p2 <= std_logic_vector(unsigned(mul_ln38_2_reg_5908) + unsigned(mul_ln38_1_reg_5903));
+    add_ln38_20_fu_4149_p2 <= std_logic_vector(unsigned(add_ln38_18_fu_4141_p2) + unsigned(add_ln38_19_fu_4145_p2));
+    add_ln38_21_fu_4155_p2 <= std_logic_vector(unsigned(add_ln38_17_fu_4135_p2) + unsigned(add_ln38_20_fu_4149_p2));
+    add_ln38_22_fu_4161_p2 <= std_logic_vector(unsigned(mul_ln38_24_reg_6018) + unsigned(mul_ln38_23_reg_6013));
+    add_ln38_23_fu_4165_p2 <= std_logic_vector(unsigned(mul_ln38_26_reg_6028) + unsigned(mul_ln38_25_reg_6023));
+    add_ln38_24_fu_4169_p2 <= std_logic_vector(unsigned(add_ln38_22_fu_4161_p2) + unsigned(add_ln38_23_fu_4165_p2));
+    add_ln38_25_fu_4175_p2 <= std_logic_vector(unsigned(mul_ln38_28_reg_6038) + unsigned(mul_ln38_27_reg_6033));
+    add_ln38_26_fu_4179_p2 <= std_logic_vector(unsigned(mul_ln38_30_reg_6048) + unsigned(mul_ln38_29_reg_6043));
+    add_ln38_27_fu_4183_p2 <= std_logic_vector(unsigned(add_ln38_25_fu_4175_p2) + unsigned(add_ln38_26_fu_4179_p2));
+    add_ln38_28_fu_4189_p2 <= std_logic_vector(unsigned(add_ln38_24_fu_4169_p2) + unsigned(add_ln38_27_fu_4183_p2));
+    add_ln38_29_fu_4292_p2 <= std_logic_vector(unsigned(add_ln38_21_reg_6268) + unsigned(add_ln38_28_reg_6273));
+    add_ln38_2_fu_4073_p2 <= std_logic_vector(unsigned(add_ln38_fu_4064_p2) + unsigned(add_ln38_1_fu_4069_p2));
+    add_ln38_30_fu_4296_p2 <= std_logic_vector(unsigned(add_ln38_14_fu_4287_p2) + unsigned(add_ln38_29_fu_4292_p2));
+    add_ln38_31_fu_4195_p2 <= std_logic_vector(unsigned(mul_ln38_32_reg_6058) + unsigned(mul_ln38_31_reg_6053));
+    add_ln38_32_fu_4199_p2 <= std_logic_vector(unsigned(mul_ln38_34_reg_6068) + unsigned(mul_ln38_33_reg_6063));
+    add_ln38_33_fu_4203_p2 <= std_logic_vector(unsigned(add_ln38_31_fu_4195_p2) + unsigned(add_ln38_32_fu_4199_p2));
+    add_ln38_34_fu_4209_p2 <= std_logic_vector(unsigned(mul_ln38_36_reg_6078) + unsigned(mul_ln38_35_reg_6073));
+    add_ln38_35_fu_4213_p2 <= std_logic_vector(unsigned(mul_ln38_38_reg_6088) + unsigned(mul_ln38_37_reg_6083));
+    add_ln38_36_fu_4217_p2 <= std_logic_vector(unsigned(add_ln38_34_fu_4209_p2) + unsigned(add_ln38_35_fu_4213_p2));
+    add_ln38_37_fu_4223_p2 <= std_logic_vector(unsigned(add_ln38_33_fu_4203_p2) + unsigned(add_ln38_36_fu_4217_p2));
+    add_ln38_38_fu_4229_p2 <= std_logic_vector(unsigned(mul_ln38_40_reg_6098) + unsigned(mul_ln38_39_reg_6093));
+    add_ln38_39_fu_4302_p2 <= std_logic_vector(unsigned(mul_ln38_42_reg_6223) + unsigned(mul_ln38_41_reg_6218));
+    add_ln38_3_fu_4079_p2 <= std_logic_vector(unsigned(mul_ln38_4_reg_5918) + unsigned(mul_ln38_3_reg_5913));
+    add_ln38_40_fu_4306_p2 <= std_logic_vector(unsigned(add_ln38_38_reg_6283) + unsigned(add_ln38_39_fu_4302_p2));
+    add_ln38_41_fu_4233_p2 <= std_logic_vector(unsigned(mul_ln38_44_reg_6118) + unsigned(mul_ln38_43_reg_6113));
+    add_ln38_42_fu_4311_p2 <= std_logic_vector(unsigned(mul_ln38_46_reg_6233) + unsigned(mul_ln38_45_reg_6228));
+    add_ln38_43_fu_4315_p2 <= std_logic_vector(unsigned(add_ln38_41_reg_6288) + unsigned(add_ln38_42_fu_4311_p2));
+    add_ln38_44_fu_4320_p2 <= std_logic_vector(unsigned(add_ln38_40_fu_4306_p2) + unsigned(add_ln38_43_fu_4315_p2));
+    add_ln38_45_fu_4326_p2 <= std_logic_vector(unsigned(add_ln38_37_reg_6278) + unsigned(add_ln38_44_fu_4320_p2));
+    add_ln38_46_fu_4237_p2 <= std_logic_vector(unsigned(mul_ln38_48_reg_6138) + unsigned(mul_ln38_47_reg_6133));
+    add_ln38_47_fu_4241_p2 <= std_logic_vector(unsigned(mul_ln38_50_reg_6148) + unsigned(mul_ln38_49_reg_6143));
+    add_ln38_48_fu_4245_p2 <= std_logic_vector(unsigned(add_ln38_46_fu_4237_p2) + unsigned(add_ln38_47_fu_4241_p2));
+    add_ln38_49_fu_4251_p2 <= std_logic_vector(unsigned(mul_ln38_52_reg_6158) + unsigned(mul_ln38_51_reg_6153));
+    add_ln38_4_fu_4083_p2 <= std_logic_vector(unsigned(mul_ln38_6_reg_5928) + unsigned(mul_ln38_5_reg_5923));
+    add_ln38_50_fu_4255_p2 <= std_logic_vector(unsigned(mul_ln38_54_reg_6168) + unsigned(mul_ln38_53_reg_6163));
+    add_ln38_51_fu_4259_p2 <= std_logic_vector(unsigned(add_ln38_49_fu_4251_p2) + unsigned(add_ln38_50_fu_4255_p2));
+    add_ln38_52_fu_4265_p2 <= std_logic_vector(unsigned(add_ln38_48_fu_4245_p2) + unsigned(add_ln38_51_fu_4259_p2));
+    add_ln38_53_fu_4271_p2 <= std_logic_vector(unsigned(mul_ln38_56_reg_6178) + unsigned(mul_ln38_55_reg_6173));
+    add_ln38_54_fu_4331_p2 <= std_logic_vector(unsigned(mul_ln38_58_reg_6243) + unsigned(mul_ln38_57_reg_6238));
+    add_ln38_55_fu_4335_p2 <= std_logic_vector(unsigned(add_ln38_53_reg_6298) + unsigned(add_ln38_54_fu_4331_p2));
+    add_ln38_56_fu_4275_p2 <= std_logic_vector(unsigned(mul_ln38_60_reg_6198) + unsigned(mul_ln38_59_reg_6193));
+    add_ln38_57_fu_4279_p2 <= std_logic_vector(unsigned(mul_ln38_63_reg_6213) + unsigned(mul_ln38_62_reg_6208));
+    add_ln38_58_fu_4340_p2 <= std_logic_vector(unsigned(mul_ln38_61_reg_6248) + unsigned(add_ln38_57_reg_6308));
+    add_ln38_59_fu_4344_p2 <= std_logic_vector(unsigned(add_ln38_56_reg_6303) + unsigned(add_ln38_58_fu_4340_p2));
+    add_ln38_5_fu_4087_p2 <= std_logic_vector(unsigned(add_ln38_3_fu_4079_p2) + unsigned(add_ln38_4_fu_4083_p2));
+    add_ln38_60_fu_4349_p2 <= std_logic_vector(unsigned(add_ln38_55_fu_4335_p2) + unsigned(add_ln38_59_fu_4344_p2));
+    add_ln38_61_fu_4355_p2 <= std_logic_vector(unsigned(add_ln38_52_reg_6293) + unsigned(add_ln38_60_fu_4349_p2));
+    add_ln38_62_fu_4360_p2 <= std_logic_vector(unsigned(add_ln38_45_fu_4326_p2) + unsigned(add_ln38_61_fu_4355_p2));
+    add_ln38_64_fu_3791_p2 <= std_logic_vector(unsigned(tmp_cast_fu_3657_p3) + unsigned(trunc_ln38_1_fu_3787_p1));
+    add_ln38_6_fu_4093_p2 <= std_logic_vector(unsigned(add_ln38_2_fu_4073_p2) + unsigned(add_ln38_5_fu_4087_p2));
+    add_ln38_7_fu_4099_p2 <= std_logic_vector(unsigned(mul_ln38_8_reg_5938) + unsigned(mul_ln38_7_reg_5933));
+    add_ln38_8_fu_4103_p2 <= std_logic_vector(unsigned(mul_ln38_10_reg_5948) + unsigned(mul_ln38_9_reg_5943));
+    add_ln38_9_fu_4107_p2 <= std_logic_vector(unsigned(add_ln38_7_fu_4099_p2) + unsigned(add_ln38_8_fu_4103_p2));
+    add_ln38_fu_4064_p2 <= std_logic_vector(unsigned(mul_ln38_reg_5898) + unsigned(out_loc_q0));
+    add_ln42_fu_4379_p2 <= std_logic_vector(unsigned(phi_ln42_reg_3351) + unsigned(ap_const_lv13_1));
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(8);
+    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(16);
+    ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(18);
+    ap_CS_fsm_pp3_stage0 <= ap_CS_fsm(20);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state12 <= ap_CS_fsm(9);
+    ap_CS_fsm_state18 <= ap_CS_fsm(15);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state22 <= ap_CS_fsm(17);
+    ap_CS_fsm_state28 <= ap_CS_fsm(19);
+    ap_CS_fsm_state36 <= ap_CS_fsm(25);
+    ap_CS_fsm_state8 <= ap_CS_fsm(7);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_11001_assign_proc : process(ap_enable_reg_pp0_iter1, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_11001 <= ((in1_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(ap_enable_reg_pp0_iter1, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_subdone <= ((in1_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp1_stage0_11001_assign_proc : process(ap_enable_reg_pp1_iter1, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_11001 <= ((in2_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp1_stage0_subdone_assign_proc : process(ap_enable_reg_pp1_iter1, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_subdone <= ((in2_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp2_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp2_stage0_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp3_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp3_stage0_01001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp3_stage0_11001_assign_proc : process(ap_enable_reg_pp3_iter2, ap_block_state31_io)
+    begin
+                ap_block_pp3_stage0_11001 <= ((ap_const_boolean_1 = ap_block_state31_io) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp3_stage0_subdone_assign_proc : process(ap_enable_reg_pp3_iter2, ap_block_state31_io)
+    begin
+                ap_block_pp3_stage0_subdone <= ((ap_const_boolean_1 = ap_block_state31_io) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state10_pp0_stage0_iter1_assign_proc : process(in1_mem_RVALID)
+    begin
+                ap_block_state10_pp0_stage0_iter1 <= (in1_mem_RVALID = ap_const_logic_0);
+    end process;
+
+        ap_block_state11_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state19_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state20_pp1_stage0_iter1_assign_proc : process(in2_mem_RVALID)
+    begin
+                ap_block_state20_pp1_stage0_iter1 <= (in2_mem_RVALID = ap_const_logic_0);
+    end process;
+
+        ap_block_state21_pp1_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state23_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state24_pp2_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state25_pp2_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state26_pp2_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state27_pp2_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state29_pp3_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state30_pp3_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state31_io_assign_proc : process(icmp_ln42_reg_6313_pp3_iter1_reg, out_mem_WREADY)
+    begin
+                ap_block_state31_io <= ((out_mem_WREADY = ap_const_logic_0) and (icmp_ln42_reg_6313_pp3_iter1_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state31_pp3_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state9_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state9_assign_proc : process(icmp_ln27_fu_3420_p2)
+    begin
+        if ((icmp_ln27_fu_3420_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp1_exit_iter0_state19_assign_proc : process(icmp_ln28_fu_3513_p2)
+    begin
+        if ((icmp_ln28_fu_3513_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_1;
+        else 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp2_exit_iter0_state23_assign_proc : process(icmp_ln31_fu_3615_p2)
+    begin
+        if ((icmp_ln31_fu_3615_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp2_exit_iter0_state23 <= ap_const_logic_1;
+        else 
+            ap_condition_pp2_exit_iter0_state23 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp3_exit_iter0_state29_assign_proc : process(icmp_ln42_fu_4373_p2)
+    begin
+        if ((icmp_ln42_fu_4373_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp3_exit_iter0_state29 <= ap_const_logic_1;
+        else 
+            ap_condition_pp3_exit_iter0_state29 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_CS_fsm_state36, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state36))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
+    ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
+    ap_enable_pp3 <= (ap_idle_pp3 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp1 <= ap_const_logic_1;
+        else 
+            ap_idle_pp1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter0, ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter2, ap_enable_reg_pp2_iter3, ap_enable_reg_pp2_iter4)
+    begin
+        if (((ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter4 = ap_const_logic_0) and (ap_enable_reg_pp2_iter3 = ap_const_logic_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp2 <= ap_const_logic_1;
+        else 
+            ap_idle_pp2 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp3_assign_proc : process(ap_enable_reg_pp3_iter2, ap_enable_reg_pp3_iter0, ap_enable_reg_pp3_iter1)
+    begin
+        if (((ap_enable_reg_pp3_iter2 = ap_const_logic_0) and (ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_0))) then 
+            ap_idle_pp3 <= ap_const_logic_1;
+        else 
+            ap_idle_pp3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_i_0_phi_fu_3333_p4_assign_proc : process(i_0_reg_3329, icmp_ln31_reg_4606, ap_CS_fsm_pp2_stage0, select_ln31_1_reg_4615, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0)
+    begin
+        if (((icmp_ln31_reg_4606 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            ap_phi_mux_i_0_phi_fu_3333_p4 <= select_ln31_1_reg_4615;
+        else 
+            ap_phi_mux_i_0_phi_fu_3333_p4 <= i_0_reg_3329;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state36, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state36))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    empty_7_fu_3411_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in_reg_4401),64));
+    empty_8_fu_3392_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in3_reg_4406),64));
+    empty_fu_3402_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(out5_reg_4396),64));
+    i_fu_3626_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(ap_phi_mux_i_0_phi_fu_3333_p4));
+    icmp_ln27_fu_3420_p2 <= "1" when (phi_ln27_reg_3296 = ap_const_lv13_1000) else "0";
+    icmp_ln28_fu_3513_p2 <= "1" when (phi_ln28_reg_3307 = ap_const_lv13_1000) else "0";
+    icmp_ln31_fu_3615_p2 <= "1" when (indvar_flatten_reg_3318 = mul_ln31_reg_4601) else "0";
+    icmp_ln33_fu_3632_p2 <= "1" when (j_0_reg_3340 = dim_read_reg_4390) else "0";
+    icmp_ln42_fu_4373_p2 <= "1" when (phi_ln42_reg_3351 = ap_const_lv13_1000) else "0";
+
+    in1_loc_0_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_0_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_0_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_0_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_0_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_0_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_0_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_0_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_0_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_10_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_10_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_10_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_10_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_10_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_10_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_10_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_10_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_11_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_11_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_11_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_11_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_11_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_11_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_11_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_11_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_11_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_11_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_12_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_12_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_12_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_12_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_12_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_12_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_12_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_12_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_12_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_12_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_13_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_13_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_13_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_13_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_13_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_13_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_13_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_13_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_14_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_14_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_14_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_14_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_14_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_14_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_14_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_14_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_15_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_15_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_15_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_15_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_15_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_15_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_15_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_15_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_15_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_15_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_16_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_16_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_16_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_16_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_16_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_16_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_16_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_16_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_10) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_16_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_16_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_17_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_17_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_17_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_17_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_17_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_17_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_17_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_11) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_17_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_18_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_18_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_18_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_18_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_18_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_18_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_18_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_12) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_18_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_19_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_19_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_19_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_19_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_19_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_19_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_19_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_19_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_13) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_19_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_19_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_1_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_1_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_1_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_1_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_1_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_1_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_1_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_1_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_1_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_20_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_20_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_20_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_20_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_20_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_20_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_20_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_20_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_14) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_20_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_20_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_21_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_21_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_21_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_21_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_21_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_21_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_21_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_21_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_15) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_21_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_21_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_22_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_22_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_22_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_22_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_22_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_22_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_22_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_22_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_16) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_22_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_22_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_23_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_23_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_23_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_23_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_23_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_23_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_23_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_23_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_17) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_23_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_23_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_24_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_24_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_24_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_24_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_24_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_24_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_24_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_24_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_18) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_24_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_24_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_25_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_25_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_25_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_25_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_25_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_25_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_25_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_19) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_25_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_26_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_26_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_26_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_26_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_26_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_26_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_26_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_1A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_26_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_27_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_27_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_27_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_27_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_27_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_27_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_27_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_27_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_1B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_27_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_27_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_28_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_28_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_28_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_28_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_28_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_28_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_28_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_28_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_1C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_28_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_28_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_29_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_29_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_29_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_29_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_29_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_29_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_29_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_29_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_1D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_29_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_29_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_2_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_2_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_2_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_2_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_2_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_2_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_2) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_2_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_2_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_30_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_30_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_30_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_30_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_30_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_30_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_30_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_30_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_1E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_30_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_30_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_31_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_31_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_31_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_31_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_31_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_31_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_31_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_31_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_1F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_31_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_31_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_32_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_32_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_32_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_32_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_32_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_32_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_32_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_32_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_20) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_32_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_32_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_33_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_33_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_33_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_33_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_33_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_33_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_33_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_21) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_33_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_34_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_34_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_34_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_34_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_34_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_34_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_34_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_22) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_34_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_35_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_35_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_35_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_35_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_35_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_35_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_35_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_35_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_23) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_35_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_35_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_36_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_36_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_36_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_36_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_36_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_36_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_36_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_36_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_24) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_36_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_36_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_37_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_37_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_37_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_37_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_37_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_37_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_37_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_37_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_25) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_37_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_37_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_38_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_38_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_38_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_38_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_38_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_38_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_38_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_38_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_26) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_38_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_38_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_39_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_39_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_39_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_39_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_39_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_39_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_39_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_39_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_27) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_39_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_39_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_3_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_3_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_3_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_3_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_3_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_3_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_3_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_3) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_3_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_3_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_40_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_40_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_40_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_40_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_40_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_40_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_40_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_40_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_28) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_40_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_40_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_41_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_reg_4620, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_41_address0 <= zext_ln31_1_reg_4620(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_41_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_41_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_41_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_41_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_41_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_29) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_41_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_42_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_reg_4620, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_42_address0 <= zext_ln31_1_reg_4620(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_42_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_42_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_42_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_42_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_42_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_2A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_42_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_43_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_43_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_43_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_43_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_43_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_43_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_43_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_43_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_2B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_43_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_43_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_44_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_44_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_44_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_44_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_44_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_44_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_44_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_44_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_2C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_44_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_44_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_45_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_reg_4620, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_45_address0 <= zext_ln31_1_reg_4620(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_45_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_45_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_45_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_45_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_45_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_2D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_45_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_46_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_reg_4620, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_46_address0 <= zext_ln31_1_reg_4620(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_46_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_46_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_46_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_46_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_46_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_2E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_46_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_47_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_47_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_47_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_47_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_47_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_47_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_47_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_47_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_2F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_47_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_47_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_48_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_48_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_48_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_48_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_48_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_48_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_48_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_48_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_30) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_48_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_48_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_49_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_49_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_49_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_49_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_49_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_49_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_49_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_31) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_49_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_4_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_4_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_4_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_4_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_4_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_4_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_4_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_4) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_4_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_4_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_50_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_50_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_50_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_50_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_50_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_50_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_50_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_32) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_50_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_51_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_51_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_51_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_51_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_51_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_51_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_51_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_51_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_33) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_51_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_51_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_52_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_52_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_52_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_52_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_52_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_52_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_52_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_52_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_34) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_52_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_52_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_53_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_53_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_53_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_53_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_53_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_53_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_53_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_53_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_35) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_53_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_53_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_54_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_54_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_54_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_54_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_54_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_54_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_54_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_54_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_36) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_54_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_54_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_55_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_55_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_55_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_55_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_55_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_55_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_55_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_55_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_37) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_55_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_55_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_56_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_56_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_56_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_56_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_56_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_56_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_56_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_56_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_38) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_56_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_56_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_57_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_reg_4620, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_57_address0 <= zext_ln31_1_reg_4620(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_57_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_57_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_57_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_57_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_57_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_39) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_57_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_58_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_reg_4620, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_58_address0 <= zext_ln31_1_reg_4620(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_58_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_58_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_58_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_58_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_58_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_3A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_58_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_59_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_59_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_59_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_59_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_59_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_59_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_59_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_59_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_3B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_59_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_59_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_5_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_5_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_5_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_5_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_5_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_5_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_5_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_5) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_5_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_5_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_60_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_60_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_60_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_60_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_60_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_60_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_60_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_60_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_3C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_60_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_60_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_61_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_reg_4620, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_61_address0 <= zext_ln31_1_reg_4620(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_61_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_61_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_61_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_61_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_61_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_3D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_61_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_62_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_62_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_62_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_62_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_62_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_62_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_62_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_62_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_3E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_62_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_62_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_63_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_63_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_63_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_63_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_63_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_63_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_63_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_63_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_3F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_63_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_63_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_6_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_6_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_6_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_6_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_6_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_6_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_6_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_6) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_6_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_6_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_7_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_7_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_7_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_7_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_7_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_7_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_7_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_7) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_7_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_7_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_8_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_8_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_8_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_8_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_8_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_8_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_8_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_8) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_8_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_8_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_9_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, zext_ln31_1_fu_3665_p1, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3446_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in1_loc_9_address0 <= zext_ln31_1_fu_3665_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_address0 <= zext_ln27_fu_3446_p1(6 - 1 downto 0);
+        else 
+            in1_loc_9_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_9_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then 
+            in1_loc_9_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_9_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4443_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4443_pp0_iter1_reg = ap_const_lv6_9) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_9_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    in1_mem_ARADDR <= empty_8_fu_3392_p1(32 - 1 downto 0);
+
+    in1_mem_ARVALID_assign_proc : process(ap_CS_fsm_state2, in1_mem_ARREADY)
+    begin
+        if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            in1_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in1_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_RREADY <= ap_const_logic_1;
+        else 
+            in1_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_AR_assign_proc : process(m_axi_in1_mem_ARREADY, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            in1_mem_blk_n_AR <= m_axi_in1_mem_ARREADY;
+        else 
+            in1_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_R_assign_proc : process(m_axi_in1_mem_RVALID, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_blk_n_R <= m_axi_in1_mem_RVALID;
+        else 
+            in1_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_loc_0_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_0_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_0_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_0_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_0_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_0_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_0_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_0_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_0_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_10_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_10_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_10_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_10_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_10_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_10_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_10_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_10_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_11_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_11_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_11_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_11_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_11_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_11_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_11_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_11_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_11_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_11_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_12_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_12_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_12_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_12_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_12_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_12_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_12_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_12_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_12_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_12_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_13_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_13_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_13_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_13_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_13_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_13_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_13_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_13_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_14_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_14_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_14_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_14_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_14_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_14_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_14_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_14_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_15_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_15_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_15_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_15_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_15_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_15_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_15_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_15_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_15_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_15_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_16_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_16_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_16_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_16_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_16_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_16_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_16_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_16_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_10) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_16_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_16_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_17_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_17_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_17_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_17_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_17_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_17_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_17_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_11) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_17_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_18_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_18_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_18_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_18_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_18_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_18_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_18_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_12) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_18_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_19_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_19_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_19_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_19_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_19_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_19_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_19_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_19_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_13) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_19_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_19_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_1_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_1_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_1_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_1_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_1_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_1_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_1_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_1_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_1_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_20_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_20_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_20_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_20_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_20_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_20_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_20_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_20_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_14) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_20_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_20_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_21_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_21_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_21_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_21_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_21_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_21_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_21_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_21_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_15) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_21_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_21_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_22_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_22_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_22_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_22_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_22_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_22_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_22_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_22_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_16) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_22_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_22_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_23_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_23_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_23_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_23_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_23_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_23_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_23_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_23_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_17) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_23_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_23_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_24_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_24_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_24_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_24_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_24_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_24_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_24_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_24_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_18) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_24_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_24_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_25_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_25_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_25_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_25_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_25_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_25_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_25_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_19) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_25_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_26_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_26_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_26_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_26_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_26_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_26_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_26_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_1A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_26_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_27_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_27_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_27_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_27_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_27_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_27_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_27_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_27_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_1B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_27_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_27_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_28_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_28_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_28_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_28_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_28_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_28_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_28_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_28_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_1C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_28_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_28_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_29_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_29_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_29_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_29_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_29_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_29_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_29_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_29_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_1D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_29_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_29_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_2_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_2_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_2_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_2_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_2_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_2_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_2_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_2) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_2_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_2_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_30_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_30_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_30_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_30_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_30_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_30_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_30_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_30_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_1E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_30_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_30_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_31_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_31_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_31_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_31_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_31_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_31_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_31_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_31_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_1F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_31_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_31_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_32_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_32_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_32_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_32_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_32_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_32_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_32_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_32_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_20) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_32_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_32_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_33_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_33_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_33_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_33_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_33_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_33_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_33_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_21) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_33_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_34_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_34_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_34_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_34_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_34_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_34_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_34_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_22) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_34_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_35_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_35_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_35_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_35_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_35_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_35_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_35_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_35_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_23) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_35_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_35_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_36_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_36_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_36_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_36_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_36_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_36_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_36_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_36_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_24) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_36_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_36_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_37_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_37_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_37_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_37_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_37_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_37_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_37_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_37_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_25) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_37_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_37_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_38_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_38_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_38_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_38_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_38_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_38_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_38_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_38_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_26) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_38_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_38_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_39_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_39_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_39_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_39_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_39_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_39_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_39_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_39_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_27) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_39_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_39_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_3_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_3_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_3_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_3_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_3_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_3_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_3_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_3) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_3_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_3_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_40_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_40_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_40_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_40_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_40_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_40_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_40_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_40_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_28) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_40_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_40_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_41_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_reg_4916, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_41_address0 <= sext_ln38_reg_4916(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_41_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_41_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_41_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_41_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_41_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_29) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_41_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_42_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_reg_4916, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_42_address0 <= sext_ln38_reg_4916(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_42_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_42_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_42_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_42_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_42_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_2A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_42_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_43_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_43_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_43_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_43_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_43_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_43_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_43_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_43_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_2B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_43_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_43_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_44_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_44_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_44_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_44_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_44_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_44_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_44_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_44_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_2C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_44_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_44_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_45_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_reg_4916, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_45_address0 <= sext_ln38_reg_4916(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_45_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_45_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_45_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_45_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_45_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_2D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_45_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_46_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_reg_4916, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_46_address0 <= sext_ln38_reg_4916(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_46_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_46_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_46_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_46_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_46_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_2E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_46_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_47_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_47_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_47_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_47_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_47_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_47_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_47_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_47_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_2F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_47_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_47_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_48_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_48_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_48_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_48_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_48_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_48_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_48_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_48_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_30) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_48_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_48_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_49_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_49_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_49_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_49_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_49_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_49_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_49_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_31) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_49_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_4_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_4_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_4_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_4_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_4_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_4_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_4_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_4) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_4_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_4_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_50_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_50_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_50_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_50_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_50_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_50_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_50_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_32) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_50_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_51_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_51_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_51_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_51_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_51_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_51_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_51_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_51_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_33) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_51_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_51_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_52_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_52_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_52_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_52_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_52_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_52_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_52_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_52_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_34) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_52_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_52_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_53_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_53_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_53_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_53_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_53_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_53_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_53_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_53_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_35) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_53_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_53_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_54_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_54_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_54_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_54_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_54_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_54_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_54_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_54_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_36) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_54_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_54_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_55_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_55_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_55_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_55_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_55_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_55_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_55_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_55_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_37) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_55_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_55_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_56_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_56_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_56_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_56_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_56_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_56_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_56_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_56_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_38) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_56_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_56_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_57_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_reg_4916, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_57_address0 <= sext_ln38_reg_4916(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_57_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_57_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_57_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_57_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_57_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_39) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_57_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_58_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_reg_4916, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_58_address0 <= sext_ln38_reg_4916(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_58_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_58_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_58_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_58_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_58_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_3A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_58_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_59_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_59_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_59_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_59_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_59_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_59_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_59_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_59_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_3B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_59_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_59_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_5_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_5_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_5_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_5_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_5_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_5_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_5_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_5) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_5_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_5_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_60_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_60_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_60_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_60_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_60_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_60_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_60_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_60_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_3C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_60_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_60_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_61_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_reg_4916, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_61_address0 <= sext_ln38_reg_4916(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_61_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_61_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter1, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_61_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_61_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_61_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_3D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_61_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_62_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_62_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_62_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_62_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_62_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_62_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_62_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_62_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_3E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_62_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_62_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_63_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_63_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_63_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_63_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_63_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_63_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_63_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_63_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_3F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_63_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_63_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_6_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_6_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_6_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_6_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_6_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_6_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_6_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_6) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_6_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_6_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_7_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_7_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_7_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_7_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_7_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_7_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_7_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_7) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_7_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_7_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_8_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_8_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_8_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_8_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_8_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_8_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_8_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_8) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_8_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_8_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_9_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter0, sext_ln38_fu_3726_p1, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3539_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+            in2_loc_9_address0 <= sext_ln38_fu_3726_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_address0 <= zext_ln28_fu_3539_p1(6 - 1 downto 0);
+        else 
+            in2_loc_9_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_9_ce0_assign_proc : process(ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)))) then 
+            in2_loc_9_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_9_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4529_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4529_pp1_iter1_reg = ap_const_lv6_9) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_9_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_ARVALID_assign_proc : process(ap_CS_fsm_state12, in2_mem_ARREADY)
+    begin
+        if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then 
+            in2_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in2_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_RREADY_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_RREADY <= ap_const_logic_1;
+        else 
+            in2_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_AR_assign_proc : process(m_axi_in2_mem_ARREADY, ap_CS_fsm_state12)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state12)) then 
+            in2_mem_blk_n_AR <= m_axi_in2_mem_ARREADY;
+        else 
+            in2_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_R_assign_proc : process(m_axi_in2_mem_RVALID, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_blk_n_R <= m_axi_in2_mem_RVALID;
+        else 
+            in2_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    j_fu_3802_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(select_ln31_fu_3637_p3));
+    mul_ln31_fu_3609_p0 <= zext_ln31_fu_3606_p1(32 - 1 downto 0);
+    mul_ln31_fu_3609_p1 <= zext_ln31_fu_3606_p1(32 - 1 downto 0);
+    mul_ln31_fu_3609_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(mul_ln31_fu_3609_p0) * unsigned(mul_ln31_fu_3609_p1), 64));
+    mul_ln38_10_fu_3848_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_10_load_reg_5593) * signed(in1_loc_10_load_reg_5273))), 32));
+    mul_ln38_11_fu_3852_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_11_load_reg_5598) * signed(in1_loc_11_load_reg_5278))), 32));
+    mul_ln38_12_fu_3856_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_12_load_reg_5603) * signed(in1_loc_12_load_reg_5283))), 32));
+    mul_ln38_13_fu_3860_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_13_load_reg_5608) * signed(in1_loc_13_load_reg_5288))), 32));
+    mul_ln38_14_fu_3864_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_14_load_reg_5613) * signed(in1_loc_14_load_reg_5293))), 32));
+    mul_ln38_15_fu_3868_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_15_load_reg_5618) * signed(in1_loc_15_load_reg_5298))), 32));
+    mul_ln38_16_fu_3872_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_16_load_reg_5623) * signed(in1_loc_16_load_reg_5303))), 32));
+    mul_ln38_17_fu_3876_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_17_load_reg_5628) * signed(in1_loc_17_load_reg_5308))), 32));
+    mul_ln38_18_fu_3880_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_18_load_reg_5633) * signed(in1_loc_18_load_reg_5313))), 32));
+    mul_ln38_19_fu_3884_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_19_load_reg_5638) * signed(in1_loc_19_load_reg_5318))), 32));
+    mul_ln38_1_fu_3812_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_1_load_reg_5548) * signed(in1_loc_1_load_reg_5228))), 32));
+    mul_ln38_20_fu_3888_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_20_load_reg_5643) * signed(in1_loc_20_load_reg_5323))), 32));
+    mul_ln38_21_fu_3892_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_21_load_reg_5648) * signed(in1_loc_21_load_reg_5328))), 32));
+    mul_ln38_22_fu_3896_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_22_load_reg_5653) * signed(in1_loc_22_load_reg_5333))), 32));
+    mul_ln38_23_fu_3900_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_23_load_reg_5658) * signed(in1_loc_23_load_reg_5338))), 32));
+    mul_ln38_24_fu_3904_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_24_load_reg_5663) * signed(in1_loc_24_load_reg_5343))), 32));
+    mul_ln38_25_fu_3908_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_25_load_reg_5668) * signed(in1_loc_25_load_reg_5348))), 32));
+    mul_ln38_26_fu_3912_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_26_load_reg_5673) * signed(in1_loc_26_load_reg_5353))), 32));
+    mul_ln38_27_fu_3916_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_27_load_reg_5678) * signed(in1_loc_27_load_reg_5358))), 32));
+    mul_ln38_28_fu_3920_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_28_load_reg_5683) * signed(in1_loc_28_load_reg_5363))), 32));
+    mul_ln38_29_fu_3924_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_29_load_reg_5688) * signed(in1_loc_29_load_reg_5368))), 32));
+    mul_ln38_2_fu_3816_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_2_load_reg_5553) * signed(in1_loc_2_load_reg_5233))), 32));
+    mul_ln38_30_fu_3928_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_30_load_reg_5693) * signed(in1_loc_30_load_reg_5373))), 32));
+    mul_ln38_31_fu_3932_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_31_load_reg_5698) * signed(in1_loc_31_load_reg_5378))), 32));
+    mul_ln38_32_fu_3936_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_32_load_reg_5703) * signed(in1_loc_32_load_reg_5383))), 32));
+    mul_ln38_33_fu_3940_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_33_load_reg_5708) * signed(in1_loc_33_load_reg_5388))), 32));
+    mul_ln38_34_fu_3944_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_34_load_reg_5713) * signed(in1_loc_34_load_reg_5393))), 32));
+    mul_ln38_35_fu_3948_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_35_load_reg_5718) * signed(in1_loc_35_load_reg_5398))), 32));
+    mul_ln38_36_fu_3952_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_36_load_reg_5723) * signed(in1_loc_36_load_reg_5403))), 32));
+    mul_ln38_37_fu_3956_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_37_load_reg_5728) * signed(in1_loc_37_load_reg_5408))), 32));
+    mul_ln38_38_fu_3960_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_38_load_reg_5733) * signed(in1_loc_38_load_reg_5413))), 32));
+    mul_ln38_39_fu_3964_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_39_load_reg_5738) * signed(in1_loc_39_load_reg_5418))), 32));
+    mul_ln38_3_fu_3820_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_3_load_reg_5558) * signed(in1_loc_3_load_reg_5238))), 32));
+    mul_ln38_40_fu_3968_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_40_load_reg_5743) * signed(in1_loc_40_load_reg_5423))), 32));
+    mul_ln38_41_fu_4036_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_41_load_reg_6103) * signed(in1_loc_41_load_reg_5863))), 32));
+    mul_ln38_42_fu_4040_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_42_load_reg_6108) * signed(in1_loc_42_load_reg_5868))), 32));
+    mul_ln38_43_fu_3972_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_43_load_reg_5758) * signed(in1_loc_43_load_reg_5438))), 32));
+    mul_ln38_44_fu_3976_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_44_load_reg_5763) * signed(in1_loc_44_load_reg_5443))), 32));
+    mul_ln38_45_fu_4044_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_45_load_reg_6123) * signed(in1_loc_45_load_reg_5873))), 32));
+    mul_ln38_46_fu_4048_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_46_load_reg_6128) * signed(in1_loc_46_load_reg_5878))), 32));
+    mul_ln38_47_fu_3980_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_47_load_reg_5778) * signed(in1_loc_47_load_reg_5458))), 32));
+    mul_ln38_48_fu_3984_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_48_load_reg_5783) * signed(in1_loc_48_load_reg_5463))), 32));
+    mul_ln38_49_fu_3988_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_49_load_reg_5788) * signed(in1_loc_49_load_reg_5468))), 32));
+    mul_ln38_4_fu_3824_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_4_load_reg_5563) * signed(in1_loc_4_load_reg_5243))), 32));
+    mul_ln38_50_fu_3992_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_50_load_reg_5793) * signed(in1_loc_50_load_reg_5473))), 32));
+    mul_ln38_51_fu_3996_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_51_load_reg_5798) * signed(in1_loc_51_load_reg_5478))), 32));
+    mul_ln38_52_fu_4000_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_52_load_reg_5803) * signed(in1_loc_52_load_reg_5483))), 32));
+    mul_ln38_53_fu_4004_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_53_load_reg_5808) * signed(in1_loc_53_load_reg_5488))), 32));
+    mul_ln38_54_fu_4008_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_54_load_reg_5813) * signed(in1_loc_54_load_reg_5493))), 32));
+    mul_ln38_55_fu_4012_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_55_load_reg_5818) * signed(in1_loc_55_load_reg_5498))), 32));
+    mul_ln38_56_fu_4016_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_56_load_reg_5823) * signed(in1_loc_56_load_reg_5503))), 32));
+    mul_ln38_57_fu_4052_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_57_load_reg_6183) * signed(in1_loc_57_load_reg_5883))), 32));
+    mul_ln38_58_fu_4056_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_58_load_reg_6188) * signed(in1_loc_58_load_reg_5888))), 32));
+    mul_ln38_59_fu_4020_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_59_load_reg_5838) * signed(in1_loc_59_load_reg_5518))), 32));
+    mul_ln38_5_fu_3828_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_5_load_reg_5568) * signed(in1_loc_5_load_reg_5248))), 32));
+    mul_ln38_60_fu_4024_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_60_load_reg_5843) * signed(in1_loc_60_load_reg_5523))), 32));
+    mul_ln38_61_fu_4060_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_61_load_reg_6203) * signed(in1_loc_61_load_reg_5893))), 32));
+    mul_ln38_62_fu_4028_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_62_load_reg_5853) * signed(in1_loc_62_load_reg_5533))), 32));
+    mul_ln38_63_fu_4032_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_63_load_reg_5858) * signed(in1_loc_63_load_reg_5538))), 32));
+    mul_ln38_6_fu_3832_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_6_load_reg_5573) * signed(in1_loc_6_load_reg_5253))), 32));
+    mul_ln38_7_fu_3836_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_7_load_reg_5578) * signed(in1_loc_7_load_reg_5258))), 32));
+    mul_ln38_8_fu_3840_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_8_load_reg_5583) * signed(in1_loc_8_load_reg_5263))), 32));
+    mul_ln38_9_fu_3844_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_9_load_reg_5588) * signed(in1_loc_9_load_reg_5268))), 32));
+    mul_ln38_fu_3808_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(in2_loc_0_load_reg_5543) * signed(in1_loc_0_load_reg_5223))), 32));
+
+    out_loc_address0_assign_proc : process(ap_block_pp3_stage0, out_loc_addr_reg_4927_pp2_iter1_reg, ap_enable_reg_pp2_iter2, ap_CS_fsm_pp3_stage0, ap_enable_reg_pp3_iter0, ap_block_pp2_stage0, zext_ln42_fu_4385_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp3_stage0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then 
+            out_loc_address0 <= zext_ln42_fu_4385_p1(12 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            out_loc_address0 <= out_loc_addr_reg_4927_pp2_iter1_reg;
+        else 
+            out_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    out_loc_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter2, ap_CS_fsm_pp3_stage0, ap_block_pp3_stage0_11001, ap_enable_reg_pp3_iter0)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)) or ((ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_const_boolean_0 = ap_block_pp3_stage0_11001)))) then 
+            out_loc_ce0 <= ap_const_logic_1;
+        else 
+            out_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_loc_ce1_assign_proc : process(ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter4)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter4 = ap_const_logic_1))) then 
+            out_loc_ce1 <= ap_const_logic_1;
+        else 
+            out_loc_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    out_loc_d1 <= std_logic_vector(unsigned(add_ln38_30_fu_4296_p2) + unsigned(add_ln38_62_fu_4360_p2));
+
+    out_loc_we1_assign_proc : process(ap_block_pp2_stage0_11001, icmp_ln31_reg_4606_pp2_iter3_reg, ap_enable_reg_pp2_iter4)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4606_pp2_iter3_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter4 = ap_const_logic_1))) then 
+            out_loc_we1 <= ap_const_logic_1;
+        else 
+            out_loc_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_AWVALID_assign_proc : process(ap_CS_fsm_state28, out_mem_AWREADY)
+    begin
+        if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state28))) then 
+            out_mem_AWVALID <= ap_const_logic_1;
+        else 
+            out_mem_AWVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_BREADY_assign_proc : process(ap_CS_fsm_state36, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state36))) then 
+            out_mem_BREADY <= ap_const_logic_1;
+        else 
+            out_mem_BREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_WVALID_assign_proc : process(ap_enable_reg_pp3_iter2, icmp_ln42_reg_6313_pp3_iter1_reg, ap_block_pp3_stage0_11001)
+    begin
+        if (((icmp_ln42_reg_6313_pp3_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_11001))) then 
+            out_mem_WVALID <= ap_const_logic_1;
+        else 
+            out_mem_WVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AW_assign_proc : process(m_axi_out_mem_AWREADY, ap_CS_fsm_state28)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state28)) then 
+            out_mem_blk_n_AW <= m_axi_out_mem_AWREADY;
+        else 
+            out_mem_blk_n_AW <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_B_assign_proc : process(m_axi_out_mem_BVALID, ap_CS_fsm_state36)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state36)) then 
+            out_mem_blk_n_B <= m_axi_out_mem_BVALID;
+        else 
+            out_mem_blk_n_B <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_W_assign_proc : process(m_axi_out_mem_WREADY, ap_enable_reg_pp3_iter2, ap_block_pp3_stage0, icmp_ln42_reg_6313_pp3_iter1_reg)
+    begin
+        if (((icmp_ln42_reg_6313_pp3_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp3_stage0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1))) then 
+            out_mem_blk_n_W <= m_axi_out_mem_WREADY;
+        else 
+            out_mem_blk_n_W <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    select_ln31_1_fu_3645_p3 <= 
+        i_fu_3626_p2 when (icmp_ln33_fu_3632_p2(0) = '1') else 
+        ap_phi_mux_i_0_phi_fu_3333_p4;
+    select_ln31_fu_3637_p3 <= 
+        ap_const_lv32_0 when (icmp_ln33_fu_3632_p2(0) = '1') else 
+        j_0_reg_3340;
+        sext_ln38_fu_3726_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(select_ln31_fu_3637_p3),64));
+
+    tmp_cast_fu_3657_p3 <= (trunc_ln38_fu_3653_p1 & ap_const_lv6_0);
+    trunc_ln27_fu_3442_p1 <= phi_ln27_reg_3296(6 - 1 downto 0);
+    trunc_ln28_fu_3525_p1 <= phi_ln28_reg_3307(6 - 1 downto 0);
+    trunc_ln38_1_fu_3787_p1 <= select_ln31_fu_3637_p3(14 - 1 downto 0);
+    trunc_ln38_fu_3653_p1 <= select_ln31_1_fu_3645_p3(8 - 1 downto 0);
+    zext_ln27_fu_3446_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(lshr_ln_reg_4438_pp0_iter1_reg),64));
+    zext_ln28_fu_3539_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(trunc_ln28_reg_4524_pp1_iter1_reg),64));
+    zext_ln31_1_fu_3665_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(select_ln31_1_fu_3645_p3),64));
+    zext_ln31_fu_3606_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(dim_read_reg_4390),64));
+    zext_ln38_fu_3797_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln38_64_fu_3791_p2),64));
+    zext_ln42_fu_4385_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln42_reg_3351),64));
+end behav;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in1_loc_0.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in1_loc_0.vhd
new file mode 100755
index 0000000..609e4b6
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in1_loc_0.vhd
@@ -0,0 +1,112 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_in1_loc_0_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 6; 
+            MEM_SIZE    : integer := 64
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_in1_loc_0_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_in1_loc_0 is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 64;
+        AddressWidth : INTEGER := 6);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_in1_loc_0 is
+    component mmult_in1_loc_0_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_in1_loc_0_ram_U :  component mmult_in1_loc_0_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in1_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in1_mem_m_axi.vhd
new file mode 100755
index 0000000..5d4f5b4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in1_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi;
+
+architecture behave of mmult_in1_mem_m_axi is
+    component mmult_in1_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_write;
+
+    component mmult_in1_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_read;
+
+    component mmult_in1_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in1_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in1_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in1_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in1_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in1_mem_m_axi_fifo;
+
+architecture behave of mmult_in1_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in1_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in1_mem_m_axi_decoder;
+
+architecture behav of mmult_in1_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in1_mem_m_axi_throttl;
+
+architecture behav of mmult_in1_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in1_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in1_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_read;
+
+architecture behave of mmult_in1_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_write;
+
+architecture behave of mmult_in1_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in1_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in1_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in2_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in2_mem_m_axi.vhd
new file mode 100755
index 0000000..84687e2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_in2_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi;
+
+architecture behave of mmult_in2_mem_m_axi is
+    component mmult_in2_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_write;
+
+    component mmult_in2_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_read;
+
+    component mmult_in2_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in2_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in2_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in2_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in2_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in2_mem_m_axi_fifo;
+
+architecture behave of mmult_in2_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in2_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in2_mem_m_axi_decoder;
+
+architecture behav of mmult_in2_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in2_mem_m_axi_throttl;
+
+architecture behav of mmult_in2_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in2_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in2_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_read;
+
+architecture behave of mmult_in2_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_write;
+
+architecture behave of mmult_in2_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in2_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in2_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_out_loc.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_out_loc.vhd
new file mode 100755
index 0000000..ea7bf78
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_out_loc.vhd
@@ -0,0 +1,129 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_out_loc_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 12; 
+            MEM_SIZE    : integer := 4096
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce1       : in std_logic; 
+          d1        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we1       : in std_logic; 
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_out_loc_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+        end if;
+    end if;
+end process;
+
+
+p_memory_access_1: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce1 = '1') then 
+            if (we1 = '1') then 
+                ram(CONV_INTEGER(addr1)) := d1; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_out_loc is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 4096;
+        AddressWidth : INTEGER := 12);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_out_loc is
+    component mmult_out_loc_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            q0 : OUT STD_LOGIC_VECTOR;
+            addr1 : IN STD_LOGIC_VECTOR;
+            ce1 : IN STD_LOGIC;
+            we1 : IN STD_LOGIC;
+            d1 : IN STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_out_loc_ram_U :  component mmult_out_loc_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        q0 => q0,
+        addr1 => address1,
+        ce1 => ce1,
+        we1 => we1,
+        d1 => d1);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_out_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_out_mem_m_axi.vhd
new file mode 100755
index 0000000..f2bd717
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_out_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi;
+
+architecture behave of mmult_out_mem_m_axi is
+    component mmult_out_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_write;
+
+    component mmult_out_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_read;
+
+    component mmult_out_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_out_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_out_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_out_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi_reg_slice;
+
+architecture behave of mmult_out_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_out_mem_m_axi_fifo;
+
+architecture behave of mmult_out_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_out_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_out_mem_m_axi_decoder;
+
+architecture behav of mmult_out_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_out_mem_m_axi_throttl;
+
+architecture behav of mmult_out_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_out_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_out_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_read;
+
+architecture behave of mmult_out_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_write;
+
+architecture behave of mmult_out_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_out_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_out_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_params_s_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_params_s_axi.vhd
new file mode 100755
index 0000000..1f9adde
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/hdl/vhdl/mmult_params_s_axi.vhd
@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/misc/logo.png b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/misc/logo.png
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diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/xgui/mmult_v8_0.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/xgui/mmult_v8_0.tcl
new file mode 100755
index 0000000..0276fbf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_8/xgui/mmult_v8_0.tcl
@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/component.xml b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/component.xml
new file mode 100755
index 0000000..fb30185
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/component.xml
@@ -0,0 +1,5614 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>hls</spirit:library>
+  <spirit:name>mmult</spirit:name>
+  <spirit:version>9.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi_params"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_params_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.ADDR_WIDTH">6</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.DATA_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.PROTOCOL">AXI4LITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_PARAMS.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_BUSIF">s_axi_params:m_axi_in1_mem:m_axi_in2_mem:m_axi_out_mem</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_CLK.ASSOCIATED_RESET">ap_rst_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ap_rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ap_rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.AP_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>interrupt</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in1_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in1_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in1_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN1_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_in2_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_in2_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_in2_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_IN2_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>m_axi_out_mem</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:master>
+        <spirit:addressSpaceRef spirit:addressSpaceRef="Data_m_axi_out_mem"/>
+      </spirit:master>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_AWREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WSTRB</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_WREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_BREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARADDR</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLEN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLEN</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARSIZE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARSIZE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARBURST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARBURST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARLOCK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARLOCK</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREGION</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREGION</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARCACHE</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARCACHE</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARPROT</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARQOS</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARQOS</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_ARREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RDATA</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RRESP</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RLAST</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RUSER</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RUSER</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RVALID</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>m_axi_out_mem_RREADY</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.ADDR_WIDTH">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_BURST_LENGTH">256</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_READ_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.NUM_WRITE_OUTSTANDING">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_READ_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_READ_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_WRITE_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.MAX_WRITE_BURST_LENGTH">16</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.PROTOCOL">AXI4</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.READ_WRITE_MODE">READ_WRITE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.HAS_BURST">0</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI_OUT_MEM.SUPPORTS_NARROW_BURST">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:addressSpaces>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in1_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN1_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_in2_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_IN2_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+    <spirit:addressSpace>
+      <spirit:name>Data_m_axi_out_mem</spirit:name>
+      <spirit:range>4G</spirit:range>
+      <spirit:width spirit:format="long">32</spirit:width>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DEPENDENT_ON</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.DEPENDENT_ON">s_axi_params</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PREFERRED_USAGE</spirit:name>
+          <spirit:value spirit:id="ADDRSPACEPARAM_VALUE.DATA_M_AXI_OUT_MEM.PREFERRED_USAGE">MEMORY</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:addressSpace>
+  </spirit:addressSpaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi_params</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>Reg</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long" spirit:resolve="generated">65536</spirit:range>
+        <spirit:width spirit:format="long">32</spirit:width>
+        <spirit:usage>register</spirit:usage>
+        <spirit:access>read-write</spirit:access>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_BASE_PARAM">C_S_AXI_PARAMS_BASEADDR</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_PARAMS.REG.OFFSET_HIGH_PARAM">C_S_AXI_PARAMS_HIGHADDR</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+        <spirit:register>
+          <spirit:name>CTRL</spirit:name>
+          <spirit:displayName>CTRL</spirit:displayName>
+          <spirit:description>Control signals</spirit:description>
+          <spirit:addressOffset>0</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>AP_START</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_start&apos;.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_DONE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_done&apos;.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_IDLE</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_idle&apos;.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AP_READY</spirit:name>
+            <spirit:description>Control signal Register for &apos;ap_ready&apos;.</spirit:description>
+            <spirit:bitOffset>3</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_1</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>4</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">3</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>AUTO_RESTART</spirit:name>
+            <spirit:description>Control signal Register for &apos;auto_restart&apos;.</spirit:description>
+            <spirit:bitOffset>7</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED_2</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>8</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">24</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>GIER</spirit:name>
+          <spirit:displayName>GIER</spirit:displayName>
+          <spirit:description>Global Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>4</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>Enable</spirit:name>
+            <spirit:description>Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">31</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_IER</spirit:name>
+          <spirit:displayName>IP_IER</spirit:displayName>
+          <spirit:description>IP Interrupt Enable Register</spirit:description>
+          <spirit:addressOffset>8</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 0 (ap_done) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_EN</spirit:name>
+            <spirit:description>Enable Channel 1 (ap_ready) Interrupt.  0 = Disabled, 1 = Enabled.</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-write</spirit:access>
+            <spirit:modifiedWriteValue>modify</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>IP_ISR</spirit:name>
+          <spirit:displayName>IP_ISR</spirit:displayName>
+          <spirit:description>IP Interrupt Status Register</spirit:description>
+          <spirit:addressOffset>12</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>read-write</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>CHAN0_INT_ST</spirit:name>
+            <spirit:description>Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 input interrupt, 1 = Channel 0 input interrup</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>CHAN1_INT_ST</spirit:name>
+            <spirit:description>Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 input interrupt, 1 = Channel 1 input interrup</spirit:description>
+            <spirit:bitOffset>1</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+          <spirit:field>
+            <spirit:name>RESERVED</spirit:name>
+            <spirit:description>Reserved.  0s on read.</spirit:description>
+            <spirit:bitOffset>2</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">30</spirit:bitWidth>
+            <spirit:access>read-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:readAction>modify</spirit:readAction>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>in1</spirit:name>
+          <spirit:displayName>in1</spirit:displayName>
+          <spirit:description>Data signal of in1</spirit:description>
+          <spirit:addressOffset>16</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>in1</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of in1</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>in2</spirit:name>
+          <spirit:displayName>in2</spirit:displayName>
+          <spirit:description>Data signal of in2</spirit:description>
+          <spirit:addressOffset>24</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>in2</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of in2</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
+        </spirit:register>
+        <spirit:register>
+          <spirit:name>out_r</spirit:name>
+          <spirit:displayName>out_r</spirit:displayName>
+          <spirit:description>Data signal of out_r</spirit:description>
+          <spirit:addressOffset>32</spirit:addressOffset>
+          <spirit:size spirit:format="long">32</spirit:size>
+          <spirit:access>write-only</spirit:access>
+          <spirit:reset>
+            <spirit:value spirit:format="long">0</spirit:value>
+          </spirit:reset>
+          <spirit:field>
+            <spirit:name>out_r</spirit:name>
+            <spirit:description>Bit 31 to 0 Data signal of out_r</spirit:description>
+            <spirit:bitOffset>0</spirit:bitOffset>
+            <spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
+            <spirit:access>write-only</spirit:access>
+            <spirit:writeValueConstraint>
+              <spirit:minimum>0</spirit:minimum>
+              <spirit:maximum>0</spirit:maximum>
+            </spirit:writeValueConstraint>
+            <spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
+          </spirit:field>
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+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_3f68c42e</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>misc/logo.png</spirit:name>
+        <spirit:userFileType>image</spirit:userFileType>
+        <spirit:userFileType>LOGO</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>An IP generated by Vivado HLS</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" spirit:order="2" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH" spirit:order="3" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="4" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" spirit:order="5" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH" spirit:order="6" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH" spirit:order="7" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH" spirit:order="8" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH" spirit:order="9" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH" spirit:order="10" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE" spirit:order="11" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN1_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE" spirit:order="12" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN1_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE" spirit:order="13" spirit:configGroups="1 m axi in1 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" spirit:order="14" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH" spirit:order="15" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="16" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" spirit:order="17" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH" spirit:order="18" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH" spirit:order="19" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH" spirit:order="20" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH" spirit:order="21" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH" spirit:order="22" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE" spirit:order="23" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_IN2_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE" spirit:order="24" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_IN2_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE" spirit:order="25" spirit:configGroups="1 m axi in2 mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_ID_PORTS</spirit:name>
+      <spirit:displayName>Enable ID ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" spirit:order="26" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ID_WIDTH</spirit:name>
+      <spirit:displayName>ID width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH" spirit:order="27" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ID_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Data width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="28" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ENABLE_USER_PORTS</spirit:name>
+      <spirit:displayName>Enable USER ports</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" spirit:order="29" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_AWUSER_WIDTH</spirit:name>
+      <spirit:displayName>AWUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH" spirit:order="30" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_AWUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_WUSER_WIDTH</spirit:name>
+      <spirit:displayName>WUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH" spirit:order="31" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_WUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_BUSER_WIDTH</spirit:name>
+      <spirit:displayName>BUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH" spirit:order="32" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_BUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_ARUSER_WIDTH</spirit:name>
+      <spirit:displayName>ARUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH" spirit:order="33" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_ARUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_RUSER_WIDTH</spirit:name>
+      <spirit:displayName>RUSER width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH" spirit:order="34" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:minimum="1" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_RUSER_WIDTH" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_USER_VALUE</spirit:name>
+      <spirit:displayName>USER value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE" spirit:order="35" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_M_AXI_OUT_MEM_USER_VALUE" xilinx:dependency="(spirit:decode(id(&apos;PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS&apos;)) = 1)">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_PROT_VALUE</spirit:name>
+      <spirit:displayName>PROT value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE" spirit:order="36" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_M_AXI_OUT_MEM_CACHE_VALUE</spirit:name>
+      <spirit:displayName>CACHE value</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE" spirit:order="37" spirit:configGroups="1 m axi out mem (AXI4 Master Interface)" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mmult_v9_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>clk_period</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.clk_period" spirit:order="38">3.333</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>machine</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.machine" spirit:order="39">64</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>combinational</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.combinational" spirit:order="40">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>latency</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.latency" spirit:order="41">16421</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>II</spirit:name>
+      <spirit:value spirit:id="PARAM_VALUE.II" spirit:order="42">x</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/VIVADO_HLS_IP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>Mmult</xilinx:displayName>
+      <xilinx:definitionSource>HLS</xilinx:definitionSource>
+      <xilinx:coreRevision>2105142056</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2021-05-14T18:56:37Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b5dd57e8"/>
+      <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="c6fd4807"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5ce530f0"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="20ed97b5"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="7681d788"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c9a673dd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="f1af38ef"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/constraints/mmult_ooc.xdc b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/constraints/mmult_ooc.xdc
new file mode 100755
index 0000000..38d0846
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/constraints/mmult_ooc.xdc
@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 3.333 [get_ports ap_clk]
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/doc/ReleaseNotes.txt b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/doc/ReleaseNotes.txt
new file mode 100755
index 0000000..61c7559
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/doc/ReleaseNotes.txt
@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 3.333 ns
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/data/mmult.mdd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/data/mmult.mdd
new file mode 100755
index 0000000..bef671f
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/data/mmult.mdd
@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v9_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 9.0;
+
+END driver
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/data/mmult.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/data/mmult.tcl
new file mode 100755
index 0000000..0de7a9c
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/data/mmult.tcl
@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/Makefile b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/Makefile
new file mode 100755
index 0000000..7f76086
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/Makefile
@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult.c
new file mode 100755
index 0000000..fb9a1fb
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult.c
@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult.h
new file mode 100755
index 0000000..4983669
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult.h
@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_hw.h b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_hw.h
new file mode 100755
index 0000000..3a0a2a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_hw.h
@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_linux.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_linux.c
new file mode 100755
index 0000000..c8dbb33
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_linux.c
@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_sinit.c b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_sinit.c
new file mode 100755
index 0000000..f099590
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/drivers/mmult_v9_0/src/xmmult_sinit.c
@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult.v
new file mode 100755
index 0000000..b1afd13
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult.v
@@ -0,0 +1,9314 @@
+// ==============================================================
+// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+// Version: 2020.1
+// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+// 
+// ===========================================================
+
+`timescale 1 ns / 1 ps 
+
+(* CORE_GENERATION_INFO="mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=3.333000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.916375,HLS_SYN_LAT=16421,HLS_SYN_TPT=none,HLS_SYN_MEM=142,HLS_SYN_DSP=260,HLS_SYN_FF=20363,HLS_SYN_LUT=10157,HLS_VERSION=2020_1}" *)
+
+module mmult (
+        ap_clk,
+        ap_rst_n,
+        m_axi_in1_mem_AWVALID,
+        m_axi_in1_mem_AWREADY,
+        m_axi_in1_mem_AWADDR,
+        m_axi_in1_mem_AWID,
+        m_axi_in1_mem_AWLEN,
+        m_axi_in1_mem_AWSIZE,
+        m_axi_in1_mem_AWBURST,
+        m_axi_in1_mem_AWLOCK,
+        m_axi_in1_mem_AWCACHE,
+        m_axi_in1_mem_AWPROT,
+        m_axi_in1_mem_AWQOS,
+        m_axi_in1_mem_AWREGION,
+        m_axi_in1_mem_AWUSER,
+        m_axi_in1_mem_WVALID,
+        m_axi_in1_mem_WREADY,
+        m_axi_in1_mem_WDATA,
+        m_axi_in1_mem_WSTRB,
+        m_axi_in1_mem_WLAST,
+        m_axi_in1_mem_WID,
+        m_axi_in1_mem_WUSER,
+        m_axi_in1_mem_ARVALID,
+        m_axi_in1_mem_ARREADY,
+        m_axi_in1_mem_ARADDR,
+        m_axi_in1_mem_ARID,
+        m_axi_in1_mem_ARLEN,
+        m_axi_in1_mem_ARSIZE,
+        m_axi_in1_mem_ARBURST,
+        m_axi_in1_mem_ARLOCK,
+        m_axi_in1_mem_ARCACHE,
+        m_axi_in1_mem_ARPROT,
+        m_axi_in1_mem_ARQOS,
+        m_axi_in1_mem_ARREGION,
+        m_axi_in1_mem_ARUSER,
+        m_axi_in1_mem_RVALID,
+        m_axi_in1_mem_RREADY,
+        m_axi_in1_mem_RDATA,
+        m_axi_in1_mem_RLAST,
+        m_axi_in1_mem_RID,
+        m_axi_in1_mem_RUSER,
+        m_axi_in1_mem_RRESP,
+        m_axi_in1_mem_BVALID,
+        m_axi_in1_mem_BREADY,
+        m_axi_in1_mem_BRESP,
+        m_axi_in1_mem_BID,
+        m_axi_in1_mem_BUSER,
+        m_axi_in2_mem_AWVALID,
+        m_axi_in2_mem_AWREADY,
+        m_axi_in2_mem_AWADDR,
+        m_axi_in2_mem_AWID,
+        m_axi_in2_mem_AWLEN,
+        m_axi_in2_mem_AWSIZE,
+        m_axi_in2_mem_AWBURST,
+        m_axi_in2_mem_AWLOCK,
+        m_axi_in2_mem_AWCACHE,
+        m_axi_in2_mem_AWPROT,
+        m_axi_in2_mem_AWQOS,
+        m_axi_in2_mem_AWREGION,
+        m_axi_in2_mem_AWUSER,
+        m_axi_in2_mem_WVALID,
+        m_axi_in2_mem_WREADY,
+        m_axi_in2_mem_WDATA,
+        m_axi_in2_mem_WSTRB,
+        m_axi_in2_mem_WLAST,
+        m_axi_in2_mem_WID,
+        m_axi_in2_mem_WUSER,
+        m_axi_in2_mem_ARVALID,
+        m_axi_in2_mem_ARREADY,
+        m_axi_in2_mem_ARADDR,
+        m_axi_in2_mem_ARID,
+        m_axi_in2_mem_ARLEN,
+        m_axi_in2_mem_ARSIZE,
+        m_axi_in2_mem_ARBURST,
+        m_axi_in2_mem_ARLOCK,
+        m_axi_in2_mem_ARCACHE,
+        m_axi_in2_mem_ARPROT,
+        m_axi_in2_mem_ARQOS,
+        m_axi_in2_mem_ARREGION,
+        m_axi_in2_mem_ARUSER,
+        m_axi_in2_mem_RVALID,
+        m_axi_in2_mem_RREADY,
+        m_axi_in2_mem_RDATA,
+        m_axi_in2_mem_RLAST,
+        m_axi_in2_mem_RID,
+        m_axi_in2_mem_RUSER,
+        m_axi_in2_mem_RRESP,
+        m_axi_in2_mem_BVALID,
+        m_axi_in2_mem_BREADY,
+        m_axi_in2_mem_BRESP,
+        m_axi_in2_mem_BID,
+        m_axi_in2_mem_BUSER,
+        m_axi_out_mem_AWVALID,
+        m_axi_out_mem_AWREADY,
+        m_axi_out_mem_AWADDR,
+        m_axi_out_mem_AWID,
+        m_axi_out_mem_AWLEN,
+        m_axi_out_mem_AWSIZE,
+        m_axi_out_mem_AWBURST,
+        m_axi_out_mem_AWLOCK,
+        m_axi_out_mem_AWCACHE,
+        m_axi_out_mem_AWPROT,
+        m_axi_out_mem_AWQOS,
+        m_axi_out_mem_AWREGION,
+        m_axi_out_mem_AWUSER,
+        m_axi_out_mem_WVALID,
+        m_axi_out_mem_WREADY,
+        m_axi_out_mem_WDATA,
+        m_axi_out_mem_WSTRB,
+        m_axi_out_mem_WLAST,
+        m_axi_out_mem_WID,
+        m_axi_out_mem_WUSER,
+        m_axi_out_mem_ARVALID,
+        m_axi_out_mem_ARREADY,
+        m_axi_out_mem_ARADDR,
+        m_axi_out_mem_ARID,
+        m_axi_out_mem_ARLEN,
+        m_axi_out_mem_ARSIZE,
+        m_axi_out_mem_ARBURST,
+        m_axi_out_mem_ARLOCK,
+        m_axi_out_mem_ARCACHE,
+        m_axi_out_mem_ARPROT,
+        m_axi_out_mem_ARQOS,
+        m_axi_out_mem_ARREGION,
+        m_axi_out_mem_ARUSER,
+        m_axi_out_mem_RVALID,
+        m_axi_out_mem_RREADY,
+        m_axi_out_mem_RDATA,
+        m_axi_out_mem_RLAST,
+        m_axi_out_mem_RID,
+        m_axi_out_mem_RUSER,
+        m_axi_out_mem_RRESP,
+        m_axi_out_mem_BVALID,
+        m_axi_out_mem_BREADY,
+        m_axi_out_mem_BRESP,
+        m_axi_out_mem_BID,
+        m_axi_out_mem_BUSER,
+        s_axi_params_AWVALID,
+        s_axi_params_AWREADY,
+        s_axi_params_AWADDR,
+        s_axi_params_WVALID,
+        s_axi_params_WREADY,
+        s_axi_params_WDATA,
+        s_axi_params_WSTRB,
+        s_axi_params_ARVALID,
+        s_axi_params_ARREADY,
+        s_axi_params_ARADDR,
+        s_axi_params_RVALID,
+        s_axi_params_RREADY,
+        s_axi_params_RDATA,
+        s_axi_params_RRESP,
+        s_axi_params_BVALID,
+        s_axi_params_BREADY,
+        s_axi_params_BRESP,
+        interrupt
+);
+
+parameter    ap_ST_fsm_state1 = 28'd1;
+parameter    ap_ST_fsm_state2 = 28'd2;
+parameter    ap_ST_fsm_state3 = 28'd4;
+parameter    ap_ST_fsm_state4 = 28'd8;
+parameter    ap_ST_fsm_state5 = 28'd16;
+parameter    ap_ST_fsm_state6 = 28'd32;
+parameter    ap_ST_fsm_state7 = 28'd64;
+parameter    ap_ST_fsm_state8 = 28'd128;
+parameter    ap_ST_fsm_pp0_stage0 = 28'd256;
+parameter    ap_ST_fsm_state12 = 28'd512;
+parameter    ap_ST_fsm_state13 = 28'd1024;
+parameter    ap_ST_fsm_state14 = 28'd2048;
+parameter    ap_ST_fsm_state15 = 28'd4096;
+parameter    ap_ST_fsm_state16 = 28'd8192;
+parameter    ap_ST_fsm_state17 = 28'd16384;
+parameter    ap_ST_fsm_state18 = 28'd32768;
+parameter    ap_ST_fsm_pp1_stage0 = 28'd65536;
+parameter    ap_ST_fsm_state22 = 28'd131072;
+parameter    ap_ST_fsm_state23 = 28'd262144;
+parameter    ap_ST_fsm_state24 = 28'd524288;
+parameter    ap_ST_fsm_pp2_stage0 = 28'd1048576;
+parameter    ap_ST_fsm_state34 = 28'd2097152;
+parameter    ap_ST_fsm_pp3_stage0 = 28'd4194304;
+parameter    ap_ST_fsm_state38 = 28'd8388608;
+parameter    ap_ST_fsm_state39 = 28'd16777216;
+parameter    ap_ST_fsm_state40 = 28'd33554432;
+parameter    ap_ST_fsm_state41 = 28'd67108864;
+parameter    ap_ST_fsm_state42 = 28'd134217728;
+parameter    C_S_AXI_PARAMS_DATA_WIDTH = 32;
+parameter    C_S_AXI_PARAMS_ADDR_WIDTH = 6;
+parameter    C_S_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN1_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN1_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN1_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_IN2_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_IN2_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_IN2_MEM_CACHE_VALUE = 3;
+parameter    C_M_AXI_OUT_MEM_ID_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ADDR_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_DATA_WIDTH = 32;
+parameter    C_M_AXI_OUT_MEM_AWUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_ARUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_WUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_RUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_BUSER_WIDTH = 1;
+parameter    C_M_AXI_OUT_MEM_USER_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_PROT_VALUE = 0;
+parameter    C_M_AXI_OUT_MEM_CACHE_VALUE = 3;
+
+parameter C_S_AXI_PARAMS_WSTRB_WIDTH = (32 / 8);
+parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN1_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_IN2_MEM_WSTRB_WIDTH = (32 / 8);
+parameter C_M_AXI_OUT_MEM_WSTRB_WIDTH = (32 / 8);
+
+input   ap_clk;
+input   ap_rst_n;
+output   m_axi_in1_mem_AWVALID;
+input   m_axi_in1_mem_AWREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_AWADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_AWID;
+output  [7:0] m_axi_in1_mem_AWLEN;
+output  [2:0] m_axi_in1_mem_AWSIZE;
+output  [1:0] m_axi_in1_mem_AWBURST;
+output  [1:0] m_axi_in1_mem_AWLOCK;
+output  [3:0] m_axi_in1_mem_AWCACHE;
+output  [2:0] m_axi_in1_mem_AWPROT;
+output  [3:0] m_axi_in1_mem_AWQOS;
+output  [3:0] m_axi_in1_mem_AWREGION;
+output  [C_M_AXI_IN1_MEM_AWUSER_WIDTH - 1:0] m_axi_in1_mem_AWUSER;
+output   m_axi_in1_mem_WVALID;
+input   m_axi_in1_mem_WREADY;
+output  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_WDATA;
+output  [C_M_AXI_IN1_MEM_WSTRB_WIDTH - 1:0] m_axi_in1_mem_WSTRB;
+output   m_axi_in1_mem_WLAST;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_WID;
+output  [C_M_AXI_IN1_MEM_WUSER_WIDTH - 1:0] m_axi_in1_mem_WUSER;
+output   m_axi_in1_mem_ARVALID;
+input   m_axi_in1_mem_ARREADY;
+output  [C_M_AXI_IN1_MEM_ADDR_WIDTH - 1:0] m_axi_in1_mem_ARADDR;
+output  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_ARID;
+output  [7:0] m_axi_in1_mem_ARLEN;
+output  [2:0] m_axi_in1_mem_ARSIZE;
+output  [1:0] m_axi_in1_mem_ARBURST;
+output  [1:0] m_axi_in1_mem_ARLOCK;
+output  [3:0] m_axi_in1_mem_ARCACHE;
+output  [2:0] m_axi_in1_mem_ARPROT;
+output  [3:0] m_axi_in1_mem_ARQOS;
+output  [3:0] m_axi_in1_mem_ARREGION;
+output  [C_M_AXI_IN1_MEM_ARUSER_WIDTH - 1:0] m_axi_in1_mem_ARUSER;
+input   m_axi_in1_mem_RVALID;
+output   m_axi_in1_mem_RREADY;
+input  [C_M_AXI_IN1_MEM_DATA_WIDTH - 1:0] m_axi_in1_mem_RDATA;
+input   m_axi_in1_mem_RLAST;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_RID;
+input  [C_M_AXI_IN1_MEM_RUSER_WIDTH - 1:0] m_axi_in1_mem_RUSER;
+input  [1:0] m_axi_in1_mem_RRESP;
+input   m_axi_in1_mem_BVALID;
+output   m_axi_in1_mem_BREADY;
+input  [1:0] m_axi_in1_mem_BRESP;
+input  [C_M_AXI_IN1_MEM_ID_WIDTH - 1:0] m_axi_in1_mem_BID;
+input  [C_M_AXI_IN1_MEM_BUSER_WIDTH - 1:0] m_axi_in1_mem_BUSER;
+output   m_axi_in2_mem_AWVALID;
+input   m_axi_in2_mem_AWREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_AWADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_AWID;
+output  [7:0] m_axi_in2_mem_AWLEN;
+output  [2:0] m_axi_in2_mem_AWSIZE;
+output  [1:0] m_axi_in2_mem_AWBURST;
+output  [1:0] m_axi_in2_mem_AWLOCK;
+output  [3:0] m_axi_in2_mem_AWCACHE;
+output  [2:0] m_axi_in2_mem_AWPROT;
+output  [3:0] m_axi_in2_mem_AWQOS;
+output  [3:0] m_axi_in2_mem_AWREGION;
+output  [C_M_AXI_IN2_MEM_AWUSER_WIDTH - 1:0] m_axi_in2_mem_AWUSER;
+output   m_axi_in2_mem_WVALID;
+input   m_axi_in2_mem_WREADY;
+output  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_WDATA;
+output  [C_M_AXI_IN2_MEM_WSTRB_WIDTH - 1:0] m_axi_in2_mem_WSTRB;
+output   m_axi_in2_mem_WLAST;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_WID;
+output  [C_M_AXI_IN2_MEM_WUSER_WIDTH - 1:0] m_axi_in2_mem_WUSER;
+output   m_axi_in2_mem_ARVALID;
+input   m_axi_in2_mem_ARREADY;
+output  [C_M_AXI_IN2_MEM_ADDR_WIDTH - 1:0] m_axi_in2_mem_ARADDR;
+output  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_ARID;
+output  [7:0] m_axi_in2_mem_ARLEN;
+output  [2:0] m_axi_in2_mem_ARSIZE;
+output  [1:0] m_axi_in2_mem_ARBURST;
+output  [1:0] m_axi_in2_mem_ARLOCK;
+output  [3:0] m_axi_in2_mem_ARCACHE;
+output  [2:0] m_axi_in2_mem_ARPROT;
+output  [3:0] m_axi_in2_mem_ARQOS;
+output  [3:0] m_axi_in2_mem_ARREGION;
+output  [C_M_AXI_IN2_MEM_ARUSER_WIDTH - 1:0] m_axi_in2_mem_ARUSER;
+input   m_axi_in2_mem_RVALID;
+output   m_axi_in2_mem_RREADY;
+input  [C_M_AXI_IN2_MEM_DATA_WIDTH - 1:0] m_axi_in2_mem_RDATA;
+input   m_axi_in2_mem_RLAST;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_RID;
+input  [C_M_AXI_IN2_MEM_RUSER_WIDTH - 1:0] m_axi_in2_mem_RUSER;
+input  [1:0] m_axi_in2_mem_RRESP;
+input   m_axi_in2_mem_BVALID;
+output   m_axi_in2_mem_BREADY;
+input  [1:0] m_axi_in2_mem_BRESP;
+input  [C_M_AXI_IN2_MEM_ID_WIDTH - 1:0] m_axi_in2_mem_BID;
+input  [C_M_AXI_IN2_MEM_BUSER_WIDTH - 1:0] m_axi_in2_mem_BUSER;
+output   m_axi_out_mem_AWVALID;
+input   m_axi_out_mem_AWREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_AWADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_AWID;
+output  [7:0] m_axi_out_mem_AWLEN;
+output  [2:0] m_axi_out_mem_AWSIZE;
+output  [1:0] m_axi_out_mem_AWBURST;
+output  [1:0] m_axi_out_mem_AWLOCK;
+output  [3:0] m_axi_out_mem_AWCACHE;
+output  [2:0] m_axi_out_mem_AWPROT;
+output  [3:0] m_axi_out_mem_AWQOS;
+output  [3:0] m_axi_out_mem_AWREGION;
+output  [C_M_AXI_OUT_MEM_AWUSER_WIDTH - 1:0] m_axi_out_mem_AWUSER;
+output   m_axi_out_mem_WVALID;
+input   m_axi_out_mem_WREADY;
+output  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_WDATA;
+output  [C_M_AXI_OUT_MEM_WSTRB_WIDTH - 1:0] m_axi_out_mem_WSTRB;
+output   m_axi_out_mem_WLAST;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_WID;
+output  [C_M_AXI_OUT_MEM_WUSER_WIDTH - 1:0] m_axi_out_mem_WUSER;
+output   m_axi_out_mem_ARVALID;
+input   m_axi_out_mem_ARREADY;
+output  [C_M_AXI_OUT_MEM_ADDR_WIDTH - 1:0] m_axi_out_mem_ARADDR;
+output  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_ARID;
+output  [7:0] m_axi_out_mem_ARLEN;
+output  [2:0] m_axi_out_mem_ARSIZE;
+output  [1:0] m_axi_out_mem_ARBURST;
+output  [1:0] m_axi_out_mem_ARLOCK;
+output  [3:0] m_axi_out_mem_ARCACHE;
+output  [2:0] m_axi_out_mem_ARPROT;
+output  [3:0] m_axi_out_mem_ARQOS;
+output  [3:0] m_axi_out_mem_ARREGION;
+output  [C_M_AXI_OUT_MEM_ARUSER_WIDTH - 1:0] m_axi_out_mem_ARUSER;
+input   m_axi_out_mem_RVALID;
+output   m_axi_out_mem_RREADY;
+input  [C_M_AXI_OUT_MEM_DATA_WIDTH - 1:0] m_axi_out_mem_RDATA;
+input   m_axi_out_mem_RLAST;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_RID;
+input  [C_M_AXI_OUT_MEM_RUSER_WIDTH - 1:0] m_axi_out_mem_RUSER;
+input  [1:0] m_axi_out_mem_RRESP;
+input   m_axi_out_mem_BVALID;
+output   m_axi_out_mem_BREADY;
+input  [1:0] m_axi_out_mem_BRESP;
+input  [C_M_AXI_OUT_MEM_ID_WIDTH - 1:0] m_axi_out_mem_BID;
+input  [C_M_AXI_OUT_MEM_BUSER_WIDTH - 1:0] m_axi_out_mem_BUSER;
+input   s_axi_params_AWVALID;
+output   s_axi_params_AWREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_AWADDR;
+input   s_axi_params_WVALID;
+output   s_axi_params_WREADY;
+input  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_WDATA;
+input  [C_S_AXI_PARAMS_WSTRB_WIDTH - 1:0] s_axi_params_WSTRB;
+input   s_axi_params_ARVALID;
+output   s_axi_params_ARREADY;
+input  [C_S_AXI_PARAMS_ADDR_WIDTH - 1:0] s_axi_params_ARADDR;
+output   s_axi_params_RVALID;
+input   s_axi_params_RREADY;
+output  [C_S_AXI_PARAMS_DATA_WIDTH - 1:0] s_axi_params_RDATA;
+output  [1:0] s_axi_params_RRESP;
+output   s_axi_params_BVALID;
+input   s_axi_params_BREADY;
+output  [1:0] s_axi_params_BRESP;
+output   interrupt;
+
+ reg    ap_rst_n_inv;
+wire    ap_start;
+reg    ap_done;
+reg    ap_idle;
+(* fsm_encoding = "none" *) reg   [27:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    ap_ready;
+wire   [31:0] in1;
+wire   [31:0] in2;
+wire   [31:0] out_r;
+wire   [31:0] dim;
+reg    in1_mem_blk_n_AR;
+wire    ap_CS_fsm_state2;
+reg    in1_mem_blk_n_R;
+wire    ap_CS_fsm_pp0_stage0;
+reg    ap_enable_reg_pp0_iter1;
+wire    ap_block_pp0_stage0;
+reg    in2_mem_blk_n_AR;
+wire    ap_CS_fsm_state12;
+reg    in2_mem_blk_n_R;
+wire    ap_CS_fsm_pp1_stage0;
+reg    ap_enable_reg_pp1_iter1;
+wire    ap_block_pp1_stage0;
+reg    out_mem_blk_n_AW;
+wire    ap_CS_fsm_state34;
+reg    out_mem_blk_n_W;
+reg    ap_enable_reg_pp3_iter2;
+wire    ap_block_pp3_stage0;
+reg   [0:0] icmp_ln42_reg_6380;
+reg   [0:0] icmp_ln42_reg_6380_pp3_iter1_reg;
+reg    out_mem_blk_n_B;
+wire    ap_CS_fsm_state42;
+wire    in1_mem_AWREADY;
+wire    in1_mem_WREADY;
+reg    in1_mem_ARVALID;
+wire    in1_mem_ARREADY;
+wire   [31:0] in1_mem_ARADDR;
+wire    in1_mem_RVALID;
+reg    in1_mem_RREADY;
+wire   [31:0] in1_mem_RDATA;
+wire    in1_mem_RLAST;
+wire   [0:0] in1_mem_RID;
+wire   [0:0] in1_mem_RUSER;
+wire   [1:0] in1_mem_RRESP;
+wire    in1_mem_BVALID;
+wire   [1:0] in1_mem_BRESP;
+wire   [0:0] in1_mem_BID;
+wire   [0:0] in1_mem_BUSER;
+wire    in2_mem_AWREADY;
+wire    in2_mem_WREADY;
+reg    in2_mem_ARVALID;
+wire    in2_mem_ARREADY;
+wire    in2_mem_RVALID;
+reg    in2_mem_RREADY;
+wire   [31:0] in2_mem_RDATA;
+wire    in2_mem_RLAST;
+wire   [0:0] in2_mem_RID;
+wire   [0:0] in2_mem_RUSER;
+wire   [1:0] in2_mem_RRESP;
+wire    in2_mem_BVALID;
+wire   [1:0] in2_mem_BRESP;
+wire   [0:0] in2_mem_BID;
+wire   [0:0] in2_mem_BUSER;
+reg    out_mem_AWVALID;
+wire    out_mem_AWREADY;
+reg    out_mem_WVALID;
+wire    out_mem_WREADY;
+wire    out_mem_ARREADY;
+wire    out_mem_RVALID;
+wire   [31:0] out_mem_RDATA;
+wire    out_mem_RLAST;
+wire   [0:0] out_mem_RID;
+wire   [0:0] out_mem_RUSER;
+wire   [1:0] out_mem_RRESP;
+wire    out_mem_BVALID;
+reg    out_mem_BREADY;
+wire   [1:0] out_mem_BRESP;
+wire   [0:0] out_mem_BID;
+wire   [0:0] out_mem_BUSER;
+reg   [12:0] phi_ln27_reg_3296;
+reg   [12:0] phi_ln28_reg_3307;
+reg   [63:0] indvar_flatten_reg_3318;
+reg   [30:0] i_0_reg_3329;
+reg   [31:0] j_0_reg_3340;
+reg   [12:0] phi_ln42_reg_3351;
+wire   [31:0] out_loc_q0;
+reg   [31:0] reg_3362;
+reg    ap_enable_reg_pp2_iter5;
+wire    ap_block_state25_pp2_stage0_iter0;
+wire    ap_block_state26_pp2_stage0_iter1;
+wire    ap_block_state27_pp2_stage0_iter2;
+wire    ap_block_state28_pp2_stage0_iter3;
+wire    ap_block_state29_pp2_stage0_iter4;
+wire    ap_block_state30_pp2_stage0_iter5;
+wire    ap_block_state31_pp2_stage0_iter6;
+wire    ap_block_state32_pp2_stage0_iter7;
+wire    ap_block_state33_pp2_stage0_iter8;
+wire    ap_block_pp2_stage0_11001;
+reg   [0:0] icmp_ln31_reg_4578;
+reg   [0:0] icmp_ln31_reg_4578_pp2_iter4_reg;
+wire    ap_CS_fsm_pp3_stage0;
+reg    ap_enable_reg_pp3_iter1;
+wire    ap_block_state35_pp3_stage0_iter0;
+wire    ap_block_state36_pp3_stage0_iter1;
+wire    ap_block_state37_pp3_stage0_iter2;
+reg    ap_block_state37_io;
+reg    ap_block_pp3_stage0_11001;
+reg   [31:0] dim_read_reg_4356;
+reg   [29:0] out5_reg_4362;
+reg   [29:0] in_reg_4367;
+reg   [29:0] in3_reg_4372;
+reg   [31:0] out_mem_addr_reg_4383;
+wire    ap_CS_fsm_state8;
+reg   [31:0] in2_mem_addr_reg_4389;
+wire   [0:0] icmp_ln27_fu_3425_p2;
+wire    ap_block_state9_pp0_stage0_iter0;
+reg    ap_block_state10_pp0_stage0_iter1;
+wire    ap_block_state11_pp0_stage0_iter2;
+reg    ap_block_pp0_stage0_11001;
+wire   [12:0] add_ln27_fu_3431_p2;
+reg    ap_enable_reg_pp0_iter0;
+reg   [6:0] lshr_ln_reg_4404;
+reg   [6:0] lshr_ln_reg_4404_pp0_iter1_reg;
+wire   [5:0] trunc_ln27_fu_3447_p1;
+reg   [5:0] trunc_ln27_reg_4409;
+reg   [5:0] trunc_ln27_reg_4409_pp0_iter1_reg;
+reg   [31:0] in1_mem_addr_read_reg_4413;
+wire   [0:0] icmp_ln28_fu_3518_p2;
+wire    ap_block_state19_pp1_stage0_iter0;
+reg    ap_block_state20_pp1_stage0_iter1;
+wire    ap_block_state21_pp1_stage0_iter2;
+reg    ap_block_pp1_stage0_11001;
+wire   [12:0] add_ln28_fu_3524_p2;
+reg    ap_enable_reg_pp1_iter0;
+wire   [5:0] trunc_ln28_fu_3530_p1;
+reg   [5:0] trunc_ln28_reg_4490;
+reg   [5:0] trunc_ln28_reg_4490_pp1_iter1_reg;
+reg   [5:0] trunc_ln1_reg_4495;
+reg   [5:0] trunc_ln1_reg_4495_pp1_iter1_reg;
+reg   [31:0] in2_mem_addr_read_reg_4499;
+wire   [63:0] zext_ln31_fu_3611_p1;
+wire    ap_CS_fsm_state22;
+wire   [63:0] grp_fu_3614_p2;
+reg   [63:0] mul_ln31_reg_4573;
+wire    ap_CS_fsm_state24;
+wire   [0:0] icmp_ln31_fu_3620_p2;
+wire    ap_CS_fsm_pp2_stage0;
+reg   [0:0] icmp_ln31_reg_4578_pp2_iter1_reg;
+reg   [0:0] icmp_ln31_reg_4578_pp2_iter2_reg;
+reg   [0:0] icmp_ln31_reg_4578_pp2_iter3_reg;
+reg   [0:0] icmp_ln31_reg_4578_pp2_iter5_reg;
+reg   [0:0] icmp_ln31_reg_4578_pp2_iter6_reg;
+reg   [0:0] icmp_ln31_reg_4578_pp2_iter7_reg;
+wire   [63:0] add_ln31_fu_3625_p2;
+reg    ap_enable_reg_pp2_iter0;
+wire  signed [31:0] select_ln31_fu_3642_p3;
+reg  signed [31:0] select_ln31_reg_4587;
+wire   [30:0] select_ln31_1_fu_3650_p3;
+reg   [30:0] select_ln31_1_reg_4592;
+reg   [11:0] out_loc_addr_reg_4598;
+reg   [11:0] out_loc_addr_reg_4598_pp2_iter1_reg;
+reg   [11:0] out_loc_addr_reg_4598_pp2_iter2_reg;
+reg   [11:0] out_loc_addr_reg_4598_pp2_iter3_reg;
+reg   [11:0] out_loc_addr_reg_4598_pp2_iter4_reg;
+reg   [11:0] out_loc_addr_reg_4598_pp2_iter5_reg;
+reg   [11:0] out_loc_addr_reg_4598_pp2_iter6_reg;
+reg   [11:0] out_loc_addr_reg_4598_pp2_iter7_reg;
+wire   [31:0] j_fu_3685_p2;
+wire   [63:0] zext_ln31_1_fu_3691_p1;
+reg   [63:0] zext_ln31_1_reg_4609;
+wire  signed [63:0] sext_ln38_fu_3739_p1;
+reg  signed [63:0] sext_ln38_reg_4857;
+wire   [31:0] in1_loc_0_q0;
+reg  signed [31:0] in1_loc_0_load_reg_5105;
+reg    ap_enable_reg_pp2_iter2;
+wire   [31:0] in1_loc_1_q0;
+reg  signed [31:0] in1_loc_1_load_reg_5110;
+wire   [31:0] in1_loc_2_q0;
+reg  signed [31:0] in1_loc_2_load_reg_5115;
+wire   [31:0] in1_loc_3_q0;
+reg  signed [31:0] in1_loc_3_load_reg_5120;
+wire   [31:0] in1_loc_4_q0;
+reg  signed [31:0] in1_loc_4_load_reg_5125;
+wire   [31:0] in1_loc_5_q0;
+reg  signed [31:0] in1_loc_5_load_reg_5130;
+wire   [31:0] in1_loc_6_q0;
+reg  signed [31:0] in1_loc_6_load_reg_5135;
+wire   [31:0] in1_loc_7_q0;
+reg  signed [31:0] in1_loc_7_load_reg_5140;
+wire   [31:0] in1_loc_8_q0;
+reg  signed [31:0] in1_loc_8_load_reg_5145;
+wire   [31:0] in1_loc_11_q0;
+reg  signed [31:0] in1_loc_11_load_reg_5160;
+wire   [31:0] in1_loc_12_q0;
+reg  signed [31:0] in1_loc_12_load_reg_5165;
+wire   [31:0] in1_loc_15_q0;
+reg  signed [31:0] in1_loc_15_load_reg_5180;
+wire   [31:0] in1_loc_16_q0;
+reg  signed [31:0] in1_loc_16_load_reg_5185;
+wire   [31:0] in1_loc_19_q0;
+reg  signed [31:0] in1_loc_19_load_reg_5200;
+wire   [31:0] in1_loc_20_q0;
+reg  signed [31:0] in1_loc_20_load_reg_5205;
+wire   [31:0] in1_loc_21_q0;
+reg  signed [31:0] in1_loc_21_load_reg_5210;
+wire   [31:0] in1_loc_22_q0;
+reg  signed [31:0] in1_loc_22_load_reg_5215;
+wire   [31:0] in1_loc_23_q0;
+reg  signed [31:0] in1_loc_23_load_reg_5220;
+wire   [31:0] in1_loc_24_q0;
+reg  signed [31:0] in1_loc_24_load_reg_5225;
+wire   [31:0] in1_loc_27_q0;
+reg  signed [31:0] in1_loc_27_load_reg_5240;
+wire   [31:0] in1_loc_28_q0;
+reg  signed [31:0] in1_loc_28_load_reg_5245;
+wire   [31:0] in1_loc_29_q0;
+reg  signed [31:0] in1_loc_29_load_reg_5250;
+wire   [31:0] in1_loc_30_q0;
+reg  signed [31:0] in1_loc_30_load_reg_5255;
+wire   [31:0] in1_loc_31_q0;
+reg  signed [31:0] in1_loc_31_load_reg_5260;
+wire   [31:0] in1_loc_32_q0;
+reg  signed [31:0] in1_loc_32_load_reg_5265;
+wire   [31:0] in1_loc_35_q0;
+reg  signed [31:0] in1_loc_35_load_reg_5280;
+wire   [31:0] in1_loc_36_q0;
+reg  signed [31:0] in1_loc_36_load_reg_5285;
+wire   [31:0] in1_loc_37_q0;
+reg  signed [31:0] in1_loc_37_load_reg_5290;
+wire   [31:0] in1_loc_38_q0;
+reg  signed [31:0] in1_loc_38_load_reg_5295;
+wire   [31:0] in1_loc_39_q0;
+reg  signed [31:0] in1_loc_39_load_reg_5300;
+wire   [31:0] in1_loc_40_q0;
+reg  signed [31:0] in1_loc_40_load_reg_5305;
+wire   [31:0] in1_loc_43_q0;
+reg  signed [31:0] in1_loc_43_load_reg_5320;
+wire   [31:0] in1_loc_44_q0;
+reg  signed [31:0] in1_loc_44_load_reg_5325;
+wire   [31:0] in1_loc_47_q0;
+reg  signed [31:0] in1_loc_47_load_reg_5340;
+wire   [31:0] in1_loc_48_q0;
+reg  signed [31:0] in1_loc_48_load_reg_5345;
+wire   [31:0] in1_loc_51_q0;
+reg  signed [31:0] in1_loc_51_load_reg_5360;
+wire   [31:0] in1_loc_52_q0;
+reg  signed [31:0] in1_loc_52_load_reg_5365;
+wire   [31:0] in1_loc_53_q0;
+reg  signed [31:0] in1_loc_53_load_reg_5370;
+wire   [31:0] in1_loc_54_q0;
+reg  signed [31:0] in1_loc_54_load_reg_5375;
+wire   [31:0] in1_loc_55_q0;
+reg  signed [31:0] in1_loc_55_load_reg_5380;
+wire   [31:0] in1_loc_56_q0;
+reg  signed [31:0] in1_loc_56_load_reg_5385;
+wire   [31:0] in1_loc_59_q0;
+reg  signed [31:0] in1_loc_59_load_reg_5400;
+wire   [31:0] in1_loc_60_q0;
+reg  signed [31:0] in1_loc_60_load_reg_5405;
+wire   [31:0] in1_loc_62_q0;
+reg  signed [31:0] in1_loc_62_load_reg_5415;
+wire   [31:0] in1_loc_63_q0;
+reg  signed [31:0] in1_loc_63_load_reg_5420;
+wire   [31:0] in2_loc_0_q0;
+reg  signed [31:0] in2_loc_0_load_reg_5425;
+wire   [31:0] in2_loc_1_q0;
+reg  signed [31:0] in2_loc_1_load_reg_5430;
+wire   [31:0] in2_loc_2_q0;
+reg  signed [31:0] in2_loc_2_load_reg_5435;
+wire   [31:0] in2_loc_3_q0;
+reg  signed [31:0] in2_loc_3_load_reg_5440;
+wire   [31:0] in2_loc_4_q0;
+reg  signed [31:0] in2_loc_4_load_reg_5445;
+wire   [31:0] in2_loc_5_q0;
+reg  signed [31:0] in2_loc_5_load_reg_5450;
+wire   [31:0] in2_loc_6_q0;
+reg  signed [31:0] in2_loc_6_load_reg_5455;
+wire   [31:0] in2_loc_7_q0;
+reg  signed [31:0] in2_loc_7_load_reg_5460;
+wire   [31:0] in2_loc_8_q0;
+reg  signed [31:0] in2_loc_8_load_reg_5465;
+wire   [31:0] in2_loc_11_q0;
+reg  signed [31:0] in2_loc_11_load_reg_5480;
+wire   [31:0] in2_loc_12_q0;
+reg  signed [31:0] in2_loc_12_load_reg_5485;
+wire   [31:0] in2_loc_15_q0;
+reg  signed [31:0] in2_loc_15_load_reg_5500;
+wire   [31:0] in2_loc_16_q0;
+reg  signed [31:0] in2_loc_16_load_reg_5505;
+wire   [31:0] in2_loc_19_q0;
+reg  signed [31:0] in2_loc_19_load_reg_5520;
+wire   [31:0] in2_loc_20_q0;
+reg  signed [31:0] in2_loc_20_load_reg_5525;
+wire   [31:0] in2_loc_21_q0;
+reg  signed [31:0] in2_loc_21_load_reg_5530;
+wire   [31:0] in2_loc_22_q0;
+reg  signed [31:0] in2_loc_22_load_reg_5535;
+wire   [31:0] in2_loc_23_q0;
+reg  signed [31:0] in2_loc_23_load_reg_5540;
+wire   [31:0] in2_loc_24_q0;
+reg  signed [31:0] in2_loc_24_load_reg_5545;
+wire   [31:0] in2_loc_27_q0;
+reg  signed [31:0] in2_loc_27_load_reg_5560;
+wire   [31:0] in2_loc_28_q0;
+reg  signed [31:0] in2_loc_28_load_reg_5565;
+wire   [31:0] in2_loc_29_q0;
+reg  signed [31:0] in2_loc_29_load_reg_5570;
+wire   [31:0] in2_loc_30_q0;
+reg  signed [31:0] in2_loc_30_load_reg_5575;
+wire   [31:0] in2_loc_31_q0;
+reg  signed [31:0] in2_loc_31_load_reg_5580;
+wire   [31:0] in2_loc_32_q0;
+reg  signed [31:0] in2_loc_32_load_reg_5585;
+wire   [31:0] in2_loc_35_q0;
+reg  signed [31:0] in2_loc_35_load_reg_5600;
+wire   [31:0] in2_loc_36_q0;
+reg  signed [31:0] in2_loc_36_load_reg_5605;
+wire   [31:0] in2_loc_37_q0;
+reg  signed [31:0] in2_loc_37_load_reg_5610;
+wire   [31:0] in2_loc_38_q0;
+reg  signed [31:0] in2_loc_38_load_reg_5615;
+wire   [31:0] in2_loc_39_q0;
+reg  signed [31:0] in2_loc_39_load_reg_5620;
+wire   [31:0] in2_loc_40_q0;
+reg  signed [31:0] in2_loc_40_load_reg_5625;
+wire   [31:0] in2_loc_43_q0;
+reg  signed [31:0] in2_loc_43_load_reg_5640;
+wire   [31:0] in2_loc_44_q0;
+reg  signed [31:0] in2_loc_44_load_reg_5645;
+wire   [31:0] in2_loc_47_q0;
+reg  signed [31:0] in2_loc_47_load_reg_5660;
+wire   [31:0] in2_loc_48_q0;
+reg  signed [31:0] in2_loc_48_load_reg_5665;
+wire   [31:0] in2_loc_51_q0;
+reg  signed [31:0] in2_loc_51_load_reg_5680;
+wire   [31:0] in2_loc_52_q0;
+reg  signed [31:0] in2_loc_52_load_reg_5685;
+wire   [31:0] in2_loc_53_q0;
+reg  signed [31:0] in2_loc_53_load_reg_5690;
+wire   [31:0] in2_loc_54_q0;
+reg  signed [31:0] in2_loc_54_load_reg_5695;
+wire   [31:0] in2_loc_55_q0;
+reg  signed [31:0] in2_loc_55_load_reg_5700;
+wire   [31:0] in2_loc_56_q0;
+reg  signed [31:0] in2_loc_56_load_reg_5705;
+wire   [31:0] in2_loc_59_q0;
+reg  signed [31:0] in2_loc_59_load_reg_5720;
+wire   [31:0] in2_loc_60_q0;
+reg  signed [31:0] in2_loc_60_load_reg_5725;
+wire   [31:0] in2_loc_62_q0;
+reg  signed [31:0] in2_loc_62_load_reg_5735;
+wire   [31:0] in2_loc_63_q0;
+reg  signed [31:0] in2_loc_63_load_reg_5740;
+wire   [31:0] in1_loc_9_q0;
+reg  signed [31:0] in1_loc_9_load_reg_5745;
+reg    ap_enable_reg_pp2_iter3;
+wire   [31:0] in1_loc_10_q0;
+reg  signed [31:0] in1_loc_10_load_reg_5750;
+wire   [31:0] in1_loc_13_q0;
+reg  signed [31:0] in1_loc_13_load_reg_5755;
+wire   [31:0] in1_loc_14_q0;
+reg  signed [31:0] in1_loc_14_load_reg_5760;
+wire   [31:0] in1_loc_17_q0;
+reg  signed [31:0] in1_loc_17_load_reg_5765;
+wire   [31:0] in1_loc_18_q0;
+reg  signed [31:0] in1_loc_18_load_reg_5770;
+wire   [31:0] in1_loc_25_q0;
+reg  signed [31:0] in1_loc_25_load_reg_5775;
+wire   [31:0] in1_loc_26_q0;
+reg  signed [31:0] in1_loc_26_load_reg_5780;
+wire   [31:0] in1_loc_33_q0;
+reg  signed [31:0] in1_loc_33_load_reg_5785;
+wire   [31:0] in1_loc_34_q0;
+reg  signed [31:0] in1_loc_34_load_reg_5790;
+wire   [31:0] in1_loc_41_q0;
+reg  signed [31:0] in1_loc_41_load_reg_5795;
+wire   [31:0] in1_loc_42_q0;
+reg  signed [31:0] in1_loc_42_load_reg_5800;
+wire   [31:0] in1_loc_45_q0;
+reg  signed [31:0] in1_loc_45_load_reg_5805;
+wire   [31:0] in1_loc_46_q0;
+reg  signed [31:0] in1_loc_46_load_reg_5810;
+wire   [31:0] in1_loc_49_q0;
+reg  signed [31:0] in1_loc_49_load_reg_5815;
+wire   [31:0] in1_loc_50_q0;
+reg  signed [31:0] in1_loc_50_load_reg_5820;
+wire   [31:0] in1_loc_57_q0;
+reg  signed [31:0] in1_loc_57_load_reg_5825;
+wire   [31:0] in1_loc_58_q0;
+reg  signed [31:0] in1_loc_58_load_reg_5830;
+wire   [31:0] in1_loc_61_q0;
+reg  signed [31:0] in1_loc_61_load_reg_5835;
+wire   [31:0] in2_loc_9_q0;
+reg  signed [31:0] in2_loc_9_load_reg_5840;
+wire   [31:0] in2_loc_10_q0;
+reg  signed [31:0] in2_loc_10_load_reg_5845;
+wire   [31:0] in2_loc_13_q0;
+reg  signed [31:0] in2_loc_13_load_reg_5850;
+wire   [31:0] in2_loc_14_q0;
+reg  signed [31:0] in2_loc_14_load_reg_5855;
+wire   [31:0] in2_loc_17_q0;
+reg  signed [31:0] in2_loc_17_load_reg_5860;
+wire   [31:0] in2_loc_18_q0;
+reg  signed [31:0] in2_loc_18_load_reg_5865;
+wire   [31:0] in2_loc_25_q0;
+reg  signed [31:0] in2_loc_25_load_reg_5870;
+wire   [31:0] in2_loc_26_q0;
+reg  signed [31:0] in2_loc_26_load_reg_5875;
+wire   [31:0] in2_loc_33_q0;
+reg  signed [31:0] in2_loc_33_load_reg_5880;
+wire   [31:0] in2_loc_34_q0;
+reg  signed [31:0] in2_loc_34_load_reg_5885;
+wire   [31:0] in2_loc_41_q0;
+reg  signed [31:0] in2_loc_41_load_reg_5890;
+wire   [31:0] in2_loc_42_q0;
+reg  signed [31:0] in2_loc_42_load_reg_5895;
+wire   [31:0] in2_loc_45_q0;
+reg  signed [31:0] in2_loc_45_load_reg_5900;
+wire   [31:0] in2_loc_46_q0;
+reg  signed [31:0] in2_loc_46_load_reg_5905;
+wire   [31:0] in2_loc_49_q0;
+reg  signed [31:0] in2_loc_49_load_reg_5910;
+wire   [31:0] in2_loc_50_q0;
+reg  signed [31:0] in2_loc_50_load_reg_5915;
+wire   [31:0] in2_loc_57_q0;
+reg  signed [31:0] in2_loc_57_load_reg_5920;
+wire   [31:0] in2_loc_58_q0;
+reg  signed [31:0] in2_loc_58_load_reg_5925;
+wire   [31:0] in2_loc_61_q0;
+reg  signed [31:0] in2_loc_61_load_reg_5930;
+wire   [31:0] grp_fu_3787_p2;
+reg   [31:0] mul_ln38_reg_5935;
+wire   [31:0] grp_fu_3791_p2;
+reg   [31:0] mul_ln38_1_reg_5940;
+wire   [31:0] grp_fu_3795_p2;
+reg   [31:0] mul_ln38_2_reg_5945;
+wire   [31:0] grp_fu_3799_p2;
+reg   [31:0] mul_ln38_3_reg_5950;
+wire   [31:0] grp_fu_3803_p2;
+reg   [31:0] mul_ln38_4_reg_5955;
+wire   [31:0] grp_fu_3807_p2;
+reg   [31:0] mul_ln38_5_reg_5960;
+wire   [31:0] grp_fu_3811_p2;
+reg   [31:0] mul_ln38_6_reg_5965;
+wire   [31:0] grp_fu_3815_p2;
+reg   [31:0] mul_ln38_7_reg_5970;
+wire   [31:0] grp_fu_3819_p2;
+reg   [31:0] mul_ln38_8_reg_5975;
+wire   [31:0] grp_fu_3823_p2;
+reg   [31:0] mul_ln38_11_reg_5980;
+wire   [31:0] grp_fu_3827_p2;
+reg   [31:0] mul_ln38_12_reg_5985;
+wire   [31:0] grp_fu_3831_p2;
+reg   [31:0] mul_ln38_15_reg_5990;
+wire   [31:0] grp_fu_3835_p2;
+reg   [31:0] mul_ln38_16_reg_5995;
+wire   [31:0] grp_fu_3839_p2;
+reg   [31:0] mul_ln38_19_reg_6000;
+wire   [31:0] grp_fu_3843_p2;
+reg   [31:0] mul_ln38_20_reg_6005;
+wire   [31:0] grp_fu_3847_p2;
+reg   [31:0] mul_ln38_21_reg_6010;
+wire   [31:0] grp_fu_3851_p2;
+reg   [31:0] mul_ln38_22_reg_6015;
+wire   [31:0] grp_fu_3855_p2;
+reg   [31:0] mul_ln38_23_reg_6020;
+wire   [31:0] grp_fu_3859_p2;
+reg   [31:0] mul_ln38_24_reg_6025;
+wire   [31:0] grp_fu_3863_p2;
+reg   [31:0] mul_ln38_27_reg_6030;
+wire   [31:0] grp_fu_3867_p2;
+reg   [31:0] mul_ln38_28_reg_6035;
+wire   [31:0] grp_fu_3871_p2;
+reg   [31:0] mul_ln38_29_reg_6040;
+wire   [31:0] grp_fu_3875_p2;
+reg   [31:0] mul_ln38_30_reg_6045;
+wire   [31:0] grp_fu_3879_p2;
+reg   [31:0] mul_ln38_31_reg_6050;
+wire   [31:0] grp_fu_3883_p2;
+reg   [31:0] mul_ln38_32_reg_6055;
+wire   [31:0] grp_fu_3887_p2;
+reg   [31:0] mul_ln38_35_reg_6060;
+wire   [31:0] grp_fu_3891_p2;
+reg   [31:0] mul_ln38_36_reg_6065;
+wire   [31:0] grp_fu_3895_p2;
+reg   [31:0] mul_ln38_37_reg_6070;
+wire   [31:0] grp_fu_3899_p2;
+reg   [31:0] mul_ln38_38_reg_6075;
+wire   [31:0] grp_fu_3903_p2;
+reg   [31:0] mul_ln38_39_reg_6080;
+wire   [31:0] grp_fu_3907_p2;
+reg   [31:0] mul_ln38_40_reg_6085;
+wire   [31:0] grp_fu_3911_p2;
+reg   [31:0] mul_ln38_43_reg_6090;
+wire   [31:0] grp_fu_3915_p2;
+reg   [31:0] mul_ln38_44_reg_6095;
+wire   [31:0] grp_fu_3919_p2;
+reg   [31:0] mul_ln38_47_reg_6100;
+wire   [31:0] grp_fu_3923_p2;
+reg   [31:0] mul_ln38_48_reg_6105;
+wire   [31:0] grp_fu_3927_p2;
+reg   [31:0] mul_ln38_51_reg_6110;
+wire   [31:0] grp_fu_3931_p2;
+reg   [31:0] mul_ln38_52_reg_6115;
+wire   [31:0] grp_fu_3935_p2;
+reg   [31:0] mul_ln38_53_reg_6120;
+wire   [31:0] grp_fu_3939_p2;
+reg   [31:0] mul_ln38_54_reg_6125;
+wire   [31:0] grp_fu_3943_p2;
+reg   [31:0] mul_ln38_55_reg_6130;
+wire   [31:0] grp_fu_3947_p2;
+reg   [31:0] mul_ln38_56_reg_6135;
+wire   [31:0] grp_fu_3951_p2;
+reg   [31:0] mul_ln38_59_reg_6140;
+wire   [31:0] grp_fu_3955_p2;
+reg   [31:0] mul_ln38_60_reg_6145;
+wire   [31:0] grp_fu_3959_p2;
+reg   [31:0] mul_ln38_62_reg_6150;
+wire   [31:0] grp_fu_3963_p2;
+reg   [31:0] mul_ln38_63_reg_6155;
+wire   [31:0] grp_fu_3967_p2;
+reg   [31:0] mul_ln38_9_reg_6160;
+wire   [31:0] grp_fu_3971_p2;
+reg   [31:0] mul_ln38_10_reg_6165;
+wire   [31:0] grp_fu_3975_p2;
+reg   [31:0] mul_ln38_13_reg_6170;
+wire   [31:0] grp_fu_3979_p2;
+reg   [31:0] mul_ln38_14_reg_6175;
+wire   [31:0] grp_fu_3983_p2;
+reg   [31:0] mul_ln38_17_reg_6180;
+wire   [31:0] grp_fu_3987_p2;
+reg   [31:0] mul_ln38_18_reg_6185;
+wire   [31:0] grp_fu_3991_p2;
+reg   [31:0] mul_ln38_25_reg_6190;
+wire   [31:0] grp_fu_3995_p2;
+reg   [31:0] mul_ln38_26_reg_6195;
+wire   [31:0] grp_fu_3999_p2;
+reg   [31:0] mul_ln38_33_reg_6200;
+wire   [31:0] grp_fu_4003_p2;
+reg   [31:0] mul_ln38_34_reg_6205;
+wire   [31:0] grp_fu_4007_p2;
+reg   [31:0] mul_ln38_41_reg_6210;
+wire   [31:0] grp_fu_4011_p2;
+reg   [31:0] mul_ln38_42_reg_6215;
+wire   [31:0] grp_fu_4015_p2;
+reg   [31:0] mul_ln38_45_reg_6220;
+wire   [31:0] grp_fu_4019_p2;
+reg   [31:0] mul_ln38_46_reg_6225;
+wire   [31:0] grp_fu_4023_p2;
+reg   [31:0] mul_ln38_49_reg_6230;
+wire   [31:0] grp_fu_4027_p2;
+reg   [31:0] mul_ln38_50_reg_6235;
+wire   [31:0] grp_fu_4031_p2;
+reg   [31:0] mul_ln38_57_reg_6240;
+wire   [31:0] grp_fu_4035_p2;
+reg   [31:0] mul_ln38_58_reg_6245;
+wire   [31:0] grp_fu_4039_p2;
+reg   [31:0] mul_ln38_61_reg_6250;
+wire   [31:0] add_ln38_2_fu_4052_p2;
+reg   [31:0] add_ln38_2_reg_6255;
+wire   [31:0] add_ln38_3_fu_4058_p2;
+reg   [31:0] add_ln38_3_reg_6260;
+wire   [31:0] add_ln38_4_fu_4062_p2;
+reg   [31:0] add_ln38_4_reg_6265;
+wire   [31:0] add_ln38_7_fu_4066_p2;
+reg   [31:0] add_ln38_7_reg_6270;
+wire   [31:0] add_ln38_10_fu_4070_p2;
+reg   [31:0] add_ln38_10_reg_6275;
+wire   [31:0] add_ln38_15_fu_4074_p2;
+reg   [31:0] add_ln38_15_reg_6280;
+wire   [31:0] add_ln38_18_fu_4078_p2;
+reg   [31:0] add_ln38_18_reg_6285;
+wire   [31:0] add_ln38_19_fu_4082_p2;
+reg   [31:0] add_ln38_19_reg_6290;
+wire   [31:0] add_ln38_22_fu_4086_p2;
+reg   [31:0] add_ln38_22_reg_6295;
+wire   [31:0] add_ln38_25_fu_4090_p2;
+reg   [31:0] add_ln38_25_reg_6300;
+wire   [31:0] add_ln38_26_fu_4094_p2;
+reg   [31:0] add_ln38_26_reg_6305;
+wire   [31:0] add_ln38_31_fu_4098_p2;
+reg   [31:0] add_ln38_31_reg_6310;
+wire   [31:0] add_ln38_34_fu_4102_p2;
+reg   [31:0] add_ln38_34_reg_6315;
+wire   [31:0] add_ln38_35_fu_4106_p2;
+reg   [31:0] add_ln38_35_reg_6320;
+wire   [31:0] add_ln38_38_fu_4110_p2;
+reg   [31:0] add_ln38_38_reg_6325;
+wire   [31:0] add_ln38_41_fu_4114_p2;
+reg   [31:0] add_ln38_41_reg_6330;
+wire   [31:0] add_ln38_46_fu_4118_p2;
+reg   [31:0] add_ln38_46_reg_6335;
+wire   [31:0] add_ln38_49_fu_4122_p2;
+reg   [31:0] add_ln38_49_reg_6340;
+wire   [31:0] add_ln38_50_fu_4126_p2;
+reg   [31:0] add_ln38_50_reg_6345;
+wire   [31:0] add_ln38_53_fu_4130_p2;
+reg   [31:0] add_ln38_53_reg_6350;
+wire   [31:0] add_ln38_56_fu_4134_p2;
+reg   [31:0] add_ln38_56_reg_6355;
+wire   [31:0] add_ln38_57_fu_4138_p2;
+reg   [31:0] add_ln38_57_reg_6360;
+wire   [31:0] add_ln38_30_fu_4225_p2;
+reg   [31:0] add_ln38_30_reg_6365;
+wire   [31:0] add_ln38_45_fu_4274_p2;
+reg   [31:0] add_ln38_45_reg_6370;
+wire   [31:0] add_ln38_61_fu_4323_p2;
+reg   [31:0] add_ln38_61_reg_6375;
+wire   [0:0] icmp_ln42_fu_4339_p2;
+wire   [12:0] add_ln42_fu_4345_p2;
+reg    ap_enable_reg_pp3_iter0;
+reg    ap_block_pp0_stage0_subdone;
+reg    ap_condition_pp0_exit_iter0_state9;
+reg    ap_enable_reg_pp0_iter2;
+wire    ap_CS_fsm_state18;
+reg    ap_block_pp1_stage0_subdone;
+reg    ap_condition_pp1_exit_iter0_state19;
+reg    ap_enable_reg_pp1_iter2;
+wire    ap_block_pp2_stage0_subdone;
+reg    ap_condition_pp2_exit_iter0_state25;
+reg    ap_enable_reg_pp2_iter1;
+reg    ap_enable_reg_pp2_iter4;
+reg    ap_enable_reg_pp2_iter6;
+reg    ap_enable_reg_pp2_iter7;
+reg    ap_enable_reg_pp2_iter8;
+reg    ap_block_pp3_stage0_subdone;
+reg    ap_condition_pp3_exit_iter0_state35;
+reg   [5:0] in1_loc_0_address0;
+reg    in1_loc_0_ce0;
+reg    in1_loc_0_we0;
+reg   [5:0] in1_loc_1_address0;
+reg    in1_loc_1_ce0;
+reg    in1_loc_1_we0;
+reg   [5:0] in1_loc_2_address0;
+reg    in1_loc_2_ce0;
+reg    in1_loc_2_we0;
+reg   [5:0] in1_loc_3_address0;
+reg    in1_loc_3_ce0;
+reg    in1_loc_3_we0;
+reg   [5:0] in1_loc_4_address0;
+reg    in1_loc_4_ce0;
+reg    in1_loc_4_we0;
+reg   [5:0] in1_loc_5_address0;
+reg    in1_loc_5_ce0;
+reg    in1_loc_5_we0;
+reg   [5:0] in1_loc_6_address0;
+reg    in1_loc_6_ce0;
+reg    in1_loc_6_we0;
+reg   [5:0] in1_loc_7_address0;
+reg    in1_loc_7_ce0;
+reg    in1_loc_7_we0;
+reg   [5:0] in1_loc_8_address0;
+reg    in1_loc_8_ce0;
+reg    in1_loc_8_we0;
+reg   [5:0] in1_loc_9_address0;
+reg    in1_loc_9_ce0;
+reg    in1_loc_9_we0;
+reg   [5:0] in1_loc_10_address0;
+reg    in1_loc_10_ce0;
+reg    in1_loc_10_we0;
+reg   [5:0] in1_loc_11_address0;
+reg    in1_loc_11_ce0;
+reg    in1_loc_11_we0;
+reg   [5:0] in1_loc_12_address0;
+reg    in1_loc_12_ce0;
+reg    in1_loc_12_we0;
+reg   [5:0] in1_loc_13_address0;
+reg    in1_loc_13_ce0;
+reg    in1_loc_13_we0;
+reg   [5:0] in1_loc_14_address0;
+reg    in1_loc_14_ce0;
+reg    in1_loc_14_we0;
+reg   [5:0] in1_loc_15_address0;
+reg    in1_loc_15_ce0;
+reg    in1_loc_15_we0;
+reg   [5:0] in1_loc_16_address0;
+reg    in1_loc_16_ce0;
+reg    in1_loc_16_we0;
+reg   [5:0] in1_loc_17_address0;
+reg    in1_loc_17_ce0;
+reg    in1_loc_17_we0;
+reg   [5:0] in1_loc_18_address0;
+reg    in1_loc_18_ce0;
+reg    in1_loc_18_we0;
+reg   [5:0] in1_loc_19_address0;
+reg    in1_loc_19_ce0;
+reg    in1_loc_19_we0;
+reg   [5:0] in1_loc_20_address0;
+reg    in1_loc_20_ce0;
+reg    in1_loc_20_we0;
+reg   [5:0] in1_loc_21_address0;
+reg    in1_loc_21_ce0;
+reg    in1_loc_21_we0;
+reg   [5:0] in1_loc_22_address0;
+reg    in1_loc_22_ce0;
+reg    in1_loc_22_we0;
+reg   [5:0] in1_loc_23_address0;
+reg    in1_loc_23_ce0;
+reg    in1_loc_23_we0;
+reg   [5:0] in1_loc_24_address0;
+reg    in1_loc_24_ce0;
+reg    in1_loc_24_we0;
+reg   [5:0] in1_loc_25_address0;
+reg    in1_loc_25_ce0;
+reg    in1_loc_25_we0;
+reg   [5:0] in1_loc_26_address0;
+reg    in1_loc_26_ce0;
+reg    in1_loc_26_we0;
+reg   [5:0] in1_loc_27_address0;
+reg    in1_loc_27_ce0;
+reg    in1_loc_27_we0;
+reg   [5:0] in1_loc_28_address0;
+reg    in1_loc_28_ce0;
+reg    in1_loc_28_we0;
+reg   [5:0] in1_loc_29_address0;
+reg    in1_loc_29_ce0;
+reg    in1_loc_29_we0;
+reg   [5:0] in1_loc_30_address0;
+reg    in1_loc_30_ce0;
+reg    in1_loc_30_we0;
+reg   [5:0] in1_loc_31_address0;
+reg    in1_loc_31_ce0;
+reg    in1_loc_31_we0;
+reg   [5:0] in1_loc_32_address0;
+reg    in1_loc_32_ce0;
+reg    in1_loc_32_we0;
+reg   [5:0] in1_loc_33_address0;
+reg    in1_loc_33_ce0;
+reg    in1_loc_33_we0;
+reg   [5:0] in1_loc_34_address0;
+reg    in1_loc_34_ce0;
+reg    in1_loc_34_we0;
+reg   [5:0] in1_loc_35_address0;
+reg    in1_loc_35_ce0;
+reg    in1_loc_35_we0;
+reg   [5:0] in1_loc_36_address0;
+reg    in1_loc_36_ce0;
+reg    in1_loc_36_we0;
+reg   [5:0] in1_loc_37_address0;
+reg    in1_loc_37_ce0;
+reg    in1_loc_37_we0;
+reg   [5:0] in1_loc_38_address0;
+reg    in1_loc_38_ce0;
+reg    in1_loc_38_we0;
+reg   [5:0] in1_loc_39_address0;
+reg    in1_loc_39_ce0;
+reg    in1_loc_39_we0;
+reg   [5:0] in1_loc_40_address0;
+reg    in1_loc_40_ce0;
+reg    in1_loc_40_we0;
+reg   [5:0] in1_loc_41_address0;
+reg    in1_loc_41_ce0;
+reg    in1_loc_41_we0;
+reg   [5:0] in1_loc_42_address0;
+reg    in1_loc_42_ce0;
+reg    in1_loc_42_we0;
+reg   [5:0] in1_loc_43_address0;
+reg    in1_loc_43_ce0;
+reg    in1_loc_43_we0;
+reg   [5:0] in1_loc_44_address0;
+reg    in1_loc_44_ce0;
+reg    in1_loc_44_we0;
+reg   [5:0] in1_loc_45_address0;
+reg    in1_loc_45_ce0;
+reg    in1_loc_45_we0;
+reg   [5:0] in1_loc_46_address0;
+reg    in1_loc_46_ce0;
+reg    in1_loc_46_we0;
+reg   [5:0] in1_loc_47_address0;
+reg    in1_loc_47_ce0;
+reg    in1_loc_47_we0;
+reg   [5:0] in1_loc_48_address0;
+reg    in1_loc_48_ce0;
+reg    in1_loc_48_we0;
+reg   [5:0] in1_loc_49_address0;
+reg    in1_loc_49_ce0;
+reg    in1_loc_49_we0;
+reg   [5:0] in1_loc_50_address0;
+reg    in1_loc_50_ce0;
+reg    in1_loc_50_we0;
+reg   [5:0] in1_loc_51_address0;
+reg    in1_loc_51_ce0;
+reg    in1_loc_51_we0;
+reg   [5:0] in1_loc_52_address0;
+reg    in1_loc_52_ce0;
+reg    in1_loc_52_we0;
+reg   [5:0] in1_loc_53_address0;
+reg    in1_loc_53_ce0;
+reg    in1_loc_53_we0;
+reg   [5:0] in1_loc_54_address0;
+reg    in1_loc_54_ce0;
+reg    in1_loc_54_we0;
+reg   [5:0] in1_loc_55_address0;
+reg    in1_loc_55_ce0;
+reg    in1_loc_55_we0;
+reg   [5:0] in1_loc_56_address0;
+reg    in1_loc_56_ce0;
+reg    in1_loc_56_we0;
+reg   [5:0] in1_loc_57_address0;
+reg    in1_loc_57_ce0;
+reg    in1_loc_57_we0;
+reg   [5:0] in1_loc_58_address0;
+reg    in1_loc_58_ce0;
+reg    in1_loc_58_we0;
+reg   [5:0] in1_loc_59_address0;
+reg    in1_loc_59_ce0;
+reg    in1_loc_59_we0;
+reg   [5:0] in1_loc_60_address0;
+reg    in1_loc_60_ce0;
+reg    in1_loc_60_we0;
+reg   [5:0] in1_loc_61_address0;
+reg    in1_loc_61_ce0;
+reg    in1_loc_61_we0;
+reg   [5:0] in1_loc_62_address0;
+reg    in1_loc_62_ce0;
+reg    in1_loc_62_we0;
+reg   [5:0] in1_loc_63_address0;
+reg    in1_loc_63_ce0;
+reg    in1_loc_63_we0;
+reg   [5:0] in2_loc_0_address0;
+reg    in2_loc_0_ce0;
+reg    in2_loc_0_we0;
+reg   [5:0] in2_loc_1_address0;
+reg    in2_loc_1_ce0;
+reg    in2_loc_1_we0;
+reg   [5:0] in2_loc_2_address0;
+reg    in2_loc_2_ce0;
+reg    in2_loc_2_we0;
+reg   [5:0] in2_loc_3_address0;
+reg    in2_loc_3_ce0;
+reg    in2_loc_3_we0;
+reg   [5:0] in2_loc_4_address0;
+reg    in2_loc_4_ce0;
+reg    in2_loc_4_we0;
+reg   [5:0] in2_loc_5_address0;
+reg    in2_loc_5_ce0;
+reg    in2_loc_5_we0;
+reg   [5:0] in2_loc_6_address0;
+reg    in2_loc_6_ce0;
+reg    in2_loc_6_we0;
+reg   [5:0] in2_loc_7_address0;
+reg    in2_loc_7_ce0;
+reg    in2_loc_7_we0;
+reg   [5:0] in2_loc_8_address0;
+reg    in2_loc_8_ce0;
+reg    in2_loc_8_we0;
+reg   [5:0] in2_loc_9_address0;
+reg    in2_loc_9_ce0;
+reg    in2_loc_9_we0;
+reg   [5:0] in2_loc_10_address0;
+reg    in2_loc_10_ce0;
+reg    in2_loc_10_we0;
+reg   [5:0] in2_loc_11_address0;
+reg    in2_loc_11_ce0;
+reg    in2_loc_11_we0;
+reg   [5:0] in2_loc_12_address0;
+reg    in2_loc_12_ce0;
+reg    in2_loc_12_we0;
+reg   [5:0] in2_loc_13_address0;
+reg    in2_loc_13_ce0;
+reg    in2_loc_13_we0;
+reg   [5:0] in2_loc_14_address0;
+reg    in2_loc_14_ce0;
+reg    in2_loc_14_we0;
+reg   [5:0] in2_loc_15_address0;
+reg    in2_loc_15_ce0;
+reg    in2_loc_15_we0;
+reg   [5:0] in2_loc_16_address0;
+reg    in2_loc_16_ce0;
+reg    in2_loc_16_we0;
+reg   [5:0] in2_loc_17_address0;
+reg    in2_loc_17_ce0;
+reg    in2_loc_17_we0;
+reg   [5:0] in2_loc_18_address0;
+reg    in2_loc_18_ce0;
+reg    in2_loc_18_we0;
+reg   [5:0] in2_loc_19_address0;
+reg    in2_loc_19_ce0;
+reg    in2_loc_19_we0;
+reg   [5:0] in2_loc_20_address0;
+reg    in2_loc_20_ce0;
+reg    in2_loc_20_we0;
+reg   [5:0] in2_loc_21_address0;
+reg    in2_loc_21_ce0;
+reg    in2_loc_21_we0;
+reg   [5:0] in2_loc_22_address0;
+reg    in2_loc_22_ce0;
+reg    in2_loc_22_we0;
+reg   [5:0] in2_loc_23_address0;
+reg    in2_loc_23_ce0;
+reg    in2_loc_23_we0;
+reg   [5:0] in2_loc_24_address0;
+reg    in2_loc_24_ce0;
+reg    in2_loc_24_we0;
+reg   [5:0] in2_loc_25_address0;
+reg    in2_loc_25_ce0;
+reg    in2_loc_25_we0;
+reg   [5:0] in2_loc_26_address0;
+reg    in2_loc_26_ce0;
+reg    in2_loc_26_we0;
+reg   [5:0] in2_loc_27_address0;
+reg    in2_loc_27_ce0;
+reg    in2_loc_27_we0;
+reg   [5:0] in2_loc_28_address0;
+reg    in2_loc_28_ce0;
+reg    in2_loc_28_we0;
+reg   [5:0] in2_loc_29_address0;
+reg    in2_loc_29_ce0;
+reg    in2_loc_29_we0;
+reg   [5:0] in2_loc_30_address0;
+reg    in2_loc_30_ce0;
+reg    in2_loc_30_we0;
+reg   [5:0] in2_loc_31_address0;
+reg    in2_loc_31_ce0;
+reg    in2_loc_31_we0;
+reg   [5:0] in2_loc_32_address0;
+reg    in2_loc_32_ce0;
+reg    in2_loc_32_we0;
+reg   [5:0] in2_loc_33_address0;
+reg    in2_loc_33_ce0;
+reg    in2_loc_33_we0;
+reg   [5:0] in2_loc_34_address0;
+reg    in2_loc_34_ce0;
+reg    in2_loc_34_we0;
+reg   [5:0] in2_loc_35_address0;
+reg    in2_loc_35_ce0;
+reg    in2_loc_35_we0;
+reg   [5:0] in2_loc_36_address0;
+reg    in2_loc_36_ce0;
+reg    in2_loc_36_we0;
+reg   [5:0] in2_loc_37_address0;
+reg    in2_loc_37_ce0;
+reg    in2_loc_37_we0;
+reg   [5:0] in2_loc_38_address0;
+reg    in2_loc_38_ce0;
+reg    in2_loc_38_we0;
+reg   [5:0] in2_loc_39_address0;
+reg    in2_loc_39_ce0;
+reg    in2_loc_39_we0;
+reg   [5:0] in2_loc_40_address0;
+reg    in2_loc_40_ce0;
+reg    in2_loc_40_we0;
+reg   [5:0] in2_loc_41_address0;
+reg    in2_loc_41_ce0;
+reg    in2_loc_41_we0;
+reg   [5:0] in2_loc_42_address0;
+reg    in2_loc_42_ce0;
+reg    in2_loc_42_we0;
+reg   [5:0] in2_loc_43_address0;
+reg    in2_loc_43_ce0;
+reg    in2_loc_43_we0;
+reg   [5:0] in2_loc_44_address0;
+reg    in2_loc_44_ce0;
+reg    in2_loc_44_we0;
+reg   [5:0] in2_loc_45_address0;
+reg    in2_loc_45_ce0;
+reg    in2_loc_45_we0;
+reg   [5:0] in2_loc_46_address0;
+reg    in2_loc_46_ce0;
+reg    in2_loc_46_we0;
+reg   [5:0] in2_loc_47_address0;
+reg    in2_loc_47_ce0;
+reg    in2_loc_47_we0;
+reg   [5:0] in2_loc_48_address0;
+reg    in2_loc_48_ce0;
+reg    in2_loc_48_we0;
+reg   [5:0] in2_loc_49_address0;
+reg    in2_loc_49_ce0;
+reg    in2_loc_49_we0;
+reg   [5:0] in2_loc_50_address0;
+reg    in2_loc_50_ce0;
+reg    in2_loc_50_we0;
+reg   [5:0] in2_loc_51_address0;
+reg    in2_loc_51_ce0;
+reg    in2_loc_51_we0;
+reg   [5:0] in2_loc_52_address0;
+reg    in2_loc_52_ce0;
+reg    in2_loc_52_we0;
+reg   [5:0] in2_loc_53_address0;
+reg    in2_loc_53_ce0;
+reg    in2_loc_53_we0;
+reg   [5:0] in2_loc_54_address0;
+reg    in2_loc_54_ce0;
+reg    in2_loc_54_we0;
+reg   [5:0] in2_loc_55_address0;
+reg    in2_loc_55_ce0;
+reg    in2_loc_55_we0;
+reg   [5:0] in2_loc_56_address0;
+reg    in2_loc_56_ce0;
+reg    in2_loc_56_we0;
+reg   [5:0] in2_loc_57_address0;
+reg    in2_loc_57_ce0;
+reg    in2_loc_57_we0;
+reg   [5:0] in2_loc_58_address0;
+reg    in2_loc_58_ce0;
+reg    in2_loc_58_we0;
+reg   [5:0] in2_loc_59_address0;
+reg    in2_loc_59_ce0;
+reg    in2_loc_59_we0;
+reg   [5:0] in2_loc_60_address0;
+reg    in2_loc_60_ce0;
+reg    in2_loc_60_we0;
+reg   [5:0] in2_loc_61_address0;
+reg    in2_loc_61_ce0;
+reg    in2_loc_61_we0;
+reg   [5:0] in2_loc_62_address0;
+reg    in2_loc_62_ce0;
+reg    in2_loc_62_we0;
+reg   [5:0] in2_loc_63_address0;
+reg    in2_loc_63_ce0;
+reg    in2_loc_63_we0;
+reg   [11:0] out_loc_address0;
+reg    out_loc_ce0;
+reg    out_loc_ce1;
+reg    out_loc_we1;
+wire   [31:0] out_loc_d1;
+reg   [30:0] ap_phi_mux_i_0_phi_fu_3333_p4;
+wire    ap_block_pp2_stage0;
+wire   [63:0] zext_ln27_fu_3451_p1;
+wire   [63:0] zext_ln28_fu_3544_p1;
+wire   [63:0] zext_ln38_fu_3680_p1;
+wire   [63:0] zext_ln42_fu_4351_p1;
+wire   [63:0] empty_8_fu_3397_p1;
+wire   [63:0] empty_fu_3407_p1;
+wire   [63:0] empty_7_fu_3416_p1;
+wire    ap_block_pp3_stage0_01001;
+wire   [31:0] grp_fu_3614_p0;
+wire   [31:0] grp_fu_3614_p1;
+wire   [0:0] icmp_ln33_fu_3637_p2;
+wire   [30:0] i_fu_3631_p2;
+wire   [7:0] trunc_ln38_fu_3658_p1;
+wire   [13:0] tmp_cast_fu_3662_p3;
+wire   [13:0] trunc_ln38_1_fu_3670_p1;
+wire   [13:0] add_ln38_64_fu_3674_p2;
+wire   [31:0] add_ln38_fu_4043_p2;
+wire   [31:0] add_ln38_1_fu_4048_p2;
+wire   [31:0] add_ln38_5_fu_4142_p2;
+wire   [31:0] add_ln38_8_fu_4151_p2;
+wire   [31:0] add_ln38_11_fu_4160_p2;
+wire   [31:0] add_ln38_9_fu_4155_p2;
+wire   [31:0] add_ln38_12_fu_4164_p2;
+wire   [31:0] add_ln38_6_fu_4146_p2;
+wire   [31:0] add_ln38_13_fu_4169_p2;
+wire   [31:0] add_ln38_16_fu_4181_p2;
+wire   [31:0] add_ln38_17_fu_4185_p2;
+wire   [31:0] add_ln38_20_fu_4190_p2;
+wire   [31:0] add_ln38_23_fu_4200_p2;
+wire   [31:0] add_ln38_24_fu_4204_p2;
+wire   [31:0] add_ln38_27_fu_4209_p2;
+wire   [31:0] add_ln38_21_fu_4194_p2;
+wire   [31:0] add_ln38_28_fu_4213_p2;
+wire   [31:0] add_ln38_14_fu_4175_p2;
+wire   [31:0] add_ln38_29_fu_4219_p2;
+wire   [31:0] add_ln38_32_fu_4231_p2;
+wire   [31:0] add_ln38_33_fu_4235_p2;
+wire   [31:0] add_ln38_36_fu_4240_p2;
+wire   [31:0] add_ln38_39_fu_4250_p2;
+wire   [31:0] add_ln38_42_fu_4259_p2;
+wire   [31:0] add_ln38_40_fu_4254_p2;
+wire   [31:0] add_ln38_43_fu_4263_p2;
+wire   [31:0] add_ln38_37_fu_4244_p2;
+wire   [31:0] add_ln38_44_fu_4268_p2;
+wire   [31:0] add_ln38_47_fu_4280_p2;
+wire   [31:0] add_ln38_48_fu_4284_p2;
+wire   [31:0] add_ln38_51_fu_4289_p2;
+wire   [31:0] add_ln38_54_fu_4299_p2;
+wire   [31:0] add_ln38_58_fu_4308_p2;
+wire   [31:0] add_ln38_55_fu_4303_p2;
+wire   [31:0] add_ln38_59_fu_4312_p2;
+wire   [31:0] add_ln38_52_fu_4293_p2;
+wire   [31:0] add_ln38_60_fu_4317_p2;
+wire   [31:0] add_ln38_62_fu_4329_p2;
+reg   [27:0] ap_NS_fsm;
+reg    ap_idle_pp0;
+wire    ap_enable_pp0;
+reg    ap_idle_pp1;
+wire    ap_enable_pp1;
+reg    ap_idle_pp2;
+wire    ap_enable_pp2;
+reg    ap_idle_pp3;
+wire    ap_enable_pp3;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 28'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_enable_reg_pp1_iter1 = 1'b0;
+#0 ap_enable_reg_pp3_iter2 = 1'b0;
+#0 ap_enable_reg_pp2_iter5 = 1'b0;
+#0 ap_enable_reg_pp3_iter1 = 1'b0;
+#0 ap_enable_reg_pp0_iter0 = 1'b0;
+#0 ap_enable_reg_pp1_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter0 = 1'b0;
+#0 ap_enable_reg_pp2_iter2 = 1'b0;
+#0 ap_enable_reg_pp2_iter3 = 1'b0;
+#0 ap_enable_reg_pp3_iter0 = 1'b0;
+#0 ap_enable_reg_pp0_iter2 = 1'b0;
+#0 ap_enable_reg_pp1_iter2 = 1'b0;
+#0 ap_enable_reg_pp2_iter1 = 1'b0;
+#0 ap_enable_reg_pp2_iter4 = 1'b0;
+#0 ap_enable_reg_pp2_iter6 = 1'b0;
+#0 ap_enable_reg_pp2_iter7 = 1'b0;
+#0 ap_enable_reg_pp2_iter8 = 1'b0;
+end
+
+mmult_params_s_axi #(
+    .C_S_AXI_ADDR_WIDTH( C_S_AXI_PARAMS_ADDR_WIDTH ),
+    .C_S_AXI_DATA_WIDTH( C_S_AXI_PARAMS_DATA_WIDTH ))
+mmult_params_s_axi_U(
+    .AWVALID(s_axi_params_AWVALID),
+    .AWREADY(s_axi_params_AWREADY),
+    .AWADDR(s_axi_params_AWADDR),
+    .WVALID(s_axi_params_WVALID),
+    .WREADY(s_axi_params_WREADY),
+    .WDATA(s_axi_params_WDATA),
+    .WSTRB(s_axi_params_WSTRB),
+    .ARVALID(s_axi_params_ARVALID),
+    .ARREADY(s_axi_params_ARREADY),
+    .ARADDR(s_axi_params_ARADDR),
+    .RVALID(s_axi_params_RVALID),
+    .RREADY(s_axi_params_RREADY),
+    .RDATA(s_axi_params_RDATA),
+    .RRESP(s_axi_params_RRESP),
+    .BVALID(s_axi_params_BVALID),
+    .BREADY(s_axi_params_BREADY),
+    .BRESP(s_axi_params_BRESP),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .ap_start(ap_start),
+    .interrupt(interrupt),
+    .ap_ready(ap_ready),
+    .ap_done(ap_done),
+    .ap_idle(ap_idle),
+    .in1(in1),
+    .in2(in2),
+    .out_r(out_r),
+    .dim(dim)
+);
+
+mmult_in1_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN1_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN1_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN1_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN1_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN1_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN1_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN1_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN1_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN1_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN1_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN1_MEM_CACHE_VALUE ))
+mmult_in1_mem_m_axi_U(
+    .AWVALID(m_axi_in1_mem_AWVALID),
+    .AWREADY(m_axi_in1_mem_AWREADY),
+    .AWADDR(m_axi_in1_mem_AWADDR),
+    .AWID(m_axi_in1_mem_AWID),
+    .AWLEN(m_axi_in1_mem_AWLEN),
+    .AWSIZE(m_axi_in1_mem_AWSIZE),
+    .AWBURST(m_axi_in1_mem_AWBURST),
+    .AWLOCK(m_axi_in1_mem_AWLOCK),
+    .AWCACHE(m_axi_in1_mem_AWCACHE),
+    .AWPROT(m_axi_in1_mem_AWPROT),
+    .AWQOS(m_axi_in1_mem_AWQOS),
+    .AWREGION(m_axi_in1_mem_AWREGION),
+    .AWUSER(m_axi_in1_mem_AWUSER),
+    .WVALID(m_axi_in1_mem_WVALID),
+    .WREADY(m_axi_in1_mem_WREADY),
+    .WDATA(m_axi_in1_mem_WDATA),
+    .WSTRB(m_axi_in1_mem_WSTRB),
+    .WLAST(m_axi_in1_mem_WLAST),
+    .WID(m_axi_in1_mem_WID),
+    .WUSER(m_axi_in1_mem_WUSER),
+    .ARVALID(m_axi_in1_mem_ARVALID),
+    .ARREADY(m_axi_in1_mem_ARREADY),
+    .ARADDR(m_axi_in1_mem_ARADDR),
+    .ARID(m_axi_in1_mem_ARID),
+    .ARLEN(m_axi_in1_mem_ARLEN),
+    .ARSIZE(m_axi_in1_mem_ARSIZE),
+    .ARBURST(m_axi_in1_mem_ARBURST),
+    .ARLOCK(m_axi_in1_mem_ARLOCK),
+    .ARCACHE(m_axi_in1_mem_ARCACHE),
+    .ARPROT(m_axi_in1_mem_ARPROT),
+    .ARQOS(m_axi_in1_mem_ARQOS),
+    .ARREGION(m_axi_in1_mem_ARREGION),
+    .ARUSER(m_axi_in1_mem_ARUSER),
+    .RVALID(m_axi_in1_mem_RVALID),
+    .RREADY(m_axi_in1_mem_RREADY),
+    .RDATA(m_axi_in1_mem_RDATA),
+    .RLAST(m_axi_in1_mem_RLAST),
+    .RID(m_axi_in1_mem_RID),
+    .RUSER(m_axi_in1_mem_RUSER),
+    .RRESP(m_axi_in1_mem_RRESP),
+    .BVALID(m_axi_in1_mem_BVALID),
+    .BREADY(m_axi_in1_mem_BREADY),
+    .BRESP(m_axi_in1_mem_BRESP),
+    .BID(m_axi_in1_mem_BID),
+    .BUSER(m_axi_in1_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in1_mem_ARVALID),
+    .I_ARREADY(in1_mem_ARREADY),
+    .I_ARADDR(in1_mem_ARADDR),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in1_mem_RVALID),
+    .I_RREADY(in1_mem_RREADY),
+    .I_RDATA(in1_mem_RDATA),
+    .I_RID(in1_mem_RID),
+    .I_RUSER(in1_mem_RUSER),
+    .I_RRESP(in1_mem_RRESP),
+    .I_RLAST(in1_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in1_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in1_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in1_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in1_mem_BRESP),
+    .I_BID(in1_mem_BID),
+    .I_BUSER(in1_mem_BUSER)
+);
+
+mmult_in2_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_IN2_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_IN2_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_IN2_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_IN2_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_IN2_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_IN2_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_IN2_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_IN2_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_IN2_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_IN2_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_IN2_MEM_CACHE_VALUE ))
+mmult_in2_mem_m_axi_U(
+    .AWVALID(m_axi_in2_mem_AWVALID),
+    .AWREADY(m_axi_in2_mem_AWREADY),
+    .AWADDR(m_axi_in2_mem_AWADDR),
+    .AWID(m_axi_in2_mem_AWID),
+    .AWLEN(m_axi_in2_mem_AWLEN),
+    .AWSIZE(m_axi_in2_mem_AWSIZE),
+    .AWBURST(m_axi_in2_mem_AWBURST),
+    .AWLOCK(m_axi_in2_mem_AWLOCK),
+    .AWCACHE(m_axi_in2_mem_AWCACHE),
+    .AWPROT(m_axi_in2_mem_AWPROT),
+    .AWQOS(m_axi_in2_mem_AWQOS),
+    .AWREGION(m_axi_in2_mem_AWREGION),
+    .AWUSER(m_axi_in2_mem_AWUSER),
+    .WVALID(m_axi_in2_mem_WVALID),
+    .WREADY(m_axi_in2_mem_WREADY),
+    .WDATA(m_axi_in2_mem_WDATA),
+    .WSTRB(m_axi_in2_mem_WSTRB),
+    .WLAST(m_axi_in2_mem_WLAST),
+    .WID(m_axi_in2_mem_WID),
+    .WUSER(m_axi_in2_mem_WUSER),
+    .ARVALID(m_axi_in2_mem_ARVALID),
+    .ARREADY(m_axi_in2_mem_ARREADY),
+    .ARADDR(m_axi_in2_mem_ARADDR),
+    .ARID(m_axi_in2_mem_ARID),
+    .ARLEN(m_axi_in2_mem_ARLEN),
+    .ARSIZE(m_axi_in2_mem_ARSIZE),
+    .ARBURST(m_axi_in2_mem_ARBURST),
+    .ARLOCK(m_axi_in2_mem_ARLOCK),
+    .ARCACHE(m_axi_in2_mem_ARCACHE),
+    .ARPROT(m_axi_in2_mem_ARPROT),
+    .ARQOS(m_axi_in2_mem_ARQOS),
+    .ARREGION(m_axi_in2_mem_ARREGION),
+    .ARUSER(m_axi_in2_mem_ARUSER),
+    .RVALID(m_axi_in2_mem_RVALID),
+    .RREADY(m_axi_in2_mem_RREADY),
+    .RDATA(m_axi_in2_mem_RDATA),
+    .RLAST(m_axi_in2_mem_RLAST),
+    .RID(m_axi_in2_mem_RID),
+    .RUSER(m_axi_in2_mem_RUSER),
+    .RRESP(m_axi_in2_mem_RRESP),
+    .BVALID(m_axi_in2_mem_BVALID),
+    .BREADY(m_axi_in2_mem_BREADY),
+    .BRESP(m_axi_in2_mem_BRESP),
+    .BID(m_axi_in2_mem_BID),
+    .BUSER(m_axi_in2_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(in2_mem_ARVALID),
+    .I_ARREADY(in2_mem_ARREADY),
+    .I_ARADDR(in2_mem_addr_reg_4389),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd4096),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(in2_mem_RVALID),
+    .I_RREADY(in2_mem_RREADY),
+    .I_RDATA(in2_mem_RDATA),
+    .I_RID(in2_mem_RID),
+    .I_RUSER(in2_mem_RUSER),
+    .I_RRESP(in2_mem_RRESP),
+    .I_RLAST(in2_mem_RLAST),
+    .I_AWVALID(1'b0),
+    .I_AWREADY(in2_mem_AWREADY),
+    .I_AWADDR(32'd0),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd0),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(1'b0),
+    .I_WREADY(in2_mem_WREADY),
+    .I_WDATA(32'd0),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd0),
+    .I_BVALID(in2_mem_BVALID),
+    .I_BREADY(1'b0),
+    .I_BRESP(in2_mem_BRESP),
+    .I_BID(in2_mem_BID),
+    .I_BUSER(in2_mem_BUSER)
+);
+
+mmult_out_mem_m_axi #(
+    .CONSERVATIVE( 0 ),
+    .USER_DW( 32 ),
+    .USER_AW( 32 ),
+    .USER_MAXREQS( 5 ),
+    .NUM_READ_OUTSTANDING( 16 ),
+    .NUM_WRITE_OUTSTANDING( 16 ),
+    .MAX_READ_BURST_LENGTH( 16 ),
+    .MAX_WRITE_BURST_LENGTH( 16 ),
+    .C_M_AXI_ID_WIDTH( C_M_AXI_OUT_MEM_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH( C_M_AXI_OUT_MEM_ADDR_WIDTH ),
+    .C_M_AXI_DATA_WIDTH( C_M_AXI_OUT_MEM_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH( C_M_AXI_OUT_MEM_AWUSER_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH( C_M_AXI_OUT_MEM_ARUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH( C_M_AXI_OUT_MEM_WUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH( C_M_AXI_OUT_MEM_RUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH( C_M_AXI_OUT_MEM_BUSER_WIDTH ),
+    .C_USER_VALUE( C_M_AXI_OUT_MEM_USER_VALUE ),
+    .C_PROT_VALUE( C_M_AXI_OUT_MEM_PROT_VALUE ),
+    .C_CACHE_VALUE( C_M_AXI_OUT_MEM_CACHE_VALUE ))
+mmult_out_mem_m_axi_U(
+    .AWVALID(m_axi_out_mem_AWVALID),
+    .AWREADY(m_axi_out_mem_AWREADY),
+    .AWADDR(m_axi_out_mem_AWADDR),
+    .AWID(m_axi_out_mem_AWID),
+    .AWLEN(m_axi_out_mem_AWLEN),
+    .AWSIZE(m_axi_out_mem_AWSIZE),
+    .AWBURST(m_axi_out_mem_AWBURST),
+    .AWLOCK(m_axi_out_mem_AWLOCK),
+    .AWCACHE(m_axi_out_mem_AWCACHE),
+    .AWPROT(m_axi_out_mem_AWPROT),
+    .AWQOS(m_axi_out_mem_AWQOS),
+    .AWREGION(m_axi_out_mem_AWREGION),
+    .AWUSER(m_axi_out_mem_AWUSER),
+    .WVALID(m_axi_out_mem_WVALID),
+    .WREADY(m_axi_out_mem_WREADY),
+    .WDATA(m_axi_out_mem_WDATA),
+    .WSTRB(m_axi_out_mem_WSTRB),
+    .WLAST(m_axi_out_mem_WLAST),
+    .WID(m_axi_out_mem_WID),
+    .WUSER(m_axi_out_mem_WUSER),
+    .ARVALID(m_axi_out_mem_ARVALID),
+    .ARREADY(m_axi_out_mem_ARREADY),
+    .ARADDR(m_axi_out_mem_ARADDR),
+    .ARID(m_axi_out_mem_ARID),
+    .ARLEN(m_axi_out_mem_ARLEN),
+    .ARSIZE(m_axi_out_mem_ARSIZE),
+    .ARBURST(m_axi_out_mem_ARBURST),
+    .ARLOCK(m_axi_out_mem_ARLOCK),
+    .ARCACHE(m_axi_out_mem_ARCACHE),
+    .ARPROT(m_axi_out_mem_ARPROT),
+    .ARQOS(m_axi_out_mem_ARQOS),
+    .ARREGION(m_axi_out_mem_ARREGION),
+    .ARUSER(m_axi_out_mem_ARUSER),
+    .RVALID(m_axi_out_mem_RVALID),
+    .RREADY(m_axi_out_mem_RREADY),
+    .RDATA(m_axi_out_mem_RDATA),
+    .RLAST(m_axi_out_mem_RLAST),
+    .RID(m_axi_out_mem_RID),
+    .RUSER(m_axi_out_mem_RUSER),
+    .RRESP(m_axi_out_mem_RRESP),
+    .BVALID(m_axi_out_mem_BVALID),
+    .BREADY(m_axi_out_mem_BREADY),
+    .BRESP(m_axi_out_mem_BRESP),
+    .BID(m_axi_out_mem_BID),
+    .BUSER(m_axi_out_mem_BUSER),
+    .ACLK(ap_clk),
+    .ARESET(ap_rst_n_inv),
+    .ACLK_EN(1'b1),
+    .I_ARVALID(1'b0),
+    .I_ARREADY(out_mem_ARREADY),
+    .I_ARADDR(32'd0),
+    .I_ARID(1'd0),
+    .I_ARLEN(32'd0),
+    .I_ARSIZE(3'd0),
+    .I_ARLOCK(2'd0),
+    .I_ARCACHE(4'd0),
+    .I_ARQOS(4'd0),
+    .I_ARPROT(3'd0),
+    .I_ARUSER(1'd0),
+    .I_ARBURST(2'd0),
+    .I_ARREGION(4'd0),
+    .I_RVALID(out_mem_RVALID),
+    .I_RREADY(1'b0),
+    .I_RDATA(out_mem_RDATA),
+    .I_RID(out_mem_RID),
+    .I_RUSER(out_mem_RUSER),
+    .I_RRESP(out_mem_RRESP),
+    .I_RLAST(out_mem_RLAST),
+    .I_AWVALID(out_mem_AWVALID),
+    .I_AWREADY(out_mem_AWREADY),
+    .I_AWADDR(out_mem_addr_reg_4383),
+    .I_AWID(1'd0),
+    .I_AWLEN(32'd4096),
+    .I_AWSIZE(3'd0),
+    .I_AWLOCK(2'd0),
+    .I_AWCACHE(4'd0),
+    .I_AWQOS(4'd0),
+    .I_AWPROT(3'd0),
+    .I_AWUSER(1'd0),
+    .I_AWBURST(2'd0),
+    .I_AWREGION(4'd0),
+    .I_WVALID(out_mem_WVALID),
+    .I_WREADY(out_mem_WREADY),
+    .I_WDATA(reg_3362),
+    .I_WID(1'd0),
+    .I_WUSER(1'd0),
+    .I_WLAST(1'b0),
+    .I_WSTRB(4'd15),
+    .I_BVALID(out_mem_BVALID),
+    .I_BREADY(out_mem_BREADY),
+    .I_BRESP(out_mem_BRESP),
+    .I_BID(out_mem_BID),
+    .I_BUSER(out_mem_BUSER)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_0_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_0_address0),
+    .ce0(in1_loc_0_ce0),
+    .we0(in1_loc_0_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_0_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_1_address0),
+    .ce0(in1_loc_1_ce0),
+    .we0(in1_loc_1_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_1_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_2_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_2_address0),
+    .ce0(in1_loc_2_ce0),
+    .we0(in1_loc_2_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_2_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_3_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_3_address0),
+    .ce0(in1_loc_3_ce0),
+    .we0(in1_loc_3_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_3_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_4_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_4_address0),
+    .ce0(in1_loc_4_ce0),
+    .we0(in1_loc_4_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_4_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_5_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_5_address0),
+    .ce0(in1_loc_5_ce0),
+    .we0(in1_loc_5_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_5_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_6_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_6_address0),
+    .ce0(in1_loc_6_ce0),
+    .we0(in1_loc_6_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_6_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_7_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_7_address0),
+    .ce0(in1_loc_7_ce0),
+    .we0(in1_loc_7_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_7_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_8_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_8_address0),
+    .ce0(in1_loc_8_ce0),
+    .we0(in1_loc_8_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_8_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_9_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_9_address0),
+    .ce0(in1_loc_9_ce0),
+    .we0(in1_loc_9_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_9_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_10_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_10_address0),
+    .ce0(in1_loc_10_ce0),
+    .we0(in1_loc_10_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_10_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_11_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_11_address0),
+    .ce0(in1_loc_11_ce0),
+    .we0(in1_loc_11_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_11_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_12_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_12_address0),
+    .ce0(in1_loc_12_ce0),
+    .we0(in1_loc_12_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_12_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_13_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_13_address0),
+    .ce0(in1_loc_13_ce0),
+    .we0(in1_loc_13_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_13_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_14_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_14_address0),
+    .ce0(in1_loc_14_ce0),
+    .we0(in1_loc_14_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_14_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_15_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_15_address0),
+    .ce0(in1_loc_15_ce0),
+    .we0(in1_loc_15_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_15_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_16_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_16_address0),
+    .ce0(in1_loc_16_ce0),
+    .we0(in1_loc_16_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_16_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_17_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_17_address0),
+    .ce0(in1_loc_17_ce0),
+    .we0(in1_loc_17_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_17_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_18_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_18_address0),
+    .ce0(in1_loc_18_ce0),
+    .we0(in1_loc_18_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_18_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_19_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_19_address0),
+    .ce0(in1_loc_19_ce0),
+    .we0(in1_loc_19_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_19_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_20_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_20_address0),
+    .ce0(in1_loc_20_ce0),
+    .we0(in1_loc_20_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_20_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_21_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_21_address0),
+    .ce0(in1_loc_21_ce0),
+    .we0(in1_loc_21_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_21_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_22_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_22_address0),
+    .ce0(in1_loc_22_ce0),
+    .we0(in1_loc_22_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_22_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_23_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_23_address0),
+    .ce0(in1_loc_23_ce0),
+    .we0(in1_loc_23_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_23_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_24_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_24_address0),
+    .ce0(in1_loc_24_ce0),
+    .we0(in1_loc_24_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_24_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_25_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_25_address0),
+    .ce0(in1_loc_25_ce0),
+    .we0(in1_loc_25_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_25_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_26_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_26_address0),
+    .ce0(in1_loc_26_ce0),
+    .we0(in1_loc_26_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_26_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_27_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_27_address0),
+    .ce0(in1_loc_27_ce0),
+    .we0(in1_loc_27_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_27_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_28_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_28_address0),
+    .ce0(in1_loc_28_ce0),
+    .we0(in1_loc_28_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_28_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_29_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_29_address0),
+    .ce0(in1_loc_29_ce0),
+    .we0(in1_loc_29_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_29_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_30_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_30_address0),
+    .ce0(in1_loc_30_ce0),
+    .we0(in1_loc_30_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_30_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_31_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_31_address0),
+    .ce0(in1_loc_31_ce0),
+    .we0(in1_loc_31_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_31_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_32_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_32_address0),
+    .ce0(in1_loc_32_ce0),
+    .we0(in1_loc_32_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_32_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_33_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_33_address0),
+    .ce0(in1_loc_33_ce0),
+    .we0(in1_loc_33_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_33_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_34_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_34_address0),
+    .ce0(in1_loc_34_ce0),
+    .we0(in1_loc_34_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_34_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_35_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_35_address0),
+    .ce0(in1_loc_35_ce0),
+    .we0(in1_loc_35_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_35_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_36_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_36_address0),
+    .ce0(in1_loc_36_ce0),
+    .we0(in1_loc_36_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_36_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_37_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_37_address0),
+    .ce0(in1_loc_37_ce0),
+    .we0(in1_loc_37_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_37_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_38_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_38_address0),
+    .ce0(in1_loc_38_ce0),
+    .we0(in1_loc_38_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_38_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_39_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_39_address0),
+    .ce0(in1_loc_39_ce0),
+    .we0(in1_loc_39_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_39_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_40_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_40_address0),
+    .ce0(in1_loc_40_ce0),
+    .we0(in1_loc_40_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_40_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_41_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_41_address0),
+    .ce0(in1_loc_41_ce0),
+    .we0(in1_loc_41_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_41_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_42_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_42_address0),
+    .ce0(in1_loc_42_ce0),
+    .we0(in1_loc_42_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_42_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_43_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_43_address0),
+    .ce0(in1_loc_43_ce0),
+    .we0(in1_loc_43_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_43_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_44_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_44_address0),
+    .ce0(in1_loc_44_ce0),
+    .we0(in1_loc_44_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_44_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_45_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_45_address0),
+    .ce0(in1_loc_45_ce0),
+    .we0(in1_loc_45_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_45_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_46_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_46_address0),
+    .ce0(in1_loc_46_ce0),
+    .we0(in1_loc_46_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_46_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_47_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_47_address0),
+    .ce0(in1_loc_47_ce0),
+    .we0(in1_loc_47_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_47_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_48_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_48_address0),
+    .ce0(in1_loc_48_ce0),
+    .we0(in1_loc_48_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_48_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_49_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_49_address0),
+    .ce0(in1_loc_49_ce0),
+    .we0(in1_loc_49_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_49_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_50_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_50_address0),
+    .ce0(in1_loc_50_ce0),
+    .we0(in1_loc_50_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_50_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_51_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_51_address0),
+    .ce0(in1_loc_51_ce0),
+    .we0(in1_loc_51_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_51_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_52_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_52_address0),
+    .ce0(in1_loc_52_ce0),
+    .we0(in1_loc_52_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_52_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_53_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_53_address0),
+    .ce0(in1_loc_53_ce0),
+    .we0(in1_loc_53_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_53_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_54_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_54_address0),
+    .ce0(in1_loc_54_ce0),
+    .we0(in1_loc_54_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_54_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_55_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_55_address0),
+    .ce0(in1_loc_55_ce0),
+    .we0(in1_loc_55_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_55_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_56_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_56_address0),
+    .ce0(in1_loc_56_ce0),
+    .we0(in1_loc_56_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_56_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_57_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_57_address0),
+    .ce0(in1_loc_57_ce0),
+    .we0(in1_loc_57_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_57_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_58_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_58_address0),
+    .ce0(in1_loc_58_ce0),
+    .we0(in1_loc_58_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_58_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_59_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_59_address0),
+    .ce0(in1_loc_59_ce0),
+    .we0(in1_loc_59_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_59_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_60_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_60_address0),
+    .ce0(in1_loc_60_ce0),
+    .we0(in1_loc_60_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_60_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_61_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_61_address0),
+    .ce0(in1_loc_61_ce0),
+    .we0(in1_loc_61_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_61_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_62_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_62_address0),
+    .ce0(in1_loc_62_ce0),
+    .we0(in1_loc_62_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_62_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in1_loc_63_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in1_loc_63_address0),
+    .ce0(in1_loc_63_ce0),
+    .we0(in1_loc_63_we0),
+    .d0(in1_mem_addr_read_reg_4413),
+    .q0(in1_loc_63_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_0_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_0_address0),
+    .ce0(in2_loc_0_ce0),
+    .we0(in2_loc_0_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_0_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_1_address0),
+    .ce0(in2_loc_1_ce0),
+    .we0(in2_loc_1_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_1_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_2_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_2_address0),
+    .ce0(in2_loc_2_ce0),
+    .we0(in2_loc_2_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_2_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_3_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_3_address0),
+    .ce0(in2_loc_3_ce0),
+    .we0(in2_loc_3_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_3_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_4_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_4_address0),
+    .ce0(in2_loc_4_ce0),
+    .we0(in2_loc_4_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_4_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_5_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_5_address0),
+    .ce0(in2_loc_5_ce0),
+    .we0(in2_loc_5_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_5_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_6_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_6_address0),
+    .ce0(in2_loc_6_ce0),
+    .we0(in2_loc_6_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_6_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_7_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_7_address0),
+    .ce0(in2_loc_7_ce0),
+    .we0(in2_loc_7_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_7_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_8_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_8_address0),
+    .ce0(in2_loc_8_ce0),
+    .we0(in2_loc_8_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_8_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_9_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_9_address0),
+    .ce0(in2_loc_9_ce0),
+    .we0(in2_loc_9_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_9_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_10_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_10_address0),
+    .ce0(in2_loc_10_ce0),
+    .we0(in2_loc_10_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_10_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_11_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_11_address0),
+    .ce0(in2_loc_11_ce0),
+    .we0(in2_loc_11_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_11_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_12_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_12_address0),
+    .ce0(in2_loc_12_ce0),
+    .we0(in2_loc_12_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_12_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_13_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_13_address0),
+    .ce0(in2_loc_13_ce0),
+    .we0(in2_loc_13_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_13_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_14_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_14_address0),
+    .ce0(in2_loc_14_ce0),
+    .we0(in2_loc_14_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_14_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_15_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_15_address0),
+    .ce0(in2_loc_15_ce0),
+    .we0(in2_loc_15_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_15_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_16_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_16_address0),
+    .ce0(in2_loc_16_ce0),
+    .we0(in2_loc_16_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_16_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_17_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_17_address0),
+    .ce0(in2_loc_17_ce0),
+    .we0(in2_loc_17_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_17_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_18_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_18_address0),
+    .ce0(in2_loc_18_ce0),
+    .we0(in2_loc_18_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_18_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_19_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_19_address0),
+    .ce0(in2_loc_19_ce0),
+    .we0(in2_loc_19_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_19_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_20_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_20_address0),
+    .ce0(in2_loc_20_ce0),
+    .we0(in2_loc_20_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_20_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_21_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_21_address0),
+    .ce0(in2_loc_21_ce0),
+    .we0(in2_loc_21_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_21_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_22_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_22_address0),
+    .ce0(in2_loc_22_ce0),
+    .we0(in2_loc_22_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_22_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_23_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_23_address0),
+    .ce0(in2_loc_23_ce0),
+    .we0(in2_loc_23_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_23_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_24_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_24_address0),
+    .ce0(in2_loc_24_ce0),
+    .we0(in2_loc_24_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_24_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_25_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_25_address0),
+    .ce0(in2_loc_25_ce0),
+    .we0(in2_loc_25_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_25_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_26_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_26_address0),
+    .ce0(in2_loc_26_ce0),
+    .we0(in2_loc_26_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_26_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_27_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_27_address0),
+    .ce0(in2_loc_27_ce0),
+    .we0(in2_loc_27_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_27_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_28_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_28_address0),
+    .ce0(in2_loc_28_ce0),
+    .we0(in2_loc_28_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_28_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_29_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_29_address0),
+    .ce0(in2_loc_29_ce0),
+    .we0(in2_loc_29_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_29_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_30_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_30_address0),
+    .ce0(in2_loc_30_ce0),
+    .we0(in2_loc_30_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_30_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_31_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_31_address0),
+    .ce0(in2_loc_31_ce0),
+    .we0(in2_loc_31_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_31_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_32_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_32_address0),
+    .ce0(in2_loc_32_ce0),
+    .we0(in2_loc_32_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_32_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_33_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_33_address0),
+    .ce0(in2_loc_33_ce0),
+    .we0(in2_loc_33_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_33_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_34_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_34_address0),
+    .ce0(in2_loc_34_ce0),
+    .we0(in2_loc_34_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_34_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_35_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_35_address0),
+    .ce0(in2_loc_35_ce0),
+    .we0(in2_loc_35_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_35_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_36_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_36_address0),
+    .ce0(in2_loc_36_ce0),
+    .we0(in2_loc_36_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_36_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_37_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_37_address0),
+    .ce0(in2_loc_37_ce0),
+    .we0(in2_loc_37_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_37_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_38_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_38_address0),
+    .ce0(in2_loc_38_ce0),
+    .we0(in2_loc_38_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_38_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_39_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_39_address0),
+    .ce0(in2_loc_39_ce0),
+    .we0(in2_loc_39_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_39_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_40_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_40_address0),
+    .ce0(in2_loc_40_ce0),
+    .we0(in2_loc_40_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_40_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_41_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_41_address0),
+    .ce0(in2_loc_41_ce0),
+    .we0(in2_loc_41_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_41_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_42_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_42_address0),
+    .ce0(in2_loc_42_ce0),
+    .we0(in2_loc_42_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_42_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_43_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_43_address0),
+    .ce0(in2_loc_43_ce0),
+    .we0(in2_loc_43_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_43_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_44_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_44_address0),
+    .ce0(in2_loc_44_ce0),
+    .we0(in2_loc_44_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_44_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_45_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_45_address0),
+    .ce0(in2_loc_45_ce0),
+    .we0(in2_loc_45_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_45_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_46_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_46_address0),
+    .ce0(in2_loc_46_ce0),
+    .we0(in2_loc_46_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_46_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_47_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_47_address0),
+    .ce0(in2_loc_47_ce0),
+    .we0(in2_loc_47_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_47_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_48_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_48_address0),
+    .ce0(in2_loc_48_ce0),
+    .we0(in2_loc_48_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_48_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_49_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_49_address0),
+    .ce0(in2_loc_49_ce0),
+    .we0(in2_loc_49_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_49_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_50_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_50_address0),
+    .ce0(in2_loc_50_ce0),
+    .we0(in2_loc_50_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_50_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_51_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_51_address0),
+    .ce0(in2_loc_51_ce0),
+    .we0(in2_loc_51_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_51_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_52_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_52_address0),
+    .ce0(in2_loc_52_ce0),
+    .we0(in2_loc_52_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_52_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_53_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_53_address0),
+    .ce0(in2_loc_53_ce0),
+    .we0(in2_loc_53_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_53_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_54_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_54_address0),
+    .ce0(in2_loc_54_ce0),
+    .we0(in2_loc_54_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_54_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_55_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_55_address0),
+    .ce0(in2_loc_55_ce0),
+    .we0(in2_loc_55_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_55_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_56_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_56_address0),
+    .ce0(in2_loc_56_ce0),
+    .we0(in2_loc_56_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_56_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_57_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_57_address0),
+    .ce0(in2_loc_57_ce0),
+    .we0(in2_loc_57_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_57_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_58_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_58_address0),
+    .ce0(in2_loc_58_ce0),
+    .we0(in2_loc_58_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_58_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_59_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_59_address0),
+    .ce0(in2_loc_59_ce0),
+    .we0(in2_loc_59_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_59_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_60_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_60_address0),
+    .ce0(in2_loc_60_ce0),
+    .we0(in2_loc_60_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_60_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_61_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_61_address0),
+    .ce0(in2_loc_61_ce0),
+    .we0(in2_loc_61_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_61_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_62_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_62_address0),
+    .ce0(in2_loc_62_ce0),
+    .we0(in2_loc_62_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_62_q0)
+);
+
+mmult_in1_loc_0 #(
+    .DataWidth( 32 ),
+    .AddressRange( 64 ),
+    .AddressWidth( 6 ))
+in2_loc_63_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(in2_loc_63_address0),
+    .ce0(in2_loc_63_ce0),
+    .we0(in2_loc_63_we0),
+    .d0(in2_mem_addr_read_reg_4499),
+    .q0(in2_loc_63_q0)
+);
+
+mmult_out_loc #(
+    .DataWidth( 32 ),
+    .AddressRange( 4096 ),
+    .AddressWidth( 12 ))
+out_loc_U(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .address0(out_loc_address0),
+    .ce0(out_loc_ce0),
+    .q0(out_loc_q0),
+    .address1(out_loc_addr_reg_4598_pp2_iter7_reg),
+    .ce1(out_loc_ce1),
+    .we1(out_loc_we1),
+    .d1(out_loc_d1)
+);
+
+mmult_mul_32ns_32bkb #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 64 ))
+mmult_mul_32ns_32bkb_U1(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(grp_fu_3614_p0),
+    .din1(grp_fu_3614_p1),
+    .ce(1'b1),
+    .dout(grp_fu_3614_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U2(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_0_load_reg_5425),
+    .din1(in1_loc_0_load_reg_5105),
+    .ce(1'b1),
+    .dout(grp_fu_3787_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U3(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_1_load_reg_5430),
+    .din1(in1_loc_1_load_reg_5110),
+    .ce(1'b1),
+    .dout(grp_fu_3791_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U4(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_2_load_reg_5435),
+    .din1(in1_loc_2_load_reg_5115),
+    .ce(1'b1),
+    .dout(grp_fu_3795_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U5(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_3_load_reg_5440),
+    .din1(in1_loc_3_load_reg_5120),
+    .ce(1'b1),
+    .dout(grp_fu_3799_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U6(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_4_load_reg_5445),
+    .din1(in1_loc_4_load_reg_5125),
+    .ce(1'b1),
+    .dout(grp_fu_3803_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U7(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_5_load_reg_5450),
+    .din1(in1_loc_5_load_reg_5130),
+    .ce(1'b1),
+    .dout(grp_fu_3807_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U8(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_6_load_reg_5455),
+    .din1(in1_loc_6_load_reg_5135),
+    .ce(1'b1),
+    .dout(grp_fu_3811_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U9(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_7_load_reg_5460),
+    .din1(in1_loc_7_load_reg_5140),
+    .ce(1'b1),
+    .dout(grp_fu_3815_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U10(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_8_load_reg_5465),
+    .din1(in1_loc_8_load_reg_5145),
+    .ce(1'b1),
+    .dout(grp_fu_3819_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U11(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_11_load_reg_5480),
+    .din1(in1_loc_11_load_reg_5160),
+    .ce(1'b1),
+    .dout(grp_fu_3823_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U12(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_12_load_reg_5485),
+    .din1(in1_loc_12_load_reg_5165),
+    .ce(1'b1),
+    .dout(grp_fu_3827_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U13(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_15_load_reg_5500),
+    .din1(in1_loc_15_load_reg_5180),
+    .ce(1'b1),
+    .dout(grp_fu_3831_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U14(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_16_load_reg_5505),
+    .din1(in1_loc_16_load_reg_5185),
+    .ce(1'b1),
+    .dout(grp_fu_3835_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U15(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_19_load_reg_5520),
+    .din1(in1_loc_19_load_reg_5200),
+    .ce(1'b1),
+    .dout(grp_fu_3839_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U16(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_20_load_reg_5525),
+    .din1(in1_loc_20_load_reg_5205),
+    .ce(1'b1),
+    .dout(grp_fu_3843_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U17(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_21_load_reg_5530),
+    .din1(in1_loc_21_load_reg_5210),
+    .ce(1'b1),
+    .dout(grp_fu_3847_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U18(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_22_load_reg_5535),
+    .din1(in1_loc_22_load_reg_5215),
+    .ce(1'b1),
+    .dout(grp_fu_3851_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U19(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_23_load_reg_5540),
+    .din1(in1_loc_23_load_reg_5220),
+    .ce(1'b1),
+    .dout(grp_fu_3855_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U20(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_24_load_reg_5545),
+    .din1(in1_loc_24_load_reg_5225),
+    .ce(1'b1),
+    .dout(grp_fu_3859_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U21(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_27_load_reg_5560),
+    .din1(in1_loc_27_load_reg_5240),
+    .ce(1'b1),
+    .dout(grp_fu_3863_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U22(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_28_load_reg_5565),
+    .din1(in1_loc_28_load_reg_5245),
+    .ce(1'b1),
+    .dout(grp_fu_3867_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U23(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_29_load_reg_5570),
+    .din1(in1_loc_29_load_reg_5250),
+    .ce(1'b1),
+    .dout(grp_fu_3871_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U24(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_30_load_reg_5575),
+    .din1(in1_loc_30_load_reg_5255),
+    .ce(1'b1),
+    .dout(grp_fu_3875_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U25(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_31_load_reg_5580),
+    .din1(in1_loc_31_load_reg_5260),
+    .ce(1'b1),
+    .dout(grp_fu_3879_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U26(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_32_load_reg_5585),
+    .din1(in1_loc_32_load_reg_5265),
+    .ce(1'b1),
+    .dout(grp_fu_3883_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U27(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_35_load_reg_5600),
+    .din1(in1_loc_35_load_reg_5280),
+    .ce(1'b1),
+    .dout(grp_fu_3887_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U28(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_36_load_reg_5605),
+    .din1(in1_loc_36_load_reg_5285),
+    .ce(1'b1),
+    .dout(grp_fu_3891_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U29(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_37_load_reg_5610),
+    .din1(in1_loc_37_load_reg_5290),
+    .ce(1'b1),
+    .dout(grp_fu_3895_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U30(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_38_load_reg_5615),
+    .din1(in1_loc_38_load_reg_5295),
+    .ce(1'b1),
+    .dout(grp_fu_3899_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U31(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_39_load_reg_5620),
+    .din1(in1_loc_39_load_reg_5300),
+    .ce(1'b1),
+    .dout(grp_fu_3903_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U32(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_40_load_reg_5625),
+    .din1(in1_loc_40_load_reg_5305),
+    .ce(1'b1),
+    .dout(grp_fu_3907_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U33(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_43_load_reg_5640),
+    .din1(in1_loc_43_load_reg_5320),
+    .ce(1'b1),
+    .dout(grp_fu_3911_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U34(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_44_load_reg_5645),
+    .din1(in1_loc_44_load_reg_5325),
+    .ce(1'b1),
+    .dout(grp_fu_3915_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U35(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_47_load_reg_5660),
+    .din1(in1_loc_47_load_reg_5340),
+    .ce(1'b1),
+    .dout(grp_fu_3919_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U36(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_48_load_reg_5665),
+    .din1(in1_loc_48_load_reg_5345),
+    .ce(1'b1),
+    .dout(grp_fu_3923_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U37(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_51_load_reg_5680),
+    .din1(in1_loc_51_load_reg_5360),
+    .ce(1'b1),
+    .dout(grp_fu_3927_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U38(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_52_load_reg_5685),
+    .din1(in1_loc_52_load_reg_5365),
+    .ce(1'b1),
+    .dout(grp_fu_3931_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U39(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_53_load_reg_5690),
+    .din1(in1_loc_53_load_reg_5370),
+    .ce(1'b1),
+    .dout(grp_fu_3935_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U40(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_54_load_reg_5695),
+    .din1(in1_loc_54_load_reg_5375),
+    .ce(1'b1),
+    .dout(grp_fu_3939_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U41(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_55_load_reg_5700),
+    .din1(in1_loc_55_load_reg_5380),
+    .ce(1'b1),
+    .dout(grp_fu_3943_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U42(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_56_load_reg_5705),
+    .din1(in1_loc_56_load_reg_5385),
+    .ce(1'b1),
+    .dout(grp_fu_3947_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U43(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_59_load_reg_5720),
+    .din1(in1_loc_59_load_reg_5400),
+    .ce(1'b1),
+    .dout(grp_fu_3951_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U44(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_60_load_reg_5725),
+    .din1(in1_loc_60_load_reg_5405),
+    .ce(1'b1),
+    .dout(grp_fu_3955_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U45(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_62_load_reg_5735),
+    .din1(in1_loc_62_load_reg_5415),
+    .ce(1'b1),
+    .dout(grp_fu_3959_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U46(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_63_load_reg_5740),
+    .din1(in1_loc_63_load_reg_5420),
+    .ce(1'b1),
+    .dout(grp_fu_3963_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U47(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_9_load_reg_5840),
+    .din1(in1_loc_9_load_reg_5745),
+    .ce(1'b1),
+    .dout(grp_fu_3967_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U48(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_10_load_reg_5845),
+    .din1(in1_loc_10_load_reg_5750),
+    .ce(1'b1),
+    .dout(grp_fu_3971_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U49(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_13_load_reg_5850),
+    .din1(in1_loc_13_load_reg_5755),
+    .ce(1'b1),
+    .dout(grp_fu_3975_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U50(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_14_load_reg_5855),
+    .din1(in1_loc_14_load_reg_5760),
+    .ce(1'b1),
+    .dout(grp_fu_3979_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U51(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_17_load_reg_5860),
+    .din1(in1_loc_17_load_reg_5765),
+    .ce(1'b1),
+    .dout(grp_fu_3983_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U52(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_18_load_reg_5865),
+    .din1(in1_loc_18_load_reg_5770),
+    .ce(1'b1),
+    .dout(grp_fu_3987_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U53(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_25_load_reg_5870),
+    .din1(in1_loc_25_load_reg_5775),
+    .ce(1'b1),
+    .dout(grp_fu_3991_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U54(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_26_load_reg_5875),
+    .din1(in1_loc_26_load_reg_5780),
+    .ce(1'b1),
+    .dout(grp_fu_3995_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U55(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_33_load_reg_5880),
+    .din1(in1_loc_33_load_reg_5785),
+    .ce(1'b1),
+    .dout(grp_fu_3999_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U56(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_34_load_reg_5885),
+    .din1(in1_loc_34_load_reg_5790),
+    .ce(1'b1),
+    .dout(grp_fu_4003_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U57(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_41_load_reg_5890),
+    .din1(in1_loc_41_load_reg_5795),
+    .ce(1'b1),
+    .dout(grp_fu_4007_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U58(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_42_load_reg_5895),
+    .din1(in1_loc_42_load_reg_5800),
+    .ce(1'b1),
+    .dout(grp_fu_4011_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U59(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_45_load_reg_5900),
+    .din1(in1_loc_45_load_reg_5805),
+    .ce(1'b1),
+    .dout(grp_fu_4015_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U60(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_46_load_reg_5905),
+    .din1(in1_loc_46_load_reg_5810),
+    .ce(1'b1),
+    .dout(grp_fu_4019_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U61(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_49_load_reg_5910),
+    .din1(in1_loc_49_load_reg_5815),
+    .ce(1'b1),
+    .dout(grp_fu_4023_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U62(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_50_load_reg_5915),
+    .din1(in1_loc_50_load_reg_5820),
+    .ce(1'b1),
+    .dout(grp_fu_4027_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U63(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_57_load_reg_5920),
+    .din1(in1_loc_57_load_reg_5825),
+    .ce(1'b1),
+    .dout(grp_fu_4031_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U64(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_58_load_reg_5925),
+    .din1(in1_loc_58_load_reg_5830),
+    .ce(1'b1),
+    .dout(grp_fu_4035_p2)
+);
+
+mmult_mul_32s_32scud #(
+    .ID( 1 ),
+    .NUM_STAGE( 3 ),
+    .din0_WIDTH( 32 ),
+    .din1_WIDTH( 32 ),
+    .dout_WIDTH( 32 ))
+mmult_mul_32s_32scud_U65(
+    .clk(ap_clk),
+    .reset(ap_rst_n_inv),
+    .din0(in2_loc_61_load_reg_5930),
+    .din1(in1_loc_61_load_reg_5835),
+    .ce(1'b1),
+    .dout(grp_fu_4039_p2)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_condition_pp0_exit_iter0_state9) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_enable_reg_pp0_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp0_exit_iter0_state9)) begin
+                ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state9);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp0_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
+            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state8)) begin
+            ap_enable_reg_pp0_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp1_stage0) & (1'b1 == ap_condition_pp1_exit_iter0_state19) & (1'b0 == ap_block_pp1_stage0_subdone))) begin
+            ap_enable_reg_pp1_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp1_exit_iter0_state19)) begin
+                ap_enable_reg_pp1_iter1 <= (1'b1 ^ ap_condition_pp1_exit_iter0_state19);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp1_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
+            ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+        end else if ((1'b1 == ap_CS_fsm_state18)) begin
+            ap_enable_reg_pp1_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp2_stage0) & (1'b1 == ap_condition_pp2_exit_iter0_state25) & (1'b0 == ap_block_pp2_stage0_subdone))) begin
+            ap_enable_reg_pp2_iter0 <= 1'b0;
+        end else if ((1'b1 == ap_CS_fsm_state24)) begin
+            ap_enable_reg_pp2_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp2_exit_iter0_state25)) begin
+                ap_enable_reg_pp2_iter1 <= (1'b1 ^ ap_condition_pp2_exit_iter0_state25);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter3 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter3 <= ap_enable_reg_pp2_iter2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter4 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter4 <= ap_enable_reg_pp2_iter3;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter5 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter5 <= ap_enable_reg_pp2_iter4;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter6 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter6 <= ap_enable_reg_pp2_iter5;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter7 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter7 <= ap_enable_reg_pp2_iter6;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp2_iter8 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
+            ap_enable_reg_pp2_iter8 <= ap_enable_reg_pp2_iter7;
+        end else if ((1'b1 == ap_CS_fsm_state24)) begin
+            ap_enable_reg_pp2_iter8 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter0 <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_pp3_stage0) & (1'b1 == ap_condition_pp3_exit_iter0_state35) & (1'b0 == ap_block_pp3_stage0_subdone))) begin
+            ap_enable_reg_pp3_iter0 <= 1'b0;
+        end else if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+            ap_enable_reg_pp3_iter0 <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter1 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp3_stage0_subdone)) begin
+            if ((1'b1 == ap_condition_pp3_exit_iter0_state35)) begin
+                ap_enable_reg_pp3_iter1 <= (1'b1 ^ ap_condition_pp3_exit_iter0_state35);
+            end else if ((1'b1 == 1'b1)) begin
+                ap_enable_reg_pp3_iter1 <= ap_enable_reg_pp3_iter0;
+            end
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst_n_inv == 1'b1) begin
+        ap_enable_reg_pp3_iter2 <= 1'b0;
+    end else begin
+        if ((1'b0 == ap_block_pp3_stage0_subdone)) begin
+            ap_enable_reg_pp3_iter2 <= ap_enable_reg_pp3_iter1;
+        end else if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+            ap_enable_reg_pp3_iter2 <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578 == 1'd0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        i_0_reg_3329 <= select_ln31_1_reg_4592;
+    end else if ((1'b1 == ap_CS_fsm_state24)) begin
+        i_0_reg_3329 <= 31'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3620_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        indvar_flatten_reg_3318 <= add_ln31_fu_3625_p2;
+    end else if ((1'b1 == ap_CS_fsm_state24)) begin
+        indvar_flatten_reg_3318 <= 64'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3620_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        j_0_reg_3340 <= j_fu_3685_p2;
+    end else if ((1'b1 == ap_CS_fsm_state24)) begin
+        j_0_reg_3340 <= 32'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_fu_3425_p2 == 1'd0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        phi_ln27_reg_3296 <= add_ln27_fu_3431_p2;
+    end else if ((1'b1 == ap_CS_fsm_state8)) begin
+        phi_ln27_reg_3296 <= 13'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state18)) begin
+        phi_ln28_reg_3307 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_fu_3518_p2 == 1'd0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        phi_ln28_reg_3307 <= add_ln28_fu_3524_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+        phi_ln42_reg_3351 <= 13'd0;
+    end else if (((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_fu_4339_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp3_stage0) & (ap_enable_reg_pp3_iter0 == 1'b1))) begin
+        phi_ln42_reg_3351 <= add_ln42_fu_4345_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578_pp2_iter5_reg == 1'd0))) begin
+        add_ln38_10_reg_6275 <= add_ln38_10_fu_4070_p2;
+        add_ln38_15_reg_6280 <= add_ln38_15_fu_4074_p2;
+        add_ln38_18_reg_6285 <= add_ln38_18_fu_4078_p2;
+        add_ln38_19_reg_6290 <= add_ln38_19_fu_4082_p2;
+        add_ln38_22_reg_6295 <= add_ln38_22_fu_4086_p2;
+        add_ln38_25_reg_6300 <= add_ln38_25_fu_4090_p2;
+        add_ln38_26_reg_6305 <= add_ln38_26_fu_4094_p2;
+        add_ln38_2_reg_6255 <= add_ln38_2_fu_4052_p2;
+        add_ln38_31_reg_6310 <= add_ln38_31_fu_4098_p2;
+        add_ln38_34_reg_6315 <= add_ln38_34_fu_4102_p2;
+        add_ln38_35_reg_6320 <= add_ln38_35_fu_4106_p2;
+        add_ln38_38_reg_6325 <= add_ln38_38_fu_4110_p2;
+        add_ln38_3_reg_6260 <= add_ln38_3_fu_4058_p2;
+        add_ln38_41_reg_6330 <= add_ln38_41_fu_4114_p2;
+        add_ln38_46_reg_6335 <= add_ln38_46_fu_4118_p2;
+        add_ln38_49_reg_6340 <= add_ln38_49_fu_4122_p2;
+        add_ln38_4_reg_6265 <= add_ln38_4_fu_4062_p2;
+        add_ln38_50_reg_6345 <= add_ln38_50_fu_4126_p2;
+        add_ln38_53_reg_6350 <= add_ln38_53_fu_4130_p2;
+        add_ln38_56_reg_6355 <= add_ln38_56_fu_4134_p2;
+        add_ln38_57_reg_6360 <= add_ln38_57_fu_4138_p2;
+        add_ln38_7_reg_6270 <= add_ln38_7_fu_4066_p2;
+        mul_ln38_10_reg_6165 <= grp_fu_3971_p2;
+        mul_ln38_13_reg_6170 <= grp_fu_3975_p2;
+        mul_ln38_14_reg_6175 <= grp_fu_3979_p2;
+        mul_ln38_17_reg_6180 <= grp_fu_3983_p2;
+        mul_ln38_18_reg_6185 <= grp_fu_3987_p2;
+        mul_ln38_25_reg_6190 <= grp_fu_3991_p2;
+        mul_ln38_26_reg_6195 <= grp_fu_3995_p2;
+        mul_ln38_33_reg_6200 <= grp_fu_3999_p2;
+        mul_ln38_34_reg_6205 <= grp_fu_4003_p2;
+        mul_ln38_41_reg_6210 <= grp_fu_4007_p2;
+        mul_ln38_42_reg_6215 <= grp_fu_4011_p2;
+        mul_ln38_45_reg_6220 <= grp_fu_4015_p2;
+        mul_ln38_46_reg_6225 <= grp_fu_4019_p2;
+        mul_ln38_49_reg_6230 <= grp_fu_4023_p2;
+        mul_ln38_50_reg_6235 <= grp_fu_4027_p2;
+        mul_ln38_57_reg_6240 <= grp_fu_4031_p2;
+        mul_ln38_58_reg_6245 <= grp_fu_4035_p2;
+        mul_ln38_61_reg_6250 <= grp_fu_4039_p2;
+        mul_ln38_9_reg_6160 <= grp_fu_3967_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578_pp2_iter6_reg == 1'd0))) begin
+        add_ln38_30_reg_6365 <= add_ln38_30_fu_4225_p2;
+        add_ln38_45_reg_6370 <= add_ln38_45_fu_4274_p2;
+        add_ln38_61_reg_6375 <= add_ln38_61_fu_4323_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        dim_read_reg_4356 <= dim;
+        in3_reg_4372 <= {{in1[31:2]}};
+        in_reg_4367 <= {{in2[31:2]}};
+        out5_reg_4362 <= {{out_r[31:2]}};
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        icmp_ln31_reg_4578 <= icmp_ln31_fu_3620_p2;
+        icmp_ln31_reg_4578_pp2_iter1_reg <= icmp_ln31_reg_4578;
+        out_loc_addr_reg_4598_pp2_iter1_reg <= out_loc_addr_reg_4598;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b0 == ap_block_pp2_stage0_11001)) begin
+        icmp_ln31_reg_4578_pp2_iter2_reg <= icmp_ln31_reg_4578_pp2_iter1_reg;
+        icmp_ln31_reg_4578_pp2_iter3_reg <= icmp_ln31_reg_4578_pp2_iter2_reg;
+        icmp_ln31_reg_4578_pp2_iter4_reg <= icmp_ln31_reg_4578_pp2_iter3_reg;
+        icmp_ln31_reg_4578_pp2_iter5_reg <= icmp_ln31_reg_4578_pp2_iter4_reg;
+        icmp_ln31_reg_4578_pp2_iter6_reg <= icmp_ln31_reg_4578_pp2_iter5_reg;
+        icmp_ln31_reg_4578_pp2_iter7_reg <= icmp_ln31_reg_4578_pp2_iter6_reg;
+        out_loc_addr_reg_4598_pp2_iter2_reg <= out_loc_addr_reg_4598_pp2_iter1_reg;
+        out_loc_addr_reg_4598_pp2_iter3_reg <= out_loc_addr_reg_4598_pp2_iter2_reg;
+        out_loc_addr_reg_4598_pp2_iter4_reg <= out_loc_addr_reg_4598_pp2_iter3_reg;
+        out_loc_addr_reg_4598_pp2_iter5_reg <= out_loc_addr_reg_4598_pp2_iter4_reg;
+        out_loc_addr_reg_4598_pp2_iter6_reg <= out_loc_addr_reg_4598_pp2_iter5_reg;
+        out_loc_addr_reg_4598_pp2_iter7_reg <= out_loc_addr_reg_4598_pp2_iter6_reg;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp3_stage0_11001) & (1'b1 == ap_CS_fsm_pp3_stage0))) begin
+        icmp_ln42_reg_6380 <= icmp_ln42_fu_4339_p2;
+        icmp_ln42_reg_6380_pp3_iter1_reg <= icmp_ln42_reg_6380;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578_pp2_iter1_reg == 1'd0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_0_load_reg_5105 <= in1_loc_0_q0;
+        in1_loc_11_load_reg_5160 <= in1_loc_11_q0;
+        in1_loc_12_load_reg_5165 <= in1_loc_12_q0;
+        in1_loc_15_load_reg_5180 <= in1_loc_15_q0;
+        in1_loc_16_load_reg_5185 <= in1_loc_16_q0;
+        in1_loc_19_load_reg_5200 <= in1_loc_19_q0;
+        in1_loc_1_load_reg_5110 <= in1_loc_1_q0;
+        in1_loc_20_load_reg_5205 <= in1_loc_20_q0;
+        in1_loc_21_load_reg_5210 <= in1_loc_21_q0;
+        in1_loc_22_load_reg_5215 <= in1_loc_22_q0;
+        in1_loc_23_load_reg_5220 <= in1_loc_23_q0;
+        in1_loc_24_load_reg_5225 <= in1_loc_24_q0;
+        in1_loc_27_load_reg_5240 <= in1_loc_27_q0;
+        in1_loc_28_load_reg_5245 <= in1_loc_28_q0;
+        in1_loc_29_load_reg_5250 <= in1_loc_29_q0;
+        in1_loc_2_load_reg_5115 <= in1_loc_2_q0;
+        in1_loc_30_load_reg_5255 <= in1_loc_30_q0;
+        in1_loc_31_load_reg_5260 <= in1_loc_31_q0;
+        in1_loc_32_load_reg_5265 <= in1_loc_32_q0;
+        in1_loc_35_load_reg_5280 <= in1_loc_35_q0;
+        in1_loc_36_load_reg_5285 <= in1_loc_36_q0;
+        in1_loc_37_load_reg_5290 <= in1_loc_37_q0;
+        in1_loc_38_load_reg_5295 <= in1_loc_38_q0;
+        in1_loc_39_load_reg_5300 <= in1_loc_39_q0;
+        in1_loc_3_load_reg_5120 <= in1_loc_3_q0;
+        in1_loc_40_load_reg_5305 <= in1_loc_40_q0;
+        in1_loc_43_load_reg_5320 <= in1_loc_43_q0;
+        in1_loc_44_load_reg_5325 <= in1_loc_44_q0;
+        in1_loc_47_load_reg_5340 <= in1_loc_47_q0;
+        in1_loc_48_load_reg_5345 <= in1_loc_48_q0;
+        in1_loc_4_load_reg_5125 <= in1_loc_4_q0;
+        in1_loc_51_load_reg_5360 <= in1_loc_51_q0;
+        in1_loc_52_load_reg_5365 <= in1_loc_52_q0;
+        in1_loc_53_load_reg_5370 <= in1_loc_53_q0;
+        in1_loc_54_load_reg_5375 <= in1_loc_54_q0;
+        in1_loc_55_load_reg_5380 <= in1_loc_55_q0;
+        in1_loc_56_load_reg_5385 <= in1_loc_56_q0;
+        in1_loc_59_load_reg_5400 <= in1_loc_59_q0;
+        in1_loc_5_load_reg_5130 <= in1_loc_5_q0;
+        in1_loc_60_load_reg_5405 <= in1_loc_60_q0;
+        in1_loc_62_load_reg_5415 <= in1_loc_62_q0;
+        in1_loc_63_load_reg_5420 <= in1_loc_63_q0;
+        in1_loc_6_load_reg_5135 <= in1_loc_6_q0;
+        in1_loc_7_load_reg_5140 <= in1_loc_7_q0;
+        in1_loc_8_load_reg_5145 <= in1_loc_8_q0;
+        in2_loc_0_load_reg_5425 <= in2_loc_0_q0;
+        in2_loc_11_load_reg_5480 <= in2_loc_11_q0;
+        in2_loc_12_load_reg_5485 <= in2_loc_12_q0;
+        in2_loc_15_load_reg_5500 <= in2_loc_15_q0;
+        in2_loc_16_load_reg_5505 <= in2_loc_16_q0;
+        in2_loc_19_load_reg_5520 <= in2_loc_19_q0;
+        in2_loc_1_load_reg_5430 <= in2_loc_1_q0;
+        in2_loc_20_load_reg_5525 <= in2_loc_20_q0;
+        in2_loc_21_load_reg_5530 <= in2_loc_21_q0;
+        in2_loc_22_load_reg_5535 <= in2_loc_22_q0;
+        in2_loc_23_load_reg_5540 <= in2_loc_23_q0;
+        in2_loc_24_load_reg_5545 <= in2_loc_24_q0;
+        in2_loc_27_load_reg_5560 <= in2_loc_27_q0;
+        in2_loc_28_load_reg_5565 <= in2_loc_28_q0;
+        in2_loc_29_load_reg_5570 <= in2_loc_29_q0;
+        in2_loc_2_load_reg_5435 <= in2_loc_2_q0;
+        in2_loc_30_load_reg_5575 <= in2_loc_30_q0;
+        in2_loc_31_load_reg_5580 <= in2_loc_31_q0;
+        in2_loc_32_load_reg_5585 <= in2_loc_32_q0;
+        in2_loc_35_load_reg_5600 <= in2_loc_35_q0;
+        in2_loc_36_load_reg_5605 <= in2_loc_36_q0;
+        in2_loc_37_load_reg_5610 <= in2_loc_37_q0;
+        in2_loc_38_load_reg_5615 <= in2_loc_38_q0;
+        in2_loc_39_load_reg_5620 <= in2_loc_39_q0;
+        in2_loc_3_load_reg_5440 <= in2_loc_3_q0;
+        in2_loc_40_load_reg_5625 <= in2_loc_40_q0;
+        in2_loc_43_load_reg_5640 <= in2_loc_43_q0;
+        in2_loc_44_load_reg_5645 <= in2_loc_44_q0;
+        in2_loc_47_load_reg_5660 <= in2_loc_47_q0;
+        in2_loc_48_load_reg_5665 <= in2_loc_48_q0;
+        in2_loc_4_load_reg_5445 <= in2_loc_4_q0;
+        in2_loc_51_load_reg_5680 <= in2_loc_51_q0;
+        in2_loc_52_load_reg_5685 <= in2_loc_52_q0;
+        in2_loc_53_load_reg_5690 <= in2_loc_53_q0;
+        in2_loc_54_load_reg_5695 <= in2_loc_54_q0;
+        in2_loc_55_load_reg_5700 <= in2_loc_55_q0;
+        in2_loc_56_load_reg_5705 <= in2_loc_56_q0;
+        in2_loc_59_load_reg_5720 <= in2_loc_59_q0;
+        in2_loc_5_load_reg_5450 <= in2_loc_5_q0;
+        in2_loc_60_load_reg_5725 <= in2_loc_60_q0;
+        in2_loc_62_load_reg_5735 <= in2_loc_62_q0;
+        in2_loc_63_load_reg_5740 <= in2_loc_63_q0;
+        in2_loc_6_load_reg_5455 <= in2_loc_6_q0;
+        in2_loc_7_load_reg_5460 <= in2_loc_7_q0;
+        in2_loc_8_load_reg_5465 <= in2_loc_8_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578_pp2_iter2_reg == 1'd0) & (ap_enable_reg_pp2_iter3 == 1'b1))) begin
+        in1_loc_10_load_reg_5750 <= in1_loc_10_q0;
+        in1_loc_13_load_reg_5755 <= in1_loc_13_q0;
+        in1_loc_14_load_reg_5760 <= in1_loc_14_q0;
+        in1_loc_17_load_reg_5765 <= in1_loc_17_q0;
+        in1_loc_18_load_reg_5770 <= in1_loc_18_q0;
+        in1_loc_25_load_reg_5775 <= in1_loc_25_q0;
+        in1_loc_26_load_reg_5780 <= in1_loc_26_q0;
+        in1_loc_33_load_reg_5785 <= in1_loc_33_q0;
+        in1_loc_34_load_reg_5790 <= in1_loc_34_q0;
+        in1_loc_41_load_reg_5795 <= in1_loc_41_q0;
+        in1_loc_42_load_reg_5800 <= in1_loc_42_q0;
+        in1_loc_45_load_reg_5805 <= in1_loc_45_q0;
+        in1_loc_46_load_reg_5810 <= in1_loc_46_q0;
+        in1_loc_49_load_reg_5815 <= in1_loc_49_q0;
+        in1_loc_50_load_reg_5820 <= in1_loc_50_q0;
+        in1_loc_57_load_reg_5825 <= in1_loc_57_q0;
+        in1_loc_58_load_reg_5830 <= in1_loc_58_q0;
+        in1_loc_61_load_reg_5835 <= in1_loc_61_q0;
+        in1_loc_9_load_reg_5745 <= in1_loc_9_q0;
+        in2_loc_10_load_reg_5845 <= in2_loc_10_q0;
+        in2_loc_13_load_reg_5850 <= in2_loc_13_q0;
+        in2_loc_14_load_reg_5855 <= in2_loc_14_q0;
+        in2_loc_17_load_reg_5860 <= in2_loc_17_q0;
+        in2_loc_18_load_reg_5865 <= in2_loc_18_q0;
+        in2_loc_25_load_reg_5870 <= in2_loc_25_q0;
+        in2_loc_26_load_reg_5875 <= in2_loc_26_q0;
+        in2_loc_33_load_reg_5880 <= in2_loc_33_q0;
+        in2_loc_34_load_reg_5885 <= in2_loc_34_q0;
+        in2_loc_41_load_reg_5890 <= in2_loc_41_q0;
+        in2_loc_42_load_reg_5895 <= in2_loc_42_q0;
+        in2_loc_45_load_reg_5900 <= in2_loc_45_q0;
+        in2_loc_46_load_reg_5905 <= in2_loc_46_q0;
+        in2_loc_49_load_reg_5910 <= in2_loc_49_q0;
+        in2_loc_50_load_reg_5915 <= in2_loc_50_q0;
+        in2_loc_57_load_reg_5920 <= in2_loc_57_q0;
+        in2_loc_58_load_reg_5925 <= in2_loc_58_q0;
+        in2_loc_61_load_reg_5930 <= in2_loc_61_q0;
+        in2_loc_9_load_reg_5840 <= in2_loc_9_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_addr_read_reg_4413 <= in1_mem_RDATA;
+        lshr_ln_reg_4404_pp0_iter1_reg <= lshr_ln_reg_4404;
+        trunc_ln27_reg_4409_pp0_iter1_reg <= trunc_ln27_reg_4409;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_addr_read_reg_4499 <= in2_mem_RDATA;
+        trunc_ln1_reg_4495_pp1_iter1_reg <= trunc_ln1_reg_4495;
+        trunc_ln28_reg_4490_pp1_iter1_reg <= trunc_ln28_reg_4490;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        in2_mem_addr_reg_4389[29 : 0] <= empty_7_fu_3416_p1[29 : 0];
+        out_mem_addr_reg_4383[29 : 0] <= empty_fu_3407_p1[29 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (icmp_ln27_fu_3425_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        lshr_ln_reg_4404 <= {{phi_ln27_reg_3296[12:6]}};
+        trunc_ln27_reg_4409 <= trunc_ln27_fu_3447_p1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state24)) begin
+        mul_ln31_reg_4573 <= grp_fu_3614_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578_pp2_iter4_reg == 1'd0))) begin
+        mul_ln38_11_reg_5980 <= grp_fu_3823_p2;
+        mul_ln38_12_reg_5985 <= grp_fu_3827_p2;
+        mul_ln38_15_reg_5990 <= grp_fu_3831_p2;
+        mul_ln38_16_reg_5995 <= grp_fu_3835_p2;
+        mul_ln38_19_reg_6000 <= grp_fu_3839_p2;
+        mul_ln38_1_reg_5940 <= grp_fu_3791_p2;
+        mul_ln38_20_reg_6005 <= grp_fu_3843_p2;
+        mul_ln38_21_reg_6010 <= grp_fu_3847_p2;
+        mul_ln38_22_reg_6015 <= grp_fu_3851_p2;
+        mul_ln38_23_reg_6020 <= grp_fu_3855_p2;
+        mul_ln38_24_reg_6025 <= grp_fu_3859_p2;
+        mul_ln38_27_reg_6030 <= grp_fu_3863_p2;
+        mul_ln38_28_reg_6035 <= grp_fu_3867_p2;
+        mul_ln38_29_reg_6040 <= grp_fu_3871_p2;
+        mul_ln38_2_reg_5945 <= grp_fu_3795_p2;
+        mul_ln38_30_reg_6045 <= grp_fu_3875_p2;
+        mul_ln38_31_reg_6050 <= grp_fu_3879_p2;
+        mul_ln38_32_reg_6055 <= grp_fu_3883_p2;
+        mul_ln38_35_reg_6060 <= grp_fu_3887_p2;
+        mul_ln38_36_reg_6065 <= grp_fu_3891_p2;
+        mul_ln38_37_reg_6070 <= grp_fu_3895_p2;
+        mul_ln38_38_reg_6075 <= grp_fu_3899_p2;
+        mul_ln38_39_reg_6080 <= grp_fu_3903_p2;
+        mul_ln38_3_reg_5950 <= grp_fu_3799_p2;
+        mul_ln38_40_reg_6085 <= grp_fu_3907_p2;
+        mul_ln38_43_reg_6090 <= grp_fu_3911_p2;
+        mul_ln38_44_reg_6095 <= grp_fu_3915_p2;
+        mul_ln38_47_reg_6100 <= grp_fu_3919_p2;
+        mul_ln38_48_reg_6105 <= grp_fu_3923_p2;
+        mul_ln38_4_reg_5955 <= grp_fu_3803_p2;
+        mul_ln38_51_reg_6110 <= grp_fu_3927_p2;
+        mul_ln38_52_reg_6115 <= grp_fu_3931_p2;
+        mul_ln38_53_reg_6120 <= grp_fu_3935_p2;
+        mul_ln38_54_reg_6125 <= grp_fu_3939_p2;
+        mul_ln38_55_reg_6130 <= grp_fu_3943_p2;
+        mul_ln38_56_reg_6135 <= grp_fu_3947_p2;
+        mul_ln38_59_reg_6140 <= grp_fu_3951_p2;
+        mul_ln38_5_reg_5960 <= grp_fu_3807_p2;
+        mul_ln38_60_reg_6145 <= grp_fu_3955_p2;
+        mul_ln38_62_reg_6150 <= grp_fu_3959_p2;
+        mul_ln38_63_reg_6155 <= grp_fu_3963_p2;
+        mul_ln38_6_reg_5965 <= grp_fu_3811_p2;
+        mul_ln38_7_reg_5970 <= grp_fu_3815_p2;
+        mul_ln38_8_reg_5975 <= grp_fu_3819_p2;
+        mul_ln38_reg_5935 <= grp_fu_3787_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3620_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        out_loc_addr_reg_4598 <= zext_ln38_fu_3680_p1;
+        select_ln31_reg_4587 <= select_ln31_fu_3642_p3;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_reg_6380 == 1'd0) & (ap_enable_reg_pp3_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp3_stage0)) | ((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578_pp2_iter4_reg == 1'd0) & (ap_enable_reg_pp2_iter5 == 1'b1)))) begin
+        reg_3362 <= out_loc_q0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_fu_3620_p2 == 1'd0) & (ap_enable_reg_pp2_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        select_ln31_1_reg_4592 <= select_ln31_1_fu_3650_p3;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578 == 1'd0) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
+        sext_ln38_reg_4857 <= sext_ln38_fu_3739_p1;
+        zext_ln31_1_reg_4609[30 : 0] <= zext_ln31_1_fu_3691_p1[30 : 0];
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (icmp_ln28_fu_3518_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        trunc_ln1_reg_4495 <= {{phi_ln28_reg_3307[11:6]}};
+        trunc_ln28_reg_4490 <= trunc_ln28_fu_3530_p1;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln27_fu_3425_p2 == 1'd1)) begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b1;
+    end else begin
+        ap_condition_pp0_exit_iter0_state9 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln28_fu_3518_p2 == 1'd1)) begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b1;
+    end else begin
+        ap_condition_pp1_exit_iter0_state19 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln31_fu_3620_p2 == 1'd1)) begin
+        ap_condition_pp2_exit_iter0_state25 = 1'b1;
+    end else begin
+        ap_condition_pp2_exit_iter0_state25 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((icmp_ln42_fu_4339_p2 == 1'd1)) begin
+        ap_condition_pp3_exit_iter0_state35 = 1'b1;
+    end else begin
+        ap_condition_pp3_exit_iter0_state35 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state42))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b0))) begin
+        ap_idle_pp1 = 1'b1;
+    end else begin
+        ap_idle_pp1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp2_iter2 == 1'b0) & (ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter5 == 1'b0) & (ap_enable_reg_pp2_iter8 == 1'b0) & (ap_enable_reg_pp2_iter7 == 1'b0) & (ap_enable_reg_pp2_iter6 == 1'b0) & (ap_enable_reg_pp2_iter4 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b0) & (ap_enable_reg_pp2_iter3 == 1'b0))) begin
+        ap_idle_pp2 = 1'b1;
+    end else begin
+        ap_idle_pp2 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b0) & (ap_enable_reg_pp3_iter0 == 1'b0))) begin
+        ap_idle_pp3 = 1'b1;
+    end else begin
+        ap_idle_pp3 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (icmp_ln31_reg_4578 == 1'd0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        ap_phi_mux_i_0_phi_fu_3333_p4 = select_ln31_1_reg_4592;
+    end else begin
+        ap_phi_mux_i_0_phi_fu_3333_p4 = i_0_reg_3329;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state42))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_0_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_0_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_0_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_0_ce0 = 1'b1;
+    end else begin
+        in1_loc_0_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd0) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_0_we0 = 1'b1;
+    end else begin
+        in1_loc_0_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_10_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_10_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_10_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_10_ce0 = 1'b1;
+    end else begin
+        in1_loc_10_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd10) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_10_we0 = 1'b1;
+    end else begin
+        in1_loc_10_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_11_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_11_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_11_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_11_ce0 = 1'b1;
+    end else begin
+        in1_loc_11_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd11) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_11_we0 = 1'b1;
+    end else begin
+        in1_loc_11_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_12_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_12_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_12_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_12_ce0 = 1'b1;
+    end else begin
+        in1_loc_12_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd12) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_12_we0 = 1'b1;
+    end else begin
+        in1_loc_12_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_13_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_13_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_13_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_13_ce0 = 1'b1;
+    end else begin
+        in1_loc_13_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd13) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_13_we0 = 1'b1;
+    end else begin
+        in1_loc_13_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_14_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_14_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_14_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_14_ce0 = 1'b1;
+    end else begin
+        in1_loc_14_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd14) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_14_we0 = 1'b1;
+    end else begin
+        in1_loc_14_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_15_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_15_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_15_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_15_ce0 = 1'b1;
+    end else begin
+        in1_loc_15_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd15) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_15_we0 = 1'b1;
+    end else begin
+        in1_loc_15_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_16_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_16_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_16_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_16_ce0 = 1'b1;
+    end else begin
+        in1_loc_16_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd16) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_16_we0 = 1'b1;
+    end else begin
+        in1_loc_16_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_17_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_17_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_17_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_17_ce0 = 1'b1;
+    end else begin
+        in1_loc_17_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd17) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_17_we0 = 1'b1;
+    end else begin
+        in1_loc_17_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_18_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_18_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_18_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_18_ce0 = 1'b1;
+    end else begin
+        in1_loc_18_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd18) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_18_we0 = 1'b1;
+    end else begin
+        in1_loc_18_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_19_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_19_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_19_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_19_ce0 = 1'b1;
+    end else begin
+        in1_loc_19_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd19) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_19_we0 = 1'b1;
+    end else begin
+        in1_loc_19_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_1_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_1_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_1_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_1_ce0 = 1'b1;
+    end else begin
+        in1_loc_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd1) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_1_we0 = 1'b1;
+    end else begin
+        in1_loc_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_20_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_20_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_20_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_20_ce0 = 1'b1;
+    end else begin
+        in1_loc_20_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd20) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_20_we0 = 1'b1;
+    end else begin
+        in1_loc_20_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_21_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_21_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_21_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_21_ce0 = 1'b1;
+    end else begin
+        in1_loc_21_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd21) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_21_we0 = 1'b1;
+    end else begin
+        in1_loc_21_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_22_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_22_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_22_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_22_ce0 = 1'b1;
+    end else begin
+        in1_loc_22_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd22) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_22_we0 = 1'b1;
+    end else begin
+        in1_loc_22_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_23_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_23_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_23_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_23_ce0 = 1'b1;
+    end else begin
+        in1_loc_23_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd23) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_23_we0 = 1'b1;
+    end else begin
+        in1_loc_23_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_24_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_24_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_24_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_24_ce0 = 1'b1;
+    end else begin
+        in1_loc_24_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd24) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_24_we0 = 1'b1;
+    end else begin
+        in1_loc_24_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_25_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_25_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_25_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_25_ce0 = 1'b1;
+    end else begin
+        in1_loc_25_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd25) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_25_we0 = 1'b1;
+    end else begin
+        in1_loc_25_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_26_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_26_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_26_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_26_ce0 = 1'b1;
+    end else begin
+        in1_loc_26_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd26) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_26_we0 = 1'b1;
+    end else begin
+        in1_loc_26_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_27_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_27_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_27_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_27_ce0 = 1'b1;
+    end else begin
+        in1_loc_27_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd27) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_27_we0 = 1'b1;
+    end else begin
+        in1_loc_27_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_28_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_28_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_28_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_28_ce0 = 1'b1;
+    end else begin
+        in1_loc_28_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd28) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_28_we0 = 1'b1;
+    end else begin
+        in1_loc_28_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_29_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_29_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_29_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_29_ce0 = 1'b1;
+    end else begin
+        in1_loc_29_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd29) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_29_we0 = 1'b1;
+    end else begin
+        in1_loc_29_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_2_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_2_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_2_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_2_ce0 = 1'b1;
+    end else begin
+        in1_loc_2_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd2) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_2_we0 = 1'b1;
+    end else begin
+        in1_loc_2_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_30_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_30_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_30_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_30_ce0 = 1'b1;
+    end else begin
+        in1_loc_30_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd30) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_30_we0 = 1'b1;
+    end else begin
+        in1_loc_30_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_31_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_31_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_31_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_31_ce0 = 1'b1;
+    end else begin
+        in1_loc_31_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd31) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_31_we0 = 1'b1;
+    end else begin
+        in1_loc_31_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_32_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_32_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_32_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_32_ce0 = 1'b1;
+    end else begin
+        in1_loc_32_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd32) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_32_we0 = 1'b1;
+    end else begin
+        in1_loc_32_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_33_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_33_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_33_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_33_ce0 = 1'b1;
+    end else begin
+        in1_loc_33_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd33) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_33_we0 = 1'b1;
+    end else begin
+        in1_loc_33_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_34_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_34_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_34_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_34_ce0 = 1'b1;
+    end else begin
+        in1_loc_34_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd34) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_34_we0 = 1'b1;
+    end else begin
+        in1_loc_34_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_35_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_35_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_35_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_35_ce0 = 1'b1;
+    end else begin
+        in1_loc_35_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd35) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_35_we0 = 1'b1;
+    end else begin
+        in1_loc_35_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_36_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_36_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_36_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_36_ce0 = 1'b1;
+    end else begin
+        in1_loc_36_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd36) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_36_we0 = 1'b1;
+    end else begin
+        in1_loc_36_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_37_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_37_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_37_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_37_ce0 = 1'b1;
+    end else begin
+        in1_loc_37_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd37) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_37_we0 = 1'b1;
+    end else begin
+        in1_loc_37_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_38_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_38_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_38_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_38_ce0 = 1'b1;
+    end else begin
+        in1_loc_38_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd38) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_38_we0 = 1'b1;
+    end else begin
+        in1_loc_38_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_39_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_39_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_39_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_39_ce0 = 1'b1;
+    end else begin
+        in1_loc_39_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd39) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_39_we0 = 1'b1;
+    end else begin
+        in1_loc_39_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_3_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_3_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_3_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_3_ce0 = 1'b1;
+    end else begin
+        in1_loc_3_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd3) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_3_we0 = 1'b1;
+    end else begin
+        in1_loc_3_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_40_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_40_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_40_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_40_ce0 = 1'b1;
+    end else begin
+        in1_loc_40_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd40) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_40_we0 = 1'b1;
+    end else begin
+        in1_loc_40_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_41_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_41_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_41_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_41_ce0 = 1'b1;
+    end else begin
+        in1_loc_41_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd41) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_41_we0 = 1'b1;
+    end else begin
+        in1_loc_41_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_42_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_42_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_42_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_42_ce0 = 1'b1;
+    end else begin
+        in1_loc_42_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd42) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_42_we0 = 1'b1;
+    end else begin
+        in1_loc_42_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_43_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_43_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_43_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_43_ce0 = 1'b1;
+    end else begin
+        in1_loc_43_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd43) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_43_we0 = 1'b1;
+    end else begin
+        in1_loc_43_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_44_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_44_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_44_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_44_ce0 = 1'b1;
+    end else begin
+        in1_loc_44_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd44) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_44_we0 = 1'b1;
+    end else begin
+        in1_loc_44_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_45_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_45_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_45_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_45_ce0 = 1'b1;
+    end else begin
+        in1_loc_45_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd45) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_45_we0 = 1'b1;
+    end else begin
+        in1_loc_45_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_46_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_46_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_46_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_46_ce0 = 1'b1;
+    end else begin
+        in1_loc_46_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd46) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_46_we0 = 1'b1;
+    end else begin
+        in1_loc_46_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_47_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_47_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_47_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_47_ce0 = 1'b1;
+    end else begin
+        in1_loc_47_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd47) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_47_we0 = 1'b1;
+    end else begin
+        in1_loc_47_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_48_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_48_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_48_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_48_ce0 = 1'b1;
+    end else begin
+        in1_loc_48_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd48) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_48_we0 = 1'b1;
+    end else begin
+        in1_loc_48_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_49_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_49_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_49_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_49_ce0 = 1'b1;
+    end else begin
+        in1_loc_49_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd49) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_49_we0 = 1'b1;
+    end else begin
+        in1_loc_49_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_4_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_4_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_4_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_4_ce0 = 1'b1;
+    end else begin
+        in1_loc_4_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd4) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_4_we0 = 1'b1;
+    end else begin
+        in1_loc_4_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_50_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_50_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_50_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_50_ce0 = 1'b1;
+    end else begin
+        in1_loc_50_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd50) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_50_we0 = 1'b1;
+    end else begin
+        in1_loc_50_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_51_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_51_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_51_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_51_ce0 = 1'b1;
+    end else begin
+        in1_loc_51_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd51) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_51_we0 = 1'b1;
+    end else begin
+        in1_loc_51_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_52_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_52_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_52_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_52_ce0 = 1'b1;
+    end else begin
+        in1_loc_52_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd52) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_52_we0 = 1'b1;
+    end else begin
+        in1_loc_52_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_53_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_53_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_53_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_53_ce0 = 1'b1;
+    end else begin
+        in1_loc_53_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd53) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_53_we0 = 1'b1;
+    end else begin
+        in1_loc_53_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_54_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_54_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_54_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_54_ce0 = 1'b1;
+    end else begin
+        in1_loc_54_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd54) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_54_we0 = 1'b1;
+    end else begin
+        in1_loc_54_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_55_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_55_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_55_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_55_ce0 = 1'b1;
+    end else begin
+        in1_loc_55_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd55) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_55_we0 = 1'b1;
+    end else begin
+        in1_loc_55_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_56_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_56_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_56_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_56_ce0 = 1'b1;
+    end else begin
+        in1_loc_56_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd56) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_56_we0 = 1'b1;
+    end else begin
+        in1_loc_56_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_57_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_57_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_57_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_57_ce0 = 1'b1;
+    end else begin
+        in1_loc_57_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd57) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_57_we0 = 1'b1;
+    end else begin
+        in1_loc_57_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_58_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_58_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_58_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_58_ce0 = 1'b1;
+    end else begin
+        in1_loc_58_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd58) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_58_we0 = 1'b1;
+    end else begin
+        in1_loc_58_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_59_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_59_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_59_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_59_ce0 = 1'b1;
+    end else begin
+        in1_loc_59_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd59) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_59_we0 = 1'b1;
+    end else begin
+        in1_loc_59_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_5_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_5_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_5_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_5_ce0 = 1'b1;
+    end else begin
+        in1_loc_5_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd5) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_5_we0 = 1'b1;
+    end else begin
+        in1_loc_5_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_60_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_60_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_60_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_60_ce0 = 1'b1;
+    end else begin
+        in1_loc_60_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd60) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_60_we0 = 1'b1;
+    end else begin
+        in1_loc_60_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_61_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_61_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_61_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_61_ce0 = 1'b1;
+    end else begin
+        in1_loc_61_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd61) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_61_we0 = 1'b1;
+    end else begin
+        in1_loc_61_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_62_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_62_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_62_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_62_ce0 = 1'b1;
+    end else begin
+        in1_loc_62_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd62) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_62_we0 = 1'b1;
+    end else begin
+        in1_loc_62_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_63_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_63_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_63_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_63_ce0 = 1'b1;
+    end else begin
+        in1_loc_63_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd63) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_63_we0 = 1'b1;
+    end else begin
+        in1_loc_63_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_6_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_6_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_6_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_6_ce0 = 1'b1;
+    end else begin
+        in1_loc_6_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd6) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_6_we0 = 1'b1;
+    end else begin
+        in1_loc_6_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_7_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_7_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_7_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_7_ce0 = 1'b1;
+    end else begin
+        in1_loc_7_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd7) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_7_we0 = 1'b1;
+    end else begin
+        in1_loc_7_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in1_loc_8_address0 = zext_ln31_1_fu_3691_p1;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_8_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_8_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in1_loc_8_ce0 = 1'b1;
+    end else begin
+        in1_loc_8_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd8) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_8_we0 = 1'b1;
+    end else begin
+        in1_loc_8_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in1_loc_9_address0 = zext_ln31_1_reg_4609;
+    end else if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_9_address0 = zext_ln27_fu_3451_p1;
+    end else begin
+        in1_loc_9_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in1_loc_9_ce0 = 1'b1;
+    end else begin
+        in1_loc_9_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln27_reg_4409_pp0_iter1_reg == 6'd9) & (1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
+        in1_loc_9_we0 = 1'b1;
+    end else begin
+        in1_loc_9_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        in1_mem_ARVALID = 1'b1;
+    end else begin
+        in1_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_RREADY = 1'b1;
+    end else begin
+        in1_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        in1_mem_blk_n_AR = m_axi_in1_mem_ARREADY;
+    end else begin
+        in1_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        in1_mem_blk_n_R = m_axi_in1_mem_RVALID;
+    end else begin
+        in1_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_0_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_0_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_0_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_0_ce0 = 1'b1;
+    end else begin
+        in2_loc_0_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd0) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_0_we0 = 1'b1;
+    end else begin
+        in2_loc_0_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_10_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_10_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_10_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_10_ce0 = 1'b1;
+    end else begin
+        in2_loc_10_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd10) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_10_we0 = 1'b1;
+    end else begin
+        in2_loc_10_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_11_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_11_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_11_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_11_ce0 = 1'b1;
+    end else begin
+        in2_loc_11_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd11) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_11_we0 = 1'b1;
+    end else begin
+        in2_loc_11_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_12_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_12_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_12_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_12_ce0 = 1'b1;
+    end else begin
+        in2_loc_12_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd12) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_12_we0 = 1'b1;
+    end else begin
+        in2_loc_12_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_13_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_13_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_13_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_13_ce0 = 1'b1;
+    end else begin
+        in2_loc_13_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd13) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_13_we0 = 1'b1;
+    end else begin
+        in2_loc_13_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_14_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_14_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_14_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_14_ce0 = 1'b1;
+    end else begin
+        in2_loc_14_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd14) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_14_we0 = 1'b1;
+    end else begin
+        in2_loc_14_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_15_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_15_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_15_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_15_ce0 = 1'b1;
+    end else begin
+        in2_loc_15_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd15) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_15_we0 = 1'b1;
+    end else begin
+        in2_loc_15_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_16_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_16_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_16_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_16_ce0 = 1'b1;
+    end else begin
+        in2_loc_16_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd16) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_16_we0 = 1'b1;
+    end else begin
+        in2_loc_16_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_17_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_17_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_17_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_17_ce0 = 1'b1;
+    end else begin
+        in2_loc_17_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd17) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_17_we0 = 1'b1;
+    end else begin
+        in2_loc_17_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_18_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_18_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_18_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_18_ce0 = 1'b1;
+    end else begin
+        in2_loc_18_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd18) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_18_we0 = 1'b1;
+    end else begin
+        in2_loc_18_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_19_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_19_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_19_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_19_ce0 = 1'b1;
+    end else begin
+        in2_loc_19_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd19) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_19_we0 = 1'b1;
+    end else begin
+        in2_loc_19_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_1_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_1_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_1_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_1_ce0 = 1'b1;
+    end else begin
+        in2_loc_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd1) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_1_we0 = 1'b1;
+    end else begin
+        in2_loc_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_20_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_20_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_20_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_20_ce0 = 1'b1;
+    end else begin
+        in2_loc_20_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd20) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_20_we0 = 1'b1;
+    end else begin
+        in2_loc_20_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_21_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_21_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_21_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_21_ce0 = 1'b1;
+    end else begin
+        in2_loc_21_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd21) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_21_we0 = 1'b1;
+    end else begin
+        in2_loc_21_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_22_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_22_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_22_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_22_ce0 = 1'b1;
+    end else begin
+        in2_loc_22_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd22) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_22_we0 = 1'b1;
+    end else begin
+        in2_loc_22_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_23_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_23_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_23_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_23_ce0 = 1'b1;
+    end else begin
+        in2_loc_23_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd23) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_23_we0 = 1'b1;
+    end else begin
+        in2_loc_23_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_24_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_24_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_24_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_24_ce0 = 1'b1;
+    end else begin
+        in2_loc_24_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd24) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_24_we0 = 1'b1;
+    end else begin
+        in2_loc_24_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_25_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_25_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_25_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_25_ce0 = 1'b1;
+    end else begin
+        in2_loc_25_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd25) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_25_we0 = 1'b1;
+    end else begin
+        in2_loc_25_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_26_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_26_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_26_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_26_ce0 = 1'b1;
+    end else begin
+        in2_loc_26_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd26) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_26_we0 = 1'b1;
+    end else begin
+        in2_loc_26_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_27_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_27_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_27_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_27_ce0 = 1'b1;
+    end else begin
+        in2_loc_27_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd27) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_27_we0 = 1'b1;
+    end else begin
+        in2_loc_27_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_28_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_28_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_28_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_28_ce0 = 1'b1;
+    end else begin
+        in2_loc_28_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd28) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_28_we0 = 1'b1;
+    end else begin
+        in2_loc_28_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_29_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_29_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_29_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_29_ce0 = 1'b1;
+    end else begin
+        in2_loc_29_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd29) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_29_we0 = 1'b1;
+    end else begin
+        in2_loc_29_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_2_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_2_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_2_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_2_ce0 = 1'b1;
+    end else begin
+        in2_loc_2_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd2) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_2_we0 = 1'b1;
+    end else begin
+        in2_loc_2_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_30_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_30_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_30_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_30_ce0 = 1'b1;
+    end else begin
+        in2_loc_30_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd30) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_30_we0 = 1'b1;
+    end else begin
+        in2_loc_30_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_31_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_31_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_31_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_31_ce0 = 1'b1;
+    end else begin
+        in2_loc_31_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd31) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_31_we0 = 1'b1;
+    end else begin
+        in2_loc_31_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_32_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_32_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_32_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_32_ce0 = 1'b1;
+    end else begin
+        in2_loc_32_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd32) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_32_we0 = 1'b1;
+    end else begin
+        in2_loc_32_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_33_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_33_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_33_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_33_ce0 = 1'b1;
+    end else begin
+        in2_loc_33_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd33) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_33_we0 = 1'b1;
+    end else begin
+        in2_loc_33_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_34_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_34_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_34_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_34_ce0 = 1'b1;
+    end else begin
+        in2_loc_34_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd34) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_34_we0 = 1'b1;
+    end else begin
+        in2_loc_34_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_35_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_35_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_35_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_35_ce0 = 1'b1;
+    end else begin
+        in2_loc_35_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd35) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_35_we0 = 1'b1;
+    end else begin
+        in2_loc_35_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_36_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_36_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_36_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_36_ce0 = 1'b1;
+    end else begin
+        in2_loc_36_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd36) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_36_we0 = 1'b1;
+    end else begin
+        in2_loc_36_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_37_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_37_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_37_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_37_ce0 = 1'b1;
+    end else begin
+        in2_loc_37_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd37) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_37_we0 = 1'b1;
+    end else begin
+        in2_loc_37_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_38_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_38_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_38_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_38_ce0 = 1'b1;
+    end else begin
+        in2_loc_38_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd38) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_38_we0 = 1'b1;
+    end else begin
+        in2_loc_38_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_39_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_39_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_39_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_39_ce0 = 1'b1;
+    end else begin
+        in2_loc_39_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd39) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_39_we0 = 1'b1;
+    end else begin
+        in2_loc_39_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_3_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_3_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_3_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_3_ce0 = 1'b1;
+    end else begin
+        in2_loc_3_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd3) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_3_we0 = 1'b1;
+    end else begin
+        in2_loc_3_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_40_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_40_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_40_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_40_ce0 = 1'b1;
+    end else begin
+        in2_loc_40_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd40) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_40_we0 = 1'b1;
+    end else begin
+        in2_loc_40_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_41_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_41_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_41_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_41_ce0 = 1'b1;
+    end else begin
+        in2_loc_41_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd41) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_41_we0 = 1'b1;
+    end else begin
+        in2_loc_41_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_42_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_42_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_42_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_42_ce0 = 1'b1;
+    end else begin
+        in2_loc_42_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd42) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_42_we0 = 1'b1;
+    end else begin
+        in2_loc_42_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_43_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_43_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_43_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_43_ce0 = 1'b1;
+    end else begin
+        in2_loc_43_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd43) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_43_we0 = 1'b1;
+    end else begin
+        in2_loc_43_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_44_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_44_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_44_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_44_ce0 = 1'b1;
+    end else begin
+        in2_loc_44_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd44) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_44_we0 = 1'b1;
+    end else begin
+        in2_loc_44_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_45_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_45_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_45_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_45_ce0 = 1'b1;
+    end else begin
+        in2_loc_45_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd45) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_45_we0 = 1'b1;
+    end else begin
+        in2_loc_45_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_46_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_46_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_46_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_46_ce0 = 1'b1;
+    end else begin
+        in2_loc_46_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd46) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_46_we0 = 1'b1;
+    end else begin
+        in2_loc_46_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_47_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_47_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_47_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_47_ce0 = 1'b1;
+    end else begin
+        in2_loc_47_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd47) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_47_we0 = 1'b1;
+    end else begin
+        in2_loc_47_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_48_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_48_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_48_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_48_ce0 = 1'b1;
+    end else begin
+        in2_loc_48_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd48) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_48_we0 = 1'b1;
+    end else begin
+        in2_loc_48_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_49_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_49_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_49_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_49_ce0 = 1'b1;
+    end else begin
+        in2_loc_49_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd49) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_49_we0 = 1'b1;
+    end else begin
+        in2_loc_49_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_4_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_4_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_4_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_4_ce0 = 1'b1;
+    end else begin
+        in2_loc_4_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd4) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_4_we0 = 1'b1;
+    end else begin
+        in2_loc_4_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_50_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_50_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_50_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_50_ce0 = 1'b1;
+    end else begin
+        in2_loc_50_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd50) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_50_we0 = 1'b1;
+    end else begin
+        in2_loc_50_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_51_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_51_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_51_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_51_ce0 = 1'b1;
+    end else begin
+        in2_loc_51_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd51) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_51_we0 = 1'b1;
+    end else begin
+        in2_loc_51_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_52_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_52_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_52_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_52_ce0 = 1'b1;
+    end else begin
+        in2_loc_52_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd52) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_52_we0 = 1'b1;
+    end else begin
+        in2_loc_52_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_53_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_53_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_53_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_53_ce0 = 1'b1;
+    end else begin
+        in2_loc_53_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd53) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_53_we0 = 1'b1;
+    end else begin
+        in2_loc_53_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_54_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_54_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_54_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_54_ce0 = 1'b1;
+    end else begin
+        in2_loc_54_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd54) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_54_we0 = 1'b1;
+    end else begin
+        in2_loc_54_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_55_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_55_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_55_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_55_ce0 = 1'b1;
+    end else begin
+        in2_loc_55_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd55) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_55_we0 = 1'b1;
+    end else begin
+        in2_loc_55_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_56_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_56_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_56_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_56_ce0 = 1'b1;
+    end else begin
+        in2_loc_56_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd56) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_56_we0 = 1'b1;
+    end else begin
+        in2_loc_56_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_57_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_57_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_57_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_57_ce0 = 1'b1;
+    end else begin
+        in2_loc_57_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd57) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_57_we0 = 1'b1;
+    end else begin
+        in2_loc_57_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_58_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_58_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_58_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_58_ce0 = 1'b1;
+    end else begin
+        in2_loc_58_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd58) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_58_we0 = 1'b1;
+    end else begin
+        in2_loc_58_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_59_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_59_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_59_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_59_ce0 = 1'b1;
+    end else begin
+        in2_loc_59_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd59) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_59_we0 = 1'b1;
+    end else begin
+        in2_loc_59_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_5_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_5_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_5_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_5_ce0 = 1'b1;
+    end else begin
+        in2_loc_5_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd5) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_5_we0 = 1'b1;
+    end else begin
+        in2_loc_5_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_60_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_60_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_60_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_60_ce0 = 1'b1;
+    end else begin
+        in2_loc_60_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd60) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_60_we0 = 1'b1;
+    end else begin
+        in2_loc_60_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_61_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_61_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_61_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_61_ce0 = 1'b1;
+    end else begin
+        in2_loc_61_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd61) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_61_we0 = 1'b1;
+    end else begin
+        in2_loc_61_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_62_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_62_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_62_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_62_ce0 = 1'b1;
+    end else begin
+        in2_loc_62_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd62) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_62_we0 = 1'b1;
+    end else begin
+        in2_loc_62_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_63_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_63_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_63_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_63_ce0 = 1'b1;
+    end else begin
+        in2_loc_63_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd63) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_63_we0 = 1'b1;
+    end else begin
+        in2_loc_63_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_6_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_6_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_6_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_6_ce0 = 1'b1;
+    end else begin
+        in2_loc_6_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd6) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_6_we0 = 1'b1;
+    end else begin
+        in2_loc_6_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_7_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_7_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_7_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_7_ce0 = 1'b1;
+    end else begin
+        in2_loc_7_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd7) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_7_we0 = 1'b1;
+    end else begin
+        in2_loc_7_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1))) begin
+        in2_loc_8_address0 = sext_ln38_fu_3739_p1;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_8_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_8_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (1'b1 == ap_CS_fsm_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1)))) begin
+        in2_loc_8_ce0 = 1'b1;
+    end else begin
+        in2_loc_8_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd8) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_8_we0 = 1'b1;
+    end else begin
+        in2_loc_8_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter2 == 1'b1))) begin
+        in2_loc_9_address0 = sext_ln38_reg_4857;
+    end else if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_9_address0 = zext_ln28_fu_3544_p1;
+    end else begin
+        in2_loc_9_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter2 == 1'b1)))) begin
+        in2_loc_9_ce0 = 1'b1;
+    end else begin
+        in2_loc_9_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((trunc_ln1_reg_4495_pp1_iter1_reg == 6'd9) & (1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter2 == 1'b1))) begin
+        in2_loc_9_we0 = 1'b1;
+    end else begin
+        in2_loc_9_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+        in2_mem_ARVALID = 1'b1;
+    end else begin
+        in2_mem_ARVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0_11001) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_RREADY = 1'b1;
+    end else begin
+        in2_mem_RREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state12)) begin
+        in2_mem_blk_n_AR = m_axi_in2_mem_ARREADY;
+    end else begin
+        in2_mem_blk_n_AR = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
+        in2_mem_blk_n_R = m_axi_in2_mem_RVALID;
+    end else begin
+        in2_mem_blk_n_R = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp3_stage0) & (1'b1 == ap_CS_fsm_pp3_stage0) & (ap_enable_reg_pp3_iter0 == 1'b1))) begin
+        out_loc_address0 = zext_ln42_fu_4351_p1;
+    end else if (((1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter4 == 1'b1))) begin
+        out_loc_address0 = out_loc_addr_reg_4598_pp2_iter3_reg;
+    end else begin
+        out_loc_address0 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((((1'b0 == ap_block_pp3_stage0_11001) & (1'b1 == ap_CS_fsm_pp3_stage0) & (ap_enable_reg_pp3_iter0 == 1'b1)) | ((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter4 == 1'b1)))) begin
+        out_loc_ce0 = 1'b1;
+    end else begin
+        out_loc_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (ap_enable_reg_pp2_iter8 == 1'b1))) begin
+        out_loc_ce1 = 1'b1;
+    end else begin
+        out_loc_ce1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp2_stage0_11001) & (icmp_ln31_reg_4578_pp2_iter7_reg == 1'd0) & (ap_enable_reg_pp2_iter8 == 1'b1))) begin
+        out_loc_we1 = 1'b1;
+    end else begin
+        out_loc_we1 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+        out_mem_AWVALID = 1'b1;
+    end else begin
+        out_mem_AWVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state42))) begin
+        out_mem_BREADY = 1'b1;
+    end else begin
+        out_mem_BREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp3_stage0_11001) & (icmp_ln42_reg_6380_pp3_iter1_reg == 1'd0) & (ap_enable_reg_pp3_iter2 == 1'b1))) begin
+        out_mem_WVALID = 1'b1;
+    end else begin
+        out_mem_WVALID = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state34)) begin
+        out_mem_blk_n_AW = m_axi_out_mem_AWREADY;
+    end else begin
+        out_mem_blk_n_AW = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state42)) begin
+        out_mem_blk_n_B = m_axi_out_mem_BVALID;
+    end else begin
+        out_mem_blk_n_B = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln42_reg_6380_pp3_iter1_reg == 1'd0) & (1'b0 == ap_block_pp3_stage0) & (ap_enable_reg_pp3_iter2 == 1'b1))) begin
+        out_mem_blk_n_W = m_axi_out_mem_WREADY;
+    end else begin
+        out_mem_blk_n_W = 1'b1;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((in1_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            ap_NS_fsm = ap_ST_fsm_state6;
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        ap_ST_fsm_pp0_stage0 : begin
+            if ((~((icmp_ln27_fu_3425_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) & ~((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end else if ((((icmp_ln27_fu_3425_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)) | ((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b1) & (1'b0 == ap_block_pp0_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+            end
+        end
+        ap_ST_fsm_state12 : begin
+            if (((in2_mem_ARREADY == 1'b1) & (1'b1 == ap_CS_fsm_state12))) begin
+                ap_NS_fsm = ap_ST_fsm_state13;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state12;
+            end
+        end
+        ap_ST_fsm_state13 : begin
+            ap_NS_fsm = ap_ST_fsm_state14;
+        end
+        ap_ST_fsm_state14 : begin
+            ap_NS_fsm = ap_ST_fsm_state15;
+        end
+        ap_ST_fsm_state15 : begin
+            ap_NS_fsm = ap_ST_fsm_state16;
+        end
+        ap_ST_fsm_state16 : begin
+            ap_NS_fsm = ap_ST_fsm_state17;
+        end
+        ap_ST_fsm_state17 : begin
+            ap_NS_fsm = ap_ST_fsm_state18;
+        end
+        ap_ST_fsm_state18 : begin
+            ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+        end
+        ap_ST_fsm_pp1_stage0 : begin
+            if ((~((icmp_ln28_fu_3518_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)) & ~((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end else if ((((icmp_ln28_fu_3518_p2 == 1'd1) & (ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)) | ((ap_enable_reg_pp1_iter1 == 1'b0) & (ap_enable_reg_pp1_iter2 == 1'b1) & (1'b0 == ap_block_pp1_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state22;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp1_stage0;
+            end
+        end
+        ap_ST_fsm_state22 : begin
+            ap_NS_fsm = ap_ST_fsm_state23;
+        end
+        ap_ST_fsm_state23 : begin
+            ap_NS_fsm = ap_ST_fsm_state24;
+        end
+        ap_ST_fsm_state24 : begin
+            ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+        end
+        ap_ST_fsm_pp2_stage0 : begin
+            if ((~((icmp_ln31_fu_3620_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (ap_enable_reg_pp2_iter1 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)) & ~((ap_enable_reg_pp2_iter8 == 1'b1) & (ap_enable_reg_pp2_iter7 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end else if ((((icmp_ln31_fu_3620_p2 == 1'd1) & (ap_enable_reg_pp2_iter0 == 1'b1) & (ap_enable_reg_pp2_iter1 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)) | ((ap_enable_reg_pp2_iter8 == 1'b1) & (ap_enable_reg_pp2_iter7 == 1'b0) & (1'b0 == ap_block_pp2_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_state34;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp2_stage0;
+            end
+        end
+        ap_ST_fsm_state34 : begin
+            if (((out_mem_AWREADY == 1'b1) & (1'b1 == ap_CS_fsm_state34))) begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state34;
+            end
+        end
+        ap_ST_fsm_pp3_stage0 : begin
+            if ((~((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone) & (icmp_ln42_fu_4339_p2 == 1'd1)) & ~((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone)))) begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end else if ((((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter2 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone)) | ((ap_enable_reg_pp3_iter1 == 1'b0) & (ap_enable_reg_pp3_iter0 == 1'b1) & (1'b0 == ap_block_pp3_stage0_subdone) & (icmp_ln42_fu_4339_p2 == 1'd1)))) begin
+                ap_NS_fsm = ap_ST_fsm_state38;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_pp3_stage0;
+            end
+        end
+        ap_ST_fsm_state38 : begin
+            ap_NS_fsm = ap_ST_fsm_state39;
+        end
+        ap_ST_fsm_state39 : begin
+            ap_NS_fsm = ap_ST_fsm_state40;
+        end
+        ap_ST_fsm_state40 : begin
+            ap_NS_fsm = ap_ST_fsm_state41;
+        end
+        ap_ST_fsm_state41 : begin
+            ap_NS_fsm = ap_ST_fsm_state42;
+        end
+        ap_ST_fsm_state42 : begin
+            if (((out_mem_BVALID == 1'b1) & (1'b1 == ap_CS_fsm_state42))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state42;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln27_fu_3431_p2 = (phi_ln27_reg_3296 + 13'd1);
+
+assign add_ln28_fu_3524_p2 = (phi_ln28_reg_3307 + 13'd1);
+
+assign add_ln31_fu_3625_p2 = (indvar_flatten_reg_3318 + 64'd1);
+
+assign add_ln38_10_fu_4070_p2 = (mul_ln38_12_reg_5985 + mul_ln38_11_reg_5980);
+
+assign add_ln38_11_fu_4160_p2 = (mul_ln38_14_reg_6175 + mul_ln38_13_reg_6170);
+
+assign add_ln38_12_fu_4164_p2 = (add_ln38_10_reg_6275 + add_ln38_11_fu_4160_p2);
+
+assign add_ln38_13_fu_4169_p2 = (add_ln38_9_fu_4155_p2 + add_ln38_12_fu_4164_p2);
+
+assign add_ln38_14_fu_4175_p2 = (add_ln38_6_fu_4146_p2 + add_ln38_13_fu_4169_p2);
+
+assign add_ln38_15_fu_4074_p2 = (mul_ln38_16_reg_5995 + mul_ln38_15_reg_5990);
+
+assign add_ln38_16_fu_4181_p2 = (mul_ln38_18_reg_6185 + mul_ln38_17_reg_6180);
+
+assign add_ln38_17_fu_4185_p2 = (add_ln38_15_reg_6280 + add_ln38_16_fu_4181_p2);
+
+assign add_ln38_18_fu_4078_p2 = (mul_ln38_20_reg_6005 + mul_ln38_19_reg_6000);
+
+assign add_ln38_19_fu_4082_p2 = (mul_ln38_22_reg_6015 + mul_ln38_21_reg_6010);
+
+assign add_ln38_1_fu_4048_p2 = (mul_ln38_2_reg_5945 + mul_ln38_1_reg_5940);
+
+assign add_ln38_20_fu_4190_p2 = (add_ln38_18_reg_6285 + add_ln38_19_reg_6290);
+
+assign add_ln38_21_fu_4194_p2 = (add_ln38_17_fu_4185_p2 + add_ln38_20_fu_4190_p2);
+
+assign add_ln38_22_fu_4086_p2 = (mul_ln38_24_reg_6025 + mul_ln38_23_reg_6020);
+
+assign add_ln38_23_fu_4200_p2 = (mul_ln38_26_reg_6195 + mul_ln38_25_reg_6190);
+
+assign add_ln38_24_fu_4204_p2 = (add_ln38_22_reg_6295 + add_ln38_23_fu_4200_p2);
+
+assign add_ln38_25_fu_4090_p2 = (mul_ln38_28_reg_6035 + mul_ln38_27_reg_6030);
+
+assign add_ln38_26_fu_4094_p2 = (mul_ln38_30_reg_6045 + mul_ln38_29_reg_6040);
+
+assign add_ln38_27_fu_4209_p2 = (add_ln38_25_reg_6300 + add_ln38_26_reg_6305);
+
+assign add_ln38_28_fu_4213_p2 = (add_ln38_24_fu_4204_p2 + add_ln38_27_fu_4209_p2);
+
+assign add_ln38_29_fu_4219_p2 = (add_ln38_21_fu_4194_p2 + add_ln38_28_fu_4213_p2);
+
+assign add_ln38_2_fu_4052_p2 = (add_ln38_fu_4043_p2 + add_ln38_1_fu_4048_p2);
+
+assign add_ln38_30_fu_4225_p2 = (add_ln38_14_fu_4175_p2 + add_ln38_29_fu_4219_p2);
+
+assign add_ln38_31_fu_4098_p2 = (mul_ln38_32_reg_6055 + mul_ln38_31_reg_6050);
+
+assign add_ln38_32_fu_4231_p2 = (mul_ln38_34_reg_6205 + mul_ln38_33_reg_6200);
+
+assign add_ln38_33_fu_4235_p2 = (add_ln38_31_reg_6310 + add_ln38_32_fu_4231_p2);
+
+assign add_ln38_34_fu_4102_p2 = (mul_ln38_36_reg_6065 + mul_ln38_35_reg_6060);
+
+assign add_ln38_35_fu_4106_p2 = (mul_ln38_38_reg_6075 + mul_ln38_37_reg_6070);
+
+assign add_ln38_36_fu_4240_p2 = (add_ln38_34_reg_6315 + add_ln38_35_reg_6320);
+
+assign add_ln38_37_fu_4244_p2 = (add_ln38_33_fu_4235_p2 + add_ln38_36_fu_4240_p2);
+
+assign add_ln38_38_fu_4110_p2 = (mul_ln38_40_reg_6085 + mul_ln38_39_reg_6080);
+
+assign add_ln38_39_fu_4250_p2 = (mul_ln38_42_reg_6215 + mul_ln38_41_reg_6210);
+
+assign add_ln38_3_fu_4058_p2 = (mul_ln38_4_reg_5955 + mul_ln38_3_reg_5950);
+
+assign add_ln38_40_fu_4254_p2 = (add_ln38_38_reg_6325 + add_ln38_39_fu_4250_p2);
+
+assign add_ln38_41_fu_4114_p2 = (mul_ln38_44_reg_6095 + mul_ln38_43_reg_6090);
+
+assign add_ln38_42_fu_4259_p2 = (mul_ln38_46_reg_6225 + mul_ln38_45_reg_6220);
+
+assign add_ln38_43_fu_4263_p2 = (add_ln38_41_reg_6330 + add_ln38_42_fu_4259_p2);
+
+assign add_ln38_44_fu_4268_p2 = (add_ln38_40_fu_4254_p2 + add_ln38_43_fu_4263_p2);
+
+assign add_ln38_45_fu_4274_p2 = (add_ln38_37_fu_4244_p2 + add_ln38_44_fu_4268_p2);
+
+assign add_ln38_46_fu_4118_p2 = (mul_ln38_48_reg_6105 + mul_ln38_47_reg_6100);
+
+assign add_ln38_47_fu_4280_p2 = (mul_ln38_50_reg_6235 + mul_ln38_49_reg_6230);
+
+assign add_ln38_48_fu_4284_p2 = (add_ln38_46_reg_6335 + add_ln38_47_fu_4280_p2);
+
+assign add_ln38_49_fu_4122_p2 = (mul_ln38_52_reg_6115 + mul_ln38_51_reg_6110);
+
+assign add_ln38_4_fu_4062_p2 = (mul_ln38_6_reg_5965 + mul_ln38_5_reg_5960);
+
+assign add_ln38_50_fu_4126_p2 = (mul_ln38_54_reg_6125 + mul_ln38_53_reg_6120);
+
+assign add_ln38_51_fu_4289_p2 = (add_ln38_49_reg_6340 + add_ln38_50_reg_6345);
+
+assign add_ln38_52_fu_4293_p2 = (add_ln38_48_fu_4284_p2 + add_ln38_51_fu_4289_p2);
+
+assign add_ln38_53_fu_4130_p2 = (mul_ln38_56_reg_6135 + mul_ln38_55_reg_6130);
+
+assign add_ln38_54_fu_4299_p2 = (mul_ln38_58_reg_6245 + mul_ln38_57_reg_6240);
+
+assign add_ln38_55_fu_4303_p2 = (add_ln38_53_reg_6350 + add_ln38_54_fu_4299_p2);
+
+assign add_ln38_56_fu_4134_p2 = (mul_ln38_60_reg_6145 + mul_ln38_59_reg_6140);
+
+assign add_ln38_57_fu_4138_p2 = (mul_ln38_63_reg_6155 + mul_ln38_62_reg_6150);
+
+assign add_ln38_58_fu_4308_p2 = (mul_ln38_61_reg_6250 + add_ln38_57_reg_6360);
+
+assign add_ln38_59_fu_4312_p2 = (add_ln38_56_reg_6355 + add_ln38_58_fu_4308_p2);
+
+assign add_ln38_5_fu_4142_p2 = (add_ln38_3_reg_6260 + add_ln38_4_reg_6265);
+
+assign add_ln38_60_fu_4317_p2 = (add_ln38_55_fu_4303_p2 + add_ln38_59_fu_4312_p2);
+
+assign add_ln38_61_fu_4323_p2 = (add_ln38_52_fu_4293_p2 + add_ln38_60_fu_4317_p2);
+
+assign add_ln38_62_fu_4329_p2 = (add_ln38_45_reg_6370 + add_ln38_61_reg_6375);
+
+assign add_ln38_64_fu_3674_p2 = (tmp_cast_fu_3662_p3 + trunc_ln38_1_fu_3670_p1);
+
+assign add_ln38_6_fu_4146_p2 = (add_ln38_2_reg_6255 + add_ln38_5_fu_4142_p2);
+
+assign add_ln38_7_fu_4066_p2 = (mul_ln38_8_reg_5975 + mul_ln38_7_reg_5970);
+
+assign add_ln38_8_fu_4151_p2 = (mul_ln38_10_reg_6165 + mul_ln38_9_reg_6160);
+
+assign add_ln38_9_fu_4155_p2 = (add_ln38_7_reg_6270 + add_ln38_8_fu_4151_p2);
+
+assign add_ln38_fu_4043_p2 = (mul_ln38_reg_5935 + reg_3362);
+
+assign add_ln42_fu_4345_p2 = (phi_ln42_reg_3351 + 13'd1);
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd8];
+
+assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd16];
+
+assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd20];
+
+assign ap_CS_fsm_pp3_stage0 = ap_CS_fsm[32'd22];
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state12 = ap_CS_fsm[32'd9];
+
+assign ap_CS_fsm_state18 = ap_CS_fsm[32'd15];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state22 = ap_CS_fsm[32'd17];
+
+assign ap_CS_fsm_state24 = ap_CS_fsm[32'd19];
+
+assign ap_CS_fsm_state34 = ap_CS_fsm[32'd21];
+
+assign ap_CS_fsm_state42 = ap_CS_fsm[32'd27];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp0_stage0_11001 = ((in1_mem_RVALID == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp0_stage0_subdone = ((in1_mem_RVALID == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b1));
+end
+
+assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp1_stage0_11001 = ((in2_mem_RVALID == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp1_stage0_subdone = ((in2_mem_RVALID == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1));
+end
+
+assign ap_block_pp2_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp2_stage0_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp2_stage0_subdone = ~(1'b1 == 1'b1);
+
+assign ap_block_pp3_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp3_stage0_01001 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_pp3_stage0_11001 = ((1'b1 == ap_block_state37_io) & (ap_enable_reg_pp3_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_pp3_stage0_subdone = ((1'b1 == ap_block_state37_io) & (ap_enable_reg_pp3_iter2 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state10_pp0_stage0_iter1 = (in1_mem_RVALID == 1'b0);
+end
+
+assign ap_block_state11_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state19_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state20_pp1_stage0_iter1 = (in2_mem_RVALID == 1'b0);
+end
+
+assign ap_block_state21_pp1_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state25_pp2_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state26_pp2_stage0_iter1 = ~(1'b1 == 1'b1);
+
+assign ap_block_state27_pp2_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state28_pp2_stage0_iter3 = ~(1'b1 == 1'b1);
+
+assign ap_block_state29_pp2_stage0_iter4 = ~(1'b1 == 1'b1);
+
+assign ap_block_state30_pp2_stage0_iter5 = ~(1'b1 == 1'b1);
+
+assign ap_block_state31_pp2_stage0_iter6 = ~(1'b1 == 1'b1);
+
+assign ap_block_state32_pp2_stage0_iter7 = ~(1'b1 == 1'b1);
+
+assign ap_block_state33_pp2_stage0_iter8 = ~(1'b1 == 1'b1);
+
+assign ap_block_state35_pp3_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_block_state36_pp3_stage0_iter1 = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_block_state37_io = ((out_mem_WREADY == 1'b0) & (icmp_ln42_reg_6380_pp3_iter1_reg == 1'd0));
+end
+
+assign ap_block_state37_pp3_stage0_iter2 = ~(1'b1 == 1'b1);
+
+assign ap_block_state9_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
+
+assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);
+
+assign ap_enable_pp3 = (ap_idle_pp3 ^ 1'b1);
+
+always @ (*) begin
+    ap_rst_n_inv = ~ap_rst_n;
+end
+
+assign empty_7_fu_3416_p1 = in_reg_4367;
+
+assign empty_8_fu_3397_p1 = in3_reg_4372;
+
+assign empty_fu_3407_p1 = out5_reg_4362;
+
+assign grp_fu_3614_p0 = zext_ln31_fu_3611_p1;
+
+assign grp_fu_3614_p1 = zext_ln31_fu_3611_p1;
+
+assign i_fu_3631_p2 = (31'd1 + ap_phi_mux_i_0_phi_fu_3333_p4);
+
+assign icmp_ln27_fu_3425_p2 = ((phi_ln27_reg_3296 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln28_fu_3518_p2 = ((phi_ln28_reg_3307 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign icmp_ln31_fu_3620_p2 = ((indvar_flatten_reg_3318 == mul_ln31_reg_4573) ? 1'b1 : 1'b0);
+
+assign icmp_ln33_fu_3637_p2 = ((j_0_reg_3340 == dim_read_reg_4356) ? 1'b1 : 1'b0);
+
+assign icmp_ln42_fu_4339_p2 = ((phi_ln42_reg_3351 == 13'd4096) ? 1'b1 : 1'b0);
+
+assign in1_mem_ARADDR = empty_8_fu_3397_p1;
+
+assign j_fu_3685_p2 = ($signed(32'd1) + $signed(select_ln31_fu_3642_p3));
+
+assign out_loc_d1 = (add_ln38_30_reg_6365 + add_ln38_62_fu_4329_p2);
+
+assign select_ln31_1_fu_3650_p3 = ((icmp_ln33_fu_3637_p2[0:0] === 1'b1) ? i_fu_3631_p2 : ap_phi_mux_i_0_phi_fu_3333_p4);
+
+assign select_ln31_fu_3642_p3 = ((icmp_ln33_fu_3637_p2[0:0] === 1'b1) ? 32'd0 : j_0_reg_3340);
+
+assign sext_ln38_fu_3739_p1 = select_ln31_reg_4587;
+
+assign tmp_cast_fu_3662_p3 = {{trunc_ln38_fu_3658_p1}, {6'd0}};
+
+assign trunc_ln27_fu_3447_p1 = phi_ln27_reg_3296[5:0];
+
+assign trunc_ln28_fu_3530_p1 = phi_ln28_reg_3307[5:0];
+
+assign trunc_ln38_1_fu_3670_p1 = select_ln31_fu_3642_p3[13:0];
+
+assign trunc_ln38_fu_3658_p1 = select_ln31_1_fu_3650_p3[7:0];
+
+assign zext_ln27_fu_3451_p1 = lshr_ln_reg_4404_pp0_iter1_reg;
+
+assign zext_ln28_fu_3544_p1 = trunc_ln28_reg_4490_pp1_iter1_reg;
+
+assign zext_ln31_1_fu_3691_p1 = select_ln31_1_reg_4592;
+
+assign zext_ln31_fu_3611_p1 = dim_read_reg_4356;
+
+assign zext_ln38_fu_3680_p1 = add_ln38_64_fu_3674_p2;
+
+assign zext_ln42_fu_4351_p1 = phi_ln42_reg_3351;
+
+always @ (posedge ap_clk) begin
+    out_mem_addr_reg_4383[31:30] <= 2'b00;
+    in2_mem_addr_reg_4389[31:30] <= 2'b00;
+    zext_ln31_1_reg_4609[63:31] <= 33'b000000000000000000000000000000000;
+end
+
+endmodule //mmult
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in1_loc_0.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in1_loc_0.v
new file mode 100755
index 0000000..7a7e881
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in1_loc_0.v
@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_0_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 6;
+parameter MEM_SIZE = 64;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_0(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd64;
+parameter AddressWidth = 32'd6;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_in1_loc_0_ram mmult_in1_loc_0_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in1_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in1_mem_m_axi.v
new file mode 100755
index 0000000..81f7248
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in1_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in1_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in1_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in1_mem_m_axi_write
+mmult_in1_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in1_mem_m_axi_read
+mmult_in1_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in1_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in1_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in1_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in1_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in1_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in1_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in1_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in1_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in1_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in1_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in2_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in2_mem_m_axi.v
new file mode 100755
index 0000000..a2eab07
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_in2_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_in2_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_in2_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_in2_mem_m_axi_write
+mmult_in2_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_in2_mem_m_axi_read
+mmult_in2_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_in2_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_in2_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_in2_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_in2_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_in2_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_in2_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_in2_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_in2_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_in2_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_in2_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_mul_32ns_32bkb.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_mul_32ns_32bkb.v
new file mode 100755
index 0000000..1a8090f
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_mul_32ns_32bkb.v
@@ -0,0 +1,61 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module mmult_mul_32ns_32bkb_MulnS_0(clk, ce, a, b, p);
+input clk;
+input ce;
+input[32 - 1 : 0] a; 
+input[32 - 1 : 0] b; 
+output[64 - 1 : 0] p;
+
+reg [32 - 1 : 0] a_reg0;
+reg [32 - 1 : 0] b_reg0;
+wire [64 - 1 : 0] tmp_product;
+reg [64 - 1 : 0] buff0;
+
+assign p = buff0;
+assign tmp_product = a_reg0 * b_reg0;
+always @ (posedge clk) begin
+    if (ce) begin
+        a_reg0 <= a;
+        b_reg0 <= b;
+        buff0 <= tmp_product;
+    end
+end
+endmodule
+`timescale 1 ns / 1 ps
+module mmult_mul_32ns_32bkb(
+    clk,
+    reset,
+    ce,
+    din0,
+    din1,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+input clk;
+input reset;
+input ce;
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+output[dout_WIDTH - 1:0] dout;
+
+
+
+mmult_mul_32ns_32bkb_MulnS_0 mmult_mul_32ns_32bkb_MulnS_0_U(
+    .clk( clk ),
+    .ce( ce ),
+    .a( din0 ),
+    .b( din1 ),
+    .p( dout ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_mul_32s_32scud.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_mul_32s_32scud.v
new file mode 100755
index 0000000..88ab6f6
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_mul_32s_32scud.v
@@ -0,0 +1,61 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module mmult_mul_32s_32scud_MulnS_1(clk, ce, a, b, p);
+input clk;
+input ce;
+input[32 - 1 : 0] a; 
+input[32 - 1 : 0] b; 
+output[32 - 1 : 0] p;
+
+reg signed [32 - 1 : 0] a_reg0;
+reg signed [32 - 1 : 0] b_reg0;
+wire signed [32 - 1 : 0] tmp_product;
+reg signed [32 - 1 : 0] buff0;
+
+assign p = buff0;
+assign tmp_product = a_reg0 * b_reg0;
+always @ (posedge clk) begin
+    if (ce) begin
+        a_reg0 <= a;
+        b_reg0 <= b;
+        buff0 <= tmp_product;
+    end
+end
+endmodule
+`timescale 1 ns / 1 ps
+module mmult_mul_32s_32scud(
+    clk,
+    reset,
+    ce,
+    din0,
+    din1,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+input clk;
+input reset;
+input ce;
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+output[dout_WIDTH - 1:0] dout;
+
+
+
+mmult_mul_32s_32scud_MulnS_1 mmult_mul_32s_32scud_MulnS_1_U(
+    .clk( clk ),
+    .ce( ce ),
+    .a( din0 ),
+    .b( din1 ),
+    .p( dout ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_out_loc.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_out_loc.v
new file mode 100755
index 0000000..9acfd8e
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_out_loc.v
@@ -0,0 +1,83 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_out_loc_ram (addr0, ce0, q0, addr1, ce1, d1, we1,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+output reg[DWIDTH-1:0] q0;
+input[AWIDTH-1:0] addr1;
+input ce1;
+input[DWIDTH-1:0] d1;
+input we1;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        q0 <= ram[addr0];
+    end
+end
+
+
+always @(posedge clk)  
+begin 
+    if (ce1) begin
+        if (we1) 
+            ram[addr1] <= d1; 
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_out_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    q0,
+    address1,
+    ce1,
+    we1,
+    d1);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+output[DataWidth - 1:0] q0;
+input[AddressWidth - 1:0] address1;
+input ce1;
+input we1;
+input[DataWidth - 1:0] d1;
+
+
+
+mmult_out_loc_ram mmult_out_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .q0( q0 ),
+    .addr1( address1 ),
+    .ce1( ce1 ),
+    .we1( we1 ),
+    .d1( d1 ));
+
+endmodule
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_out_mem_m_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_out_mem_m_axi.v
new file mode 100755
index 0000000..cc472db
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_out_mem_m_axi.v
@@ -0,0 +1,2692 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+`default_nettype none
+
+module mmult_out_mem_m_axi
+#(parameter
+    CONSERVATIVE            = 0,
+    NUM_READ_OUTSTANDING    = 2,
+    NUM_WRITE_OUTSTANDING   = 2,
+    MAX_READ_BURST_LENGTH   = 16,
+    MAX_WRITE_BURST_LENGTH  = 16,
+    C_M_AXI_ID_WIDTH        = 1,
+    C_M_AXI_ADDR_WIDTH      = 32,
+    C_TARGET_ADDR           = 32'h00000000,
+    C_M_AXI_DATA_WIDTH      = 32,
+    C_M_AXI_AWUSER_WIDTH    = 1,
+    C_M_AXI_ARUSER_WIDTH    = 1,
+    C_M_AXI_WUSER_WIDTH     = 1,
+    C_M_AXI_RUSER_WIDTH     = 1,
+    C_M_AXI_BUSER_WIDTH     = 1,
+    C_USER_VALUE            = 1'b0,
+    C_PROT_VALUE            = 3'b000,
+    C_CACHE_VALUE           = 4'b0011,
+    USER_DW                 = 16,
+    USER_AW                 = 32,
+    USER_MAXREQS            = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+
+    // internal bus ports
+    // write address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_AWID,
+    input  wire [USER_AW-1:0]           I_AWADDR,
+    input  wire [31:0]                  I_AWLEN,
+    input  wire [2:0]                   I_AWSIZE,
+    input  wire [1:0]                   I_AWBURST,
+    input  wire [1:0]                   I_AWLOCK,
+    input  wire [3:0]                   I_AWCACHE,
+    input  wire [2:0]                   I_AWPROT,
+    input  wire [3:0]                   I_AWQOS,
+    input  wire [3:0]                   I_AWREGION,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    I_AWUSER,
+    input  wire                         I_AWVALID,
+    output wire                         I_AWREADY,
+    // write data
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_WID,
+    input  wire [USER_DW-1:0]           I_WDATA,
+    input  wire                         I_WLAST,
+    input  wire [USER_DW/8-1:0]         I_WSTRB,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     I_WUSER,
+    input  wire                         I_WVALID,
+    output wire                         I_WREADY,
+    // write response
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_BID,
+    output wire [1:0]                   I_BRESP,
+    output wire [C_M_AXI_BUSER_WIDTH-1:0]     I_BUSER,
+    output wire                         I_BVALID,
+    input  wire                         I_BREADY,
+    // read address
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        I_ARID,
+    input  wire [USER_AW-1:0]           I_ARADDR,
+    input  wire [31:0]                  I_ARLEN,
+    input  wire [2:0]                   I_ARSIZE,
+    input  wire [1:0]                   I_ARBURST,
+    input  wire [1:0]                   I_ARLOCK,
+    input  wire [3:0]                   I_ARCACHE,
+    input  wire [2:0]                   I_ARPROT,
+    input  wire [3:0]                   I_ARQOS,
+    input  wire [3:0]                   I_ARREGION,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    I_ARUSER,
+    input  wire                         I_ARVALID,
+    output wire                         I_ARREADY,
+    // read data
+    output wire [C_M_AXI_ID_WIDTH-1:0]        I_RID,
+    output wire [USER_DW-1:0]           I_RDATA,
+    output wire [1:0]                   I_RRESP,
+    output wire                         I_RLAST,
+    output wire [C_M_AXI_RUSER_WIDTH-1:0]     I_RUSER,
+    output wire                         I_RVALID,
+    input  wire                         I_RREADY
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire  [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR_Dummy;
+wire  [7:0]                         AWLEN_Dummy;
+wire                                AWVALID_Dummy;
+wire                                AWREADY_Dummy;
+wire  [C_M_AXI_DATA_WIDTH-1:0]      WDATA_Dummy;
+wire  [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB_Dummy;
+wire                                WLAST_Dummy;
+wire                                WVALID_Dummy;
+wire                                WREADY_Dummy;
+
+// Write Address channel throttling unit
+mmult_out_mem_m_axi_throttl #(
+    .USED_FIX(0),
+    .ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
+    .DATA_WIDTH(C_M_AXI_DATA_WIDTH),
+    .DEPTH(MAX_WRITE_BURST_LENGTH),
+    .USER_MAXREQS(NUM_WRITE_OUTSTANDING),
+    .CONSERVATIVE(CONSERVATIVE),
+    .AVERAGE_MODE(0)
+) wreq_throttl (
+    .clk(ACLK),
+    .reset(ARESET),
+    .ce(ACLK_EN),
+    .in_addr(AWADDR_Dummy),
+    .in_len(AWLEN_Dummy),
+    .in_req_valid(AWVALID_Dummy),
+    .out_req_ready(AWREADY_Dummy),
+    .out_addr(AWADDR),
+    .out_len(AWLEN),
+    .out_req_valid(AWVALID),
+    .in_req_ready(AWREADY),
+    .in_data(WDATA_Dummy),
+    .in_strb(WSTRB_Dummy),
+    .in_last(WLAST_Dummy),
+    .in_data_valid(WVALID_Dummy),
+    .out_data_ready(WREADY_Dummy),
+    .out_data(WDATA),
+    .out_strb(WSTRB),
+    .out_last(WLAST),
+    .out_data_valid(WVALID),
+    .in_data_ready(WREADY)
+);
+// END of write Address channel throttling unit
+
+assign I_BID = 1'b0;
+assign I_BUSER = C_USER_VALUE;
+assign I_RID = 1'b0;
+assign I_RLAST = 1'b0;
+assign I_RUSER = C_USER_VALUE;
+//------------------------Instantiation------------------
+
+// mmult_out_mem_m_axi_write
+mmult_out_mem_m_axi_write #(
+    .NUM_WRITE_OUTSTANDING   ( NUM_WRITE_OUTSTANDING ),
+    .MAX_WRITE_BURST_LENGTH  ( MAX_WRITE_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH        ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH      ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR           ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH      ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_AWUSER_WIDTH    ( C_M_AXI_AWUSER_WIDTH ),
+    .C_M_AXI_WUSER_WIDTH     ( C_M_AXI_WUSER_WIDTH ),
+    .C_M_AXI_BUSER_WIDTH     ( C_M_AXI_BUSER_WIDTH ),
+    .C_USER_VALUE            ( C_USER_VALUE ),
+    .C_PROT_VALUE            ( C_PROT_VALUE ),
+    .C_CACHE_VALUE           ( C_CACHE_VALUE ),
+    .USER_DW                 ( USER_DW ),
+    .USER_AW                 ( USER_AW ),
+    .USER_MAXREQS            ( USER_MAXREQS )
+) bus_write (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .AWID              ( AWID ),
+    .AWADDR            ( AWADDR_Dummy ),
+    .AWLEN             ( AWLEN_Dummy ),
+    .AWSIZE            ( AWSIZE ),
+    .AWBURST           ( AWBURST ),
+    .AWLOCK            ( AWLOCK ),
+    .AWCACHE           ( AWCACHE ),
+    .AWPROT            ( AWPROT ),
+    .AWQOS             ( AWQOS ),
+    .AWREGION          ( AWREGION ),
+    .AWUSER            ( AWUSER ),
+    .AWVALID           ( AWVALID_Dummy ),
+    .AWREADY           ( AWREADY_Dummy ),
+    .WID               ( WID),
+    .WDATA             ( WDATA_Dummy ),
+    .WSTRB             ( WSTRB_Dummy ),
+    .WLAST             ( WLAST_Dummy ),
+    .WUSER             ( WUSER),
+    .WVALID            ( WVALID_Dummy ),
+    .WREADY            ( WREADY_Dummy ),
+    .BID               ( BID ),
+    .BRESP             ( BRESP ),
+    .BUSER             ( BUSER ),
+    .BVALID            ( BVALID ),
+    .BREADY            ( BREADY ),
+    .wreq_valid        ( I_AWVALID ),
+    .wreq_ack    ( I_AWREADY ),
+    .wreq_addr         ( I_AWADDR ),
+    .wreq_length       ( I_AWLEN ),
+    .wreq_cache        ( I_AWCACHE ),
+    .wreq_prot         ( I_AWPROT ),
+    .wreq_qos          ( I_AWQOS ),
+    .wreq_region       ( I_AWREGION ),
+    .wreq_user         ( I_AWUSER ),
+    .wdata_valid     ( I_WVALID ),
+    .wdata_ack         ( I_WREADY ),
+    .wdata_strb        ( I_WSTRB ),
+    .wdata_user        ( I_WUSER ),
+    .wdata_data        ( I_WDATA ),
+    .wrsp_valid        ( I_BVALID ),
+    .wrsp_ack          ( I_BREADY ),
+    .wrsp              ( I_BRESP )
+);
+
+// mmult_out_mem_m_axi_read
+mmult_out_mem_m_axi_read #(
+    .NUM_READ_OUTSTANDING     ( NUM_READ_OUTSTANDING ),
+    .MAX_READ_BURST_LENGTH    ( MAX_READ_BURST_LENGTH ),
+    .C_M_AXI_ID_WIDTH         ( C_M_AXI_ID_WIDTH ),
+    .C_M_AXI_ADDR_WIDTH       ( C_M_AXI_ADDR_WIDTH ),
+    .C_TARGET_ADDR            ( C_TARGET_ADDR ),
+    .C_M_AXI_DATA_WIDTH       ( C_M_AXI_DATA_WIDTH ),
+    .C_M_AXI_ARUSER_WIDTH     ( C_M_AXI_ARUSER_WIDTH ),
+    .C_M_AXI_RUSER_WIDTH      ( C_M_AXI_RUSER_WIDTH ),
+    .C_USER_VALUE             ( C_USER_VALUE ),
+    .C_PROT_VALUE             ( C_PROT_VALUE ),
+    .C_CACHE_VALUE            ( C_CACHE_VALUE ),
+    .USER_DW                  ( USER_DW ),
+    .USER_AW                  ( USER_AW ),
+    .USER_MAXREQS             ( USER_MAXREQS )
+) bus_read (
+    .ACLK              ( ACLK ),
+    .ARESET            ( ARESET ),
+    .ACLK_EN           ( ACLK_EN ),
+    .ARID              ( ARID ),
+    .ARADDR            ( ARADDR ),
+    .ARLEN             ( ARLEN ),
+    .ARSIZE            ( ARSIZE ),
+    .ARBURST           ( ARBURST ),
+    .ARLOCK            ( ARLOCK ),
+    .ARCACHE           ( ARCACHE ),
+    .ARPROT            ( ARPROT ),
+    .ARQOS             ( ARQOS ),
+    .ARREGION          ( ARREGION ),
+    .ARUSER            ( ARUSER ),
+    .ARVALID           ( ARVALID ),
+    .ARREADY           ( ARREADY ),
+    .RID               ( RID ),
+    .RDATA             ( RDATA ),
+    .RRESP             ( RRESP ),
+    .RLAST             ( RLAST ),
+    .RUSER             ( RUSER ),
+    .RVALID            ( RVALID ),
+    .RREADY            ( RREADY ),
+    .rreq_valid        ( I_ARVALID ),
+    .rreq_ack     ( I_ARREADY ),
+    .rreq_addr         ( I_ARADDR ),
+    .rreq_length       ( I_ARLEN ),
+    .rreq_cache        ( I_ARCACHE ),
+    .rreq_prot         ( I_ARPROT ),
+    .rreq_qos          ( I_ARQOS ),
+    .rreq_region       ( I_ARREGION ),
+    .rreq_user         ( I_ARUSER ),
+    .rdata_valid       ( I_RVALID ),
+    .rdata_ack         ( I_RREADY ),
+    .rdata_data        ( I_RDATA ),
+    .rrsp              ( I_RRESP )
+);
+endmodule
+`default_nettype wire
+
+module mmult_out_mem_m_axi_reg_slice
+#(parameter
+    N = 8   // data width
+) (
+    // system signals
+    input  wire         sclk,
+    input  wire         reset,
+    // slave side
+    input  wire [N-1:0] s_data,
+    input  wire         s_valid,
+    output wire         s_ready,
+    // master side
+    output wire [N-1:0] m_data,
+    output wire         m_valid,
+    input  wire         m_ready
+);
+//------------------------Parameter----------------------
+// state
+localparam [1:0]
+    ZERO = 2'b10,
+    ONE  = 2'b11,
+    TWO  = 2'b01;
+//------------------------Local signal-------------------
+reg  [N-1:0] data_p1;
+reg  [N-1:0] data_p2;
+wire         load_p1;
+wire         load_p2;
+wire         load_p1_from_p2;
+reg          s_ready_t;
+reg  [1:0]   state;
+reg  [1:0]   next;
+//------------------------Body---------------------------
+assign s_ready = s_ready_t;
+assign m_data  = data_p1;
+assign m_valid = state[0];
+
+assign load_p1 = (state == ZERO && s_valid) ||
+                 (state == ONE && s_valid && m_ready) ||
+                 (state == TWO && m_ready);
+assign load_p2 = s_valid & s_ready;
+assign load_p1_from_p2 = (state == TWO);
+
+// data_p1
+always @(posedge sclk) begin
+    if (load_p1) begin
+        if (load_p1_from_p2)
+            data_p1 <= data_p2;
+        else
+            data_p1 <= s_data;
+    end
+end
+
+// data_p2
+always @(posedge sclk) begin
+    if (load_p2) data_p2 <= s_data;
+end
+
+// s_ready_t
+always @(posedge sclk) begin
+    if (reset)
+        s_ready_t <= 1'b0;
+    else if (state == ZERO)
+        s_ready_t <= 1'b1;
+    else if (state == ONE && next == TWO)
+        s_ready_t <= 1'b0;
+    else if (state == TWO && next == ONE)
+        s_ready_t <= 1'b1;
+end
+
+// state
+always @(posedge sclk) begin
+    if (reset)
+        state <= ZERO;
+    else
+        state <= next;
+end
+
+// next
+always @(*) begin
+    case (state)
+        ZERO:
+            if (s_valid & s_ready)
+                next = ONE;
+            else
+                next = ZERO;
+        ONE:
+            if (~s_valid & m_ready)
+                next = ZERO;
+            else if (s_valid & ~m_ready)
+                next = TWO;
+            else
+                next = ONE;
+        TWO:
+            if (m_ready)
+                next = ONE;
+            else
+                next = TWO;
+        default:
+            next = ZERO;
+    endcase
+end
+
+endmodule
+
+module mmult_out_mem_m_axi_fifo
+#(parameter
+    DATA_BITS  = 8,
+    DEPTH      = 16,
+    DEPTH_BITS = 4
+)(
+    input  wire                 sclk,
+    input  wire                 reset,
+    input  wire                 sclk_en,
+    output reg                  empty_n,
+    output reg                  full_n,
+    input  wire                 rdreq,
+    input  wire                 wrreq,
+    output reg  [DATA_BITS-1:0] q,
+    input  wire [DATA_BITS-1:0] data
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+wire                  push;
+wire                  pop;
+wire                  full_cond;
+reg                   data_vld;
+reg  [DEPTH_BITS-1:0] pout;
+reg  [DATA_BITS-1:0]  mem[0:DEPTH-1];
+//------------------------Body---------------------------
+assign push = full_n & wrreq;
+assign pop  = data_vld & (~(empty_n & ~rdreq));
+if (DEPTH >= 2) begin
+assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
+end else begin
+assign full_cond = push && ~pop;
+end
+
+// q
+always @(posedge sclk)
+begin
+    if (reset)
+        q <= 0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            q <= mem[pout];
+    end
+end
+
+// empty_n
+always @(posedge sclk)
+begin
+    if (reset)
+        empty_n <= 1'b0;
+    else if (sclk_en) begin
+        if (~(empty_n & ~rdreq))
+            empty_n <= data_vld;
+    end
+end
+
+// data_vld
+always @(posedge sclk)
+begin
+    if (reset)
+        data_vld <= 1'b0;
+    else if (sclk_en) begin
+        if (push)
+            data_vld <= 1'b1;
+        else if (~push && pop && pout == 1'b0)
+            data_vld <= 1'b0;
+    end
+end
+
+// full_n
+always @(posedge sclk)
+begin
+    if (reset)
+        full_n <= 1'b1;
+    else if (sclk_en) begin
+        if (pop)
+            full_n <= 1'b1;
+        else if (full_cond)
+            full_n <= 1'b0;
+    end
+end
+
+// pout
+always @(posedge sclk)
+begin
+    if (reset)
+        pout <= 1'b0;
+    else if (sclk_en) begin
+        if (push & ~pop & data_vld)
+            pout <= pout + 1'b1;
+        else if (~push && pop && pout != 1'b0)
+            pout <= pout - 1'b1;
+    end
+end
+
+integer i;
+always @(posedge sclk)
+begin
+    if (sclk_en) begin
+        if (push) begin
+            for (i = 0; i < DEPTH - 1; i = i + 1) begin
+                mem[i+1] <= mem[i];
+            end
+            mem[0] <= data;
+        end
+    end
+end
+endmodule
+
+module mmult_out_mem_m_axi_buffer
+#(parameter
+    MEM_STYLE  = "block",
+    DATA_WIDTH = 32,
+    ADDR_WIDTH = 5,
+    DEPTH      = 32
+) (
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  sclk_en,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+
+    // read
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+
+//------------------------Local signal-------------------
+(* ram_style = MEM_STYLE *)
+reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+reg  [DATA_WIDTH-1:0] q_buf = 1'b0;
+reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
+reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
+wire [ADDR_WIDTH-1:0] wnext;
+wire [ADDR_WIDTH-1:0] rnext;
+wire                  push;
+wire                  pop;
+reg  [ADDR_WIDTH-1:0] usedw = 1'b0;
+reg                   full_n = 1'b1;
+reg                   empty_n = 1'b0;
+reg  [DATA_WIDTH-1:0] q_tmp = 1'b0;
+reg                   show_ahead = 1'b0;
+reg  [DATA_WIDTH-1:0] dout_buf = 1'b0;
+reg                   dout_valid = 1'b0;
+
+
+//------------------------Instantiation------------------
+
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+assign if_full_n  = full_n;
+assign if_empty_n = dout_valid;
+assign if_dout    = dout_buf;
+assign push       = full_n & if_write_ce & if_write;
+assign pop        = empty_n & if_read_ce & (~dout_valid | if_read);
+assign wnext      = !push                ? waddr :
+                    (waddr == DEPTH - 1) ? 1'b0  :
+                    waddr + 1'b1;
+assign rnext      = !pop                 ? raddr :
+                    (raddr == DEPTH - 1) ? 1'b0  :
+                    raddr + 1'b1;
+
+// waddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        waddr <= 1'b0;
+    else if (sclk_en)
+        waddr <= wnext;
+end
+
+// raddr
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        raddr <= 1'b0;
+    else if (sclk_en)
+        raddr <= rnext;
+end
+
+// usedw
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        usedw <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            usedw <= usedw + 1'b1;
+        else if (~push & pop)
+            usedw <= usedw - 1'b1;
+end
+
+// full_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        full_n <= 1'b1;
+    else if (sclk_en)
+        if (push & ~pop)
+            full_n <= (usedw != DEPTH - 1);
+        else if (~push & pop)
+            full_n <= 1'b1;
+end
+
+// empty_n
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        empty_n <= 1'b0;
+    else if (sclk_en)
+        if (push & ~pop)
+            empty_n <= 1'b1;
+        else if (~push & pop)
+            empty_n <= (usedw != 1'b1);
+end
+
+// mem
+always @(posedge clk) begin
+    if (push)
+        mem[waddr] <= if_din;
+end
+
+// q_buf
+always @(posedge clk) begin
+    q_buf <= mem[rnext];
+end
+
+// q_tmp
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        q_tmp <= 1'b0;
+    else if (sclk_en)
+        if (push)
+            q_tmp <= if_din;
+end
+
+// show_ahead
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        show_ahead <= 1'b0;
+    else if (sclk_en)
+        if (push && usedw == pop)
+            show_ahead <= 1'b1;
+        else
+            show_ahead <= 1'b0;
+end
+
+// dout_buf
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_buf <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_buf <= show_ahead? q_tmp : q_buf;
+end
+
+// dout_valid
+always @(posedge clk) begin
+    if (reset == 1'b1)
+        dout_valid <= 1'b0;
+    else if (sclk_en)
+        if (pop)
+            dout_valid <= 1'b1;
+        else if (if_read_ce & if_read)
+            dout_valid <= 1'b0;
+end
+
+endmodule
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_decoder
+#(parameter
+    DIN_WIDTH       = 3
+)(
+    input  wire [DIN_WIDTH-1:0]         din,
+    output reg  [2**DIN_WIDTH-1:0]      dout
+);
+    integer i;
+    always @(din) begin
+        dout = {2**DIN_WIDTH{1'b0}};
+        for (i=0; i < din; i = i + 1)
+            dout[i] = 1'b1;
+    end
+endmodule
+
+
+module mmult_out_mem_m_axi_throttl
+#(parameter
+    USED_FIX       = 0,
+    FIX_VALUE      = 4,
+    ADDR_WIDTH     = 32,
+    DATA_WIDTH     = 32,
+    DEPTH          = 16,
+    USER_MAXREQS   = 16,
+    CONSERVATIVE   = 0, 
+    AVERAGE_MODE   = 0 
+)(
+    input  wire                      clk,
+    input  wire                      reset,
+    input  wire                      ce,
+    input  wire [ADDR_WIDTH-1:0]     in_addr,
+    input  wire [7:0]                in_len,
+    input  wire                      in_req_valid,
+    output wire                      out_req_ready,
+    output wire [ADDR_WIDTH-1:0]     out_addr,
+    output wire [7:0]                out_len,
+    output wire                      out_req_valid,
+    input  wire                      in_req_ready,
+    input  wire [DATA_WIDTH-1:0]     in_data,
+    input  wire [DATA_WIDTH/8-1:0]   in_strb,
+    input  wire                      in_last,
+    input  wire                      in_data_valid,
+    output wire                      out_data_ready,
+    output wire [DATA_WIDTH-1:0]     out_data,
+    output wire [DATA_WIDTH/8-1:0]   out_strb,
+    output wire                      out_last,
+    output wire                      out_data_valid,
+    input  wire                      in_data_ready
+);
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+generate
+if (CONSERVATIVE == 0) begin
+localparam threshold = (USED_FIX)? FIX_VALUE-1 : 0;
+
+wire                req_en;
+wire                handshake;
+wire  [7:0]         load_init;
+reg   [7:0]         throttl_cnt;
+
+// AW Channel
+assign out_addr       = in_addr;
+assign out_len        = in_len;
+
+// W Channel
+assign out_data       = in_data;
+assign out_strb       = in_strb;
+assign out_last       = in_last;
+assign out_data_valid = in_data_valid;
+assign out_data_ready = in_data_ready;
+
+if (USED_FIX) begin
+    assign load_init = FIX_VALUE-1;
+    assign handshake = 1'b1;
+end else if (AVERAGE_MODE) begin
+    assign load_init = in_len;
+    assign handshake = 1'b1;
+end else begin
+    assign load_init = in_len;
+    assign handshake = out_data_valid & in_data_ready;
+end
+
+assign out_req_valid = in_req_valid & req_en;
+assign out_req_ready = in_req_ready & req_en;
+assign req_en = (throttl_cnt == 0);
+
+always @(posedge clk)
+begin
+    if (reset)
+        throttl_cnt <= 0;
+    else if (ce) begin
+        if (in_len > threshold && throttl_cnt == 0 && in_req_valid && in_req_ready)
+            throttl_cnt <= load_init; //load
+        else if (throttl_cnt > 0 && handshake)
+            throttl_cnt <= throttl_cnt - 1'b1;
+    end
+end
+
+end // AGGRESSIVE end
+else begin
+localparam CNT_WIDTH = (DEPTH < 4)? 2 : log2(DEPTH);
+
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_in;
+wire  [DATA_WIDTH + DATA_WIDTH/8 : 0]   data_out;
+wire  [ADDR_WIDTH + 7 : 0]              req_in;
+wire  [ADDR_WIDTH + 7 : 0]              req_out;
+wire                                    req_en;
+wire                                    data_en;
+wire                                    fifo_valid;
+wire                                    read_fifo;
+wire                                    req_fifo_valid;
+wire                                    read_req;
+wire                                    data_push;
+wire                                    data_pop;
+reg                                     flying_req;
+reg   [CNT_WIDTH-1 : 0]                 last_cnt;
+
+//AW Channel
+assign req_in   = {in_len, in_addr};
+assign out_addr = req_out[ADDR_WIDTH-1 : 0];
+assign out_len  = req_out[ADDR_WIDTH+7 : ADDR_WIDTH];
+assign out_req_valid = req_fifo_valid & req_en;
+
+assign req_en        = ~flying_req & data_en || (flying_req & (out_last & data_pop) & (last_cnt[CNT_WIDTH-1:1] != 0));
+assign read_req      = in_req_ready & req_en;
+
+always @(posedge clk)
+begin
+    if (reset)
+        flying_req <= 0;
+    else if (ce) begin
+        if (out_req_valid & in_req_ready)
+            flying_req <= 1;
+        else if (out_last & data_pop)
+            flying_req <= 0;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(ADDR_WIDTH + 8),
+    .DEPTH(USER_MAXREQS),
+    .DEPTH_BITS(log2(USER_MAXREQS))
+) req_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(req_fifo_valid),
+    .full_n(out_req_ready),
+    .rdreq(read_req),
+    .wrreq(in_req_valid),
+    .q(req_out),
+    .data(req_in));
+
+//W Channel
+assign data_in  = {in_last, in_strb, in_data};
+assign out_data = data_out[DATA_WIDTH-1 : 0];
+assign out_strb = data_out[DATA_WIDTH+DATA_WIDTH/8-1 : DATA_WIDTH];
+assign out_last = data_out[DATA_WIDTH+DATA_WIDTH/8];
+assign out_data_valid = fifo_valid & data_en & flying_req;
+
+assign data_en   = last_cnt != 0;
+assign data_push = in_data_valid & out_data_ready;
+assign data_pop  = fifo_valid & read_fifo;
+assign read_fifo = in_data_ready & data_en & flying_req;
+
+always @(posedge clk)
+begin
+    if (reset)
+        last_cnt <= 0;
+    else if (ce) begin
+        if ((in_last & data_push) && ~(out_last & data_pop))
+            last_cnt <= last_cnt + 1;
+        else if (~(in_last & data_push) && (out_last & data_pop))
+            last_cnt <= last_cnt - 1;
+    end
+end
+
+mmult_out_mem_m_axi_fifo #(
+    .DATA_BITS(DATA_WIDTH + DATA_WIDTH/8 + 1),
+    .DEPTH(DEPTH),
+    .DEPTH_BITS(log2(DEPTH))
+) data_fifo (
+    .sclk(clk),
+    .reset(reset),
+    .sclk_en(ce),
+    .empty_n(fifo_valid),
+    .full_n(out_data_ready),
+    .rdreq(read_fifo),
+    .wrreq(in_data_valid),
+    .q(data_out),
+    .data(data_in));
+
+end
+endgenerate
+
+endmodule
+
+`timescale 1ns/1ps
+
+module mmult_out_mem_m_axi_read
+#(parameter
+    NUM_READ_OUTSTANDING      = 2,
+    MAX_READ_BURST_LENGTH     = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_ARUSER_WIDTH      = 1,
+    C_M_AXI_RUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // read address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        ARID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      ARADDR,
+    output wire [7:0]                   ARLEN,
+    output wire [2:0]                   ARSIZE,
+    output wire [1:0]                   ARBURST,
+    output wire [1:0]                   ARLOCK,
+    output wire [3:0]                   ARCACHE,
+    output wire [2:0]                   ARPROT,
+    output wire [3:0]                   ARQOS,
+    output wire [3:0]                   ARREGION,
+    output wire [C_M_AXI_ARUSER_WIDTH-1:0]    ARUSER,
+    output wire                         ARVALID,
+    input  wire                         ARREADY,
+    // read data channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        RID,
+    input  wire [C_M_AXI_DATA_WIDTH-1:0]      RDATA,
+    input  wire [1:0]                   RRESP,
+    input  wire                         RLAST,
+    input  wire [C_M_AXI_RUSER_WIDTH-1:0]     RUSER,
+    input  wire                         RVALID,
+    output wire                         RREADY,
+    // read
+    input  wire                         rreq_valid,
+    output wire                         rreq_ack,
+    input  wire [USER_AW-1:0]           rreq_addr,
+    input  wire [31:0]                  rreq_length,
+    input  wire [3:0]                   rreq_cache,
+    input  wire [2:0]                   rreq_prot,
+    input  wire [3:0]                   rreq_qos,
+    input  wire [3:0]                   rreq_region,
+    input  wire [C_M_AXI_ARUSER_WIDTH-1:0]    rreq_user,
+    output wire [USER_DW-1:0]           rdata_data,
+    output wire [1:0]                   rrsp,
+    output wire                         rdata_valid,
+    input  wire                         rdata_ack
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_READ_WIDTH = log2(MAX_READ_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AR channel
+    wire [USER_AW + 31:0]                   rreq_data;
+    wire [USER_AW + 31:0]                   rs2f_rreq_data;
+    wire                                      rs2f_rreq_valid;
+    wire                                      rs2f_rreq_ack;
+    wire [USER_AW + 31:0]                   fifo_rreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              arlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               araddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]               sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]              sect_cnt;
+    wire [1:0]                              ar2r_ardata;
+    wire                                    fifo_rctl_r;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_rreq_valid;
+    reg                                     fifo_rreq_valid_buf;
+    wire                                    fifo_rreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     ARVALID_Dummy;
+    wire                                    ready_for_sect;
+    wire                                    next_rreq;
+    wire                                    ready_for_rreq;
+    reg                                     rreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // R channel
+    wire    [BUS_DATA_WIDTH + 2:0]          fifo_rresp_rdata;
+    wire    [BUS_DATA_WIDTH + 2:0]          data_pack;
+    wire    [BUS_DATA_WIDTH - 1:0]          tmp_data;
+    wire    [USER_DW + 1:0]                 rs_rrsp_rdata;
+    wire    [USER_DW + 1:0]                 rdata_data_pack;
+    reg     [7:0]                           len_cnt;
+    wire    [1:0]                           ar2r_rdata;
+    wire    [1:0]                           tmp_resp;
+    reg     [1:0]                           resp_buf;
+    wire                                    tmp_last;
+    wire                                    tmp_last_2;
+    wire                                    need_rlast;
+    wire                                    fifo_rctl_ready;
+    wire                                    beat_valid;
+    wire                                    next_beat;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    rdata_ack_t;
+    reg                                     rdata_valid_t;
+
+//------------------------AR channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rreq_data),
+        .s_valid(rreq_valid),
+        .s_ready(rreq_ack),
+        .m_data(rs2f_rreq_data),
+        .m_valid(rs2f_rreq_valid),
+        .m_ready(rs2f_rreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_rreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_rreq_ack),
+        .wrreq(rs2f_rreq_valid),
+        .data(rs2f_rreq_data),
+        .empty_n(fifo_rreq_valid),
+        .rdreq(fifo_rreq_read),
+        .q(fifo_rreq_data));
+
+//------------------------Body---------------------------
+    assign rreq_data   = {rreq_length, rreq_addr};
+    assign tmp_addr    = fifo_rreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_rreq_data[USER_AW + 31:USER_AW];
+    assign end_addr    = start_addr + align_len;
+
+    assign zero_len_event = fifo_rreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_rreq_valid? tmp_len[31] : 0;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_rreq_valid && ready_for_rreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_rreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                fifo_rreq_valid_buf <= fifo_rreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if((fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_rreq      = (fifo_rreq_valid || fifo_rreq_valid_buf) && ready_for_rreq;
+    assign ready_for_rreq = ~(rreq_handling && ~(last_sect && next_sect));
+    assign fifo_rreq_read = next_rreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            rreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_rreq_valid_buf && ~rreq_handling && ~invalid_len_event)
+                rreq_handling <= 1'b1;
+            else if ((~fifo_rreq_valid_buf || invalid_len_event) && last_sect && next_sect)
+                rreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_rreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = rreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign ARID     = 0;
+    assign ARSIZE   = BUS_ADDR_ALIGN;
+    assign ARBURST  = 2'b01;
+    assign ARLOCK   = 2'b00;
+    assign ARCACHE  = C_CACHE_VALUE;
+    assign ARPROT   = C_PROT_VALUE;
+    assign ARUSER   = C_USER_VALUE;
+    assign ARQOS    = rreq_qos;
+    assign ARREGION = rreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) begin : must_one_burst
+        assign ARADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign ARLEN   = sect_len_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign ready_for_sect = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_sect && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r  = next_sect;
+        assign ar2r_ardata  = {last_sect, 1'b0};
+
+        assign fifo_burst_w = next_sect;
+        assign araddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign arlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                 araddr_buf;
+        reg  [7:0]                                      arlen_buf;
+        reg  [11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN:0]   loop_cnt;
+        reg                                             sect_handling;
+        wire                                            last_loop;
+        wire                                            next_loop;
+        wire                                            ready_for_loop;
+
+        assign ARADDR  = araddr_buf;
+        assign ARLEN   = arlen_buf;
+        assign ARVALID = ARVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_READ_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(ARVALID_Dummy && ~ARREADY) && fifo_burst_ready && fifo_rctl_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (rreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~rreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign araddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (araddr_buf + ((arlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                araddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    araddr_buf <= {araddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign arlen_tmp  = (last_loop)? sect_len_buf[NUM_READ_WIDTH - 1:0] : { NUM_READ_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                arlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    arlen_buf <= arlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                ARVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    ARVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    ARVALID_Dummy <= 1'b1;
+                else if (~next_loop && ARREADY)
+                    ARVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_rctl_r = next_loop;
+        assign ar2r_ardata = {last_loop, 1'b0};
+
+        assign fifo_burst_w = next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AR channel end-----------------
+
+//------------------------R channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(BUS_DATA_WIDTH + 3),
+        .DEPTH(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+    ) buff_rdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(RREADY),
+        .if_write_ce(1'b1),
+        .if_write(RVALID),
+        .if_din(fifo_rresp_rdata),
+        .if_empty_n(beat_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_beat),
+        .if_dout(data_pack));
+
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_DW + 2)
+    ) rs_rdata (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(rs_rrsp_rdata),
+        .s_valid(rdata_valid_t),
+        .s_ready(rdata_ack_t),
+        .m_data(rdata_data_pack),
+        .m_valid(rdata_valid),
+        .m_ready(rdata_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_READ_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_READ_OUTSTANDING-1))
+    ) fifo_rctl (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_rlast),
+        .full_n(fifo_rctl_ready),
+        .rdreq(tmp_last_2),
+        .wrreq(fifo_rctl_r),
+        .q(ar2r_rdata),
+        .data(ar2r_ardata));
+
+    assign fifo_rresp_rdata = {RLAST, RRESP, RDATA};
+    assign tmp_data         = data_pack[BUS_DATA_WIDTH - 1:0];
+    assign tmp_resp         = data_pack[BUS_DATA_WIDTH + 1:BUS_DATA_WIDTH];
+    assign tmp_last         = data_pack[BUS_DATA_WIDTH + 2] && beat_valid;
+    assign tmp_last_2       = tmp_last && next_beat;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        wire                                ready_for_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = beat_valid && ready_for_data;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_beat)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    rdata_valid_t <= 1'b1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 1'b0;
+            end
+        end
+    end
+    else if (USER_DATA_WIDTH < BUS_DATA_WIDTH) begin : bus_wide_gen
+        localparam
+        TOTAL_SPLIT     = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        wire [2*SPLIT_ALIGN + 7:0]      tmp_burst_info;
+        wire [2*SPLIT_ALIGN + 7:0]      burst_pack;
+        reg  [BUS_DATA_WIDTH - 1:0]     data_buf;
+        wire [SPLIT_ALIGN - 1:0]        split_cnt;
+        reg  [SPLIT_ALIGN - 1:0]        split_cnt_buf;
+        wire [SPLIT_ALIGN - 1:0]        head_split;
+        wire [SPLIT_ALIGN - 1:0]        tail_split;
+        wire [7:0]                      arlen_tmp_t;
+        wire [7:0]                      burst_len;
+        wire                            first_beat;
+        wire                            last_beat;
+        wire                            first_split;
+        wire                            next_split;
+        wire                            last_split;
+        wire                            ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(2*SPLIT_ALIGN + 8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign arlen_tmp_t    = arlen_tmp;
+        assign tmp_burst_info = {araddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], arlen_tmp_t};
+        assign head_split     = burst_pack[2*SPLIT_ALIGN + 7:8 + SPLIT_ALIGN];
+        assign tail_split     = burst_pack[SPLIT_ALIGN + 7:8];
+        assign burst_len      = burst_pack[7:0];
+
+        assign next_beat        = last_split;
+        assign next_burst       = last_beat && last_split;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign first_beat = (len_cnt == 0) && burst_valid && beat_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid && beat_valid;
+
+        assign first_split = (~first_beat)? (split_cnt == 0 && beat_valid && ready_for_data) : ((split_cnt == head_split) && ready_for_data);
+        assign last_split  = (~last_beat)? (split_cnt == (TOTAL_SPLIT - 1) && ready_for_data) : ((split_cnt == tail_split) && ready_for_data);
+        assign next_split  = (~first_beat)? ((split_cnt != 0) && ready_for_data) : ((split_cnt != head_split) && ready_for_data);
+
+        assign split_cnt = (first_beat && (split_cnt_buf == 0))? head_split : split_cnt_buf;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt_buf <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt_buf <= 0;
+                else if (first_split || next_split)
+                    split_cnt_buf <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_beat && last_split)
+                    len_cnt <= 0;
+                else if (last_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (first_split && first_beat)
+                    data_buf <= tmp_data >> (head_split * USER_DATA_WIDTH);
+                else if (first_split)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> USER_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (first_split)
+                    rdata_valid_t <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+
+    end
+    else begin: bus_narrow_gen
+        localparam
+            TOTAL_PADS      = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [USER_DATA_WIDTH - 1:0]        data_buf;
+        wire [TOTAL_PADS - 1:0]             pad_oh;
+        reg  [TOTAL_PADS - 1:0]             pad_oh_reg;
+        wire                                ready_for_data;
+        wire                                next_pad;
+        reg                                 first_pad;
+        wire                                last_pad;
+        wire                                next_data;
+
+        assign rs_rrsp_rdata = {resp_buf, data_buf[USER_DW - 1:0]};
+        assign rrsp          = rdata_data_pack[USER_DW + 1:USER_DW];
+        assign rdata_data    = rdata_data_pack[USER_DW - 1:0];
+
+        assign fifo_burst_ready = 1'b1;
+        assign next_beat        = next_pad;
+        assign ready_for_data   = ~(rdata_valid_t && ~rdata_ack_t);
+
+        assign next_pad  = beat_valid && ready_for_data;
+        assign last_pad  = pad_oh[TOTAL_PADS - 1];
+        assign next_data = last_pad && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (beat_valid == 0)?  0 :
+                        (first_pad)?        1 :
+                                            pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*BUS_DATA_WIDTH - 1:(i-1)*BUS_DATA_WIDTH] <= tmp_data;
+                end
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                resp_buf <= 2'b00;
+            else if (ACLK_EN) begin
+                if (next_beat && (resp_buf[0] ==1'b0))
+                    resp_buf <= tmp_resp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                rdata_valid_t <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    rdata_valid_t <= 1;
+                else if (ready_for_data)
+                    rdata_valid_t <= 0;
+            end
+        end
+    end
+    endgenerate
+
+//------------------------Body---------------------------
+//------------------------R channel end------------------
+endmodule
+
+module mmult_out_mem_m_axi_write
+#(parameter
+    NUM_WRITE_OUTSTANDING     = 2,
+    MAX_WRITE_BURST_LENGTH    = 16,
+    C_M_AXI_ID_WIDTH          = 1,
+    C_M_AXI_ADDR_WIDTH        = 32,
+    C_TARGET_ADDR             = 32'h00000000,
+    C_M_AXI_DATA_WIDTH        = 32,
+    C_M_AXI_AWUSER_WIDTH      = 1,
+    C_M_AXI_WUSER_WIDTH       = 1,
+    C_M_AXI_BUSER_WIDTH       = 1,
+    C_USER_VALUE              = 1'b0,
+    C_PROT_VALUE              = 3'b000,
+    C_CACHE_VALUE             = 4'b0011,
+    USER_DW                   = 16,
+    USER_AW                   = 32,
+    USER_MAXREQS              = 16
+)(
+    // system signal
+    input  wire                         ACLK,
+    input  wire                         ARESET,
+    input  wire                         ACLK_EN,
+    // write address channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        AWID,
+    output wire [C_M_AXI_ADDR_WIDTH-1:0]      AWADDR,
+    output wire [7:0]                   AWLEN,
+    output wire [2:0]                   AWSIZE,
+    output wire [1:0]                   AWBURST,
+    output wire [1:0]                   AWLOCK,
+    output wire [3:0]                   AWCACHE,
+    output wire [2:0]                   AWPROT,
+    output wire [3:0]                   AWQOS,
+    output wire [3:0]                   AWREGION,
+    output wire [C_M_AXI_AWUSER_WIDTH-1:0]    AWUSER,
+    output wire                         AWVALID,
+    input  wire                         AWREADY,
+    // write data channel
+    output wire [C_M_AXI_ID_WIDTH-1:0]        WID,
+    output wire [C_M_AXI_DATA_WIDTH-1:0]      WDATA,
+    output wire [C_M_AXI_DATA_WIDTH/8-1:0]    WSTRB,
+    output wire                         WLAST,
+    output wire [C_M_AXI_WUSER_WIDTH-1:0]     WUSER,
+    output wire                         WVALID,
+    input  wire                         WREADY,
+    // write response channel
+    input  wire [C_M_AXI_ID_WIDTH-1:0]        BID,
+    input  wire [1:0]                   BRESP,
+    input  wire [C_M_AXI_BUSER_WIDTH-1:0]     BUSER,
+    input  wire                         BVALID,
+    output wire                         BREADY,
+    // write request
+    input  wire                         wreq_valid,
+    output wire                         wreq_ack,
+    input  wire [USER_AW-1:0]           wreq_addr,
+    input  wire [31:0]                  wreq_length,
+    input  wire [3:0]                   wreq_cache,
+    input  wire [2:0]                   wreq_prot,
+    input  wire [3:0]                   wreq_qos,
+    input  wire [3:0]                   wreq_region,
+    input  wire [C_M_AXI_AWUSER_WIDTH-1:0]    wreq_user,
+    input  wire                         wdata_valid,
+    output wire                         wdata_ack,
+    input  wire [USER_DW/8-1:0]         wdata_strb,
+    input  wire [C_M_AXI_WUSER_WIDTH-1:0]     wdata_user,
+    input  wire [USER_DW-1:0]           wdata_data,
+    output wire                         wrsp_valid,
+    input  wire                         wrsp_ack,
+    output wire [1:0]                   wrsp
+);
+
+//------------------------Parameter----------------------
+localparam
+    USER_DATA_WIDTH = calc_data_width(USER_DW),
+    USER_DATA_BYTES = USER_DATA_WIDTH / 8,
+    USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
+    BUS_DATA_WIDTH  = C_M_AXI_DATA_WIDTH,
+    BUS_DATA_BYTES  = BUS_DATA_WIDTH / 8,
+    BUS_ADDR_ALIGN  = log2(BUS_DATA_BYTES),
+    NUM_WRITE_WIDTH = log2(MAX_WRITE_BURST_LENGTH),
+    TARGET_ADDR     = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN),
+    BOUNDARY_BEATS  = {12-BUS_ADDR_ALIGN{1'b1}};
+
+//------------------------Task and function--------------
+function integer calc_data_width;
+    input integer x;
+    integer y;
+begin
+    y = 8;
+    while (y < x) y = y * 2;
+    calc_data_width = y;
+end
+endfunction
+
+function integer log2;
+    input integer x;
+    integer n, m;
+begin
+    n = 0;
+    m = 1;
+    while (m < x) begin
+        n = n + 1;
+        m = m * 2;
+    end
+    log2 = n;
+end
+endfunction
+
+//------------------------Local signal-------------------
+    // AW channel
+    wire [USER_AW + 31:0]                   wreq_data;
+    wire [USER_AW + 31:0]                   rs2f_wreq_data;
+    wire                                      rs2f_wreq_valid;
+    wire                                      rs2f_wreq_ack;
+    wire [USER_AW + 31:0]                   fifo_wreq_data;
+    wire [USER_AW - 1:0]                    tmp_addr;
+    wire [31:0]                             tmp_len;
+    reg  [31:0]                             align_len;
+    wire [7:0]                              awlen_tmp;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         awaddr_tmp;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         start_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         end_addr_buf;
+    wire [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr;
+    reg  [C_M_AXI_ADDR_WIDTH - 1:0]         sect_addr_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             sect_end;
+    reg  [BUS_ADDR_ALIGN - 1:0]             sect_end_buf;
+    wire [BUS_ADDR_ALIGN - 1:0]             burst_end;
+    wire [11 - BUS_ADDR_ALIGN:0]            start_to_4k;
+    wire [11 - BUS_ADDR_ALIGN:0]            sect_len;
+    reg  [11 - BUS_ADDR_ALIGN:0]            sect_len_buf;
+    reg  [11 - BUS_ADDR_ALIGN:0]            beat_len_buf;
+    wire [1:0]                              aw2b_awdata;
+    reg  [C_M_AXI_ADDR_WIDTH - 13:0]        sect_cnt;
+    wire                                    zero_len_event;
+    wire                                    negative_len_event;
+    reg                                     invalid_len_event;
+    reg                                     invalid_len_event_reg1;
+    reg                                     invalid_len_event_reg2;
+    wire                                    fifo_wreq_valid;
+    reg                                     fifo_wreq_valid_buf;
+    wire                                    fifo_wreq_read;
+    wire                                    fifo_burst_w;
+    wire                                    fifo_resp_w;
+    reg                                     AWVALID_Dummy;
+    reg                                     last_sect_buf;
+    wire                                    ready_for_sect;
+    wire                                    next_wreq;
+    wire                                    ready_for_wreq;
+    reg                                     wreq_handling;
+    wire                                    first_sect;
+    wire                                    last_sect;
+    wire                                    next_sect;
+    // W channel
+    wire    [USER_DW + USER_DW/8 - 1:0]     fifo_wdata_wstrb;
+    wire    [USER_DW + USER_DW/8 - 1:0]     data_pack;
+    wire    [USER_DATA_WIDTH - 1:0]         tmp_data;
+    wire    [USER_DATA_BYTES - 1:0]         tmp_strb;
+    reg     [7:0]                           len_cnt;
+    wire    [7:0]                           burst_len;
+    wire                                    beat_valid;
+    wire                                    next_data;
+    wire                                    burst_valid;
+    wire                                    fifo_burst_ready;
+    wire                                    next_burst;
+    wire                                    data_valid;
+    reg                                     WVALID_Dummy;
+    reg                                     WLAST_Dummy;
+    //B channel
+    wire    [1:0]                           aw2b_bdata;
+    reg     [1:0]                           bresp_tmp;
+    reg                                     next_resp;
+    wire                                    last_resp;
+    wire                                    invalid_event;
+    wire                                    fifo_resp_ready;
+    wire                                    need_wrsp;
+    wire                                    resp_match;
+    wire                                    resp_ready;
+
+//------------------------AW channel begin---------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_reg_slice #(
+        .N(USER_AW + 32)
+    ) rs_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .s_data(wreq_data),
+        .s_valid(wreq_valid),
+        .s_ready(wreq_ack),
+        .m_data(rs2f_wreq_data),
+        .m_valid(rs2f_wreq_valid),
+        .m_ready(rs2f_wreq_ack));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(USER_AW + 32),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_wreq (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .full_n(rs2f_wreq_ack),
+        .wrreq(rs2f_wreq_valid),
+        .data(rs2f_wreq_data),
+        .empty_n(fifo_wreq_valid),
+        .rdreq(fifo_wreq_read),
+        .q(fifo_wreq_data));
+
+//------------------------Body---------------------------
+    assign wreq_data   = {wreq_length, wreq_addr};
+    assign tmp_addr    = fifo_wreq_data[USER_AW - 1:0];
+    assign tmp_len     = fifo_wreq_data[USER_AW + 31:USER_AW];
+
+    assign zero_len_event = fifo_wreq_valid? (tmp_len == 32'b0) : 0;
+    assign negative_len_event = fifo_wreq_valid? tmp_len[31] : 0;
+
+    assign end_addr    = start_addr + align_len;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            align_len   <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq) begin
+                if (zero_len_event || negative_len_event)
+                    align_len   <= 32'b0;
+                else
+                    align_len   <= (tmp_len << USER_ADDR_ALIGN) - 1;
+            end
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr <= 0;
+        else if (ACLK_EN) begin
+            if(fifo_wreq_valid && ready_for_wreq)
+                start_addr <= TARGET_ADDR + (tmp_addr << USER_ADDR_ALIGN);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            fifo_wreq_valid_buf <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                fifo_wreq_valid_buf <= fifo_wreq_valid;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event <= 1'b0;
+        else if (ACLK_EN) begin
+            if(next_wreq)
+                invalid_len_event <= zero_len_event || negative_len_event;
+        end
+    end
+
+    assign next_wreq      = (fifo_wreq_valid || fifo_wreq_valid_buf) && ready_for_wreq;
+    assign ready_for_wreq = ~(wreq_handling && ~(last_sect && next_sect));
+    assign fifo_wreq_read = next_wreq;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            wreq_handling <= 1'b0;
+        else if (ACLK_EN) begin
+            if (fifo_wreq_valid_buf && ~wreq_handling)
+                wreq_handling <= 1'b1;
+            else if (~fifo_wreq_valid_buf && last_sect && next_sect)
+                wreq_handling <= 1'b0;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            start_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                start_addr_buf <= start_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            end_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                end_addr_buf <= end_addr;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            beat_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                beat_len_buf <= (align_len[11:0] + start_addr[BUS_ADDR_ALIGN-1:0]) >> BUS_ADDR_ALIGN;
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_cnt <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq)
+                sect_cnt <= start_addr[C_M_AXI_ADDR_WIDTH-1:12];
+            else if (next_sect)
+                sect_cnt <= sect_cnt + 1;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg1 <= 0;
+        else if (ACLK_EN) begin
+            if (next_wreq) begin
+                 invalid_len_event_reg1 <= invalid_len_event;
+            end
+        end
+    end
+    // end event registers
+
+    assign first_sect = (sect_cnt == start_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign last_sect  = (sect_cnt == end_addr_buf[C_M_AXI_ADDR_WIDTH-1:12]);
+    assign next_sect  = wreq_handling && ready_for_sect;
+
+    assign sect_addr  = (first_sect)? start_addr_buf : {sect_cnt, {12{1'b0}}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_addr_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_addr_buf <= sect_addr;
+        end
+    end
+
+    assign start_to_4k = BOUNDARY_BEATS - start_addr_buf[11:BUS_ADDR_ALIGN];
+    assign sect_len    = ( first_sect &&  last_sect)? beat_len_buf :
+                         ( first_sect && ~last_sect)? start_to_4k:
+                         (~first_sect &&  last_sect)? end_addr_buf[11:BUS_ADDR_ALIGN] :
+                                                      BOUNDARY_BEATS;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_len_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_len_buf <= sect_len;
+        end
+    end
+
+    assign sect_end = (last_sect)? end_addr_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            sect_end_buf <= 0;
+        else if (ACLK_EN) begin
+            if (next_sect)
+                sect_end_buf <= sect_end;
+        end
+    end
+
+    // event registers
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            invalid_len_event_reg2 <= 0;
+        else if (ACLK_EN) begin
+            if(next_sect) begin
+                invalid_len_event_reg2 <= invalid_len_event_reg1;
+            end
+        end
+    end 
+    // end event registers
+
+    assign AWID     = 0;
+    assign AWSIZE   = BUS_ADDR_ALIGN;
+    assign AWBURST  = 2'b01;
+    assign AWLOCK   = 2'b00;
+    assign AWCACHE  = C_CACHE_VALUE;
+    assign AWPROT   = C_PROT_VALUE;
+    assign AWUSER   = C_USER_VALUE;
+    assign AWQOS    = wreq_qos;
+    assign AWREGION = wreq_region;
+
+    generate
+    if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) begin : must_one_burst
+        assign AWADDR  = {sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+        assign AWLEN   = sect_len_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign ready_for_sect = ~(AWVALID_Dummy && ~AWREADY) && fifo_burst_ready && fifo_resp_ready;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_sect && invalid_len_event_reg1)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_sect)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_sect && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_sect;
+        assign aw2b_awdata = {last_sect, invalid_len_event_reg1};
+
+        assign fifo_burst_w = ~invalid_len_event_reg1 & next_sect;
+        assign awaddr_tmp   = sect_addr[C_M_AXI_ADDR_WIDTH - 1:0];
+        assign awlen_tmp    = sect_len;
+        assign burst_end    = sect_end;
+    end
+    else begin : could_multi_bursts
+        reg  [C_M_AXI_ADDR_WIDTH - 1:0]                     awaddr_buf;
+        reg  [7:0]                                          awlen_buf;
+        reg  [11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN : 0]    loop_cnt;
+        reg                                                 sect_handling;
+        wire                                                last_loop;
+        wire                                                next_loop;
+        wire                                                ready_for_loop;
+
+        assign AWADDR  = awaddr_buf;
+        assign AWLEN   = awlen_buf;
+        assign AWVALID = AWVALID_Dummy;
+
+        assign last_loop      = (loop_cnt == sect_len_buf[11 - BUS_ADDR_ALIGN : NUM_WRITE_WIDTH]);
+        assign next_loop      = sect_handling && ready_for_loop;
+        assign ready_for_loop = ~(AWVALID_Dummy && ~AWREADY) && fifo_resp_ready && fifo_burst_ready;
+        assign ready_for_sect = ~(sect_handling && ~(last_loop && next_loop));
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                sect_handling <= 1'b0;
+            else if (ACLK_EN) begin
+                if (wreq_handling && ~sect_handling)
+                    sect_handling <= 1'b1;
+                else if (~wreq_handling && last_loop && next_loop)
+                    sect_handling <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                loop_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect)
+                    loop_cnt <= 0;
+                else if (next_loop)
+                    loop_cnt <= loop_cnt + 1;
+            end
+        end
+
+        assign awaddr_tmp = (loop_cnt == 0)? sect_addr_buf[C_M_AXI_ADDR_WIDTH - 1:0] : (awaddr_buf + ((awlen_buf + 1) << BUS_ADDR_ALIGN));
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awaddr_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awaddr_buf <= {awaddr_tmp[C_M_AXI_ADDR_WIDTH - 1:BUS_ADDR_ALIGN], {BUS_ADDR_ALIGN{1'b0}}};
+            end
+        end
+
+        assign awlen_tmp  = (last_loop)? sect_len_buf[NUM_WRITE_WIDTH - 1:0] : { NUM_WRITE_WIDTH{1'b1} };
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                awlen_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_loop)
+                    awlen_buf <= awlen_tmp;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                AWVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_loop && invalid_len_event_reg2)
+                    AWVALID_Dummy <= 1'b0;
+                else if (next_loop)
+                    AWVALID_Dummy <= 1'b1;
+                else if (~next_loop && AWREADY)
+                    AWVALID_Dummy <= 1'b0;
+            end
+        end
+
+        assign fifo_resp_w = next_loop;
+        assign aw2b_awdata = {(last_loop & last_sect_buf), invalid_len_event_reg2};
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                last_sect_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_sect && last_sect)
+                    last_sect_buf <= 1;
+                else if (next_sect)
+                    last_sect_buf <= 0;
+            end
+        end
+
+        assign fifo_burst_w = ~invalid_len_event_reg2 & next_loop;
+        assign burst_end    = (last_loop)? sect_end_buf[BUS_ADDR_ALIGN - 1:0] : {BUS_ADDR_ALIGN{1'b1}};
+    end
+    endgenerate
+//------------------------AW channel end-----------------
+
+//------------------------W channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_buffer #(
+        .DATA_WIDTH(USER_DW + USER_DW/8),
+        .DEPTH(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH),
+        .ADDR_WIDTH(log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+    ) buff_wdata (
+        .clk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .if_full_n(wdata_ack),
+        .if_write_ce(1'b1),
+        .if_write(wdata_valid),
+        .if_din(fifo_wdata_wstrb),
+        .if_empty_n(data_valid),
+        .if_read_ce(1'b1),
+        .if_read(next_data),
+        .if_dout(data_pack)
+    );
+
+//------------------------Body---------------------------
+    assign fifo_wdata_wstrb = {wdata_strb, wdata_data};
+    assign tmp_data         = data_pack[USER_DW - 1:0];
+    assign tmp_strb         = data_pack[USER_DW + USER_DW/8 - 1:USER_DW];
+
+    assign WID   = 0;
+    assign WUSER = C_USER_VALUE;
+
+    generate
+    if (USER_DATA_WIDTH == BUS_DATA_WIDTH) begin : bus_equal_gen
+        reg  [BUS_DATA_WIDTH - 1:0]         data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]         strb_buf;
+        wire [7:0]                          tmp_burst_info;
+        wire                                ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = burst_valid && data_valid && ready_for_data;
+        assign next_burst       = (len_cnt == burst_len) && next_data;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 1'b0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1'b1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 1'b0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    else if (USER_DATA_WIDTH > BUS_DATA_WIDTH) begin : bus_narrow_gen
+        localparam
+            TOTAL_SPLIT     = USER_DATA_WIDTH / BUS_DATA_WIDTH,
+            SPLIT_ALIGN     = log2(TOTAL_SPLIT);
+
+        reg  [USER_DATA_WIDTH - 1:0]                data_buf;
+        reg  [USER_DATA_BYTES - 1:0]                strb_buf;
+        reg  [SPLIT_ALIGN - 1:0]                    split_cnt;
+        wire [7:0]                                  tmp_burst_info;
+        wire                                        first_split;
+        wire                                        next_split;
+        wire                                        last_split;
+        wire                                        ready_for_data;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_len),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf[BUS_DATA_WIDTH - 1:0];
+        assign WSTRB   = strb_buf[BUS_DATA_BYTES - 1:0];
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign tmp_burst_info = awlen_tmp;
+
+        assign next_data        = first_split;
+        assign next_burst       = (len_cnt == burst_len) && burst_valid && last_split;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_split = (split_cnt == 0) && data_valid && burst_valid && ready_for_data;
+        assign last_split  = (split_cnt == (TOTAL_SPLIT - 1)) && ready_for_data;
+        assign next_split  = (split_cnt != 0) && ready_for_data;
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                split_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (last_split)
+                    split_cnt <= 0;
+                else if (first_split || next_split)
+                    split_cnt <= split_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_data || next_split)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ACLK_EN) begin
+                if (next_data)
+                    data_buf <= tmp_data;
+                else if (next_split)
+                    data_buf <= data_buf >> BUS_DATA_WIDTH;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                strb_buf <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    strb_buf <= tmp_strb;
+                else if (next_split)
+                    strb_buf <= strb_buf >> BUS_DATA_BYTES;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_data)
+                    WVALID_Dummy <= 1;
+                else if (~(first_split || next_split) && ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst && last_split)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+    end
+    else begin: bus_wide_gen
+        localparam
+            TOTAL_PADS      = BUS_DATA_WIDTH / USER_DATA_WIDTH,
+            PAD_ALIGN       = log2(TOTAL_PADS);
+
+        reg  [BUS_DATA_WIDTH - 1:0]                 data_buf;
+        reg  [BUS_DATA_BYTES - 1:0]                 strb_buf;
+        wire [2*PAD_ALIGN + 7:0]                    burst_pack;
+        wire [2*PAD_ALIGN + 7:0]                    tmp_burst_info;
+        wire [PAD_ALIGN - 1:0]                      head_pads;
+        wire [PAD_ALIGN - 1:0]                      tail_pads;
+        wire [TOTAL_PADS - 1:0]                     add_head;
+        wire [TOTAL_PADS - 1:0]                     add_tail;
+        wire [TOTAL_PADS - 1:0]                     pad_oh;
+        reg  [TOTAL_PADS - 1:0]                     pad_oh_reg;
+        wire [TOTAL_PADS - 1:0]                     head_pad_sel;
+        wire [0:TOTAL_PADS - 1]                     tail_pad_sel;
+        wire [7:0]                                  awlen_tmp_t;
+        wire                                        ready_for_data;
+        wire                                        next_pad;
+        reg                                         first_pad;
+        wire                                        last_pad;
+        wire                                        first_beat;
+        wire                                        last_beat;
+        wire                                        next_beat;
+
+        mmult_out_mem_m_axi_fifo #(
+            .DATA_BITS(8 + 2*PAD_ALIGN),
+            .DEPTH(USER_MAXREQS),
+            .DEPTH_BITS(log2(USER_MAXREQS))
+        ) fifo_burst (
+            .sclk(ACLK),
+            .reset(ARESET),
+            .sclk_en(ACLK_EN),
+            .empty_n(burst_valid),
+            .full_n(fifo_burst_ready),
+            .rdreq(next_burst),
+            .wrreq(fifo_burst_w),
+            .q(burst_pack),
+            .data(tmp_burst_info));
+
+        assign WDATA   = data_buf;
+        assign WSTRB   = strb_buf;
+        assign WLAST   = WLAST_Dummy;
+        assign WVALID  = WVALID_Dummy;
+
+        assign awlen_tmp_t = awlen_tmp;
+        assign tmp_burst_info = {awaddr_tmp[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], burst_end[BUS_ADDR_ALIGN - 1:USER_ADDR_ALIGN], awlen_tmp_t};
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) head_pad_decoder (
+            .din(head_pads),
+            .dout(head_pad_sel));
+
+        mmult_out_mem_m_axi_decoder #(
+            .DIN_WIDTH(PAD_ALIGN)
+        ) tail_pad_decoder (
+            .din(tail_pads),
+            .dout(tail_pad_sel));
+
+        assign head_pads = burst_pack[2*PAD_ALIGN + 7:8 + PAD_ALIGN];
+        assign tail_pads = ~burst_pack[PAD_ALIGN + 7:8];
+        assign burst_len = burst_pack[7:0];
+
+        assign next_data        = next_pad;
+        assign next_burst       = last_beat && next_beat;
+        assign ready_for_data   = ~(WVALID_Dummy && ~WREADY);
+
+        assign first_beat = (len_cnt == 0) && burst_valid;
+        assign last_beat  = (len_cnt == burst_len) && burst_valid;
+        assign next_beat  = burst_valid && last_pad && ready_for_data;
+
+        assign next_pad  = burst_valid && data_valid && ready_for_data;
+        assign last_pad  = (last_beat)? pad_oh[TOTAL_PADS - tail_pads - 1] : pad_oh[TOTAL_PADS - 1];
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                first_pad <= 1;
+            else if (ACLK_EN) begin
+                if (next_pad && ~last_pad)
+                    first_pad <= 0;
+                else if (next_pad && last_pad)
+                    first_pad <= 1;
+            end
+        end
+
+        assign pad_oh = (data_valid == 0)?          0 :
+                        (first_pad && first_beat)?  1 << head_pads :
+                        (first_pad)?                1 :
+                                                    pad_oh_reg;
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                pad_oh_reg <= 0;
+            else if (ACLK_EN) begin
+                if (next_pad)
+                    pad_oh_reg <= {pad_oh[TOTAL_PADS - 2:0], 1'b0};
+            end
+        end
+
+        genvar  i;
+        for (i = 1; i <= TOTAL_PADS; i = i + 1) begin : data_gen
+            assign add_head[i-1] = head_pad_sel[i-1] && first_beat;
+            assign add_tail[i-1] = tail_pad_sel[i-1] && last_beat;
+
+            always @(posedge ACLK)
+            begin
+                if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        data_buf[i*USER_DATA_WIDTH - 1:(i-1)*USER_DATA_WIDTH] <= tmp_data;
+                end
+            end
+
+            always @(posedge ACLK)
+            begin
+                if (ARESET)
+                    strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                else if (ACLK_EN) begin
+                    if ((add_head[i-1] || add_tail[i-1]) && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= 0;
+                    else if (pad_oh[i-1] == 1'b1 && ready_for_data)
+                        strb_buf[i*USER_DATA_BYTES - 1:(i-1)*USER_DATA_BYTES] <= tmp_strb;
+                end
+            end
+
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WVALID_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_beat)
+                    WVALID_Dummy <= 1;
+                else if (ready_for_data)
+                    WVALID_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                WLAST_Dummy <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    WLAST_Dummy <= 1;
+                else if (ready_for_data)
+                    WLAST_Dummy <= 0;
+            end
+        end
+
+        always @(posedge ACLK)
+        begin
+            if (ARESET)
+                len_cnt <= 0;
+            else if (ACLK_EN) begin
+                if (next_burst)
+                    len_cnt <= 0;
+                else if (next_beat)
+                    len_cnt <= len_cnt + 1;
+            end
+        end
+
+    end
+    endgenerate
+
+//------------------------W channel end------------------
+
+//------------------------B channel begin----------------
+//------------------------Instantiation------------------
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(NUM_WRITE_OUTSTANDING-1),
+        .DEPTH_BITS(log2(NUM_WRITE_OUTSTANDING-1))
+    ) fifo_resp (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(need_wrsp),
+        .full_n(fifo_resp_ready),
+        .rdreq(next_resp),
+        .wrreq(fifo_resp_w),
+        .q(aw2b_bdata),
+        .data(aw2b_awdata));
+
+    mmult_out_mem_m_axi_fifo #(
+        .DATA_BITS(2),
+        .DEPTH(USER_MAXREQS),
+        .DEPTH_BITS(log2(USER_MAXREQS))
+    ) fifo_resp_to_user (
+        .sclk(ACLK),
+        .reset(ARESET),
+        .sclk_en(ACLK_EN),
+        .empty_n(wrsp_valid),
+        .full_n(resp_ready),
+        .rdreq(wrsp_ack),
+        .wrreq(resp_match),
+        .q(wrsp),
+        .data(bresp_tmp));
+
+//------------------------Body---------------------------
+    assign BREADY = resp_ready;
+    assign last_resp = aw2b_bdata[1];
+    assign invalid_event = aw2b_bdata[0];
+    assign resp_match = (next_resp && (last_resp || invalid_event)) && need_wrsp;
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            next_resp <= 1'b0;
+        else if (ACLK_EN) begin
+            next_resp <= BVALID && resp_ready || (invalid_event && need_wrsp && ~next_resp);
+        end
+    end
+
+    always @(posedge ACLK)
+    begin
+        if (ARESET)
+            bresp_tmp <= 2'b00;
+        else if (ACLK_EN) begin
+            if (resp_match && ~next_resp)           // last resp and no resp for next cycle: reset to 0
+                bresp_tmp <= 2'b00;
+            else if (resp_match && next_resp)       // last resp but has resp for next cycle
+                bresp_tmp <= BRESP;
+            else if (BVALID && resp_ready && ~bresp_tmp[1])
+                bresp_tmp <= BRESP;
+        end
+    end
+
+//------------------------B channel end------------------
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_params_s_axi.v b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_params_s_axi.v
new file mode 100755
index 0000000..d470352
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/verilog/mmult_params_s_axi.v
@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult.vhd
new file mode 100755
index 0000000..8b229a7
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult.vhd
@@ -0,0 +1,10532 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
+-- Version: 2020.1
+-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult is
+generic (
+    C_M_AXI_IN1_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN1_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN2_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_IN2_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ADDR_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_ID_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_AWUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_OUT_MEM_WUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_ARUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_RUSER_WIDTH : INTEGER := 1;
+    C_M_AXI_OUT_MEM_BUSER_WIDTH : INTEGER := 1;
+    C_S_AXI_PARAMS_ADDR_WIDTH : INTEGER := 6;
+    C_S_AXI_PARAMS_DATA_WIDTH : INTEGER := 32;
+    C_M_AXI_IN1_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN1_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_IN2_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_IN2_MEM_CACHE_VALUE : INTEGER := 3;
+    C_M_AXI_OUT_MEM_USER_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_PROT_VALUE : INTEGER := 0;
+    C_M_AXI_OUT_MEM_CACHE_VALUE : INTEGER := 3 );
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    m_axi_in1_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in1_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_WREADY : IN STD_LOGIC;
+    m_axi_in1_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in1_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in1_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in1_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in1_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in1_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in1_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in1_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RVALID : IN STD_LOGIC;
+    m_axi_in1_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in1_mem_RLAST : IN STD_LOGIC;
+    m_axi_in1_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in1_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BVALID : IN STD_LOGIC;
+    m_axi_in1_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in1_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in1_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in1_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN1_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_AWREADY : IN STD_LOGIC;
+    m_axi_in2_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_WVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_WREADY : IN STD_LOGIC;
+    m_axi_in2_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_in2_mem_WLAST : OUT STD_LOGIC;
+    m_axi_in2_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_in2_mem_ARREADY : IN STD_LOGIC;
+    m_axi_in2_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_in2_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_in2_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_in2_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RVALID : IN STD_LOGIC;
+    m_axi_in2_mem_RREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_in2_mem_RLAST : IN STD_LOGIC;
+    m_axi_in2_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_in2_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BVALID : IN STD_LOGIC;
+    m_axi_in2_mem_BREADY : OUT STD_LOGIC;
+    m_axi_in2_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_in2_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_ID_WIDTH-1 downto 0);
+    m_axi_in2_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_IN2_MEM_BUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_AWVALID : OUT STD_LOGIC;
+    m_axi_out_mem_AWREADY : IN STD_LOGIC;
+    m_axi_out_mem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_AWUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_WVALID : OUT STD_LOGIC;
+    m_axi_out_mem_WREADY : IN STD_LOGIC;
+    m_axi_out_mem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH/8-1 downto 0);
+    m_axi_out_mem_WLAST : OUT STD_LOGIC;
+    m_axi_out_mem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_WUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_ARVALID : OUT STD_LOGIC;
+    m_axi_out_mem_ARREADY : IN STD_LOGIC;
+    m_axi_out_mem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ADDR_WIDTH-1 downto 0);
+    m_axi_out_mem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+    m_axi_out_mem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+    m_axi_out_mem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+    m_axi_out_mem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ARUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RVALID : IN STD_LOGIC;
+    m_axi_out_mem_RREADY : OUT STD_LOGIC;
+    m_axi_out_mem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_DATA_WIDTH-1 downto 0);
+    m_axi_out_mem_RLAST : IN STD_LOGIC;
+    m_axi_out_mem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_RUSER_WIDTH-1 downto 0);
+    m_axi_out_mem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BVALID : IN STD_LOGIC;
+    m_axi_out_mem_BREADY : OUT STD_LOGIC;
+    m_axi_out_mem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+    m_axi_out_mem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_ID_WIDTH-1 downto 0);
+    m_axi_out_mem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_OUT_MEM_BUSER_WIDTH-1 downto 0);
+    s_axi_params_AWVALID : IN STD_LOGIC;
+    s_axi_params_AWREADY : OUT STD_LOGIC;
+    s_axi_params_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_WVALID : IN STD_LOGIC;
+    s_axi_params_WREADY : OUT STD_LOGIC;
+    s_axi_params_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH/8-1 downto 0);
+    s_axi_params_ARVALID : IN STD_LOGIC;
+    s_axi_params_ARREADY : OUT STD_LOGIC;
+    s_axi_params_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_PARAMS_ADDR_WIDTH-1 downto 0);
+    s_axi_params_RVALID : OUT STD_LOGIC;
+    s_axi_params_RREADY : IN STD_LOGIC;
+    s_axi_params_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_PARAMS_DATA_WIDTH-1 downto 0);
+    s_axi_params_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    s_axi_params_BVALID : OUT STD_LOGIC;
+    s_axi_params_BREADY : IN STD_LOGIC;
+    s_axi_params_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+    interrupt : OUT STD_LOGIC );
+end;
+
+
+architecture behav of mmult is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "mmult,hls_ip_2020_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu3eg-sbva484-1-e,HLS_INPUT_CLOCK=3.333000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.916375,HLS_SYN_LAT=16421,HLS_SYN_TPT=none,HLS_SYN_MEM=142,HLS_SYN_DSP=260,HLS_SYN_FF=20363,HLS_SYN_LUT=10157,HLS_VERSION=2020_1}";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000100";
+    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000001000";
+    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000010000";
+    constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000100000";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000001000000";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000010000000";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000100000000";
+    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000001000000000";
+    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000010000000000";
+    constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000100000000000";
+    constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000001000000000000";
+    constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000010000000000000";
+    constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000100000000000000";
+    constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000001000000000000000";
+    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000010000000000000000";
+    constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000100000000000000000";
+    constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (27 downto 0) := "0000000001000000000000000000";
+    constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (27 downto 0) := "0000000010000000000000000000";
+    constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (27 downto 0) := "0000000100000000000000000000";
+    constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (27 downto 0) := "0000001000000000000000000000";
+    constant ap_ST_fsm_pp3_stage0 : STD_LOGIC_VECTOR (27 downto 0) := "0000010000000000000000000000";
+    constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (27 downto 0) := "0000100000000000000000000000";
+    constant ap_ST_fsm_state39 : STD_LOGIC_VECTOR (27 downto 0) := "0001000000000000000000000000";
+    constant ap_ST_fsm_state40 : STD_LOGIC_VECTOR (27 downto 0) := "0010000000000000000000000000";
+    constant ap_ST_fsm_state41 : STD_LOGIC_VECTOR (27 downto 0) := "0100000000000000000000000000";
+    constant ap_ST_fsm_state42 : STD_LOGIC_VECTOR (27 downto 0) := "1000000000000000000000000000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
+    constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
+    constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
+    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
+    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
+    constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
+    constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
+    constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
+    constant ap_const_lv32_1000 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000001000000000000";
+    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
+    constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
+    constant ap_const_lv6_3E : STD_LOGIC_VECTOR (5 downto 0) := "111110";
+    constant ap_const_lv6_3D : STD_LOGIC_VECTOR (5 downto 0) := "111101";
+    constant ap_const_lv6_3C : STD_LOGIC_VECTOR (5 downto 0) := "111100";
+    constant ap_const_lv6_3B : STD_LOGIC_VECTOR (5 downto 0) := "111011";
+    constant ap_const_lv6_3A : STD_LOGIC_VECTOR (5 downto 0) := "111010";
+    constant ap_const_lv6_39 : STD_LOGIC_VECTOR (5 downto 0) := "111001";
+    constant ap_const_lv6_38 : STD_LOGIC_VECTOR (5 downto 0) := "111000";
+    constant ap_const_lv6_37 : STD_LOGIC_VECTOR (5 downto 0) := "110111";
+    constant ap_const_lv6_36 : STD_LOGIC_VECTOR (5 downto 0) := "110110";
+    constant ap_const_lv6_35 : STD_LOGIC_VECTOR (5 downto 0) := "110101";
+    constant ap_const_lv6_34 : STD_LOGIC_VECTOR (5 downto 0) := "110100";
+    constant ap_const_lv6_33 : STD_LOGIC_VECTOR (5 downto 0) := "110011";
+    constant ap_const_lv6_32 : STD_LOGIC_VECTOR (5 downto 0) := "110010";
+    constant ap_const_lv6_31 : STD_LOGIC_VECTOR (5 downto 0) := "110001";
+    constant ap_const_lv6_30 : STD_LOGIC_VECTOR (5 downto 0) := "110000";
+    constant ap_const_lv6_2F : STD_LOGIC_VECTOR (5 downto 0) := "101111";
+    constant ap_const_lv6_2E : STD_LOGIC_VECTOR (5 downto 0) := "101110";
+    constant ap_const_lv6_2D : STD_LOGIC_VECTOR (5 downto 0) := "101101";
+    constant ap_const_lv6_2C : STD_LOGIC_VECTOR (5 downto 0) := "101100";
+    constant ap_const_lv6_2B : STD_LOGIC_VECTOR (5 downto 0) := "101011";
+    constant ap_const_lv6_2A : STD_LOGIC_VECTOR (5 downto 0) := "101010";
+    constant ap_const_lv6_29 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
+    constant ap_const_lv6_28 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
+    constant ap_const_lv6_27 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
+    constant ap_const_lv6_26 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
+    constant ap_const_lv6_25 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
+    constant ap_const_lv6_24 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
+    constant ap_const_lv6_23 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
+    constant ap_const_lv6_22 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
+    constant ap_const_lv6_21 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
+    constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
+    constant ap_const_lv6_1F : STD_LOGIC_VECTOR (5 downto 0) := "011111";
+    constant ap_const_lv6_1E : STD_LOGIC_VECTOR (5 downto 0) := "011110";
+    constant ap_const_lv6_1D : STD_LOGIC_VECTOR (5 downto 0) := "011101";
+    constant ap_const_lv6_1C : STD_LOGIC_VECTOR (5 downto 0) := "011100";
+    constant ap_const_lv6_1B : STD_LOGIC_VECTOR (5 downto 0) := "011011";
+    constant ap_const_lv6_1A : STD_LOGIC_VECTOR (5 downto 0) := "011010";
+    constant ap_const_lv6_19 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
+    constant ap_const_lv6_18 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
+    constant ap_const_lv6_17 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
+    constant ap_const_lv6_16 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
+    constant ap_const_lv6_15 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
+    constant ap_const_lv6_14 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
+    constant ap_const_lv6_13 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
+    constant ap_const_lv6_12 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
+    constant ap_const_lv6_11 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
+    constant ap_const_lv6_10 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
+    constant ap_const_lv6_F : STD_LOGIC_VECTOR (5 downto 0) := "001111";
+    constant ap_const_lv6_E : STD_LOGIC_VECTOR (5 downto 0) := "001110";
+    constant ap_const_lv6_D : STD_LOGIC_VECTOR (5 downto 0) := "001101";
+    constant ap_const_lv6_C : STD_LOGIC_VECTOR (5 downto 0) := "001100";
+    constant ap_const_lv6_B : STD_LOGIC_VECTOR (5 downto 0) := "001011";
+    constant ap_const_lv6_A : STD_LOGIC_VECTOR (5 downto 0) := "001010";
+    constant ap_const_lv6_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
+    constant ap_const_lv6_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
+    constant ap_const_lv6_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
+    constant ap_const_lv6_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
+    constant ap_const_lv6_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
+    constant ap_const_lv6_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
+    constant ap_const_lv6_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
+    constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
+    constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
+    constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
+    constant ap_const_lv6_3F : STD_LOGIC_VECTOR (5 downto 0) := "111111";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv13_1000 : STD_LOGIC_VECTOR (12 downto 0) := "1000000000000";
+    constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
+    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
+    constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
+    constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal ap_start : STD_LOGIC;
+    signal ap_done : STD_LOGIC;
+    signal ap_idle : STD_LOGIC;
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal ap_ready : STD_LOGIC;
+    signal in1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_r : STD_LOGIC_VECTOR (31 downto 0);
+    signal dim : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal in1_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal in2_mem_blk_n_AR : STD_LOGIC;
+    signal ap_CS_fsm_state12 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
+    signal in2_mem_blk_n_R : STD_LOGIC;
+    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
+    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp1_stage0 : BOOLEAN;
+    signal out_mem_blk_n_AW : STD_LOGIC;
+    signal ap_CS_fsm_state34 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state34 : signal is "none";
+    signal out_mem_blk_n_W : STD_LOGIC;
+    signal ap_enable_reg_pp3_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp3_stage0 : BOOLEAN;
+    signal icmp_ln42_reg_6380 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln42_reg_6380_pp3_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_blk_n_B : STD_LOGIC;
+    signal ap_CS_fsm_state42 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state42 : signal is "none";
+    signal in1_mem_AWREADY : STD_LOGIC;
+    signal in1_mem_WREADY : STD_LOGIC;
+    signal in1_mem_ARVALID : STD_LOGIC;
+    signal in1_mem_ARREADY : STD_LOGIC;
+    signal in1_mem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RVALID : STD_LOGIC;
+    signal in1_mem_RREADY : STD_LOGIC;
+    signal in1_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_mem_RLAST : STD_LOGIC;
+    signal in1_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BVALID : STD_LOGIC;
+    signal in1_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in1_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in1_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_AWREADY : STD_LOGIC;
+    signal in2_mem_WREADY : STD_LOGIC;
+    signal in2_mem_ARVALID : STD_LOGIC;
+    signal in2_mem_ARREADY : STD_LOGIC;
+    signal in2_mem_RVALID : STD_LOGIC;
+    signal in2_mem_RREADY : STD_LOGIC;
+    signal in2_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_mem_RLAST : STD_LOGIC;
+    signal in2_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BVALID : STD_LOGIC;
+    signal in2_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal in2_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal in2_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_AWVALID : STD_LOGIC;
+    signal out_mem_AWREADY : STD_LOGIC;
+    signal out_mem_WVALID : STD_LOGIC;
+    signal out_mem_WREADY : STD_LOGIC;
+    signal out_mem_ARREADY : STD_LOGIC;
+    signal out_mem_RVALID : STD_LOGIC;
+    signal out_mem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal out_mem_RLAST : STD_LOGIC;
+    signal out_mem_RID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BVALID : STD_LOGIC;
+    signal out_mem_BREADY : STD_LOGIC;
+    signal out_mem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
+    signal out_mem_BID : STD_LOGIC_VECTOR (0 downto 0);
+    signal out_mem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
+    signal phi_ln27_reg_3296 : STD_LOGIC_VECTOR (12 downto 0);
+    signal phi_ln28_reg_3307 : STD_LOGIC_VECTOR (12 downto 0);
+    signal indvar_flatten_reg_3318 : STD_LOGIC_VECTOR (63 downto 0);
+    signal i_0_reg_3329 : STD_LOGIC_VECTOR (30 downto 0);
+    signal j_0_reg_3340 : STD_LOGIC_VECTOR (31 downto 0);
+    signal phi_ln42_reg_3351 : STD_LOGIC_VECTOR (12 downto 0);
+    signal out_loc_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal reg_3362 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp2_iter5 : STD_LOGIC := '0';
+    signal ap_block_state25_pp2_stage0_iter0 : BOOLEAN;
+    signal ap_block_state26_pp2_stage0_iter1 : BOOLEAN;
+    signal ap_block_state27_pp2_stage0_iter2 : BOOLEAN;
+    signal ap_block_state28_pp2_stage0_iter3 : BOOLEAN;
+    signal ap_block_state29_pp2_stage0_iter4 : BOOLEAN;
+    signal ap_block_state30_pp2_stage0_iter5 : BOOLEAN;
+    signal ap_block_state31_pp2_stage0_iter6 : BOOLEAN;
+    signal ap_block_state32_pp2_stage0_iter7 : BOOLEAN;
+    signal ap_block_state33_pp2_stage0_iter8 : BOOLEAN;
+    signal ap_block_pp2_stage0_11001 : BOOLEAN;
+    signal icmp_ln31_reg_4578 : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4578_pp2_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp3_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp3_stage0 : signal is "none";
+    signal ap_enable_reg_pp3_iter1 : STD_LOGIC := '0';
+    signal ap_block_state35_pp3_stage0_iter0 : BOOLEAN;
+    signal ap_block_state36_pp3_stage0_iter1 : BOOLEAN;
+    signal ap_block_state37_pp3_stage0_iter2 : BOOLEAN;
+    signal ap_block_state37_io : BOOLEAN;
+    signal ap_block_pp3_stage0_11001 : BOOLEAN;
+    signal dim_read_reg_4356 : STD_LOGIC_VECTOR (31 downto 0);
+    signal out5_reg_4362 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in_reg_4367 : STD_LOGIC_VECTOR (29 downto 0);
+    signal in3_reg_4372 : STD_LOGIC_VECTOR (29 downto 0);
+    signal out_mem_addr_reg_4383 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
+    signal in2_mem_addr_reg_4389 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln27_fu_3425_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state9_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state11_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal add_ln27_fu_3431_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal lshr_ln_reg_4404 : STD_LOGIC_VECTOR (6 downto 0);
+    signal lshr_ln_reg_4404_pp0_iter1_reg : STD_LOGIC_VECTOR (6 downto 0);
+    signal trunc_ln27_fu_3447_p1 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln27_reg_4409 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln27_reg_4409_pp0_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_mem_addr_read_reg_4413 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln28_fu_3518_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state19_pp1_stage0_iter0 : BOOLEAN;
+    signal ap_block_state20_pp1_stage0_iter1 : BOOLEAN;
+    signal ap_block_state21_pp1_stage0_iter2 : BOOLEAN;
+    signal ap_block_pp1_stage0_11001 : BOOLEAN;
+    signal add_ln28_fu_3524_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
+    signal trunc_ln28_fu_3530_p1 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln28_reg_4490 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln28_reg_4490_pp1_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln1_reg_4495 : STD_LOGIC_VECTOR (5 downto 0);
+    signal trunc_ln1_reg_4495_pp1_iter1_reg : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_mem_addr_read_reg_4499 : STD_LOGIC_VECTOR (31 downto 0);
+    signal zext_ln31_fu_3611_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_CS_fsm_state22 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none";
+    signal grp_fu_3614_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal mul_ln31_reg_4573 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_CS_fsm_state24 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state24 : signal is "none";
+    signal icmp_ln31_fu_3620_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
+    signal icmp_ln31_reg_4578_pp2_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4578_pp2_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4578_pp2_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4578_pp2_iter5_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4578_pp2_iter6_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal icmp_ln31_reg_4578_pp2_iter7_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln31_fu_3625_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
+    signal select_ln31_fu_3642_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln31_reg_4587 : STD_LOGIC_VECTOR (31 downto 0);
+    signal select_ln31_1_fu_3650_p3 : STD_LOGIC_VECTOR (30 downto 0);
+    signal select_ln31_1_reg_4592 : STD_LOGIC_VECTOR (30 downto 0);
+    signal out_loc_addr_reg_4598 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4598_pp2_iter1_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4598_pp2_iter2_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4598_pp2_iter3_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4598_pp2_iter4_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4598_pp2_iter5_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4598_pp2_iter6_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_addr_reg_4598_pp2_iter7_reg : STD_LOGIC_VECTOR (11 downto 0);
+    signal j_fu_3685_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal zext_ln31_1_fu_3691_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln31_1_reg_4609 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_fu_3739_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal sext_ln38_reg_4857 : STD_LOGIC_VECTOR (63 downto 0);
+    signal in1_loc_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_0_load_reg_5105 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp2_iter2 : STD_LOGIC := '0';
+    signal in1_loc_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_1_load_reg_5110 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_2_load_reg_5115 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_3_load_reg_5120 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_4_load_reg_5125 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_5_load_reg_5130 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_6_load_reg_5135 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_7_load_reg_5140 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_8_load_reg_5145 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_11_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_11_load_reg_5160 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_12_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_12_load_reg_5165 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_15_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_15_load_reg_5180 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_16_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_16_load_reg_5185 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_19_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_19_load_reg_5200 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_20_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_20_load_reg_5205 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_21_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_21_load_reg_5210 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_22_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_22_load_reg_5215 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_23_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_23_load_reg_5220 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_24_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_24_load_reg_5225 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_27_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_27_load_reg_5240 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_28_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_28_load_reg_5245 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_29_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_29_load_reg_5250 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_30_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_30_load_reg_5255 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_31_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_31_load_reg_5260 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_32_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_32_load_reg_5265 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_35_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_35_load_reg_5280 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_36_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_36_load_reg_5285 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_37_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_37_load_reg_5290 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_38_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_38_load_reg_5295 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_39_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_39_load_reg_5300 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_40_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_40_load_reg_5305 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_43_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_43_load_reg_5320 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_44_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_44_load_reg_5325 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_47_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_47_load_reg_5340 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_48_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_48_load_reg_5345 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_51_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_51_load_reg_5360 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_52_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_52_load_reg_5365 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_53_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_53_load_reg_5370 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_54_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_54_load_reg_5375 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_55_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_55_load_reg_5380 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_56_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_56_load_reg_5385 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_59_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_59_load_reg_5400 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_60_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_60_load_reg_5405 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_62_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_62_load_reg_5415 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_63_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_63_load_reg_5420 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_0_load_reg_5425 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_1_load_reg_5430 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_2_load_reg_5435 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_3_load_reg_5440 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_4_load_reg_5445 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_5_load_reg_5450 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_6_load_reg_5455 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_7_load_reg_5460 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_8_load_reg_5465 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_11_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_11_load_reg_5480 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_12_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_12_load_reg_5485 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_15_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_15_load_reg_5500 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_16_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_16_load_reg_5505 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_19_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_19_load_reg_5520 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_20_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_20_load_reg_5525 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_21_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_21_load_reg_5530 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_22_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_22_load_reg_5535 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_23_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_23_load_reg_5540 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_24_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_24_load_reg_5545 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_27_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_27_load_reg_5560 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_28_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_28_load_reg_5565 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_29_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_29_load_reg_5570 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_30_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_30_load_reg_5575 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_31_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_31_load_reg_5580 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_32_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_32_load_reg_5585 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_35_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_35_load_reg_5600 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_36_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_36_load_reg_5605 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_37_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_37_load_reg_5610 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_38_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_38_load_reg_5615 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_39_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_39_load_reg_5620 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_40_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_40_load_reg_5625 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_43_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_43_load_reg_5640 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_44_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_44_load_reg_5645 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_47_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_47_load_reg_5660 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_48_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_48_load_reg_5665 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_51_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_51_load_reg_5680 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_52_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_52_load_reg_5685 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_53_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_53_load_reg_5690 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_54_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_54_load_reg_5695 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_55_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_55_load_reg_5700 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_56_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_56_load_reg_5705 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_59_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_59_load_reg_5720 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_60_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_60_load_reg_5725 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_62_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_62_load_reg_5735 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_63_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_63_load_reg_5740 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_9_load_reg_5745 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp2_iter3 : STD_LOGIC := '0';
+    signal in1_loc_10_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_10_load_reg_5750 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_13_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_13_load_reg_5755 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_14_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_14_load_reg_5760 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_17_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_17_load_reg_5765 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_18_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_18_load_reg_5770 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_25_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_25_load_reg_5775 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_26_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_26_load_reg_5780 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_33_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_33_load_reg_5785 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_34_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_34_load_reg_5790 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_41_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_41_load_reg_5795 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_42_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_42_load_reg_5800 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_45_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_45_load_reg_5805 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_46_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_46_load_reg_5810 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_49_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_49_load_reg_5815 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_50_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_50_load_reg_5820 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_57_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_57_load_reg_5825 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_58_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_58_load_reg_5830 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_61_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in1_loc_61_load_reg_5835 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_9_load_reg_5840 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_10_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_10_load_reg_5845 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_13_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_13_load_reg_5850 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_14_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_14_load_reg_5855 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_17_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_17_load_reg_5860 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_18_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_18_load_reg_5865 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_25_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_25_load_reg_5870 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_26_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_26_load_reg_5875 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_33_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_33_load_reg_5880 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_34_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_34_load_reg_5885 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_41_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_41_load_reg_5890 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_42_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_42_load_reg_5895 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_45_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_45_load_reg_5900 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_46_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_46_load_reg_5905 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_49_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_49_load_reg_5910 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_50_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_50_load_reg_5915 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_57_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_57_load_reg_5920 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_58_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_58_load_reg_5925 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_61_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal in2_loc_61_load_reg_5930 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3787_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_reg_5935 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3791_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_1_reg_5940 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3795_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_2_reg_5945 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3799_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_3_reg_5950 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3803_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_4_reg_5955 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3807_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_5_reg_5960 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3811_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_6_reg_5965 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3815_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_7_reg_5970 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3819_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_8_reg_5975 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3823_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_11_reg_5980 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3827_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_12_reg_5985 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3831_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_15_reg_5990 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3835_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_16_reg_5995 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3839_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_19_reg_6000 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3843_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_20_reg_6005 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3847_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_21_reg_6010 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3851_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_22_reg_6015 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3855_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_23_reg_6020 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3859_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_24_reg_6025 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3863_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_27_reg_6030 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3867_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_28_reg_6035 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3871_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_29_reg_6040 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3875_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_30_reg_6045 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3879_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_31_reg_6050 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3883_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_32_reg_6055 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3887_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_35_reg_6060 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3891_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_36_reg_6065 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3895_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_37_reg_6070 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3899_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_38_reg_6075 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3903_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_39_reg_6080 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3907_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_40_reg_6085 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3911_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_43_reg_6090 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3915_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_44_reg_6095 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3919_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_47_reg_6100 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3923_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_48_reg_6105 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3927_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_51_reg_6110 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3931_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_52_reg_6115 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3935_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_53_reg_6120 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3939_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_54_reg_6125 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3943_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_55_reg_6130 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3947_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_56_reg_6135 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3951_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_59_reg_6140 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3955_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_60_reg_6145 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3959_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_62_reg_6150 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3963_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_63_reg_6155 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3967_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_9_reg_6160 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3971_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_10_reg_6165 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3975_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_13_reg_6170 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3979_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_14_reg_6175 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3983_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_17_reg_6180 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3987_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_18_reg_6185 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3991_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_25_reg_6190 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3995_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_26_reg_6195 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3999_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_33_reg_6200 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4003_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_34_reg_6205 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4007_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_41_reg_6210 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4011_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_42_reg_6215 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4015_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_45_reg_6220 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4019_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_46_reg_6225 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4023_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_49_reg_6230 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4027_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_50_reg_6235 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4031_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_57_reg_6240 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4035_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_58_reg_6245 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_4039_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal mul_ln38_61_reg_6250 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_2_fu_4052_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_2_reg_6255 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_3_fu_4058_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_3_reg_6260 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_4_fu_4062_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_4_reg_6265 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_7_fu_4066_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_7_reg_6270 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_10_fu_4070_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_10_reg_6275 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_15_fu_4074_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_15_reg_6280 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_18_fu_4078_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_18_reg_6285 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_19_fu_4082_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_19_reg_6290 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_22_fu_4086_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_22_reg_6295 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_25_fu_4090_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_25_reg_6300 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_26_fu_4094_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_26_reg_6305 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_31_fu_4098_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_31_reg_6310 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_34_fu_4102_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_34_reg_6315 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_35_fu_4106_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_35_reg_6320 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_38_fu_4110_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_38_reg_6325 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_41_fu_4114_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_41_reg_6330 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_46_fu_4118_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_46_reg_6335 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_49_fu_4122_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_49_reg_6340 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_50_fu_4126_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_50_reg_6345 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_53_fu_4130_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_53_reg_6350 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_56_fu_4134_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_56_reg_6355 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_57_fu_4138_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_57_reg_6360 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_30_fu_4225_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_30_reg_6365 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_45_fu_4274_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_45_reg_6370 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_61_fu_4323_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_61_reg_6375 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln42_fu_4339_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal add_ln42_fu_4345_p2 : STD_LOGIC_VECTOR (12 downto 0);
+    signal ap_enable_reg_pp3_iter0 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state9 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_CS_fsm_state18 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state18 : signal is "none";
+    signal ap_block_pp1_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp1_exit_iter0_state19 : STD_LOGIC;
+    signal ap_enable_reg_pp1_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp2_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp2_exit_iter0_state25 : STD_LOGIC;
+    signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp2_iter4 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp2_iter6 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp2_iter7 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp2_iter8 : STD_LOGIC := '0';
+    signal ap_block_pp3_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp3_exit_iter0_state35 : STD_LOGIC;
+    signal in1_loc_0_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_0_ce0 : STD_LOGIC;
+    signal in1_loc_0_we0 : STD_LOGIC;
+    signal in1_loc_1_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_1_ce0 : STD_LOGIC;
+    signal in1_loc_1_we0 : STD_LOGIC;
+    signal in1_loc_2_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_2_ce0 : STD_LOGIC;
+    signal in1_loc_2_we0 : STD_LOGIC;
+    signal in1_loc_3_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_3_ce0 : STD_LOGIC;
+    signal in1_loc_3_we0 : STD_LOGIC;
+    signal in1_loc_4_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_4_ce0 : STD_LOGIC;
+    signal in1_loc_4_we0 : STD_LOGIC;
+    signal in1_loc_5_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_5_ce0 : STD_LOGIC;
+    signal in1_loc_5_we0 : STD_LOGIC;
+    signal in1_loc_6_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_6_ce0 : STD_LOGIC;
+    signal in1_loc_6_we0 : STD_LOGIC;
+    signal in1_loc_7_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_7_ce0 : STD_LOGIC;
+    signal in1_loc_7_we0 : STD_LOGIC;
+    signal in1_loc_8_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_8_ce0 : STD_LOGIC;
+    signal in1_loc_8_we0 : STD_LOGIC;
+    signal in1_loc_9_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_9_ce0 : STD_LOGIC;
+    signal in1_loc_9_we0 : STD_LOGIC;
+    signal in1_loc_10_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_10_ce0 : STD_LOGIC;
+    signal in1_loc_10_we0 : STD_LOGIC;
+    signal in1_loc_11_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_11_ce0 : STD_LOGIC;
+    signal in1_loc_11_we0 : STD_LOGIC;
+    signal in1_loc_12_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_12_ce0 : STD_LOGIC;
+    signal in1_loc_12_we0 : STD_LOGIC;
+    signal in1_loc_13_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_13_ce0 : STD_LOGIC;
+    signal in1_loc_13_we0 : STD_LOGIC;
+    signal in1_loc_14_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_14_ce0 : STD_LOGIC;
+    signal in1_loc_14_we0 : STD_LOGIC;
+    signal in1_loc_15_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_15_ce0 : STD_LOGIC;
+    signal in1_loc_15_we0 : STD_LOGIC;
+    signal in1_loc_16_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_16_ce0 : STD_LOGIC;
+    signal in1_loc_16_we0 : STD_LOGIC;
+    signal in1_loc_17_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_17_ce0 : STD_LOGIC;
+    signal in1_loc_17_we0 : STD_LOGIC;
+    signal in1_loc_18_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_18_ce0 : STD_LOGIC;
+    signal in1_loc_18_we0 : STD_LOGIC;
+    signal in1_loc_19_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_19_ce0 : STD_LOGIC;
+    signal in1_loc_19_we0 : STD_LOGIC;
+    signal in1_loc_20_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_20_ce0 : STD_LOGIC;
+    signal in1_loc_20_we0 : STD_LOGIC;
+    signal in1_loc_21_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_21_ce0 : STD_LOGIC;
+    signal in1_loc_21_we0 : STD_LOGIC;
+    signal in1_loc_22_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_22_ce0 : STD_LOGIC;
+    signal in1_loc_22_we0 : STD_LOGIC;
+    signal in1_loc_23_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_23_ce0 : STD_LOGIC;
+    signal in1_loc_23_we0 : STD_LOGIC;
+    signal in1_loc_24_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_24_ce0 : STD_LOGIC;
+    signal in1_loc_24_we0 : STD_LOGIC;
+    signal in1_loc_25_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_25_ce0 : STD_LOGIC;
+    signal in1_loc_25_we0 : STD_LOGIC;
+    signal in1_loc_26_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_26_ce0 : STD_LOGIC;
+    signal in1_loc_26_we0 : STD_LOGIC;
+    signal in1_loc_27_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_27_ce0 : STD_LOGIC;
+    signal in1_loc_27_we0 : STD_LOGIC;
+    signal in1_loc_28_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_28_ce0 : STD_LOGIC;
+    signal in1_loc_28_we0 : STD_LOGIC;
+    signal in1_loc_29_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_29_ce0 : STD_LOGIC;
+    signal in1_loc_29_we0 : STD_LOGIC;
+    signal in1_loc_30_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_30_ce0 : STD_LOGIC;
+    signal in1_loc_30_we0 : STD_LOGIC;
+    signal in1_loc_31_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_31_ce0 : STD_LOGIC;
+    signal in1_loc_31_we0 : STD_LOGIC;
+    signal in1_loc_32_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_32_ce0 : STD_LOGIC;
+    signal in1_loc_32_we0 : STD_LOGIC;
+    signal in1_loc_33_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_33_ce0 : STD_LOGIC;
+    signal in1_loc_33_we0 : STD_LOGIC;
+    signal in1_loc_34_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_34_ce0 : STD_LOGIC;
+    signal in1_loc_34_we0 : STD_LOGIC;
+    signal in1_loc_35_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_35_ce0 : STD_LOGIC;
+    signal in1_loc_35_we0 : STD_LOGIC;
+    signal in1_loc_36_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_36_ce0 : STD_LOGIC;
+    signal in1_loc_36_we0 : STD_LOGIC;
+    signal in1_loc_37_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_37_ce0 : STD_LOGIC;
+    signal in1_loc_37_we0 : STD_LOGIC;
+    signal in1_loc_38_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_38_ce0 : STD_LOGIC;
+    signal in1_loc_38_we0 : STD_LOGIC;
+    signal in1_loc_39_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_39_ce0 : STD_LOGIC;
+    signal in1_loc_39_we0 : STD_LOGIC;
+    signal in1_loc_40_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_40_ce0 : STD_LOGIC;
+    signal in1_loc_40_we0 : STD_LOGIC;
+    signal in1_loc_41_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_41_ce0 : STD_LOGIC;
+    signal in1_loc_41_we0 : STD_LOGIC;
+    signal in1_loc_42_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_42_ce0 : STD_LOGIC;
+    signal in1_loc_42_we0 : STD_LOGIC;
+    signal in1_loc_43_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_43_ce0 : STD_LOGIC;
+    signal in1_loc_43_we0 : STD_LOGIC;
+    signal in1_loc_44_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_44_ce0 : STD_LOGIC;
+    signal in1_loc_44_we0 : STD_LOGIC;
+    signal in1_loc_45_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_45_ce0 : STD_LOGIC;
+    signal in1_loc_45_we0 : STD_LOGIC;
+    signal in1_loc_46_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_46_ce0 : STD_LOGIC;
+    signal in1_loc_46_we0 : STD_LOGIC;
+    signal in1_loc_47_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_47_ce0 : STD_LOGIC;
+    signal in1_loc_47_we0 : STD_LOGIC;
+    signal in1_loc_48_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_48_ce0 : STD_LOGIC;
+    signal in1_loc_48_we0 : STD_LOGIC;
+    signal in1_loc_49_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_49_ce0 : STD_LOGIC;
+    signal in1_loc_49_we0 : STD_LOGIC;
+    signal in1_loc_50_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_50_ce0 : STD_LOGIC;
+    signal in1_loc_50_we0 : STD_LOGIC;
+    signal in1_loc_51_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_51_ce0 : STD_LOGIC;
+    signal in1_loc_51_we0 : STD_LOGIC;
+    signal in1_loc_52_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_52_ce0 : STD_LOGIC;
+    signal in1_loc_52_we0 : STD_LOGIC;
+    signal in1_loc_53_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_53_ce0 : STD_LOGIC;
+    signal in1_loc_53_we0 : STD_LOGIC;
+    signal in1_loc_54_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_54_ce0 : STD_LOGIC;
+    signal in1_loc_54_we0 : STD_LOGIC;
+    signal in1_loc_55_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_55_ce0 : STD_LOGIC;
+    signal in1_loc_55_we0 : STD_LOGIC;
+    signal in1_loc_56_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_56_ce0 : STD_LOGIC;
+    signal in1_loc_56_we0 : STD_LOGIC;
+    signal in1_loc_57_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_57_ce0 : STD_LOGIC;
+    signal in1_loc_57_we0 : STD_LOGIC;
+    signal in1_loc_58_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_58_ce0 : STD_LOGIC;
+    signal in1_loc_58_we0 : STD_LOGIC;
+    signal in1_loc_59_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_59_ce0 : STD_LOGIC;
+    signal in1_loc_59_we0 : STD_LOGIC;
+    signal in1_loc_60_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_60_ce0 : STD_LOGIC;
+    signal in1_loc_60_we0 : STD_LOGIC;
+    signal in1_loc_61_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_61_ce0 : STD_LOGIC;
+    signal in1_loc_61_we0 : STD_LOGIC;
+    signal in1_loc_62_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_62_ce0 : STD_LOGIC;
+    signal in1_loc_62_we0 : STD_LOGIC;
+    signal in1_loc_63_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in1_loc_63_ce0 : STD_LOGIC;
+    signal in1_loc_63_we0 : STD_LOGIC;
+    signal in2_loc_0_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_0_ce0 : STD_LOGIC;
+    signal in2_loc_0_we0 : STD_LOGIC;
+    signal in2_loc_1_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_1_ce0 : STD_LOGIC;
+    signal in2_loc_1_we0 : STD_LOGIC;
+    signal in2_loc_2_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_2_ce0 : STD_LOGIC;
+    signal in2_loc_2_we0 : STD_LOGIC;
+    signal in2_loc_3_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_3_ce0 : STD_LOGIC;
+    signal in2_loc_3_we0 : STD_LOGIC;
+    signal in2_loc_4_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_4_ce0 : STD_LOGIC;
+    signal in2_loc_4_we0 : STD_LOGIC;
+    signal in2_loc_5_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_5_ce0 : STD_LOGIC;
+    signal in2_loc_5_we0 : STD_LOGIC;
+    signal in2_loc_6_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_6_ce0 : STD_LOGIC;
+    signal in2_loc_6_we0 : STD_LOGIC;
+    signal in2_loc_7_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_7_ce0 : STD_LOGIC;
+    signal in2_loc_7_we0 : STD_LOGIC;
+    signal in2_loc_8_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_8_ce0 : STD_LOGIC;
+    signal in2_loc_8_we0 : STD_LOGIC;
+    signal in2_loc_9_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_9_ce0 : STD_LOGIC;
+    signal in2_loc_9_we0 : STD_LOGIC;
+    signal in2_loc_10_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_10_ce0 : STD_LOGIC;
+    signal in2_loc_10_we0 : STD_LOGIC;
+    signal in2_loc_11_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_11_ce0 : STD_LOGIC;
+    signal in2_loc_11_we0 : STD_LOGIC;
+    signal in2_loc_12_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_12_ce0 : STD_LOGIC;
+    signal in2_loc_12_we0 : STD_LOGIC;
+    signal in2_loc_13_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_13_ce0 : STD_LOGIC;
+    signal in2_loc_13_we0 : STD_LOGIC;
+    signal in2_loc_14_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_14_ce0 : STD_LOGIC;
+    signal in2_loc_14_we0 : STD_LOGIC;
+    signal in2_loc_15_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_15_ce0 : STD_LOGIC;
+    signal in2_loc_15_we0 : STD_LOGIC;
+    signal in2_loc_16_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_16_ce0 : STD_LOGIC;
+    signal in2_loc_16_we0 : STD_LOGIC;
+    signal in2_loc_17_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_17_ce0 : STD_LOGIC;
+    signal in2_loc_17_we0 : STD_LOGIC;
+    signal in2_loc_18_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_18_ce0 : STD_LOGIC;
+    signal in2_loc_18_we0 : STD_LOGIC;
+    signal in2_loc_19_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_19_ce0 : STD_LOGIC;
+    signal in2_loc_19_we0 : STD_LOGIC;
+    signal in2_loc_20_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_20_ce0 : STD_LOGIC;
+    signal in2_loc_20_we0 : STD_LOGIC;
+    signal in2_loc_21_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_21_ce0 : STD_LOGIC;
+    signal in2_loc_21_we0 : STD_LOGIC;
+    signal in2_loc_22_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_22_ce0 : STD_LOGIC;
+    signal in2_loc_22_we0 : STD_LOGIC;
+    signal in2_loc_23_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_23_ce0 : STD_LOGIC;
+    signal in2_loc_23_we0 : STD_LOGIC;
+    signal in2_loc_24_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_24_ce0 : STD_LOGIC;
+    signal in2_loc_24_we0 : STD_LOGIC;
+    signal in2_loc_25_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_25_ce0 : STD_LOGIC;
+    signal in2_loc_25_we0 : STD_LOGIC;
+    signal in2_loc_26_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_26_ce0 : STD_LOGIC;
+    signal in2_loc_26_we0 : STD_LOGIC;
+    signal in2_loc_27_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_27_ce0 : STD_LOGIC;
+    signal in2_loc_27_we0 : STD_LOGIC;
+    signal in2_loc_28_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_28_ce0 : STD_LOGIC;
+    signal in2_loc_28_we0 : STD_LOGIC;
+    signal in2_loc_29_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_29_ce0 : STD_LOGIC;
+    signal in2_loc_29_we0 : STD_LOGIC;
+    signal in2_loc_30_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_30_ce0 : STD_LOGIC;
+    signal in2_loc_30_we0 : STD_LOGIC;
+    signal in2_loc_31_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_31_ce0 : STD_LOGIC;
+    signal in2_loc_31_we0 : STD_LOGIC;
+    signal in2_loc_32_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_32_ce0 : STD_LOGIC;
+    signal in2_loc_32_we0 : STD_LOGIC;
+    signal in2_loc_33_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_33_ce0 : STD_LOGIC;
+    signal in2_loc_33_we0 : STD_LOGIC;
+    signal in2_loc_34_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_34_ce0 : STD_LOGIC;
+    signal in2_loc_34_we0 : STD_LOGIC;
+    signal in2_loc_35_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_35_ce0 : STD_LOGIC;
+    signal in2_loc_35_we0 : STD_LOGIC;
+    signal in2_loc_36_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_36_ce0 : STD_LOGIC;
+    signal in2_loc_36_we0 : STD_LOGIC;
+    signal in2_loc_37_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_37_ce0 : STD_LOGIC;
+    signal in2_loc_37_we0 : STD_LOGIC;
+    signal in2_loc_38_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_38_ce0 : STD_LOGIC;
+    signal in2_loc_38_we0 : STD_LOGIC;
+    signal in2_loc_39_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_39_ce0 : STD_LOGIC;
+    signal in2_loc_39_we0 : STD_LOGIC;
+    signal in2_loc_40_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_40_ce0 : STD_LOGIC;
+    signal in2_loc_40_we0 : STD_LOGIC;
+    signal in2_loc_41_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_41_ce0 : STD_LOGIC;
+    signal in2_loc_41_we0 : STD_LOGIC;
+    signal in2_loc_42_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_42_ce0 : STD_LOGIC;
+    signal in2_loc_42_we0 : STD_LOGIC;
+    signal in2_loc_43_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_43_ce0 : STD_LOGIC;
+    signal in2_loc_43_we0 : STD_LOGIC;
+    signal in2_loc_44_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_44_ce0 : STD_LOGIC;
+    signal in2_loc_44_we0 : STD_LOGIC;
+    signal in2_loc_45_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_45_ce0 : STD_LOGIC;
+    signal in2_loc_45_we0 : STD_LOGIC;
+    signal in2_loc_46_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_46_ce0 : STD_LOGIC;
+    signal in2_loc_46_we0 : STD_LOGIC;
+    signal in2_loc_47_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_47_ce0 : STD_LOGIC;
+    signal in2_loc_47_we0 : STD_LOGIC;
+    signal in2_loc_48_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_48_ce0 : STD_LOGIC;
+    signal in2_loc_48_we0 : STD_LOGIC;
+    signal in2_loc_49_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_49_ce0 : STD_LOGIC;
+    signal in2_loc_49_we0 : STD_LOGIC;
+    signal in2_loc_50_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_50_ce0 : STD_LOGIC;
+    signal in2_loc_50_we0 : STD_LOGIC;
+    signal in2_loc_51_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_51_ce0 : STD_LOGIC;
+    signal in2_loc_51_we0 : STD_LOGIC;
+    signal in2_loc_52_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_52_ce0 : STD_LOGIC;
+    signal in2_loc_52_we0 : STD_LOGIC;
+    signal in2_loc_53_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_53_ce0 : STD_LOGIC;
+    signal in2_loc_53_we0 : STD_LOGIC;
+    signal in2_loc_54_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_54_ce0 : STD_LOGIC;
+    signal in2_loc_54_we0 : STD_LOGIC;
+    signal in2_loc_55_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_55_ce0 : STD_LOGIC;
+    signal in2_loc_55_we0 : STD_LOGIC;
+    signal in2_loc_56_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_56_ce0 : STD_LOGIC;
+    signal in2_loc_56_we0 : STD_LOGIC;
+    signal in2_loc_57_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_57_ce0 : STD_LOGIC;
+    signal in2_loc_57_we0 : STD_LOGIC;
+    signal in2_loc_58_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_58_ce0 : STD_LOGIC;
+    signal in2_loc_58_we0 : STD_LOGIC;
+    signal in2_loc_59_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_59_ce0 : STD_LOGIC;
+    signal in2_loc_59_we0 : STD_LOGIC;
+    signal in2_loc_60_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_60_ce0 : STD_LOGIC;
+    signal in2_loc_60_we0 : STD_LOGIC;
+    signal in2_loc_61_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_61_ce0 : STD_LOGIC;
+    signal in2_loc_61_we0 : STD_LOGIC;
+    signal in2_loc_62_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_62_ce0 : STD_LOGIC;
+    signal in2_loc_62_we0 : STD_LOGIC;
+    signal in2_loc_63_address0 : STD_LOGIC_VECTOR (5 downto 0);
+    signal in2_loc_63_ce0 : STD_LOGIC;
+    signal in2_loc_63_we0 : STD_LOGIC;
+    signal out_loc_address0 : STD_LOGIC_VECTOR (11 downto 0);
+    signal out_loc_ce0 : STD_LOGIC;
+    signal out_loc_ce1 : STD_LOGIC;
+    signal out_loc_we1 : STD_LOGIC;
+    signal out_loc_d1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_phi_mux_i_0_phi_fu_3333_p4 : STD_LOGIC_VECTOR (30 downto 0);
+    signal ap_block_pp2_stage0 : BOOLEAN;
+    signal zext_ln27_fu_3451_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln28_fu_3544_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln38_fu_3680_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal zext_ln42_fu_4351_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_8_fu_3397_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_fu_3407_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal empty_7_fu_3416_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp3_stage0_01001 : BOOLEAN;
+    signal grp_fu_3614_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal grp_fu_3614_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal icmp_ln33_fu_3637_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal i_fu_3631_p2 : STD_LOGIC_VECTOR (30 downto 0);
+    signal trunc_ln38_fu_3658_p1 : STD_LOGIC_VECTOR (7 downto 0);
+    signal tmp_cast_fu_3662_p3 : STD_LOGIC_VECTOR (13 downto 0);
+    signal trunc_ln38_1_fu_3670_p1 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_64_fu_3674_p2 : STD_LOGIC_VECTOR (13 downto 0);
+    signal add_ln38_fu_4043_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_1_fu_4048_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_5_fu_4142_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_8_fu_4151_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_11_fu_4160_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_9_fu_4155_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_12_fu_4164_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_6_fu_4146_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_13_fu_4169_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_16_fu_4181_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_17_fu_4185_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_20_fu_4190_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_23_fu_4200_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_24_fu_4204_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_27_fu_4209_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_21_fu_4194_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_28_fu_4213_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_14_fu_4175_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_29_fu_4219_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_32_fu_4231_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_33_fu_4235_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_36_fu_4240_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_39_fu_4250_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_42_fu_4259_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_40_fu_4254_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_43_fu_4263_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_37_fu_4244_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_44_fu_4268_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_47_fu_4280_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_48_fu_4284_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_51_fu_4289_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_54_fu_4299_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_58_fu_4308_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_55_fu_4303_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_59_fu_4312_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_52_fu_4293_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_60_fu_4317_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal add_ln38_62_fu_4329_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (27 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal ap_idle_pp1 : STD_LOGIC;
+    signal ap_enable_pp1 : STD_LOGIC;
+    signal ap_idle_pp2 : STD_LOGIC;
+    signal ap_enable_pp2 : STD_LOGIC;
+    signal ap_idle_pp3 : STD_LOGIC;
+    signal ap_enable_pp3 : STD_LOGIC;
+
+    component mmult_mul_32ns_32bkb IS
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        din0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        din1 : IN STD_LOGIC_VECTOR (31 downto 0);
+        ce : IN STD_LOGIC;
+        dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
+    end component;
+
+
+    component mmult_mul_32s_32scud IS
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        din0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        din1 : IN STD_LOGIC_VECTOR (31 downto 0);
+        ce : IN STD_LOGIC;
+        dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_loc_0 IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (5 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_out_loc IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        address1 : IN STD_LOGIC_VECTOR (11 downto 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_params_s_axi IS
+    generic (
+        C_S_AXI_ADDR_WIDTH : INTEGER;
+        C_S_AXI_DATA_WIDTH : INTEGER );
+    port (
+        AWVALID : IN STD_LOGIC;
+        AWREADY : OUT STD_LOGIC;
+        AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        WVALID : IN STD_LOGIC;
+        WREADY : OUT STD_LOGIC;
+        WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
+        ARVALID : IN STD_LOGIC;
+        ARREADY : OUT STD_LOGIC;
+        ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
+        RVALID : OUT STD_LOGIC;
+        RREADY : IN STD_LOGIC;
+        RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
+        RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : OUT STD_LOGIC;
+        BREADY : IN STD_LOGIC;
+        BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        ap_start : OUT STD_LOGIC;
+        interrupt : OUT STD_LOGIC;
+        ap_ready : IN STD_LOGIC;
+        ap_done : IN STD_LOGIC;
+        ap_idle : IN STD_LOGIC;
+        in1 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        in2 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        out_r : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dim : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+    component mmult_in1_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_in2_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+    component mmult_out_mem_m_axi IS
+    generic (
+        CONSERVATIVE : INTEGER;
+        USER_DW : INTEGER;
+        USER_AW : INTEGER;
+        USER_MAXREQS : INTEGER;
+        NUM_READ_OUTSTANDING : INTEGER;
+        NUM_WRITE_OUTSTANDING : INTEGER;
+        MAX_READ_BURST_LENGTH : INTEGER;
+        MAX_WRITE_BURST_LENGTH : INTEGER;
+        C_M_AXI_ID_WIDTH : INTEGER;
+        C_M_AXI_ADDR_WIDTH : INTEGER;
+        C_M_AXI_DATA_WIDTH : INTEGER;
+        C_M_AXI_AWUSER_WIDTH : INTEGER;
+        C_M_AXI_ARUSER_WIDTH : INTEGER;
+        C_M_AXI_WUSER_WIDTH : INTEGER;
+        C_M_AXI_RUSER_WIDTH : INTEGER;
+        C_M_AXI_BUSER_WIDTH : INTEGER;
+        C_USER_VALUE : INTEGER;
+        C_PROT_VALUE : INTEGER;
+        C_CACHE_VALUE : INTEGER );
+    port (
+        AWVALID : OUT STD_LOGIC;
+        AWREADY : IN STD_LOGIC;
+        AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        WVALID : OUT STD_LOGIC;
+        WREADY : IN STD_LOGIC;
+        WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST : OUT STD_LOGIC;
+        WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
+        ARVALID : OUT STD_LOGIC;
+        ARREADY : IN STD_LOGIC;
+        ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
+        ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
+        ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
+        ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
+        ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        RVALID : IN STD_LOGIC;
+        RREADY : OUT STD_LOGIC;
+        RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
+        RLAST : IN STD_LOGIC;
+        RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BVALID : IN STD_LOGIC;
+        BREADY : OUT STD_LOGIC;
+        BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
+        BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
+        BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
+        ACLK : IN STD_LOGIC;
+        ARESET : IN STD_LOGIC;
+        ACLK_EN : IN STD_LOGIC;
+        I_ARVALID : IN STD_LOGIC;
+        I_ARREADY : OUT STD_LOGIC;
+        I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_RVALID : OUT STD_LOGIC;
+        I_RREADY : IN STD_LOGIC;
+        I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_RLAST : OUT STD_LOGIC;
+        I_AWVALID : IN STD_LOGIC;
+        I_AWREADY : OUT STD_LOGIC;
+        I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
+        I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
+        I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_WVALID : IN STD_LOGIC;
+        I_WREADY : OUT STD_LOGIC;
+        I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
+        I_WLAST : IN STD_LOGIC;
+        I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
+        I_BVALID : OUT STD_LOGIC;
+        I_BREADY : IN STD_LOGIC;
+        I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
+        I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
+        I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
+    end component;
+
+
+
+begin
+    mmult_params_s_axi_U : component mmult_params_s_axi
+    generic map (
+        C_S_AXI_ADDR_WIDTH => C_S_AXI_PARAMS_ADDR_WIDTH,
+        C_S_AXI_DATA_WIDTH => C_S_AXI_PARAMS_DATA_WIDTH)
+    port map (
+        AWVALID => s_axi_params_AWVALID,
+        AWREADY => s_axi_params_AWREADY,
+        AWADDR => s_axi_params_AWADDR,
+        WVALID => s_axi_params_WVALID,
+        WREADY => s_axi_params_WREADY,
+        WDATA => s_axi_params_WDATA,
+        WSTRB => s_axi_params_WSTRB,
+        ARVALID => s_axi_params_ARVALID,
+        ARREADY => s_axi_params_ARREADY,
+        ARADDR => s_axi_params_ARADDR,
+        RVALID => s_axi_params_RVALID,
+        RREADY => s_axi_params_RREADY,
+        RDATA => s_axi_params_RDATA,
+        RRESP => s_axi_params_RRESP,
+        BVALID => s_axi_params_BVALID,
+        BREADY => s_axi_params_BREADY,
+        BRESP => s_axi_params_BRESP,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        ap_start => ap_start,
+        interrupt => interrupt,
+        ap_ready => ap_ready,
+        ap_done => ap_done,
+        ap_idle => ap_idle,
+        in1 => in1,
+        in2 => in2,
+        out_r => out_r,
+        dim => dim);
+
+    mmult_in1_mem_m_axi_U : component mmult_in1_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN1_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN1_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN1_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN1_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN1_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN1_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN1_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN1_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN1_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN1_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN1_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in1_mem_AWVALID,
+        AWREADY => m_axi_in1_mem_AWREADY,
+        AWADDR => m_axi_in1_mem_AWADDR,
+        AWID => m_axi_in1_mem_AWID,
+        AWLEN => m_axi_in1_mem_AWLEN,
+        AWSIZE => m_axi_in1_mem_AWSIZE,
+        AWBURST => m_axi_in1_mem_AWBURST,
+        AWLOCK => m_axi_in1_mem_AWLOCK,
+        AWCACHE => m_axi_in1_mem_AWCACHE,
+        AWPROT => m_axi_in1_mem_AWPROT,
+        AWQOS => m_axi_in1_mem_AWQOS,
+        AWREGION => m_axi_in1_mem_AWREGION,
+        AWUSER => m_axi_in1_mem_AWUSER,
+        WVALID => m_axi_in1_mem_WVALID,
+        WREADY => m_axi_in1_mem_WREADY,
+        WDATA => m_axi_in1_mem_WDATA,
+        WSTRB => m_axi_in1_mem_WSTRB,
+        WLAST => m_axi_in1_mem_WLAST,
+        WID => m_axi_in1_mem_WID,
+        WUSER => m_axi_in1_mem_WUSER,
+        ARVALID => m_axi_in1_mem_ARVALID,
+        ARREADY => m_axi_in1_mem_ARREADY,
+        ARADDR => m_axi_in1_mem_ARADDR,
+        ARID => m_axi_in1_mem_ARID,
+        ARLEN => m_axi_in1_mem_ARLEN,
+        ARSIZE => m_axi_in1_mem_ARSIZE,
+        ARBURST => m_axi_in1_mem_ARBURST,
+        ARLOCK => m_axi_in1_mem_ARLOCK,
+        ARCACHE => m_axi_in1_mem_ARCACHE,
+        ARPROT => m_axi_in1_mem_ARPROT,
+        ARQOS => m_axi_in1_mem_ARQOS,
+        ARREGION => m_axi_in1_mem_ARREGION,
+        ARUSER => m_axi_in1_mem_ARUSER,
+        RVALID => m_axi_in1_mem_RVALID,
+        RREADY => m_axi_in1_mem_RREADY,
+        RDATA => m_axi_in1_mem_RDATA,
+        RLAST => m_axi_in1_mem_RLAST,
+        RID => m_axi_in1_mem_RID,
+        RUSER => m_axi_in1_mem_RUSER,
+        RRESP => m_axi_in1_mem_RRESP,
+        BVALID => m_axi_in1_mem_BVALID,
+        BREADY => m_axi_in1_mem_BREADY,
+        BRESP => m_axi_in1_mem_BRESP,
+        BID => m_axi_in1_mem_BID,
+        BUSER => m_axi_in1_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in1_mem_ARVALID,
+        I_ARREADY => in1_mem_ARREADY,
+        I_ARADDR => in1_mem_ARADDR,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in1_mem_RVALID,
+        I_RREADY => in1_mem_RREADY,
+        I_RDATA => in1_mem_RDATA,
+        I_RID => in1_mem_RID,
+        I_RUSER => in1_mem_RUSER,
+        I_RRESP => in1_mem_RRESP,
+        I_RLAST => in1_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in1_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in1_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in1_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in1_mem_BRESP,
+        I_BID => in1_mem_BID,
+        I_BUSER => in1_mem_BUSER);
+
+    mmult_in2_mem_m_axi_U : component mmult_in2_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_IN2_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_IN2_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_IN2_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_IN2_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_IN2_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_IN2_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_IN2_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_IN2_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_IN2_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_IN2_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_IN2_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_in2_mem_AWVALID,
+        AWREADY => m_axi_in2_mem_AWREADY,
+        AWADDR => m_axi_in2_mem_AWADDR,
+        AWID => m_axi_in2_mem_AWID,
+        AWLEN => m_axi_in2_mem_AWLEN,
+        AWSIZE => m_axi_in2_mem_AWSIZE,
+        AWBURST => m_axi_in2_mem_AWBURST,
+        AWLOCK => m_axi_in2_mem_AWLOCK,
+        AWCACHE => m_axi_in2_mem_AWCACHE,
+        AWPROT => m_axi_in2_mem_AWPROT,
+        AWQOS => m_axi_in2_mem_AWQOS,
+        AWREGION => m_axi_in2_mem_AWREGION,
+        AWUSER => m_axi_in2_mem_AWUSER,
+        WVALID => m_axi_in2_mem_WVALID,
+        WREADY => m_axi_in2_mem_WREADY,
+        WDATA => m_axi_in2_mem_WDATA,
+        WSTRB => m_axi_in2_mem_WSTRB,
+        WLAST => m_axi_in2_mem_WLAST,
+        WID => m_axi_in2_mem_WID,
+        WUSER => m_axi_in2_mem_WUSER,
+        ARVALID => m_axi_in2_mem_ARVALID,
+        ARREADY => m_axi_in2_mem_ARREADY,
+        ARADDR => m_axi_in2_mem_ARADDR,
+        ARID => m_axi_in2_mem_ARID,
+        ARLEN => m_axi_in2_mem_ARLEN,
+        ARSIZE => m_axi_in2_mem_ARSIZE,
+        ARBURST => m_axi_in2_mem_ARBURST,
+        ARLOCK => m_axi_in2_mem_ARLOCK,
+        ARCACHE => m_axi_in2_mem_ARCACHE,
+        ARPROT => m_axi_in2_mem_ARPROT,
+        ARQOS => m_axi_in2_mem_ARQOS,
+        ARREGION => m_axi_in2_mem_ARREGION,
+        ARUSER => m_axi_in2_mem_ARUSER,
+        RVALID => m_axi_in2_mem_RVALID,
+        RREADY => m_axi_in2_mem_RREADY,
+        RDATA => m_axi_in2_mem_RDATA,
+        RLAST => m_axi_in2_mem_RLAST,
+        RID => m_axi_in2_mem_RID,
+        RUSER => m_axi_in2_mem_RUSER,
+        RRESP => m_axi_in2_mem_RRESP,
+        BVALID => m_axi_in2_mem_BVALID,
+        BREADY => m_axi_in2_mem_BREADY,
+        BRESP => m_axi_in2_mem_BRESP,
+        BID => m_axi_in2_mem_BID,
+        BUSER => m_axi_in2_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => in2_mem_ARVALID,
+        I_ARREADY => in2_mem_ARREADY,
+        I_ARADDR => in2_mem_addr_reg_4389,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_1000,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => in2_mem_RVALID,
+        I_RREADY => in2_mem_RREADY,
+        I_RDATA => in2_mem_RDATA,
+        I_RID => in2_mem_RID,
+        I_RUSER => in2_mem_RUSER,
+        I_RRESP => in2_mem_RRESP,
+        I_RLAST => in2_mem_RLAST,
+        I_AWVALID => ap_const_logic_0,
+        I_AWREADY => in2_mem_AWREADY,
+        I_AWADDR => ap_const_lv32_0,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_0,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => ap_const_logic_0,
+        I_WREADY => in2_mem_WREADY,
+        I_WDATA => ap_const_lv32_0,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_0,
+        I_BVALID => in2_mem_BVALID,
+        I_BREADY => ap_const_logic_0,
+        I_BRESP => in2_mem_BRESP,
+        I_BID => in2_mem_BID,
+        I_BUSER => in2_mem_BUSER);
+
+    mmult_out_mem_m_axi_U : component mmult_out_mem_m_axi
+    generic map (
+        CONSERVATIVE => 0,
+        USER_DW => 32,
+        USER_AW => 32,
+        USER_MAXREQS => 5,
+        NUM_READ_OUTSTANDING => 16,
+        NUM_WRITE_OUTSTANDING => 16,
+        MAX_READ_BURST_LENGTH => 16,
+        MAX_WRITE_BURST_LENGTH => 16,
+        C_M_AXI_ID_WIDTH => C_M_AXI_OUT_MEM_ID_WIDTH,
+        C_M_AXI_ADDR_WIDTH => C_M_AXI_OUT_MEM_ADDR_WIDTH,
+        C_M_AXI_DATA_WIDTH => C_M_AXI_OUT_MEM_DATA_WIDTH,
+        C_M_AXI_AWUSER_WIDTH => C_M_AXI_OUT_MEM_AWUSER_WIDTH,
+        C_M_AXI_ARUSER_WIDTH => C_M_AXI_OUT_MEM_ARUSER_WIDTH,
+        C_M_AXI_WUSER_WIDTH => C_M_AXI_OUT_MEM_WUSER_WIDTH,
+        C_M_AXI_RUSER_WIDTH => C_M_AXI_OUT_MEM_RUSER_WIDTH,
+        C_M_AXI_BUSER_WIDTH => C_M_AXI_OUT_MEM_BUSER_WIDTH,
+        C_USER_VALUE => C_M_AXI_OUT_MEM_USER_VALUE,
+        C_PROT_VALUE => C_M_AXI_OUT_MEM_PROT_VALUE,
+        C_CACHE_VALUE => C_M_AXI_OUT_MEM_CACHE_VALUE)
+    port map (
+        AWVALID => m_axi_out_mem_AWVALID,
+        AWREADY => m_axi_out_mem_AWREADY,
+        AWADDR => m_axi_out_mem_AWADDR,
+        AWID => m_axi_out_mem_AWID,
+        AWLEN => m_axi_out_mem_AWLEN,
+        AWSIZE => m_axi_out_mem_AWSIZE,
+        AWBURST => m_axi_out_mem_AWBURST,
+        AWLOCK => m_axi_out_mem_AWLOCK,
+        AWCACHE => m_axi_out_mem_AWCACHE,
+        AWPROT => m_axi_out_mem_AWPROT,
+        AWQOS => m_axi_out_mem_AWQOS,
+        AWREGION => m_axi_out_mem_AWREGION,
+        AWUSER => m_axi_out_mem_AWUSER,
+        WVALID => m_axi_out_mem_WVALID,
+        WREADY => m_axi_out_mem_WREADY,
+        WDATA => m_axi_out_mem_WDATA,
+        WSTRB => m_axi_out_mem_WSTRB,
+        WLAST => m_axi_out_mem_WLAST,
+        WID => m_axi_out_mem_WID,
+        WUSER => m_axi_out_mem_WUSER,
+        ARVALID => m_axi_out_mem_ARVALID,
+        ARREADY => m_axi_out_mem_ARREADY,
+        ARADDR => m_axi_out_mem_ARADDR,
+        ARID => m_axi_out_mem_ARID,
+        ARLEN => m_axi_out_mem_ARLEN,
+        ARSIZE => m_axi_out_mem_ARSIZE,
+        ARBURST => m_axi_out_mem_ARBURST,
+        ARLOCK => m_axi_out_mem_ARLOCK,
+        ARCACHE => m_axi_out_mem_ARCACHE,
+        ARPROT => m_axi_out_mem_ARPROT,
+        ARQOS => m_axi_out_mem_ARQOS,
+        ARREGION => m_axi_out_mem_ARREGION,
+        ARUSER => m_axi_out_mem_ARUSER,
+        RVALID => m_axi_out_mem_RVALID,
+        RREADY => m_axi_out_mem_RREADY,
+        RDATA => m_axi_out_mem_RDATA,
+        RLAST => m_axi_out_mem_RLAST,
+        RID => m_axi_out_mem_RID,
+        RUSER => m_axi_out_mem_RUSER,
+        RRESP => m_axi_out_mem_RRESP,
+        BVALID => m_axi_out_mem_BVALID,
+        BREADY => m_axi_out_mem_BREADY,
+        BRESP => m_axi_out_mem_BRESP,
+        BID => m_axi_out_mem_BID,
+        BUSER => m_axi_out_mem_BUSER,
+        ACLK => ap_clk,
+        ARESET => ap_rst_n_inv,
+        ACLK_EN => ap_const_logic_1,
+        I_ARVALID => ap_const_logic_0,
+        I_ARREADY => out_mem_ARREADY,
+        I_ARADDR => ap_const_lv32_0,
+        I_ARID => ap_const_lv1_0,
+        I_ARLEN => ap_const_lv32_0,
+        I_ARSIZE => ap_const_lv3_0,
+        I_ARLOCK => ap_const_lv2_0,
+        I_ARCACHE => ap_const_lv4_0,
+        I_ARQOS => ap_const_lv4_0,
+        I_ARPROT => ap_const_lv3_0,
+        I_ARUSER => ap_const_lv1_0,
+        I_ARBURST => ap_const_lv2_0,
+        I_ARREGION => ap_const_lv4_0,
+        I_RVALID => out_mem_RVALID,
+        I_RREADY => ap_const_logic_0,
+        I_RDATA => out_mem_RDATA,
+        I_RID => out_mem_RID,
+        I_RUSER => out_mem_RUSER,
+        I_RRESP => out_mem_RRESP,
+        I_RLAST => out_mem_RLAST,
+        I_AWVALID => out_mem_AWVALID,
+        I_AWREADY => out_mem_AWREADY,
+        I_AWADDR => out_mem_addr_reg_4383,
+        I_AWID => ap_const_lv1_0,
+        I_AWLEN => ap_const_lv32_1000,
+        I_AWSIZE => ap_const_lv3_0,
+        I_AWLOCK => ap_const_lv2_0,
+        I_AWCACHE => ap_const_lv4_0,
+        I_AWQOS => ap_const_lv4_0,
+        I_AWPROT => ap_const_lv3_0,
+        I_AWUSER => ap_const_lv1_0,
+        I_AWBURST => ap_const_lv2_0,
+        I_AWREGION => ap_const_lv4_0,
+        I_WVALID => out_mem_WVALID,
+        I_WREADY => out_mem_WREADY,
+        I_WDATA => reg_3362,
+        I_WID => ap_const_lv1_0,
+        I_WUSER => ap_const_lv1_0,
+        I_WLAST => ap_const_logic_0,
+        I_WSTRB => ap_const_lv4_F,
+        I_BVALID => out_mem_BVALID,
+        I_BREADY => out_mem_BREADY,
+        I_BRESP => out_mem_BRESP,
+        I_BID => out_mem_BID,
+        I_BUSER => out_mem_BUSER);
+
+    in1_loc_0_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_0_address0,
+        ce0 => in1_loc_0_ce0,
+        we0 => in1_loc_0_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_0_q0);
+
+    in1_loc_1_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_1_address0,
+        ce0 => in1_loc_1_ce0,
+        we0 => in1_loc_1_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_1_q0);
+
+    in1_loc_2_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_2_address0,
+        ce0 => in1_loc_2_ce0,
+        we0 => in1_loc_2_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_2_q0);
+
+    in1_loc_3_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_3_address0,
+        ce0 => in1_loc_3_ce0,
+        we0 => in1_loc_3_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_3_q0);
+
+    in1_loc_4_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_4_address0,
+        ce0 => in1_loc_4_ce0,
+        we0 => in1_loc_4_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_4_q0);
+
+    in1_loc_5_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_5_address0,
+        ce0 => in1_loc_5_ce0,
+        we0 => in1_loc_5_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_5_q0);
+
+    in1_loc_6_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_6_address0,
+        ce0 => in1_loc_6_ce0,
+        we0 => in1_loc_6_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_6_q0);
+
+    in1_loc_7_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_7_address0,
+        ce0 => in1_loc_7_ce0,
+        we0 => in1_loc_7_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_7_q0);
+
+    in1_loc_8_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_8_address0,
+        ce0 => in1_loc_8_ce0,
+        we0 => in1_loc_8_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_8_q0);
+
+    in1_loc_9_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_9_address0,
+        ce0 => in1_loc_9_ce0,
+        we0 => in1_loc_9_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_9_q0);
+
+    in1_loc_10_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_10_address0,
+        ce0 => in1_loc_10_ce0,
+        we0 => in1_loc_10_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_10_q0);
+
+    in1_loc_11_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_11_address0,
+        ce0 => in1_loc_11_ce0,
+        we0 => in1_loc_11_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_11_q0);
+
+    in1_loc_12_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_12_address0,
+        ce0 => in1_loc_12_ce0,
+        we0 => in1_loc_12_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_12_q0);
+
+    in1_loc_13_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_13_address0,
+        ce0 => in1_loc_13_ce0,
+        we0 => in1_loc_13_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_13_q0);
+
+    in1_loc_14_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_14_address0,
+        ce0 => in1_loc_14_ce0,
+        we0 => in1_loc_14_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_14_q0);
+
+    in1_loc_15_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_15_address0,
+        ce0 => in1_loc_15_ce0,
+        we0 => in1_loc_15_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_15_q0);
+
+    in1_loc_16_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_16_address0,
+        ce0 => in1_loc_16_ce0,
+        we0 => in1_loc_16_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_16_q0);
+
+    in1_loc_17_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_17_address0,
+        ce0 => in1_loc_17_ce0,
+        we0 => in1_loc_17_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_17_q0);
+
+    in1_loc_18_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_18_address0,
+        ce0 => in1_loc_18_ce0,
+        we0 => in1_loc_18_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_18_q0);
+
+    in1_loc_19_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_19_address0,
+        ce0 => in1_loc_19_ce0,
+        we0 => in1_loc_19_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_19_q0);
+
+    in1_loc_20_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_20_address0,
+        ce0 => in1_loc_20_ce0,
+        we0 => in1_loc_20_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_20_q0);
+
+    in1_loc_21_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_21_address0,
+        ce0 => in1_loc_21_ce0,
+        we0 => in1_loc_21_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_21_q0);
+
+    in1_loc_22_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_22_address0,
+        ce0 => in1_loc_22_ce0,
+        we0 => in1_loc_22_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_22_q0);
+
+    in1_loc_23_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_23_address0,
+        ce0 => in1_loc_23_ce0,
+        we0 => in1_loc_23_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_23_q0);
+
+    in1_loc_24_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_24_address0,
+        ce0 => in1_loc_24_ce0,
+        we0 => in1_loc_24_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_24_q0);
+
+    in1_loc_25_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_25_address0,
+        ce0 => in1_loc_25_ce0,
+        we0 => in1_loc_25_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_25_q0);
+
+    in1_loc_26_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_26_address0,
+        ce0 => in1_loc_26_ce0,
+        we0 => in1_loc_26_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_26_q0);
+
+    in1_loc_27_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_27_address0,
+        ce0 => in1_loc_27_ce0,
+        we0 => in1_loc_27_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_27_q0);
+
+    in1_loc_28_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_28_address0,
+        ce0 => in1_loc_28_ce0,
+        we0 => in1_loc_28_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_28_q0);
+
+    in1_loc_29_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_29_address0,
+        ce0 => in1_loc_29_ce0,
+        we0 => in1_loc_29_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_29_q0);
+
+    in1_loc_30_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_30_address0,
+        ce0 => in1_loc_30_ce0,
+        we0 => in1_loc_30_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_30_q0);
+
+    in1_loc_31_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_31_address0,
+        ce0 => in1_loc_31_ce0,
+        we0 => in1_loc_31_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_31_q0);
+
+    in1_loc_32_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_32_address0,
+        ce0 => in1_loc_32_ce0,
+        we0 => in1_loc_32_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_32_q0);
+
+    in1_loc_33_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_33_address0,
+        ce0 => in1_loc_33_ce0,
+        we0 => in1_loc_33_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_33_q0);
+
+    in1_loc_34_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_34_address0,
+        ce0 => in1_loc_34_ce0,
+        we0 => in1_loc_34_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_34_q0);
+
+    in1_loc_35_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_35_address0,
+        ce0 => in1_loc_35_ce0,
+        we0 => in1_loc_35_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_35_q0);
+
+    in1_loc_36_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_36_address0,
+        ce0 => in1_loc_36_ce0,
+        we0 => in1_loc_36_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_36_q0);
+
+    in1_loc_37_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_37_address0,
+        ce0 => in1_loc_37_ce0,
+        we0 => in1_loc_37_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_37_q0);
+
+    in1_loc_38_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_38_address0,
+        ce0 => in1_loc_38_ce0,
+        we0 => in1_loc_38_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_38_q0);
+
+    in1_loc_39_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_39_address0,
+        ce0 => in1_loc_39_ce0,
+        we0 => in1_loc_39_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_39_q0);
+
+    in1_loc_40_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_40_address0,
+        ce0 => in1_loc_40_ce0,
+        we0 => in1_loc_40_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_40_q0);
+
+    in1_loc_41_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_41_address0,
+        ce0 => in1_loc_41_ce0,
+        we0 => in1_loc_41_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_41_q0);
+
+    in1_loc_42_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_42_address0,
+        ce0 => in1_loc_42_ce0,
+        we0 => in1_loc_42_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_42_q0);
+
+    in1_loc_43_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_43_address0,
+        ce0 => in1_loc_43_ce0,
+        we0 => in1_loc_43_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_43_q0);
+
+    in1_loc_44_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_44_address0,
+        ce0 => in1_loc_44_ce0,
+        we0 => in1_loc_44_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_44_q0);
+
+    in1_loc_45_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_45_address0,
+        ce0 => in1_loc_45_ce0,
+        we0 => in1_loc_45_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_45_q0);
+
+    in1_loc_46_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_46_address0,
+        ce0 => in1_loc_46_ce0,
+        we0 => in1_loc_46_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_46_q0);
+
+    in1_loc_47_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_47_address0,
+        ce0 => in1_loc_47_ce0,
+        we0 => in1_loc_47_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_47_q0);
+
+    in1_loc_48_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_48_address0,
+        ce0 => in1_loc_48_ce0,
+        we0 => in1_loc_48_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_48_q0);
+
+    in1_loc_49_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_49_address0,
+        ce0 => in1_loc_49_ce0,
+        we0 => in1_loc_49_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_49_q0);
+
+    in1_loc_50_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_50_address0,
+        ce0 => in1_loc_50_ce0,
+        we0 => in1_loc_50_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_50_q0);
+
+    in1_loc_51_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_51_address0,
+        ce0 => in1_loc_51_ce0,
+        we0 => in1_loc_51_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_51_q0);
+
+    in1_loc_52_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_52_address0,
+        ce0 => in1_loc_52_ce0,
+        we0 => in1_loc_52_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_52_q0);
+
+    in1_loc_53_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_53_address0,
+        ce0 => in1_loc_53_ce0,
+        we0 => in1_loc_53_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_53_q0);
+
+    in1_loc_54_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_54_address0,
+        ce0 => in1_loc_54_ce0,
+        we0 => in1_loc_54_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_54_q0);
+
+    in1_loc_55_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_55_address0,
+        ce0 => in1_loc_55_ce0,
+        we0 => in1_loc_55_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_55_q0);
+
+    in1_loc_56_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_56_address0,
+        ce0 => in1_loc_56_ce0,
+        we0 => in1_loc_56_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_56_q0);
+
+    in1_loc_57_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_57_address0,
+        ce0 => in1_loc_57_ce0,
+        we0 => in1_loc_57_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_57_q0);
+
+    in1_loc_58_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_58_address0,
+        ce0 => in1_loc_58_ce0,
+        we0 => in1_loc_58_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_58_q0);
+
+    in1_loc_59_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_59_address0,
+        ce0 => in1_loc_59_ce0,
+        we0 => in1_loc_59_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_59_q0);
+
+    in1_loc_60_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_60_address0,
+        ce0 => in1_loc_60_ce0,
+        we0 => in1_loc_60_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_60_q0);
+
+    in1_loc_61_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_61_address0,
+        ce0 => in1_loc_61_ce0,
+        we0 => in1_loc_61_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_61_q0);
+
+    in1_loc_62_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_62_address0,
+        ce0 => in1_loc_62_ce0,
+        we0 => in1_loc_62_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_62_q0);
+
+    in1_loc_63_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in1_loc_63_address0,
+        ce0 => in1_loc_63_ce0,
+        we0 => in1_loc_63_we0,
+        d0 => in1_mem_addr_read_reg_4413,
+        q0 => in1_loc_63_q0);
+
+    in2_loc_0_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_0_address0,
+        ce0 => in2_loc_0_ce0,
+        we0 => in2_loc_0_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_0_q0);
+
+    in2_loc_1_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_1_address0,
+        ce0 => in2_loc_1_ce0,
+        we0 => in2_loc_1_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_1_q0);
+
+    in2_loc_2_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_2_address0,
+        ce0 => in2_loc_2_ce0,
+        we0 => in2_loc_2_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_2_q0);
+
+    in2_loc_3_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_3_address0,
+        ce0 => in2_loc_3_ce0,
+        we0 => in2_loc_3_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_3_q0);
+
+    in2_loc_4_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_4_address0,
+        ce0 => in2_loc_4_ce0,
+        we0 => in2_loc_4_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_4_q0);
+
+    in2_loc_5_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_5_address0,
+        ce0 => in2_loc_5_ce0,
+        we0 => in2_loc_5_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_5_q0);
+
+    in2_loc_6_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_6_address0,
+        ce0 => in2_loc_6_ce0,
+        we0 => in2_loc_6_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_6_q0);
+
+    in2_loc_7_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_7_address0,
+        ce0 => in2_loc_7_ce0,
+        we0 => in2_loc_7_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_7_q0);
+
+    in2_loc_8_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_8_address0,
+        ce0 => in2_loc_8_ce0,
+        we0 => in2_loc_8_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_8_q0);
+
+    in2_loc_9_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_9_address0,
+        ce0 => in2_loc_9_ce0,
+        we0 => in2_loc_9_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_9_q0);
+
+    in2_loc_10_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_10_address0,
+        ce0 => in2_loc_10_ce0,
+        we0 => in2_loc_10_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_10_q0);
+
+    in2_loc_11_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_11_address0,
+        ce0 => in2_loc_11_ce0,
+        we0 => in2_loc_11_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_11_q0);
+
+    in2_loc_12_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_12_address0,
+        ce0 => in2_loc_12_ce0,
+        we0 => in2_loc_12_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_12_q0);
+
+    in2_loc_13_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_13_address0,
+        ce0 => in2_loc_13_ce0,
+        we0 => in2_loc_13_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_13_q0);
+
+    in2_loc_14_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_14_address0,
+        ce0 => in2_loc_14_ce0,
+        we0 => in2_loc_14_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_14_q0);
+
+    in2_loc_15_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_15_address0,
+        ce0 => in2_loc_15_ce0,
+        we0 => in2_loc_15_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_15_q0);
+
+    in2_loc_16_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_16_address0,
+        ce0 => in2_loc_16_ce0,
+        we0 => in2_loc_16_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_16_q0);
+
+    in2_loc_17_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_17_address0,
+        ce0 => in2_loc_17_ce0,
+        we0 => in2_loc_17_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_17_q0);
+
+    in2_loc_18_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_18_address0,
+        ce0 => in2_loc_18_ce0,
+        we0 => in2_loc_18_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_18_q0);
+
+    in2_loc_19_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_19_address0,
+        ce0 => in2_loc_19_ce0,
+        we0 => in2_loc_19_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_19_q0);
+
+    in2_loc_20_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_20_address0,
+        ce0 => in2_loc_20_ce0,
+        we0 => in2_loc_20_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_20_q0);
+
+    in2_loc_21_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_21_address0,
+        ce0 => in2_loc_21_ce0,
+        we0 => in2_loc_21_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_21_q0);
+
+    in2_loc_22_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_22_address0,
+        ce0 => in2_loc_22_ce0,
+        we0 => in2_loc_22_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_22_q0);
+
+    in2_loc_23_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_23_address0,
+        ce0 => in2_loc_23_ce0,
+        we0 => in2_loc_23_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_23_q0);
+
+    in2_loc_24_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_24_address0,
+        ce0 => in2_loc_24_ce0,
+        we0 => in2_loc_24_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_24_q0);
+
+    in2_loc_25_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_25_address0,
+        ce0 => in2_loc_25_ce0,
+        we0 => in2_loc_25_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_25_q0);
+
+    in2_loc_26_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_26_address0,
+        ce0 => in2_loc_26_ce0,
+        we0 => in2_loc_26_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_26_q0);
+
+    in2_loc_27_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_27_address0,
+        ce0 => in2_loc_27_ce0,
+        we0 => in2_loc_27_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_27_q0);
+
+    in2_loc_28_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_28_address0,
+        ce0 => in2_loc_28_ce0,
+        we0 => in2_loc_28_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_28_q0);
+
+    in2_loc_29_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_29_address0,
+        ce0 => in2_loc_29_ce0,
+        we0 => in2_loc_29_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_29_q0);
+
+    in2_loc_30_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_30_address0,
+        ce0 => in2_loc_30_ce0,
+        we0 => in2_loc_30_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_30_q0);
+
+    in2_loc_31_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_31_address0,
+        ce0 => in2_loc_31_ce0,
+        we0 => in2_loc_31_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_31_q0);
+
+    in2_loc_32_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_32_address0,
+        ce0 => in2_loc_32_ce0,
+        we0 => in2_loc_32_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_32_q0);
+
+    in2_loc_33_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_33_address0,
+        ce0 => in2_loc_33_ce0,
+        we0 => in2_loc_33_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_33_q0);
+
+    in2_loc_34_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_34_address0,
+        ce0 => in2_loc_34_ce0,
+        we0 => in2_loc_34_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_34_q0);
+
+    in2_loc_35_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_35_address0,
+        ce0 => in2_loc_35_ce0,
+        we0 => in2_loc_35_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_35_q0);
+
+    in2_loc_36_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_36_address0,
+        ce0 => in2_loc_36_ce0,
+        we0 => in2_loc_36_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_36_q0);
+
+    in2_loc_37_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_37_address0,
+        ce0 => in2_loc_37_ce0,
+        we0 => in2_loc_37_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_37_q0);
+
+    in2_loc_38_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_38_address0,
+        ce0 => in2_loc_38_ce0,
+        we0 => in2_loc_38_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_38_q0);
+
+    in2_loc_39_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_39_address0,
+        ce0 => in2_loc_39_ce0,
+        we0 => in2_loc_39_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_39_q0);
+
+    in2_loc_40_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_40_address0,
+        ce0 => in2_loc_40_ce0,
+        we0 => in2_loc_40_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_40_q0);
+
+    in2_loc_41_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_41_address0,
+        ce0 => in2_loc_41_ce0,
+        we0 => in2_loc_41_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_41_q0);
+
+    in2_loc_42_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_42_address0,
+        ce0 => in2_loc_42_ce0,
+        we0 => in2_loc_42_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_42_q0);
+
+    in2_loc_43_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_43_address0,
+        ce0 => in2_loc_43_ce0,
+        we0 => in2_loc_43_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_43_q0);
+
+    in2_loc_44_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_44_address0,
+        ce0 => in2_loc_44_ce0,
+        we0 => in2_loc_44_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_44_q0);
+
+    in2_loc_45_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_45_address0,
+        ce0 => in2_loc_45_ce0,
+        we0 => in2_loc_45_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_45_q0);
+
+    in2_loc_46_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_46_address0,
+        ce0 => in2_loc_46_ce0,
+        we0 => in2_loc_46_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_46_q0);
+
+    in2_loc_47_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_47_address0,
+        ce0 => in2_loc_47_ce0,
+        we0 => in2_loc_47_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_47_q0);
+
+    in2_loc_48_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_48_address0,
+        ce0 => in2_loc_48_ce0,
+        we0 => in2_loc_48_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_48_q0);
+
+    in2_loc_49_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_49_address0,
+        ce0 => in2_loc_49_ce0,
+        we0 => in2_loc_49_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_49_q0);
+
+    in2_loc_50_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_50_address0,
+        ce0 => in2_loc_50_ce0,
+        we0 => in2_loc_50_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_50_q0);
+
+    in2_loc_51_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_51_address0,
+        ce0 => in2_loc_51_ce0,
+        we0 => in2_loc_51_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_51_q0);
+
+    in2_loc_52_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_52_address0,
+        ce0 => in2_loc_52_ce0,
+        we0 => in2_loc_52_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_52_q0);
+
+    in2_loc_53_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_53_address0,
+        ce0 => in2_loc_53_ce0,
+        we0 => in2_loc_53_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_53_q0);
+
+    in2_loc_54_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_54_address0,
+        ce0 => in2_loc_54_ce0,
+        we0 => in2_loc_54_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_54_q0);
+
+    in2_loc_55_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_55_address0,
+        ce0 => in2_loc_55_ce0,
+        we0 => in2_loc_55_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_55_q0);
+
+    in2_loc_56_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_56_address0,
+        ce0 => in2_loc_56_ce0,
+        we0 => in2_loc_56_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_56_q0);
+
+    in2_loc_57_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_57_address0,
+        ce0 => in2_loc_57_ce0,
+        we0 => in2_loc_57_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_57_q0);
+
+    in2_loc_58_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_58_address0,
+        ce0 => in2_loc_58_ce0,
+        we0 => in2_loc_58_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_58_q0);
+
+    in2_loc_59_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_59_address0,
+        ce0 => in2_loc_59_ce0,
+        we0 => in2_loc_59_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_59_q0);
+
+    in2_loc_60_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_60_address0,
+        ce0 => in2_loc_60_ce0,
+        we0 => in2_loc_60_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_60_q0);
+
+    in2_loc_61_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_61_address0,
+        ce0 => in2_loc_61_ce0,
+        we0 => in2_loc_61_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_61_q0);
+
+    in2_loc_62_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_62_address0,
+        ce0 => in2_loc_62_ce0,
+        we0 => in2_loc_62_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_62_q0);
+
+    in2_loc_63_U : component mmult_in1_loc_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 64,
+        AddressWidth => 6)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => in2_loc_63_address0,
+        ce0 => in2_loc_63_ce0,
+        we0 => in2_loc_63_we0,
+        d0 => in2_mem_addr_read_reg_4499,
+        q0 => in2_loc_63_q0);
+
+    out_loc_U : component mmult_out_loc
+    generic map (
+        DataWidth => 32,
+        AddressRange => 4096,
+        AddressWidth => 12)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        address0 => out_loc_address0,
+        ce0 => out_loc_ce0,
+        q0 => out_loc_q0,
+        address1 => out_loc_addr_reg_4598_pp2_iter7_reg,
+        ce1 => out_loc_ce1,
+        we1 => out_loc_we1,
+        d1 => out_loc_d1);
+
+    mmult_mul_32ns_32bkb_U1 : component mmult_mul_32ns_32bkb
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 64)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => grp_fu_3614_p0,
+        din1 => grp_fu_3614_p1,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3614_p2);
+
+    mmult_mul_32s_32scud_U2 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_0_load_reg_5425,
+        din1 => in1_loc_0_load_reg_5105,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3787_p2);
+
+    mmult_mul_32s_32scud_U3 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_1_load_reg_5430,
+        din1 => in1_loc_1_load_reg_5110,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3791_p2);
+
+    mmult_mul_32s_32scud_U4 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_2_load_reg_5435,
+        din1 => in1_loc_2_load_reg_5115,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3795_p2);
+
+    mmult_mul_32s_32scud_U5 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_3_load_reg_5440,
+        din1 => in1_loc_3_load_reg_5120,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3799_p2);
+
+    mmult_mul_32s_32scud_U6 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_4_load_reg_5445,
+        din1 => in1_loc_4_load_reg_5125,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3803_p2);
+
+    mmult_mul_32s_32scud_U7 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_5_load_reg_5450,
+        din1 => in1_loc_5_load_reg_5130,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3807_p2);
+
+    mmult_mul_32s_32scud_U8 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_6_load_reg_5455,
+        din1 => in1_loc_6_load_reg_5135,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3811_p2);
+
+    mmult_mul_32s_32scud_U9 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_7_load_reg_5460,
+        din1 => in1_loc_7_load_reg_5140,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3815_p2);
+
+    mmult_mul_32s_32scud_U10 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_8_load_reg_5465,
+        din1 => in1_loc_8_load_reg_5145,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3819_p2);
+
+    mmult_mul_32s_32scud_U11 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_11_load_reg_5480,
+        din1 => in1_loc_11_load_reg_5160,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3823_p2);
+
+    mmult_mul_32s_32scud_U12 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_12_load_reg_5485,
+        din1 => in1_loc_12_load_reg_5165,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3827_p2);
+
+    mmult_mul_32s_32scud_U13 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_15_load_reg_5500,
+        din1 => in1_loc_15_load_reg_5180,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3831_p2);
+
+    mmult_mul_32s_32scud_U14 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_16_load_reg_5505,
+        din1 => in1_loc_16_load_reg_5185,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3835_p2);
+
+    mmult_mul_32s_32scud_U15 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_19_load_reg_5520,
+        din1 => in1_loc_19_load_reg_5200,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3839_p2);
+
+    mmult_mul_32s_32scud_U16 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_20_load_reg_5525,
+        din1 => in1_loc_20_load_reg_5205,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3843_p2);
+
+    mmult_mul_32s_32scud_U17 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_21_load_reg_5530,
+        din1 => in1_loc_21_load_reg_5210,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3847_p2);
+
+    mmult_mul_32s_32scud_U18 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_22_load_reg_5535,
+        din1 => in1_loc_22_load_reg_5215,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3851_p2);
+
+    mmult_mul_32s_32scud_U19 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_23_load_reg_5540,
+        din1 => in1_loc_23_load_reg_5220,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3855_p2);
+
+    mmult_mul_32s_32scud_U20 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_24_load_reg_5545,
+        din1 => in1_loc_24_load_reg_5225,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3859_p2);
+
+    mmult_mul_32s_32scud_U21 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_27_load_reg_5560,
+        din1 => in1_loc_27_load_reg_5240,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3863_p2);
+
+    mmult_mul_32s_32scud_U22 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_28_load_reg_5565,
+        din1 => in1_loc_28_load_reg_5245,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3867_p2);
+
+    mmult_mul_32s_32scud_U23 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_29_load_reg_5570,
+        din1 => in1_loc_29_load_reg_5250,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3871_p2);
+
+    mmult_mul_32s_32scud_U24 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_30_load_reg_5575,
+        din1 => in1_loc_30_load_reg_5255,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3875_p2);
+
+    mmult_mul_32s_32scud_U25 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_31_load_reg_5580,
+        din1 => in1_loc_31_load_reg_5260,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3879_p2);
+
+    mmult_mul_32s_32scud_U26 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_32_load_reg_5585,
+        din1 => in1_loc_32_load_reg_5265,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3883_p2);
+
+    mmult_mul_32s_32scud_U27 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_35_load_reg_5600,
+        din1 => in1_loc_35_load_reg_5280,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3887_p2);
+
+    mmult_mul_32s_32scud_U28 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_36_load_reg_5605,
+        din1 => in1_loc_36_load_reg_5285,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3891_p2);
+
+    mmult_mul_32s_32scud_U29 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_37_load_reg_5610,
+        din1 => in1_loc_37_load_reg_5290,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3895_p2);
+
+    mmult_mul_32s_32scud_U30 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_38_load_reg_5615,
+        din1 => in1_loc_38_load_reg_5295,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3899_p2);
+
+    mmult_mul_32s_32scud_U31 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_39_load_reg_5620,
+        din1 => in1_loc_39_load_reg_5300,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3903_p2);
+
+    mmult_mul_32s_32scud_U32 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_40_load_reg_5625,
+        din1 => in1_loc_40_load_reg_5305,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3907_p2);
+
+    mmult_mul_32s_32scud_U33 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_43_load_reg_5640,
+        din1 => in1_loc_43_load_reg_5320,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3911_p2);
+
+    mmult_mul_32s_32scud_U34 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_44_load_reg_5645,
+        din1 => in1_loc_44_load_reg_5325,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3915_p2);
+
+    mmult_mul_32s_32scud_U35 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_47_load_reg_5660,
+        din1 => in1_loc_47_load_reg_5340,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3919_p2);
+
+    mmult_mul_32s_32scud_U36 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_48_load_reg_5665,
+        din1 => in1_loc_48_load_reg_5345,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3923_p2);
+
+    mmult_mul_32s_32scud_U37 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_51_load_reg_5680,
+        din1 => in1_loc_51_load_reg_5360,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3927_p2);
+
+    mmult_mul_32s_32scud_U38 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_52_load_reg_5685,
+        din1 => in1_loc_52_load_reg_5365,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3931_p2);
+
+    mmult_mul_32s_32scud_U39 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_53_load_reg_5690,
+        din1 => in1_loc_53_load_reg_5370,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3935_p2);
+
+    mmult_mul_32s_32scud_U40 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_54_load_reg_5695,
+        din1 => in1_loc_54_load_reg_5375,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3939_p2);
+
+    mmult_mul_32s_32scud_U41 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_55_load_reg_5700,
+        din1 => in1_loc_55_load_reg_5380,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3943_p2);
+
+    mmult_mul_32s_32scud_U42 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_56_load_reg_5705,
+        din1 => in1_loc_56_load_reg_5385,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3947_p2);
+
+    mmult_mul_32s_32scud_U43 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_59_load_reg_5720,
+        din1 => in1_loc_59_load_reg_5400,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3951_p2);
+
+    mmult_mul_32s_32scud_U44 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_60_load_reg_5725,
+        din1 => in1_loc_60_load_reg_5405,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3955_p2);
+
+    mmult_mul_32s_32scud_U45 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_62_load_reg_5735,
+        din1 => in1_loc_62_load_reg_5415,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3959_p2);
+
+    mmult_mul_32s_32scud_U46 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_63_load_reg_5740,
+        din1 => in1_loc_63_load_reg_5420,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3963_p2);
+
+    mmult_mul_32s_32scud_U47 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_9_load_reg_5840,
+        din1 => in1_loc_9_load_reg_5745,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3967_p2);
+
+    mmult_mul_32s_32scud_U48 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_10_load_reg_5845,
+        din1 => in1_loc_10_load_reg_5750,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3971_p2);
+
+    mmult_mul_32s_32scud_U49 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_13_load_reg_5850,
+        din1 => in1_loc_13_load_reg_5755,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3975_p2);
+
+    mmult_mul_32s_32scud_U50 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_14_load_reg_5855,
+        din1 => in1_loc_14_load_reg_5760,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3979_p2);
+
+    mmult_mul_32s_32scud_U51 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_17_load_reg_5860,
+        din1 => in1_loc_17_load_reg_5765,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3983_p2);
+
+    mmult_mul_32s_32scud_U52 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_18_load_reg_5865,
+        din1 => in1_loc_18_load_reg_5770,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3987_p2);
+
+    mmult_mul_32s_32scud_U53 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_25_load_reg_5870,
+        din1 => in1_loc_25_load_reg_5775,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3991_p2);
+
+    mmult_mul_32s_32scud_U54 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_26_load_reg_5875,
+        din1 => in1_loc_26_load_reg_5780,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3995_p2);
+
+    mmult_mul_32s_32scud_U55 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_33_load_reg_5880,
+        din1 => in1_loc_33_load_reg_5785,
+        ce => ap_const_logic_1,
+        dout => grp_fu_3999_p2);
+
+    mmult_mul_32s_32scud_U56 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_34_load_reg_5885,
+        din1 => in1_loc_34_load_reg_5790,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4003_p2);
+
+    mmult_mul_32s_32scud_U57 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_41_load_reg_5890,
+        din1 => in1_loc_41_load_reg_5795,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4007_p2);
+
+    mmult_mul_32s_32scud_U58 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_42_load_reg_5895,
+        din1 => in1_loc_42_load_reg_5800,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4011_p2);
+
+    mmult_mul_32s_32scud_U59 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_45_load_reg_5900,
+        din1 => in1_loc_45_load_reg_5805,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4015_p2);
+
+    mmult_mul_32s_32scud_U60 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_46_load_reg_5905,
+        din1 => in1_loc_46_load_reg_5810,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4019_p2);
+
+    mmult_mul_32s_32scud_U61 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_49_load_reg_5910,
+        din1 => in1_loc_49_load_reg_5815,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4023_p2);
+
+    mmult_mul_32s_32scud_U62 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_50_load_reg_5915,
+        din1 => in1_loc_50_load_reg_5820,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4027_p2);
+
+    mmult_mul_32s_32scud_U63 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_57_load_reg_5920,
+        din1 => in1_loc_57_load_reg_5825,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4031_p2);
+
+    mmult_mul_32s_32scud_U64 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_58_load_reg_5925,
+        din1 => in1_loc_58_load_reg_5830,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4035_p2);
+
+    mmult_mul_32s_32scud_U65 : component mmult_mul_32s_32scud
+    generic map (
+        ID => 1,
+        NUM_STAGE => 3,
+        din0_WIDTH => 32,
+        din1_WIDTH => 32,
+        dout_WIDTH => 32)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        din0 => in2_loc_61_load_reg_5930,
+        din1 => in1_loc_61_load_reg_5835,
+        ce => ap_const_logic_1,
+        dout => grp_fu_4039_p2);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state9)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state9);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp1_exit_iter0_state19)) then 
+                        ap_enable_reg_pp1_iter1 <= (ap_const_logic_1 xor ap_condition_pp1_exit_iter0_state19);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp1_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                    ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_const_logic_1 = ap_condition_pp2_exit_iter0_state25) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                    ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp2_exit_iter0_state25)) then 
+                        ap_enable_reg_pp2_iter1 <= (ap_const_logic_1 xor ap_condition_pp2_exit_iter0_state25);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter2 <= ap_enable_reg_pp2_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter3 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter3 <= ap_enable_reg_pp2_iter2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter4_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter4 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter4 <= ap_enable_reg_pp2_iter3;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter5_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter5 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter5 <= ap_enable_reg_pp2_iter4;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter6_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter6 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter6 <= ap_enable_reg_pp2_iter5;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter7_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter7 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter7 <= ap_enable_reg_pp2_iter6;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp2_iter8_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp2_iter8 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then 
+                    ap_enable_reg_pp2_iter8 <= ap_enable_reg_pp2_iter7;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                    ap_enable_reg_pp2_iter8 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_const_logic_1 = ap_condition_pp3_exit_iter0_state35) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone))) then 
+                    ap_enable_reg_pp3_iter0 <= ap_const_logic_0;
+                elsif (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then 
+                    ap_enable_reg_pp3_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp3_exit_iter0_state35)) then 
+                        ap_enable_reg_pp3_iter1 <= (ap_const_logic_1 xor ap_condition_pp3_exit_iter0_state35);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp3_iter1 <= ap_enable_reg_pp3_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp3_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_enable_reg_pp3_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) then 
+                    ap_enable_reg_pp3_iter2 <= ap_enable_reg_pp3_iter1;
+                elsif (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then 
+                    ap_enable_reg_pp3_iter2 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0_reg_3329_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+                i_0_reg_3329 <= select_ln31_1_reg_4592;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                i_0_reg_3329 <= ap_const_lv31_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_3318_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3620_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+                indvar_flatten_reg_3318 <= add_ln31_fu_3625_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                indvar_flatten_reg_3318 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    j_0_reg_3340_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3620_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then 
+                j_0_reg_3340 <= j_fu_3685_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state24)) then 
+                j_0_reg_3340 <= ap_const_lv32_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln27_reg_3296_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_fu_3425_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                phi_ln27_reg_3296 <= add_ln27_fu_3431_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
+                phi_ln27_reg_3296 <= ap_const_lv13_0;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln28_reg_3307_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state18)) then 
+                phi_ln28_reg_3307 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_fu_3518_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+                phi_ln28_reg_3307 <= add_ln28_fu_3524_p2;
+            end if; 
+        end if;
+    end process;
+
+    phi_ln42_reg_3351_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then 
+                phi_ln42_reg_3351 <= ap_const_lv13_0;
+            elsif (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_fu_4339_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1))) then 
+                phi_ln42_reg_3351 <= add_ln42_fu_4345_p2;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578_pp2_iter5_reg = ap_const_lv1_0))) then
+                add_ln38_10_reg_6275 <= add_ln38_10_fu_4070_p2;
+                add_ln38_15_reg_6280 <= add_ln38_15_fu_4074_p2;
+                add_ln38_18_reg_6285 <= add_ln38_18_fu_4078_p2;
+                add_ln38_19_reg_6290 <= add_ln38_19_fu_4082_p2;
+                add_ln38_22_reg_6295 <= add_ln38_22_fu_4086_p2;
+                add_ln38_25_reg_6300 <= add_ln38_25_fu_4090_p2;
+                add_ln38_26_reg_6305 <= add_ln38_26_fu_4094_p2;
+                add_ln38_2_reg_6255 <= add_ln38_2_fu_4052_p2;
+                add_ln38_31_reg_6310 <= add_ln38_31_fu_4098_p2;
+                add_ln38_34_reg_6315 <= add_ln38_34_fu_4102_p2;
+                add_ln38_35_reg_6320 <= add_ln38_35_fu_4106_p2;
+                add_ln38_38_reg_6325 <= add_ln38_38_fu_4110_p2;
+                add_ln38_3_reg_6260 <= add_ln38_3_fu_4058_p2;
+                add_ln38_41_reg_6330 <= add_ln38_41_fu_4114_p2;
+                add_ln38_46_reg_6335 <= add_ln38_46_fu_4118_p2;
+                add_ln38_49_reg_6340 <= add_ln38_49_fu_4122_p2;
+                add_ln38_4_reg_6265 <= add_ln38_4_fu_4062_p2;
+                add_ln38_50_reg_6345 <= add_ln38_50_fu_4126_p2;
+                add_ln38_53_reg_6350 <= add_ln38_53_fu_4130_p2;
+                add_ln38_56_reg_6355 <= add_ln38_56_fu_4134_p2;
+                add_ln38_57_reg_6360 <= add_ln38_57_fu_4138_p2;
+                add_ln38_7_reg_6270 <= add_ln38_7_fu_4066_p2;
+                mul_ln38_10_reg_6165 <= grp_fu_3971_p2;
+                mul_ln38_13_reg_6170 <= grp_fu_3975_p2;
+                mul_ln38_14_reg_6175 <= grp_fu_3979_p2;
+                mul_ln38_17_reg_6180 <= grp_fu_3983_p2;
+                mul_ln38_18_reg_6185 <= grp_fu_3987_p2;
+                mul_ln38_25_reg_6190 <= grp_fu_3991_p2;
+                mul_ln38_26_reg_6195 <= grp_fu_3995_p2;
+                mul_ln38_33_reg_6200 <= grp_fu_3999_p2;
+                mul_ln38_34_reg_6205 <= grp_fu_4003_p2;
+                mul_ln38_41_reg_6210 <= grp_fu_4007_p2;
+                mul_ln38_42_reg_6215 <= grp_fu_4011_p2;
+                mul_ln38_45_reg_6220 <= grp_fu_4015_p2;
+                mul_ln38_46_reg_6225 <= grp_fu_4019_p2;
+                mul_ln38_49_reg_6230 <= grp_fu_4023_p2;
+                mul_ln38_50_reg_6235 <= grp_fu_4027_p2;
+                mul_ln38_57_reg_6240 <= grp_fu_4031_p2;
+                mul_ln38_58_reg_6245 <= grp_fu_4035_p2;
+                mul_ln38_61_reg_6250 <= grp_fu_4039_p2;
+                mul_ln38_9_reg_6160 <= grp_fu_3967_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578_pp2_iter6_reg = ap_const_lv1_0))) then
+                add_ln38_30_reg_6365 <= add_ln38_30_fu_4225_p2;
+                add_ln38_45_reg_6370 <= add_ln38_45_fu_4274_p2;
+                add_ln38_61_reg_6375 <= add_ln38_61_fu_4323_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                dim_read_reg_4356 <= dim;
+                in3_reg_4372 <= in1(31 downto 2);
+                in_reg_4367 <= in2(31 downto 2);
+                out5_reg_4362 <= out_r(31 downto 2);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                icmp_ln31_reg_4578 <= icmp_ln31_fu_3620_p2;
+                icmp_ln31_reg_4578_pp2_iter1_reg <= icmp_ln31_reg_4578;
+                out_loc_addr_reg_4598_pp2_iter1_reg <= out_loc_addr_reg_4598;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_boolean_0 = ap_block_pp2_stage0_11001)) then
+                icmp_ln31_reg_4578_pp2_iter2_reg <= icmp_ln31_reg_4578_pp2_iter1_reg;
+                icmp_ln31_reg_4578_pp2_iter3_reg <= icmp_ln31_reg_4578_pp2_iter2_reg;
+                icmp_ln31_reg_4578_pp2_iter4_reg <= icmp_ln31_reg_4578_pp2_iter3_reg;
+                icmp_ln31_reg_4578_pp2_iter5_reg <= icmp_ln31_reg_4578_pp2_iter4_reg;
+                icmp_ln31_reg_4578_pp2_iter6_reg <= icmp_ln31_reg_4578_pp2_iter5_reg;
+                icmp_ln31_reg_4578_pp2_iter7_reg <= icmp_ln31_reg_4578_pp2_iter6_reg;
+                out_loc_addr_reg_4598_pp2_iter2_reg <= out_loc_addr_reg_4598_pp2_iter1_reg;
+                out_loc_addr_reg_4598_pp2_iter3_reg <= out_loc_addr_reg_4598_pp2_iter2_reg;
+                out_loc_addr_reg_4598_pp2_iter4_reg <= out_loc_addr_reg_4598_pp2_iter3_reg;
+                out_loc_addr_reg_4598_pp2_iter5_reg <= out_loc_addr_reg_4598_pp2_iter4_reg;
+                out_loc_addr_reg_4598_pp2_iter6_reg <= out_loc_addr_reg_4598_pp2_iter5_reg;
+                out_loc_addr_reg_4598_pp2_iter7_reg <= out_loc_addr_reg_4598_pp2_iter6_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0))) then
+                icmp_ln42_reg_6380 <= icmp_ln42_fu_4339_p2;
+                icmp_ln42_reg_6380_pp3_iter1_reg <= icmp_ln42_reg_6380;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578_pp2_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then
+                in1_loc_0_load_reg_5105 <= in1_loc_0_q0;
+                in1_loc_11_load_reg_5160 <= in1_loc_11_q0;
+                in1_loc_12_load_reg_5165 <= in1_loc_12_q0;
+                in1_loc_15_load_reg_5180 <= in1_loc_15_q0;
+                in1_loc_16_load_reg_5185 <= in1_loc_16_q0;
+                in1_loc_19_load_reg_5200 <= in1_loc_19_q0;
+                in1_loc_1_load_reg_5110 <= in1_loc_1_q0;
+                in1_loc_20_load_reg_5205 <= in1_loc_20_q0;
+                in1_loc_21_load_reg_5210 <= in1_loc_21_q0;
+                in1_loc_22_load_reg_5215 <= in1_loc_22_q0;
+                in1_loc_23_load_reg_5220 <= in1_loc_23_q0;
+                in1_loc_24_load_reg_5225 <= in1_loc_24_q0;
+                in1_loc_27_load_reg_5240 <= in1_loc_27_q0;
+                in1_loc_28_load_reg_5245 <= in1_loc_28_q0;
+                in1_loc_29_load_reg_5250 <= in1_loc_29_q0;
+                in1_loc_2_load_reg_5115 <= in1_loc_2_q0;
+                in1_loc_30_load_reg_5255 <= in1_loc_30_q0;
+                in1_loc_31_load_reg_5260 <= in1_loc_31_q0;
+                in1_loc_32_load_reg_5265 <= in1_loc_32_q0;
+                in1_loc_35_load_reg_5280 <= in1_loc_35_q0;
+                in1_loc_36_load_reg_5285 <= in1_loc_36_q0;
+                in1_loc_37_load_reg_5290 <= in1_loc_37_q0;
+                in1_loc_38_load_reg_5295 <= in1_loc_38_q0;
+                in1_loc_39_load_reg_5300 <= in1_loc_39_q0;
+                in1_loc_3_load_reg_5120 <= in1_loc_3_q0;
+                in1_loc_40_load_reg_5305 <= in1_loc_40_q0;
+                in1_loc_43_load_reg_5320 <= in1_loc_43_q0;
+                in1_loc_44_load_reg_5325 <= in1_loc_44_q0;
+                in1_loc_47_load_reg_5340 <= in1_loc_47_q0;
+                in1_loc_48_load_reg_5345 <= in1_loc_48_q0;
+                in1_loc_4_load_reg_5125 <= in1_loc_4_q0;
+                in1_loc_51_load_reg_5360 <= in1_loc_51_q0;
+                in1_loc_52_load_reg_5365 <= in1_loc_52_q0;
+                in1_loc_53_load_reg_5370 <= in1_loc_53_q0;
+                in1_loc_54_load_reg_5375 <= in1_loc_54_q0;
+                in1_loc_55_load_reg_5380 <= in1_loc_55_q0;
+                in1_loc_56_load_reg_5385 <= in1_loc_56_q0;
+                in1_loc_59_load_reg_5400 <= in1_loc_59_q0;
+                in1_loc_5_load_reg_5130 <= in1_loc_5_q0;
+                in1_loc_60_load_reg_5405 <= in1_loc_60_q0;
+                in1_loc_62_load_reg_5415 <= in1_loc_62_q0;
+                in1_loc_63_load_reg_5420 <= in1_loc_63_q0;
+                in1_loc_6_load_reg_5135 <= in1_loc_6_q0;
+                in1_loc_7_load_reg_5140 <= in1_loc_7_q0;
+                in1_loc_8_load_reg_5145 <= in1_loc_8_q0;
+                in2_loc_0_load_reg_5425 <= in2_loc_0_q0;
+                in2_loc_11_load_reg_5480 <= in2_loc_11_q0;
+                in2_loc_12_load_reg_5485 <= in2_loc_12_q0;
+                in2_loc_15_load_reg_5500 <= in2_loc_15_q0;
+                in2_loc_16_load_reg_5505 <= in2_loc_16_q0;
+                in2_loc_19_load_reg_5520 <= in2_loc_19_q0;
+                in2_loc_1_load_reg_5430 <= in2_loc_1_q0;
+                in2_loc_20_load_reg_5525 <= in2_loc_20_q0;
+                in2_loc_21_load_reg_5530 <= in2_loc_21_q0;
+                in2_loc_22_load_reg_5535 <= in2_loc_22_q0;
+                in2_loc_23_load_reg_5540 <= in2_loc_23_q0;
+                in2_loc_24_load_reg_5545 <= in2_loc_24_q0;
+                in2_loc_27_load_reg_5560 <= in2_loc_27_q0;
+                in2_loc_28_load_reg_5565 <= in2_loc_28_q0;
+                in2_loc_29_load_reg_5570 <= in2_loc_29_q0;
+                in2_loc_2_load_reg_5435 <= in2_loc_2_q0;
+                in2_loc_30_load_reg_5575 <= in2_loc_30_q0;
+                in2_loc_31_load_reg_5580 <= in2_loc_31_q0;
+                in2_loc_32_load_reg_5585 <= in2_loc_32_q0;
+                in2_loc_35_load_reg_5600 <= in2_loc_35_q0;
+                in2_loc_36_load_reg_5605 <= in2_loc_36_q0;
+                in2_loc_37_load_reg_5610 <= in2_loc_37_q0;
+                in2_loc_38_load_reg_5615 <= in2_loc_38_q0;
+                in2_loc_39_load_reg_5620 <= in2_loc_39_q0;
+                in2_loc_3_load_reg_5440 <= in2_loc_3_q0;
+                in2_loc_40_load_reg_5625 <= in2_loc_40_q0;
+                in2_loc_43_load_reg_5640 <= in2_loc_43_q0;
+                in2_loc_44_load_reg_5645 <= in2_loc_44_q0;
+                in2_loc_47_load_reg_5660 <= in2_loc_47_q0;
+                in2_loc_48_load_reg_5665 <= in2_loc_48_q0;
+                in2_loc_4_load_reg_5445 <= in2_loc_4_q0;
+                in2_loc_51_load_reg_5680 <= in2_loc_51_q0;
+                in2_loc_52_load_reg_5685 <= in2_loc_52_q0;
+                in2_loc_53_load_reg_5690 <= in2_loc_53_q0;
+                in2_loc_54_load_reg_5695 <= in2_loc_54_q0;
+                in2_loc_55_load_reg_5700 <= in2_loc_55_q0;
+                in2_loc_56_load_reg_5705 <= in2_loc_56_q0;
+                in2_loc_59_load_reg_5720 <= in2_loc_59_q0;
+                in2_loc_5_load_reg_5450 <= in2_loc_5_q0;
+                in2_loc_60_load_reg_5725 <= in2_loc_60_q0;
+                in2_loc_62_load_reg_5735 <= in2_loc_62_q0;
+                in2_loc_63_load_reg_5740 <= in2_loc_63_q0;
+                in2_loc_6_load_reg_5455 <= in2_loc_6_q0;
+                in2_loc_7_load_reg_5460 <= in2_loc_7_q0;
+                in2_loc_8_load_reg_5465 <= in2_loc_8_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578_pp2_iter2_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter3 = ap_const_logic_1))) then
+                in1_loc_10_load_reg_5750 <= in1_loc_10_q0;
+                in1_loc_13_load_reg_5755 <= in1_loc_13_q0;
+                in1_loc_14_load_reg_5760 <= in1_loc_14_q0;
+                in1_loc_17_load_reg_5765 <= in1_loc_17_q0;
+                in1_loc_18_load_reg_5770 <= in1_loc_18_q0;
+                in1_loc_25_load_reg_5775 <= in1_loc_25_q0;
+                in1_loc_26_load_reg_5780 <= in1_loc_26_q0;
+                in1_loc_33_load_reg_5785 <= in1_loc_33_q0;
+                in1_loc_34_load_reg_5790 <= in1_loc_34_q0;
+                in1_loc_41_load_reg_5795 <= in1_loc_41_q0;
+                in1_loc_42_load_reg_5800 <= in1_loc_42_q0;
+                in1_loc_45_load_reg_5805 <= in1_loc_45_q0;
+                in1_loc_46_load_reg_5810 <= in1_loc_46_q0;
+                in1_loc_49_load_reg_5815 <= in1_loc_49_q0;
+                in1_loc_50_load_reg_5820 <= in1_loc_50_q0;
+                in1_loc_57_load_reg_5825 <= in1_loc_57_q0;
+                in1_loc_58_load_reg_5830 <= in1_loc_58_q0;
+                in1_loc_61_load_reg_5835 <= in1_loc_61_q0;
+                in1_loc_9_load_reg_5745 <= in1_loc_9_q0;
+                in2_loc_10_load_reg_5845 <= in2_loc_10_q0;
+                in2_loc_13_load_reg_5850 <= in2_loc_13_q0;
+                in2_loc_14_load_reg_5855 <= in2_loc_14_q0;
+                in2_loc_17_load_reg_5860 <= in2_loc_17_q0;
+                in2_loc_18_load_reg_5865 <= in2_loc_18_q0;
+                in2_loc_25_load_reg_5870 <= in2_loc_25_q0;
+                in2_loc_26_load_reg_5875 <= in2_loc_26_q0;
+                in2_loc_33_load_reg_5880 <= in2_loc_33_q0;
+                in2_loc_34_load_reg_5885 <= in2_loc_34_q0;
+                in2_loc_41_load_reg_5890 <= in2_loc_41_q0;
+                in2_loc_42_load_reg_5895 <= in2_loc_42_q0;
+                in2_loc_45_load_reg_5900 <= in2_loc_45_q0;
+                in2_loc_46_load_reg_5905 <= in2_loc_46_q0;
+                in2_loc_49_load_reg_5910 <= in2_loc_49_q0;
+                in2_loc_50_load_reg_5915 <= in2_loc_50_q0;
+                in2_loc_57_load_reg_5920 <= in2_loc_57_q0;
+                in2_loc_58_load_reg_5925 <= in2_loc_58_q0;
+                in2_loc_61_load_reg_5930 <= in2_loc_61_q0;
+                in2_loc_9_load_reg_5840 <= in2_loc_9_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                in1_mem_addr_read_reg_4413 <= in1_mem_RDATA;
+                lshr_ln_reg_4404_pp0_iter1_reg <= lshr_ln_reg_4404;
+                trunc_ln27_reg_4409_pp0_iter1_reg <= trunc_ln27_reg_4409;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                in2_mem_addr_read_reg_4499 <= in2_mem_RDATA;
+                trunc_ln1_reg_4495_pp1_iter1_reg <= trunc_ln1_reg_4495;
+                trunc_ln28_reg_4490_pp1_iter1_reg <= trunc_ln28_reg_4490;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
+                    in2_mem_addr_reg_4389(29 downto 0) <= empty_7_fu_3416_p1(32 - 1 downto 0)(29 downto 0);
+                    out_mem_addr_reg_4383(29 downto 0) <= empty_fu_3407_p1(32 - 1 downto 0)(29 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln27_fu_3425_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                lshr_ln_reg_4404 <= phi_ln27_reg_3296(12 downto 6);
+                trunc_ln27_reg_4409 <= trunc_ln27_fu_3447_p1;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state24)) then
+                mul_ln31_reg_4573 <= grp_fu_3614_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578_pp2_iter4_reg = ap_const_lv1_0))) then
+                mul_ln38_11_reg_5980 <= grp_fu_3823_p2;
+                mul_ln38_12_reg_5985 <= grp_fu_3827_p2;
+                mul_ln38_15_reg_5990 <= grp_fu_3831_p2;
+                mul_ln38_16_reg_5995 <= grp_fu_3835_p2;
+                mul_ln38_19_reg_6000 <= grp_fu_3839_p2;
+                mul_ln38_1_reg_5940 <= grp_fu_3791_p2;
+                mul_ln38_20_reg_6005 <= grp_fu_3843_p2;
+                mul_ln38_21_reg_6010 <= grp_fu_3847_p2;
+                mul_ln38_22_reg_6015 <= grp_fu_3851_p2;
+                mul_ln38_23_reg_6020 <= grp_fu_3855_p2;
+                mul_ln38_24_reg_6025 <= grp_fu_3859_p2;
+                mul_ln38_27_reg_6030 <= grp_fu_3863_p2;
+                mul_ln38_28_reg_6035 <= grp_fu_3867_p2;
+                mul_ln38_29_reg_6040 <= grp_fu_3871_p2;
+                mul_ln38_2_reg_5945 <= grp_fu_3795_p2;
+                mul_ln38_30_reg_6045 <= grp_fu_3875_p2;
+                mul_ln38_31_reg_6050 <= grp_fu_3879_p2;
+                mul_ln38_32_reg_6055 <= grp_fu_3883_p2;
+                mul_ln38_35_reg_6060 <= grp_fu_3887_p2;
+                mul_ln38_36_reg_6065 <= grp_fu_3891_p2;
+                mul_ln38_37_reg_6070 <= grp_fu_3895_p2;
+                mul_ln38_38_reg_6075 <= grp_fu_3899_p2;
+                mul_ln38_39_reg_6080 <= grp_fu_3903_p2;
+                mul_ln38_3_reg_5950 <= grp_fu_3799_p2;
+                mul_ln38_40_reg_6085 <= grp_fu_3907_p2;
+                mul_ln38_43_reg_6090 <= grp_fu_3911_p2;
+                mul_ln38_44_reg_6095 <= grp_fu_3915_p2;
+                mul_ln38_47_reg_6100 <= grp_fu_3919_p2;
+                mul_ln38_48_reg_6105 <= grp_fu_3923_p2;
+                mul_ln38_4_reg_5955 <= grp_fu_3803_p2;
+                mul_ln38_51_reg_6110 <= grp_fu_3927_p2;
+                mul_ln38_52_reg_6115 <= grp_fu_3931_p2;
+                mul_ln38_53_reg_6120 <= grp_fu_3935_p2;
+                mul_ln38_54_reg_6125 <= grp_fu_3939_p2;
+                mul_ln38_55_reg_6130 <= grp_fu_3943_p2;
+                mul_ln38_56_reg_6135 <= grp_fu_3947_p2;
+                mul_ln38_59_reg_6140 <= grp_fu_3951_p2;
+                mul_ln38_5_reg_5960 <= grp_fu_3807_p2;
+                mul_ln38_60_reg_6145 <= grp_fu_3955_p2;
+                mul_ln38_62_reg_6150 <= grp_fu_3959_p2;
+                mul_ln38_63_reg_6155 <= grp_fu_3963_p2;
+                mul_ln38_6_reg_5965 <= grp_fu_3811_p2;
+                mul_ln38_7_reg_5970 <= grp_fu_3815_p2;
+                mul_ln38_8_reg_5975 <= grp_fu_3819_p2;
+                mul_ln38_reg_5935 <= grp_fu_3787_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3620_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                out_loc_addr_reg_4598 <= zext_ln38_fu_3680_p1(12 - 1 downto 0);
+                select_ln31_reg_4587 <= select_ln31_fu_3642_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_reg_6380 = ap_const_lv1_0) and (ap_enable_reg_pp3_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578_pp2_iter4_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter5 = ap_const_logic_1)))) then
+                reg_3362 <= out_loc_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_fu_3620_p2 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                select_ln31_1_reg_4592 <= select_ln31_1_fu_3650_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
+                sext_ln38_reg_4857 <= sext_ln38_fu_3739_p1;
+                    zext_ln31_1_reg_4609(30 downto 0) <= zext_ln31_1_fu_3691_p1(30 downto 0);
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln28_fu_3518_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
+                trunc_ln1_reg_4495 <= phi_ln28_reg_3307(11 downto 6);
+                trunc_ln28_reg_4490 <= trunc_ln28_fu_3530_p1;
+            end if;
+        end if;
+    end process;
+    out_mem_addr_reg_4383(31 downto 30) <= "00";
+    in2_mem_addr_reg_4389(31 downto 30) <= "00";
+    zext_ln31_1_reg_4609(63 downto 31) <= "000000000000000000000000000000000";
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_enable_reg_pp0_iter1, ap_CS_fsm_state12, ap_enable_reg_pp1_iter1, ap_CS_fsm_state34, ap_enable_reg_pp3_iter2, ap_CS_fsm_state42, in1_mem_ARREADY, in2_mem_ARREADY, out_mem_AWREADY, out_mem_BVALID, ap_enable_reg_pp3_iter1, icmp_ln27_fu_3425_p2, ap_enable_reg_pp0_iter0, icmp_ln28_fu_3518_p2, ap_enable_reg_pp1_iter0, icmp_ln31_fu_3620_p2, ap_enable_reg_pp2_iter0, icmp_ln42_fu_4339_p2, ap_enable_reg_pp3_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter2, ap_block_pp1_stage0_subdone, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0_subdone, ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter7, ap_enable_reg_pp2_iter8, ap_block_pp3_stage0_subdone)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when ap_ST_fsm_state3 => 
+                ap_NS_fsm <= ap_ST_fsm_state4;
+            when ap_ST_fsm_state4 => 
+                ap_NS_fsm <= ap_ST_fsm_state5;
+            when ap_ST_fsm_state5 => 
+                ap_NS_fsm <= ap_ST_fsm_state6;
+            when ap_ST_fsm_state6 => 
+                ap_NS_fsm <= ap_ST_fsm_state7;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state8;
+            when ap_ST_fsm_state8 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((icmp_ln27_fu_3425_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) and not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((icmp_ln27_fu_3425_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state12 => 
+                if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then
+                    ap_NS_fsm <= ap_ST_fsm_state13;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state12;
+                end if;
+            when ap_ST_fsm_state13 => 
+                ap_NS_fsm <= ap_ST_fsm_state14;
+            when ap_ST_fsm_state14 => 
+                ap_NS_fsm <= ap_ST_fsm_state15;
+            when ap_ST_fsm_state15 => 
+                ap_NS_fsm <= ap_ST_fsm_state16;
+            when ap_ST_fsm_state16 => 
+                ap_NS_fsm <= ap_ST_fsm_state17;
+            when ap_ST_fsm_state17 => 
+                ap_NS_fsm <= ap_ST_fsm_state18;
+            when ap_ST_fsm_state18 => 
+                ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+            when ap_ST_fsm_pp1_stage0 => 
+                if ((not(((icmp_ln28_fu_3518_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))) and not(((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                elsif ((((icmp_ln28_fu_3518_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) or ((ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state22;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
+                end if;
+            when ap_ST_fsm_state22 => 
+                ap_NS_fsm <= ap_ST_fsm_state23;
+            when ap_ST_fsm_state23 => 
+                ap_NS_fsm <= ap_ST_fsm_state24;
+            when ap_ST_fsm_state24 => 
+                ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+            when ap_ST_fsm_pp2_stage0 => 
+                if ((not(((icmp_ln31_fu_3620_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))) and not(((ap_enable_reg_pp2_iter8 = ap_const_logic_1) and (ap_enable_reg_pp2_iter7 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                elsif ((((icmp_ln31_fu_3620_p2 = ap_const_lv1_1) and (ap_enable_reg_pp2_iter0 = ap_const_logic_1) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) or ((ap_enable_reg_pp2_iter8 = ap_const_logic_1) and (ap_enable_reg_pp2_iter7 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state34;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
+                end if;
+            when ap_ST_fsm_state34 => 
+                if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state34;
+                end if;
+            when ap_ST_fsm_pp3_stage0 => 
+                if ((not(((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (icmp_ln42_fu_4339_p2 = ap_const_lv1_1))) and not(((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                elsif ((((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone)) or ((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp3_stage0_subdone) and (icmp_ln42_fu_4339_p2 = ap_const_lv1_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state38;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp3_stage0;
+                end if;
+            when ap_ST_fsm_state38 => 
+                ap_NS_fsm <= ap_ST_fsm_state39;
+            when ap_ST_fsm_state39 => 
+                ap_NS_fsm <= ap_ST_fsm_state40;
+            when ap_ST_fsm_state40 => 
+                ap_NS_fsm <= ap_ST_fsm_state41;
+            when ap_ST_fsm_state41 => 
+                ap_NS_fsm <= ap_ST_fsm_state42;
+            when ap_ST_fsm_state42 => 
+                if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state42))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state42;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+        end case;
+    end process;
+    add_ln27_fu_3431_p2 <= std_logic_vector(unsigned(phi_ln27_reg_3296) + unsigned(ap_const_lv13_1));
+    add_ln28_fu_3524_p2 <= std_logic_vector(unsigned(phi_ln28_reg_3307) + unsigned(ap_const_lv13_1));
+    add_ln31_fu_3625_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_3318) + unsigned(ap_const_lv64_1));
+    add_ln38_10_fu_4070_p2 <= std_logic_vector(unsigned(mul_ln38_12_reg_5985) + unsigned(mul_ln38_11_reg_5980));
+    add_ln38_11_fu_4160_p2 <= std_logic_vector(unsigned(mul_ln38_14_reg_6175) + unsigned(mul_ln38_13_reg_6170));
+    add_ln38_12_fu_4164_p2 <= std_logic_vector(unsigned(add_ln38_10_reg_6275) + unsigned(add_ln38_11_fu_4160_p2));
+    add_ln38_13_fu_4169_p2 <= std_logic_vector(unsigned(add_ln38_9_fu_4155_p2) + unsigned(add_ln38_12_fu_4164_p2));
+    add_ln38_14_fu_4175_p2 <= std_logic_vector(unsigned(add_ln38_6_fu_4146_p2) + unsigned(add_ln38_13_fu_4169_p2));
+    add_ln38_15_fu_4074_p2 <= std_logic_vector(unsigned(mul_ln38_16_reg_5995) + unsigned(mul_ln38_15_reg_5990));
+    add_ln38_16_fu_4181_p2 <= std_logic_vector(unsigned(mul_ln38_18_reg_6185) + unsigned(mul_ln38_17_reg_6180));
+    add_ln38_17_fu_4185_p2 <= std_logic_vector(unsigned(add_ln38_15_reg_6280) + unsigned(add_ln38_16_fu_4181_p2));
+    add_ln38_18_fu_4078_p2 <= std_logic_vector(unsigned(mul_ln38_20_reg_6005) + unsigned(mul_ln38_19_reg_6000));
+    add_ln38_19_fu_4082_p2 <= std_logic_vector(unsigned(mul_ln38_22_reg_6015) + unsigned(mul_ln38_21_reg_6010));
+    add_ln38_1_fu_4048_p2 <= std_logic_vector(unsigned(mul_ln38_2_reg_5945) + unsigned(mul_ln38_1_reg_5940));
+    add_ln38_20_fu_4190_p2 <= std_logic_vector(unsigned(add_ln38_18_reg_6285) + unsigned(add_ln38_19_reg_6290));
+    add_ln38_21_fu_4194_p2 <= std_logic_vector(unsigned(add_ln38_17_fu_4185_p2) + unsigned(add_ln38_20_fu_4190_p2));
+    add_ln38_22_fu_4086_p2 <= std_logic_vector(unsigned(mul_ln38_24_reg_6025) + unsigned(mul_ln38_23_reg_6020));
+    add_ln38_23_fu_4200_p2 <= std_logic_vector(unsigned(mul_ln38_26_reg_6195) + unsigned(mul_ln38_25_reg_6190));
+    add_ln38_24_fu_4204_p2 <= std_logic_vector(unsigned(add_ln38_22_reg_6295) + unsigned(add_ln38_23_fu_4200_p2));
+    add_ln38_25_fu_4090_p2 <= std_logic_vector(unsigned(mul_ln38_28_reg_6035) + unsigned(mul_ln38_27_reg_6030));
+    add_ln38_26_fu_4094_p2 <= std_logic_vector(unsigned(mul_ln38_30_reg_6045) + unsigned(mul_ln38_29_reg_6040));
+    add_ln38_27_fu_4209_p2 <= std_logic_vector(unsigned(add_ln38_25_reg_6300) + unsigned(add_ln38_26_reg_6305));
+    add_ln38_28_fu_4213_p2 <= std_logic_vector(unsigned(add_ln38_24_fu_4204_p2) + unsigned(add_ln38_27_fu_4209_p2));
+    add_ln38_29_fu_4219_p2 <= std_logic_vector(unsigned(add_ln38_21_fu_4194_p2) + unsigned(add_ln38_28_fu_4213_p2));
+    add_ln38_2_fu_4052_p2 <= std_logic_vector(unsigned(add_ln38_fu_4043_p2) + unsigned(add_ln38_1_fu_4048_p2));
+    add_ln38_30_fu_4225_p2 <= std_logic_vector(unsigned(add_ln38_14_fu_4175_p2) + unsigned(add_ln38_29_fu_4219_p2));
+    add_ln38_31_fu_4098_p2 <= std_logic_vector(unsigned(mul_ln38_32_reg_6055) + unsigned(mul_ln38_31_reg_6050));
+    add_ln38_32_fu_4231_p2 <= std_logic_vector(unsigned(mul_ln38_34_reg_6205) + unsigned(mul_ln38_33_reg_6200));
+    add_ln38_33_fu_4235_p2 <= std_logic_vector(unsigned(add_ln38_31_reg_6310) + unsigned(add_ln38_32_fu_4231_p2));
+    add_ln38_34_fu_4102_p2 <= std_logic_vector(unsigned(mul_ln38_36_reg_6065) + unsigned(mul_ln38_35_reg_6060));
+    add_ln38_35_fu_4106_p2 <= std_logic_vector(unsigned(mul_ln38_38_reg_6075) + unsigned(mul_ln38_37_reg_6070));
+    add_ln38_36_fu_4240_p2 <= std_logic_vector(unsigned(add_ln38_34_reg_6315) + unsigned(add_ln38_35_reg_6320));
+    add_ln38_37_fu_4244_p2 <= std_logic_vector(unsigned(add_ln38_33_fu_4235_p2) + unsigned(add_ln38_36_fu_4240_p2));
+    add_ln38_38_fu_4110_p2 <= std_logic_vector(unsigned(mul_ln38_40_reg_6085) + unsigned(mul_ln38_39_reg_6080));
+    add_ln38_39_fu_4250_p2 <= std_logic_vector(unsigned(mul_ln38_42_reg_6215) + unsigned(mul_ln38_41_reg_6210));
+    add_ln38_3_fu_4058_p2 <= std_logic_vector(unsigned(mul_ln38_4_reg_5955) + unsigned(mul_ln38_3_reg_5950));
+    add_ln38_40_fu_4254_p2 <= std_logic_vector(unsigned(add_ln38_38_reg_6325) + unsigned(add_ln38_39_fu_4250_p2));
+    add_ln38_41_fu_4114_p2 <= std_logic_vector(unsigned(mul_ln38_44_reg_6095) + unsigned(mul_ln38_43_reg_6090));
+    add_ln38_42_fu_4259_p2 <= std_logic_vector(unsigned(mul_ln38_46_reg_6225) + unsigned(mul_ln38_45_reg_6220));
+    add_ln38_43_fu_4263_p2 <= std_logic_vector(unsigned(add_ln38_41_reg_6330) + unsigned(add_ln38_42_fu_4259_p2));
+    add_ln38_44_fu_4268_p2 <= std_logic_vector(unsigned(add_ln38_40_fu_4254_p2) + unsigned(add_ln38_43_fu_4263_p2));
+    add_ln38_45_fu_4274_p2 <= std_logic_vector(unsigned(add_ln38_37_fu_4244_p2) + unsigned(add_ln38_44_fu_4268_p2));
+    add_ln38_46_fu_4118_p2 <= std_logic_vector(unsigned(mul_ln38_48_reg_6105) + unsigned(mul_ln38_47_reg_6100));
+    add_ln38_47_fu_4280_p2 <= std_logic_vector(unsigned(mul_ln38_50_reg_6235) + unsigned(mul_ln38_49_reg_6230));
+    add_ln38_48_fu_4284_p2 <= std_logic_vector(unsigned(add_ln38_46_reg_6335) + unsigned(add_ln38_47_fu_4280_p2));
+    add_ln38_49_fu_4122_p2 <= std_logic_vector(unsigned(mul_ln38_52_reg_6115) + unsigned(mul_ln38_51_reg_6110));
+    add_ln38_4_fu_4062_p2 <= std_logic_vector(unsigned(mul_ln38_6_reg_5965) + unsigned(mul_ln38_5_reg_5960));
+    add_ln38_50_fu_4126_p2 <= std_logic_vector(unsigned(mul_ln38_54_reg_6125) + unsigned(mul_ln38_53_reg_6120));
+    add_ln38_51_fu_4289_p2 <= std_logic_vector(unsigned(add_ln38_49_reg_6340) + unsigned(add_ln38_50_reg_6345));
+    add_ln38_52_fu_4293_p2 <= std_logic_vector(unsigned(add_ln38_48_fu_4284_p2) + unsigned(add_ln38_51_fu_4289_p2));
+    add_ln38_53_fu_4130_p2 <= std_logic_vector(unsigned(mul_ln38_56_reg_6135) + unsigned(mul_ln38_55_reg_6130));
+    add_ln38_54_fu_4299_p2 <= std_logic_vector(unsigned(mul_ln38_58_reg_6245) + unsigned(mul_ln38_57_reg_6240));
+    add_ln38_55_fu_4303_p2 <= std_logic_vector(unsigned(add_ln38_53_reg_6350) + unsigned(add_ln38_54_fu_4299_p2));
+    add_ln38_56_fu_4134_p2 <= std_logic_vector(unsigned(mul_ln38_60_reg_6145) + unsigned(mul_ln38_59_reg_6140));
+    add_ln38_57_fu_4138_p2 <= std_logic_vector(unsigned(mul_ln38_63_reg_6155) + unsigned(mul_ln38_62_reg_6150));
+    add_ln38_58_fu_4308_p2 <= std_logic_vector(unsigned(mul_ln38_61_reg_6250) + unsigned(add_ln38_57_reg_6360));
+    add_ln38_59_fu_4312_p2 <= std_logic_vector(unsigned(add_ln38_56_reg_6355) + unsigned(add_ln38_58_fu_4308_p2));
+    add_ln38_5_fu_4142_p2 <= std_logic_vector(unsigned(add_ln38_3_reg_6260) + unsigned(add_ln38_4_reg_6265));
+    add_ln38_60_fu_4317_p2 <= std_logic_vector(unsigned(add_ln38_55_fu_4303_p2) + unsigned(add_ln38_59_fu_4312_p2));
+    add_ln38_61_fu_4323_p2 <= std_logic_vector(unsigned(add_ln38_52_fu_4293_p2) + unsigned(add_ln38_60_fu_4317_p2));
+    add_ln38_62_fu_4329_p2 <= std_logic_vector(unsigned(add_ln38_45_reg_6370) + unsigned(add_ln38_61_reg_6375));
+    add_ln38_64_fu_3674_p2 <= std_logic_vector(unsigned(tmp_cast_fu_3662_p3) + unsigned(trunc_ln38_1_fu_3670_p1));
+    add_ln38_6_fu_4146_p2 <= std_logic_vector(unsigned(add_ln38_2_reg_6255) + unsigned(add_ln38_5_fu_4142_p2));
+    add_ln38_7_fu_4066_p2 <= std_logic_vector(unsigned(mul_ln38_8_reg_5975) + unsigned(mul_ln38_7_reg_5970));
+    add_ln38_8_fu_4151_p2 <= std_logic_vector(unsigned(mul_ln38_10_reg_6165) + unsigned(mul_ln38_9_reg_6160));
+    add_ln38_9_fu_4155_p2 <= std_logic_vector(unsigned(add_ln38_7_reg_6270) + unsigned(add_ln38_8_fu_4151_p2));
+    add_ln38_fu_4043_p2 <= std_logic_vector(unsigned(mul_ln38_reg_5935) + unsigned(reg_3362));
+    add_ln42_fu_4345_p2 <= std_logic_vector(unsigned(phi_ln42_reg_3351) + unsigned(ap_const_lv13_1));
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(8);
+    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(16);
+    ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(20);
+    ap_CS_fsm_pp3_stage0 <= ap_CS_fsm(22);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state12 <= ap_CS_fsm(9);
+    ap_CS_fsm_state18 <= ap_CS_fsm(15);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state22 <= ap_CS_fsm(17);
+    ap_CS_fsm_state24 <= ap_CS_fsm(19);
+    ap_CS_fsm_state34 <= ap_CS_fsm(21);
+    ap_CS_fsm_state42 <= ap_CS_fsm(27);
+    ap_CS_fsm_state8 <= ap_CS_fsm(7);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_11001_assign_proc : process(ap_enable_reg_pp0_iter1, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_11001 <= ((in1_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(ap_enable_reg_pp0_iter1, in1_mem_RVALID)
+    begin
+                ap_block_pp0_stage0_subdone <= ((in1_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp1_stage0_11001_assign_proc : process(ap_enable_reg_pp1_iter1, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_11001 <= ((in2_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp1_stage0_subdone_assign_proc : process(ap_enable_reg_pp1_iter1, in2_mem_RVALID)
+    begin
+                ap_block_pp1_stage0_subdone <= ((in2_mem_RVALID = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1));
+    end process;
+
+        ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp2_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp2_stage0_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp3_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_pp3_stage0_01001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp3_stage0_11001_assign_proc : process(ap_enable_reg_pp3_iter2, ap_block_state37_io)
+    begin
+                ap_block_pp3_stage0_11001 <= ((ap_const_boolean_1 = ap_block_state37_io) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp3_stage0_subdone_assign_proc : process(ap_enable_reg_pp3_iter2, ap_block_state37_io)
+    begin
+                ap_block_pp3_stage0_subdone <= ((ap_const_boolean_1 = ap_block_state37_io) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state10_pp0_stage0_iter1_assign_proc : process(in1_mem_RVALID)
+    begin
+                ap_block_state10_pp0_stage0_iter1 <= (in1_mem_RVALID = ap_const_logic_0);
+    end process;
+
+        ap_block_state11_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state19_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state20_pp1_stage0_iter1_assign_proc : process(in2_mem_RVALID)
+    begin
+                ap_block_state20_pp1_stage0_iter1 <= (in2_mem_RVALID = ap_const_logic_0);
+    end process;
+
+        ap_block_state21_pp1_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state25_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state26_pp2_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state27_pp2_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state28_pp2_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state29_pp2_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state30_pp2_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state31_pp2_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state32_pp2_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state33_pp2_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state35_pp3_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state36_pp3_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state37_io_assign_proc : process(icmp_ln42_reg_6380_pp3_iter1_reg, out_mem_WREADY)
+    begin
+                ap_block_state37_io <= ((out_mem_WREADY = ap_const_logic_0) and (icmp_ln42_reg_6380_pp3_iter1_reg = ap_const_lv1_0));
+    end process;
+
+        ap_block_state37_pp3_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state9_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state9_assign_proc : process(icmp_ln27_fu_3425_p2)
+    begin
+        if ((icmp_ln27_fu_3425_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state9 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp1_exit_iter0_state19_assign_proc : process(icmp_ln28_fu_3518_p2)
+    begin
+        if ((icmp_ln28_fu_3518_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_1;
+        else 
+            ap_condition_pp1_exit_iter0_state19 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp2_exit_iter0_state25_assign_proc : process(icmp_ln31_fu_3620_p2)
+    begin
+        if ((icmp_ln31_fu_3620_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp2_exit_iter0_state25 <= ap_const_logic_1;
+        else 
+            ap_condition_pp2_exit_iter0_state25 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_condition_pp3_exit_iter0_state35_assign_proc : process(icmp_ln42_fu_4339_p2)
+    begin
+        if ((icmp_ln42_fu_4339_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp3_exit_iter0_state35 <= ap_const_logic_1;
+        else 
+            ap_condition_pp3_exit_iter0_state35 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_CS_fsm_state42, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state42))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
+    ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
+    ap_enable_pp3 <= (ap_idle_pp3 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter2)
+    begin
+        if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_0))) then 
+            ap_idle_pp1 <= ap_const_logic_1;
+        else 
+            ap_idle_pp1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter5, ap_enable_reg_pp2_iter0, ap_enable_reg_pp2_iter2, ap_enable_reg_pp2_iter3, ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter4, ap_enable_reg_pp2_iter6, ap_enable_reg_pp2_iter7, ap_enable_reg_pp2_iter8)
+    begin
+        if (((ap_enable_reg_pp2_iter2 = ap_const_logic_0) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter5 = ap_const_logic_0) and (ap_enable_reg_pp2_iter8 = ap_const_logic_0) and (ap_enable_reg_pp2_iter7 = ap_const_logic_0) and (ap_enable_reg_pp2_iter6 = ap_const_logic_0) and (ap_enable_reg_pp2_iter4 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0) and (ap_enable_reg_pp2_iter3 = ap_const_logic_0))) then 
+            ap_idle_pp2 <= ap_const_logic_1;
+        else 
+            ap_idle_pp2 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp3_assign_proc : process(ap_enable_reg_pp3_iter2, ap_enable_reg_pp3_iter1, ap_enable_reg_pp3_iter0)
+    begin
+        if (((ap_enable_reg_pp3_iter1 = ap_const_logic_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_0))) then 
+            ap_idle_pp3 <= ap_const_logic_1;
+        else 
+            ap_idle_pp3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_phi_mux_i_0_phi_fu_3333_p4_assign_proc : process(i_0_reg_3329, icmp_ln31_reg_4578, ap_CS_fsm_pp2_stage0, select_ln31_1_reg_4592, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (icmp_ln31_reg_4578 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            ap_phi_mux_i_0_phi_fu_3333_p4 <= select_ln31_1_reg_4592;
+        else 
+            ap_phi_mux_i_0_phi_fu_3333_p4 <= i_0_reg_3329;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state42, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state42))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    empty_7_fu_3416_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in_reg_4367),64));
+    empty_8_fu_3397_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(in3_reg_4372),64));
+    empty_fu_3407_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(out5_reg_4362),64));
+    grp_fu_3614_p0 <= zext_ln31_fu_3611_p1(32 - 1 downto 0);
+    grp_fu_3614_p1 <= zext_ln31_fu_3611_p1(32 - 1 downto 0);
+    i_fu_3631_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(ap_phi_mux_i_0_phi_fu_3333_p4));
+    icmp_ln27_fu_3425_p2 <= "1" when (phi_ln27_reg_3296 = ap_const_lv13_1000) else "0";
+    icmp_ln28_fu_3518_p2 <= "1" when (phi_ln28_reg_3307 = ap_const_lv13_1000) else "0";
+    icmp_ln31_fu_3620_p2 <= "1" when (indvar_flatten_reg_3318 = mul_ln31_reg_4573) else "0";
+    icmp_ln33_fu_3637_p2 <= "1" when (j_0_reg_3340 = dim_read_reg_4356) else "0";
+    icmp_ln42_fu_4339_p2 <= "1" when (phi_ln42_reg_3351 = ap_const_lv13_1000) else "0";
+
+    in1_loc_0_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_0_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_0_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_0_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_0_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_0_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_0_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_0_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_0_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_10_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_10_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_10_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_10_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_10_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_10_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_10_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_10_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_11_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_11_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_11_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_11_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_11_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_11_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_11_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_11_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_11_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_11_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_12_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_12_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_12_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_12_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_12_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_12_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_12_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_12_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_12_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_12_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_13_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_13_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_13_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_13_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_13_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_13_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_13_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_13_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_14_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_14_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_14_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_14_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_14_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_14_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_14_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_14_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_15_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_15_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_15_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_15_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_15_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_15_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_15_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_15_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_15_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_15_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_16_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_16_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_16_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_16_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_16_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_16_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_16_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_16_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_10) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_16_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_16_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_17_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_17_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_17_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_17_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_17_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_17_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_11) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_17_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_17_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_18_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_18_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_18_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_18_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_18_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_18_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_12) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_18_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_18_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_19_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_19_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_19_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_19_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_19_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_19_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_19_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_19_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_13) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_19_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_19_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_1_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_1_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_1_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_1_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_1_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_1_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_1_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_1_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_1_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_20_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_20_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_20_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_20_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_20_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_20_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_20_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_20_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_14) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_20_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_20_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_21_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_21_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_21_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_21_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_21_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_21_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_21_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_21_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_15) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_21_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_21_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_22_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_22_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_22_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_22_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_22_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_22_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_22_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_22_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_16) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_22_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_22_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_23_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_23_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_23_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_23_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_23_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_23_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_23_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_23_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_17) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_23_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_23_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_24_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_24_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_24_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_24_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_24_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_24_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_24_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_24_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_18) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_24_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_24_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_25_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_25_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_25_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_25_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_25_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_25_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_19) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_25_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_25_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_26_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_26_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_26_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_26_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_26_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_26_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_1A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_26_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_26_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_27_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_27_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_27_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_27_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_27_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_27_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_27_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_27_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_1B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_27_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_27_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_28_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_28_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_28_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_28_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_28_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_28_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_28_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_28_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_1C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_28_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_28_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_29_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_29_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_29_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_29_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_29_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_29_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_29_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_29_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_1D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_29_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_29_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_2_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_2_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_2_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_2_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_2_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_2_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_2_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_2) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_2_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_2_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_30_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_30_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_30_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_30_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_30_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_30_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_30_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_30_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_1E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_30_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_30_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_31_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_31_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_31_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_31_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_31_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_31_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_31_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_31_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_1F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_31_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_31_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_32_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_32_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_32_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_32_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_32_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_32_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_32_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_32_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_20) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_32_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_32_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_33_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_33_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_33_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_33_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_33_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_33_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_21) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_33_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_33_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_34_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_34_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_34_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_34_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_34_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_34_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_22) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_34_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_34_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_35_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_35_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_35_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_35_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_35_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_35_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_35_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_35_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_23) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_35_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_35_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_36_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_36_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_36_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_36_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_36_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_36_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_36_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_36_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_24) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_36_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_36_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_37_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_37_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_37_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_37_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_37_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_37_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_37_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_37_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_25) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_37_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_37_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_38_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_38_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_38_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_38_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_38_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_38_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_38_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_38_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_26) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_38_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_38_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_39_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_39_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_39_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_39_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_39_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_39_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_39_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_39_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_27) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_39_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_39_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_3_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_3_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_3_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_3_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_3_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_3_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_3_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_3) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_3_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_3_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_40_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_40_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_40_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_40_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_40_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_40_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_40_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_40_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_28) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_40_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_40_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_41_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_41_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_41_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_41_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_41_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_41_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_29) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_41_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_41_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_42_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_42_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_42_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_42_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_42_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_42_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_2A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_42_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_42_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_43_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_43_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_43_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_43_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_43_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_43_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_43_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_43_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_2B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_43_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_43_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_44_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_44_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_44_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_44_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_44_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_44_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_44_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_44_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_2C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_44_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_44_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_45_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_45_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_45_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_45_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_45_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_45_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_2D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_45_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_45_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_46_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_46_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_46_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_46_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_46_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_46_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_2E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_46_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_46_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_47_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_47_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_47_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_47_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_47_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_47_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_47_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_47_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_2F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_47_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_47_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_48_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_48_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_48_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_48_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_48_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_48_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_48_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_48_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_30) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_48_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_48_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_49_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_49_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_49_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_49_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_49_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_49_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_31) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_49_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_49_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_4_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_4_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_4_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_4_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_4_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_4_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_4_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_4) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_4_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_4_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_50_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_50_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_50_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_50_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_50_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_50_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_32) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_50_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_50_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_51_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_51_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_51_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_51_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_51_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_51_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_51_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_51_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_33) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_51_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_51_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_52_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_52_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_52_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_52_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_52_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_52_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_52_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_52_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_34) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_52_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_52_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_53_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_53_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_53_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_53_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_53_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_53_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_53_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_53_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_35) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_53_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_53_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_54_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_54_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_54_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_54_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_54_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_54_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_54_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_54_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_36) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_54_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_54_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_55_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_55_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_55_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_55_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_55_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_55_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_55_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_55_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_37) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_55_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_55_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_56_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_56_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_56_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_56_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_56_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_56_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_56_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_56_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_38) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_56_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_56_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_57_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_57_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_57_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_57_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_57_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_57_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_39) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_57_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_57_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_58_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_58_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_58_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_58_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_58_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_58_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_3A) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_58_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_58_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_59_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_59_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_59_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_59_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_59_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_59_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_59_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_59_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_3B) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_59_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_59_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_5_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_5_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_5_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_5_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_5_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_5_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_5_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_5) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_5_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_5_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_60_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_60_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_60_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_60_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_60_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_60_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_60_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_60_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_3C) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_60_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_60_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_61_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_61_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_61_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_61_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_61_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_61_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_3D) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_61_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_61_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_62_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_62_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_62_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_62_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_62_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_62_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_62_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_62_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_3E) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_62_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_62_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_63_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_63_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_63_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_63_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_63_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_63_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_63_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_63_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_3F) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_63_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_63_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_6_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_6_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_6_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_6_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_6_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_6_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_6_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_6) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_6_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_6_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_7_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_7_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_7_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_7_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_7_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_7_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_7_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_7) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_7_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_7_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_8_address0_assign_proc : process(ap_block_pp0_stage0, ap_CS_fsm_pp2_stage0, zext_ln31_1_fu_3691_p1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in1_loc_8_address0 <= zext_ln31_1_fu_3691_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_8_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_8_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_8_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in1_loc_8_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_8_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_8) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_8_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_8_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_9_address0_assign_proc : process(ap_block_pp0_stage0, zext_ln31_1_reg_4609, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2, ap_block_pp2_stage0, zext_ln27_fu_3451_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_address0 <= zext_ln31_1_reg_4609(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_address0 <= zext_ln27_fu_3451_p1(6 - 1 downto 0);
+        else 
+            in1_loc_9_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in1_loc_9_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp0_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp0_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in1_loc_9_ce0 <= ap_const_logic_1;
+        else 
+            in1_loc_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_loc_9_we0_assign_proc : process(ap_block_pp0_stage0_11001, trunc_ln27_reg_4409_pp0_iter1_reg, ap_enable_reg_pp0_iter2)
+    begin
+        if (((trunc_ln27_reg_4409_pp0_iter1_reg = ap_const_lv6_9) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then 
+            in1_loc_9_we0 <= ap_const_logic_1;
+        else 
+            in1_loc_9_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    in1_mem_ARADDR <= empty_8_fu_3397_p1(32 - 1 downto 0);
+
+    in1_mem_ARVALID_assign_proc : process(ap_CS_fsm_state2, in1_mem_ARREADY)
+    begin
+        if (((in1_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            in1_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in1_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_RREADY_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_RREADY <= ap_const_logic_1;
+        else 
+            in1_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_AR_assign_proc : process(m_axi_in1_mem_ARREADY, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            in1_mem_blk_n_AR <= m_axi_in1_mem_ARREADY;
+        else 
+            in1_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in1_mem_blk_n_R_assign_proc : process(m_axi_in1_mem_RVALID, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            in1_mem_blk_n_R <= m_axi_in1_mem_RVALID;
+        else 
+            in1_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_loc_0_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_0_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_0_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_0_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_0_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_0_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_0_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_0_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_0_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_10_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_10_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_10_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_10_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_10_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_10_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_10_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_10_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_11_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_11_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_11_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_11_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_11_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_11_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_11_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_11_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_11_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_11_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_12_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_12_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_12_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_12_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_12_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_12_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_12_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_12_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_12_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_12_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_13_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_13_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_13_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_13_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_13_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_13_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_13_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_13_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_14_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_14_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_14_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_14_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_14_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_14_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_14_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_14_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_15_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_15_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_15_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_15_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_15_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_15_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_15_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_15_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_15_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_15_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_16_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_16_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_16_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_16_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_16_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_16_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_16_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_16_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_10) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_16_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_16_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_17_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_17_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_17_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_17_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_17_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_17_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_11) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_17_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_17_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_18_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_18_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_18_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_18_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_18_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_18_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_12) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_18_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_18_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_19_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_19_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_19_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_19_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_19_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_19_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_19_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_19_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_13) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_19_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_19_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_1_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_1_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_1_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_1_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_1_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_1_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_1_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_1_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_1_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_20_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_20_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_20_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_20_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_20_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_20_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_20_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_20_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_14) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_20_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_20_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_21_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_21_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_21_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_21_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_21_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_21_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_21_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_21_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_15) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_21_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_21_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_22_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_22_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_22_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_22_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_22_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_22_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_22_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_22_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_16) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_22_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_22_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_23_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_23_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_23_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_23_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_23_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_23_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_23_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_23_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_17) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_23_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_23_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_24_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_24_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_24_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_24_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_24_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_24_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_24_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_24_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_18) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_24_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_24_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_25_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_25_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_25_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_25_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_25_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_25_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_19) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_25_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_25_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_26_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_26_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_26_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_26_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_26_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_26_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_1A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_26_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_26_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_27_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_27_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_27_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_27_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_27_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_27_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_27_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_27_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_1B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_27_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_27_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_28_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_28_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_28_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_28_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_28_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_28_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_28_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_28_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_1C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_28_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_28_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_29_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_29_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_29_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_29_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_29_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_29_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_29_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_29_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_1D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_29_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_29_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_2_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_2_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_2_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_2_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_2_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_2_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_2_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_2) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_2_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_2_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_30_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_30_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_30_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_30_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_30_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_30_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_30_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_30_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_1E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_30_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_30_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_31_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_31_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_31_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_31_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_31_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_31_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_31_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_31_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_1F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_31_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_31_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_32_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_32_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_32_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_32_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_32_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_32_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_32_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_32_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_20) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_32_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_32_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_33_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_33_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_33_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_33_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_33_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_33_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_21) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_33_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_33_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_34_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_34_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_34_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_34_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_34_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_34_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_22) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_34_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_34_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_35_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_35_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_35_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_35_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_35_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_35_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_35_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_35_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_23) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_35_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_35_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_36_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_36_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_36_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_36_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_36_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_36_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_36_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_36_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_24) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_36_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_36_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_37_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_37_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_37_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_37_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_37_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_37_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_37_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_37_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_25) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_37_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_37_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_38_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_38_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_38_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_38_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_38_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_38_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_38_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_38_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_26) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_38_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_38_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_39_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_39_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_39_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_39_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_39_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_39_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_39_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_39_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_27) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_39_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_39_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_3_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_3_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_3_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_3_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_3_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_3_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_3_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_3) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_3_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_3_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_40_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_40_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_40_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_40_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_40_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_40_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_40_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_40_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_28) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_40_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_40_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_41_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_41_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_41_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_41_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_41_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_41_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_29) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_41_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_41_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_42_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_42_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_42_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_42_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_42_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_42_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_2A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_42_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_42_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_43_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_43_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_43_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_43_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_43_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_43_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_43_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_43_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_2B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_43_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_43_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_44_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_44_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_44_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_44_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_44_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_44_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_44_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_44_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_2C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_44_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_44_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_45_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_45_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_45_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_45_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_45_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_45_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_2D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_45_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_45_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_46_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_46_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_46_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_46_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_46_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_46_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_2E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_46_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_46_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_47_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_47_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_47_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_47_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_47_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_47_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_47_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_47_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_2F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_47_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_47_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_48_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_48_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_48_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_48_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_48_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_48_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_48_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_48_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_30) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_48_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_48_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_49_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_49_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_49_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_49_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_49_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_49_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_31) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_49_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_49_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_4_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_4_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_4_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_4_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_4_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_4_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_4_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_4) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_4_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_4_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_50_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_50_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_50_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_50_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_50_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_50_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_32) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_50_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_50_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_51_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_51_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_51_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_51_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_51_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_51_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_51_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_51_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_33) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_51_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_51_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_52_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_52_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_52_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_52_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_52_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_52_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_52_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_52_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_34) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_52_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_52_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_53_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_53_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_53_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_53_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_53_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_53_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_53_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_53_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_35) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_53_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_53_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_54_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_54_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_54_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_54_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_54_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_54_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_54_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_54_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_36) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_54_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_54_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_55_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_55_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_55_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_55_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_55_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_55_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_55_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_55_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_37) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_55_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_55_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_56_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_56_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_56_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_56_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_56_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_56_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_56_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_56_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_38) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_56_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_56_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_57_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_57_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_57_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_57_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_57_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_57_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_39) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_57_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_57_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_58_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_58_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_58_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_58_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_58_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_58_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_3A) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_58_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_58_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_59_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_59_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_59_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_59_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_59_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_59_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_59_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_59_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_3B) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_59_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_59_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_5_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_5_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_5_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_5_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_5_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_5_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_5_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_5) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_5_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_5_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_60_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_60_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_60_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_60_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_60_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_60_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_60_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_60_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_3C) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_60_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_60_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_61_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_61_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_61_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_61_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_61_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_61_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_3D) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_61_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_61_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_62_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_62_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_62_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_62_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_62_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_62_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_62_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_62_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_3E) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_62_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_62_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_63_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_63_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_63_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_63_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_63_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_63_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_63_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_63_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_3F) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_63_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_63_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_6_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_6_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_6_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_6_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_6_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_6_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_6_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_6) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_6_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_6_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_7_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_7_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_7_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_7_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_7_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_7_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_7_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_7) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_7_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_7_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_8_address0_assign_proc : process(ap_block_pp1_stage0, ap_CS_fsm_pp2_stage0, sext_ln38_fu_3739_p1, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1))) then 
+            in2_loc_8_address0 <= sext_ln38_fu_3739_p1(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_8_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_8_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_8_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp1_iter2, ap_enable_reg_pp2_iter1)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1)))) then 
+            in2_loc_8_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_8_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_8) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_8_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_8_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_9_address0_assign_proc : process(ap_block_pp1_stage0, sext_ln38_reg_4857, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2, ap_block_pp2_stage0, zext_ln28_fu_3544_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_address0 <= sext_ln38_reg_4857(6 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_address0 <= zext_ln28_fu_3544_p1(6 - 1 downto 0);
+        else 
+            in2_loc_9_address0 <= "XXXXXX";
+        end if; 
+    end process;
+
+
+    in2_loc_9_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_block_pp1_stage0_11001, ap_enable_reg_pp2_iter2, ap_enable_reg_pp1_iter2)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter2 = ap_const_logic_1)))) then 
+            in2_loc_9_ce0 <= ap_const_logic_1;
+        else 
+            in2_loc_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_loc_9_we0_assign_proc : process(ap_block_pp1_stage0_11001, trunc_ln1_reg_4495_pp1_iter1_reg, ap_enable_reg_pp1_iter2)
+    begin
+        if (((trunc_ln1_reg_4495_pp1_iter1_reg = ap_const_lv6_9) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter2 = ap_const_logic_1))) then 
+            in2_loc_9_we0 <= ap_const_logic_1;
+        else 
+            in2_loc_9_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_ARVALID_assign_proc : process(ap_CS_fsm_state12, in2_mem_ARREADY)
+    begin
+        if (((in2_mem_ARREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state12))) then 
+            in2_mem_ARVALID <= ap_const_logic_1;
+        else 
+            in2_mem_ARVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_RREADY_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_RREADY <= ap_const_logic_1;
+        else 
+            in2_mem_RREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_AR_assign_proc : process(m_axi_in2_mem_ARREADY, ap_CS_fsm_state12)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state12)) then 
+            in2_mem_blk_n_AR <= m_axi_in2_mem_ARREADY;
+        else 
+            in2_mem_blk_n_AR <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    in2_mem_blk_n_R_assign_proc : process(m_axi_in2_mem_RVALID, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
+            in2_mem_blk_n_R <= m_axi_in2_mem_RVALID;
+        else 
+            in2_mem_blk_n_R <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    j_fu_3685_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(select_ln31_fu_3642_p3));
+
+    out_loc_address0_assign_proc : process(ap_block_pp3_stage0, ap_CS_fsm_pp3_stage0, out_loc_addr_reg_4598_pp2_iter3_reg, ap_enable_reg_pp3_iter0, ap_enable_reg_pp2_iter4, ap_block_pp2_stage0, zext_ln42_fu_4351_p1)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp3_stage0) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1))) then 
+            out_loc_address0 <= zext_ln42_fu_4351_p1(12 - 1 downto 0);
+        elsif (((ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter4 = ap_const_logic_1))) then 
+            out_loc_address0 <= out_loc_addr_reg_4598_pp2_iter3_reg;
+        else 
+            out_loc_address0 <= "XXXXXXXXXXXX";
+        end if; 
+    end process;
+
+
+    out_loc_ce0_assign_proc : process(ap_block_pp2_stage0_11001, ap_CS_fsm_pp3_stage0, ap_block_pp3_stage0_11001, ap_enable_reg_pp3_iter0, ap_enable_reg_pp2_iter4)
+    begin
+        if ((((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp3_stage0) and (ap_enable_reg_pp3_iter0 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter4 = ap_const_logic_1)))) then 
+            out_loc_ce0 <= ap_const_logic_1;
+        else 
+            out_loc_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_loc_ce1_assign_proc : process(ap_block_pp2_stage0_11001, ap_enable_reg_pp2_iter8)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter8 = ap_const_logic_1))) then 
+            out_loc_ce1 <= ap_const_logic_1;
+        else 
+            out_loc_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    out_loc_d1 <= std_logic_vector(unsigned(add_ln38_30_reg_6365) + unsigned(add_ln38_62_fu_4329_p2));
+
+    out_loc_we1_assign_proc : process(ap_block_pp2_stage0_11001, icmp_ln31_reg_4578_pp2_iter7_reg, ap_enable_reg_pp2_iter8)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (icmp_ln31_reg_4578_pp2_iter7_reg = ap_const_lv1_0) and (ap_enable_reg_pp2_iter8 = ap_const_logic_1))) then 
+            out_loc_we1 <= ap_const_logic_1;
+        else 
+            out_loc_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_AWVALID_assign_proc : process(ap_CS_fsm_state34, out_mem_AWREADY)
+    begin
+        if (((out_mem_AWREADY = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state34))) then 
+            out_mem_AWVALID <= ap_const_logic_1;
+        else 
+            out_mem_AWVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_BREADY_assign_proc : process(ap_CS_fsm_state42, out_mem_BVALID)
+    begin
+        if (((out_mem_BVALID = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state42))) then 
+            out_mem_BREADY <= ap_const_logic_1;
+        else 
+            out_mem_BREADY <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_WVALID_assign_proc : process(ap_enable_reg_pp3_iter2, icmp_ln42_reg_6380_pp3_iter1_reg, ap_block_pp3_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp3_stage0_11001) and (icmp_ln42_reg_6380_pp3_iter1_reg = ap_const_lv1_0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1))) then 
+            out_mem_WVALID <= ap_const_logic_1;
+        else 
+            out_mem_WVALID <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_AW_assign_proc : process(m_axi_out_mem_AWREADY, ap_CS_fsm_state34)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state34)) then 
+            out_mem_blk_n_AW <= m_axi_out_mem_AWREADY;
+        else 
+            out_mem_blk_n_AW <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_B_assign_proc : process(m_axi_out_mem_BVALID, ap_CS_fsm_state42)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state42)) then 
+            out_mem_blk_n_B <= m_axi_out_mem_BVALID;
+        else 
+            out_mem_blk_n_B <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    out_mem_blk_n_W_assign_proc : process(m_axi_out_mem_WREADY, ap_enable_reg_pp3_iter2, ap_block_pp3_stage0, icmp_ln42_reg_6380_pp3_iter1_reg)
+    begin
+        if (((icmp_ln42_reg_6380_pp3_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp3_stage0) and (ap_enable_reg_pp3_iter2 = ap_const_logic_1))) then 
+            out_mem_blk_n_W <= m_axi_out_mem_WREADY;
+        else 
+            out_mem_blk_n_W <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    select_ln31_1_fu_3650_p3 <= 
+        i_fu_3631_p2 when (icmp_ln33_fu_3637_p2(0) = '1') else 
+        ap_phi_mux_i_0_phi_fu_3333_p4;
+    select_ln31_fu_3642_p3 <= 
+        ap_const_lv32_0 when (icmp_ln33_fu_3637_p2(0) = '1') else 
+        j_0_reg_3340;
+        sext_ln38_fu_3739_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(select_ln31_reg_4587),64));
+
+    tmp_cast_fu_3662_p3 <= (trunc_ln38_fu_3658_p1 & ap_const_lv6_0);
+    trunc_ln27_fu_3447_p1 <= phi_ln27_reg_3296(6 - 1 downto 0);
+    trunc_ln28_fu_3530_p1 <= phi_ln28_reg_3307(6 - 1 downto 0);
+    trunc_ln38_1_fu_3670_p1 <= select_ln31_fu_3642_p3(14 - 1 downto 0);
+    trunc_ln38_fu_3658_p1 <= select_ln31_1_fu_3650_p3(8 - 1 downto 0);
+    zext_ln27_fu_3451_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(lshr_ln_reg_4404_pp0_iter1_reg),64));
+    zext_ln28_fu_3544_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(trunc_ln28_reg_4490_pp1_iter1_reg),64));
+    zext_ln31_1_fu_3691_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(select_ln31_1_reg_4592),64));
+    zext_ln31_fu_3611_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(dim_read_reg_4356),64));
+    zext_ln38_fu_3680_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(add_ln38_64_fu_3674_p2),64));
+    zext_ln42_fu_4351_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(phi_ln42_reg_3351),64));
+end behav;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in1_loc_0.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in1_loc_0.vhd
new file mode 100755
index 0000000..609e4b6
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in1_loc_0.vhd
@@ -0,0 +1,112 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_in1_loc_0_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 6; 
+            MEM_SIZE    : integer := 64
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_in1_loc_0_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_in1_loc_0 is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 64;
+        AddressWidth : INTEGER := 6);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_in1_loc_0 is
+    component mmult_in1_loc_0_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_in1_loc_0_ram_U :  component mmult_in1_loc_0_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in1_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in1_mem_m_axi.vhd
new file mode 100755
index 0000000..5d4f5b4
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in1_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi;
+
+architecture behave of mmult_in1_mem_m_axi is
+    component mmult_in1_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_write;
+
+    component mmult_in1_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in1_mem_m_axi_read;
+
+    component mmult_in1_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in1_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in1_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in1_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in1_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in1_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in1_mem_m_axi_fifo;
+
+architecture behave of mmult_in1_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in1_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in1_mem_m_axi_decoder;
+
+architecture behav of mmult_in1_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in1_mem_m_axi_throttl;
+
+architecture behav of mmult_in1_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in1_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in1_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_read;
+
+architecture behave of mmult_in1_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in1_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in1_mem_m_axi_write;
+
+architecture behave of mmult_in1_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in1_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in1_mem_m_axi_fifo;
+
+    component mmult_in1_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in1_mem_m_axi_reg_slice;
+
+    component mmult_in1_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in1_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in1_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in1_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in1_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in1_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in1_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in1_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in1_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in2_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in2_mem_m_axi.vhd
new file mode 100755
index 0000000..84687e2
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_in2_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi;
+
+architecture behave of mmult_in2_mem_m_axi is
+    component mmult_in2_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_write;
+
+    component mmult_in2_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_in2_mem_m_axi_read;
+
+    component mmult_in2_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_in2_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_in2_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_in2_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_in2_mem_m_axi_reg_slice;
+
+architecture behave of mmult_in2_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_in2_mem_m_axi_fifo;
+
+architecture behave of mmult_in2_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_in2_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_in2_mem_m_axi_decoder;
+
+architecture behav of mmult_in2_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_in2_mem_m_axi_throttl;
+
+architecture behav of mmult_in2_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_in2_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_in2_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_read;
+
+architecture behave of mmult_in2_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_in2_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_in2_mem_m_axi_write;
+
+architecture behave of mmult_in2_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_in2_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_in2_mem_m_axi_fifo;
+
+    component mmult_in2_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_in2_mem_m_axi_reg_slice;
+
+    component mmult_in2_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_in2_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_in2_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_in2_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_in2_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_in2_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_in2_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_in2_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_in2_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_mul_32ns_32bkb.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_mul_32ns_32bkb.vhd
new file mode 100755
index 0000000..0c59c29
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_mul_32ns_32bkb.vhd
@@ -0,0 +1,88 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult_mul_32ns_32bkb_MulnS_0 is
+port (
+    clk: in std_logic;
+    ce: in std_logic;
+    a: in std_logic_vector(32 - 1 downto 0);
+    b: in std_logic_vector(32 - 1 downto 0);
+    p: out std_logic_vector(64 - 1 downto 0));
+end entity;
+
+architecture behav of mmult_mul_32ns_32bkb_MulnS_0 is
+    signal tmp_product : std_logic_vector(64 - 1 downto 0);
+    signal a_i : std_logic_vector(32 - 1 downto 0);
+    signal b_i : std_logic_vector(32 - 1 downto 0);
+    signal p_tmp : std_logic_vector(64 - 1 downto 0);
+    signal a_reg0 : std_logic_vector(32 - 1 downto 0);
+    signal b_reg0 : std_logic_vector(32 - 1 downto 0);
+
+    signal buff0 : std_logic_vector(64 - 1 downto 0);
+begin
+    a_i <= a;
+    b_i <= b;
+    p <= p_tmp;
+
+    p_tmp <= buff0;
+    tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 64));
+
+    process(clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (ce = '1') then
+                a_reg0 <= a_i;
+                b_reg0 <= b_i;
+                buff0 <= tmp_product;
+            end if;
+        end if;
+    end process;
+end architecture;
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_mul_32ns_32bkb is
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        ce : IN STD_LOGIC;
+        din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
+        din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
+        dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_mul_32ns_32bkb is
+    component mmult_mul_32ns_32bkb_MulnS_0 is
+        port (
+            clk : IN STD_LOGIC;
+            ce : IN STD_LOGIC;
+            a : IN STD_LOGIC_VECTOR;
+            b : IN STD_LOGIC_VECTOR;
+            p : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_mul_32ns_32bkb_MulnS_0_U :  component mmult_mul_32ns_32bkb_MulnS_0
+    port map (
+        clk => clk,
+        ce => ce,
+        a => din0,
+        b => din1,
+        p => dout);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_mul_32s_32scud.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_mul_32s_32scud.vhd
new file mode 100755
index 0000000..3664256
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_mul_32s_32scud.vhd
@@ -0,0 +1,88 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mmult_mul_32s_32scud_MulnS_1 is
+port (
+    clk: in std_logic;
+    ce: in std_logic;
+    a: in std_logic_vector(32 - 1 downto 0);
+    b: in std_logic_vector(32 - 1 downto 0);
+    p: out std_logic_vector(32 - 1 downto 0));
+end entity;
+
+architecture behav of mmult_mul_32s_32scud_MulnS_1 is
+    signal tmp_product : std_logic_vector(32 - 1 downto 0);
+    signal a_i : std_logic_vector(32 - 1 downto 0);
+    signal b_i : std_logic_vector(32 - 1 downto 0);
+    signal p_tmp : std_logic_vector(32 - 1 downto 0);
+    signal a_reg0 : std_logic_vector(32 - 1 downto 0);
+    signal b_reg0 : std_logic_vector(32 - 1 downto 0);
+
+    signal buff0 : std_logic_vector(32 - 1 downto 0);
+begin
+    a_i <= a;
+    b_i <= b;
+    p <= p_tmp;
+
+    p_tmp <= buff0;
+    tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 32));
+
+    process(clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (ce = '1') then
+                a_reg0 <= a_i;
+                b_reg0 <= b_i;
+                buff0 <= tmp_product;
+            end if;
+        end if;
+    end process;
+end architecture;
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_mul_32s_32scud is
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        ce : IN STD_LOGIC;
+        din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
+        din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
+        dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_mul_32s_32scud is
+    component mmult_mul_32s_32scud_MulnS_1 is
+        port (
+            clk : IN STD_LOGIC;
+            ce : IN STD_LOGIC;
+            a : IN STD_LOGIC_VECTOR;
+            b : IN STD_LOGIC_VECTOR;
+            p : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_mul_32s_32scud_MulnS_1_U :  component mmult_mul_32s_32scud_MulnS_1
+    port map (
+        clk => clk,
+        ce => ce,
+        a => din0,
+        b => din1,
+        p => dout);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_out_loc.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_out_loc.vhd
new file mode 100755
index 0000000..ea7bf78
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_out_loc.vhd
@@ -0,0 +1,129 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_out_loc_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 12; 
+            MEM_SIZE    : integer := 4096
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce1       : in std_logic; 
+          d1        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we1       : in std_logic; 
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_out_loc_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+        end if;
+    end if;
+end process;
+
+
+p_memory_access_1: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce1 = '1') then 
+            if (we1 = '1') then 
+                ram(CONV_INTEGER(addr1)) := d1; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_out_loc is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 4096;
+        AddressWidth : INTEGER := 12);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_out_loc is
+    component mmult_out_loc_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            q0 : OUT STD_LOGIC_VECTOR;
+            addr1 : IN STD_LOGIC_VECTOR;
+            ce1 : IN STD_LOGIC;
+            we1 : IN STD_LOGIC;
+            d1 : IN STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_out_loc_ram_U :  component mmult_out_loc_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        q0 => q0,
+        addr1 => address1,
+        ce1 => ce1,
+        we1 => we1,
+        d1 => d1);
+
+end architecture;
+
+
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_out_mem_m_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_out_mem_m_axi.vhd
new file mode 100755
index 0000000..f2bd717
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_out_mem_m_axi.vhd
@@ -0,0 +1,3306 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi is
+    generic (
+        CONSERVATIVE              : INTEGER := 0;
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 2#000#;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        -- system signal
+        ACLK            : in STD_LOGIC;
+        ARESET          : in STD_LOGIC;
+        ACLK_EN         : in STD_LOGIC;
+        -- write address channel
+        AWID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        AWSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        AWLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        AWCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        AWPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        AWQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        AWREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        AWUSER          : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        -- write data channel
+        WID             : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        -- write response channel
+        BID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        BUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        -- read address channel
+        ARID            : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out STD_LOGIC_VECTOR(7 downto 0);
+        ARSIZE          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARBURST         : out STD_LOGIC_VECTOR(1 downto 0);
+        ARLOCK          : out STD_LOGIC_VECTOR(1 downto 0);
+        ARCACHE         : out STD_LOGIC_VECTOR(3 downto 0);
+        ARPROT          : out STD_LOGIC_VECTOR(2 downto 0);
+        ARQOS           : out STD_LOGIC_VECTOR(3 downto 0);
+        ARREGION        : out STD_LOGIC_VECTOR(3 downto 0);
+        ARUSER          : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        -- read data channel
+        RID             : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  STD_LOGIC_VECTOR(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+
+        -- internal bus ports
+        -- write address channel
+        I_AWID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_AWADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_AWLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_AWSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_AWCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_AWQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_AWUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        I_AWVALID       : in  STD_LOGIC;
+        I_AWREADY       : out STD_LOGIC;
+        -- write data channel
+        I_WID           : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_WDATA         : in  STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_WSTRB         : in  STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
+        I_WLAST         : in  STD_LOGIC;
+        I_WUSER         : in  STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        I_WVALID        : in  STD_LOGIC;
+        I_WREADY        : out STD_LOGIC;
+        -- write response channel
+        I_BID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_BRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_BUSER         : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        I_BVALID        : out STD_LOGIC;
+        I_BREADY        : in  STD_LOGIC;
+        -- read address channel
+        I_ARID          : in  STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_ARADDR        : in  STD_LOGIC_VECTOR(USER_AW-1 downto 0);
+        I_ARLEN         : in  STD_LOGIC_VECTOR(31 downto 0);
+        I_ARSIZE        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARBURST       : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARLOCK        : in  STD_LOGIC_VECTOR(1 downto 0);
+        I_ARCACHE       : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARPROT        : in  STD_LOGIC_VECTOR(2 downto 0);
+        I_ARQOS         : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARREGION      : in  STD_LOGIC_VECTOR(3 downto 0);
+        I_ARUSER        : in  STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        I_ARVALID       : in  STD_LOGIC;
+        I_ARREADY       : out STD_LOGIC;
+        -- read data channel
+        I_RID           : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
+        I_RDATA         : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
+        I_RRESP         : out STD_LOGIC_VECTOR(1 downto 0);
+        I_RLAST         : out STD_LOGIC;
+        I_RUSER         : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        I_RVALID        : out STD_LOGIC;
+        I_RREADY        : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi;
+
+architecture behave of mmult_out_mem_m_axi is
+    component mmult_out_mem_m_axi_write is
+        generic (
+            NUM_WRITE_OUTSTANDING     : INTEGER := 1;
+            MAX_WRITE_BURST_LENGTH    : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+            C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            AWLEN           : out UNSIGNED(7 downto 0);
+            AWSIZE          : out UNSIGNED(2 downto 0);
+            AWBURST         : out UNSIGNED(1 downto 0);
+            AWLOCK          : out UNSIGNED(1 downto 0);
+            AWCACHE         : out UNSIGNED(3 downto 0);
+            AWPROT          : out UNSIGNED(2 downto 0);
+            AWQOS           : out UNSIGNED(3 downto 0);
+            AWREGION        : out UNSIGNED(3 downto 0);
+            AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            AWVALID         : out STD_LOGIC;
+            AWREADY         : in  STD_LOGIC;
+            WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+            WLAST           : out STD_LOGIC;
+            WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            WVALID          : out STD_LOGIC;
+            WREADY          : in  STD_LOGIC;
+            BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            BRESP           : in  UNSIGNED(1 downto 0);
+            BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+            BVALID          : in  STD_LOGIC;
+            BREADY          : out STD_LOGIC;
+            wreq_valid      : in  STD_LOGIC;
+            wreq_ack        : out STD_LOGIC;
+            wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            wreq_length     : in  UNSIGNED(31 downto 0);
+            wreq_cache      : in  UNSIGNED(3 downto 0);
+            wreq_prot       : in  UNSIGNED(2 downto 0);
+            wreq_qos        : in  UNSIGNED(3 downto 0);
+            wreq_region     : in  UNSIGNED(3 downto 0);
+            wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+            wdata_valid     : in  STD_LOGIC;
+            wdata_ack       : out STD_LOGIC;
+            wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+            wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+            wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+            wrsp_valid      : out STD_LOGIC;
+            wrsp_ack        : in  STD_LOGIC;
+            wrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_write;
+
+    component mmult_out_mem_m_axi_read is
+        generic (
+            NUM_READ_OUTSTANDING      : INTEGER := 1;
+            MAX_READ_BURST_LENGTH     : INTEGER := 1;
+            C_M_AXI_ID_WIDTH          : INTEGER := 1;
+            C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+            C_TARGET_ADDR             : INTEGER := 16#00000000#;
+            C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+            C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+            C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+            C_USER_VALUE              : INTEGER := 0;
+            C_PROT_VALUE              : INTEGER := 0;
+            C_CACHE_VALUE             : INTEGER := 2#0011#;
+            USER_DW                   : INTEGER := 16;
+            USER_AW                   : INTEGER := 32;
+            USER_MAXREQS              : INTEGER := 16);
+        port (
+            ACLK            : in  STD_LOGIC;
+            ARESET          : in  STD_LOGIC;
+            ACLK_EN         : in  STD_LOGIC;
+            ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+            ARLEN           : out UNSIGNED(7 downto 0);
+            ARSIZE          : out UNSIGNED(2 downto 0);
+            ARBURST         : out UNSIGNED(1 downto 0);
+            ARLOCK          : out UNSIGNED(1 downto 0);
+            ARCACHE         : out UNSIGNED(3 downto 0);
+            ARPROT          : out UNSIGNED(2 downto 0);
+            ARQOS           : out UNSIGNED(3 downto 0);
+            ARREGION        : out UNSIGNED(3 downto 0);
+            ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            ARVALID         : out STD_LOGIC;
+            ARREADY         : in  STD_LOGIC;
+            RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+            RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+            RRESP           : in  UNSIGNED(1 downto 0);
+            RLAST           : in  STD_LOGIC;
+            RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+            RVALID          : in  STD_LOGIC;
+            RREADY          : out STD_LOGIC;
+            rreq_valid      : in  STD_LOGIC;
+            rreq_ack        : out STD_LOGIC;
+            rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+            rreq_length     : in  UNSIGNED(31 downto 0);
+            rreq_cache      : in  UNSIGNED(3 downto 0);
+            rreq_prot       : in  UNSIGNED(2 downto 0);
+            rreq_qos        : in  UNSIGNED(3 downto 0);
+            rreq_region     : in  UNSIGNED(3 downto 0);
+            rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+            rdata_valid     : out STD_LOGIC;
+            rdata_ack       : in  STD_LOGIC;
+            rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+            rrsp            : out UNSIGNED(1 downto 0));
+    end component mmult_out_mem_m_axi_read;
+
+    component mmult_out_mem_m_axi_throttl is
+        generic (
+            USED_FIX      : BOOLEAN := true;
+            FIX_VALUE     : INTEGER := 4;
+            ADDR_WIDTH    : INTEGER := 32;
+            DATA_WIDTH    : INTEGER := 32;
+            DEPTH         : INTEGER := 16;
+            USER_MAXREQS  : INTEGER := 16;
+            CONSERVATIVE  : INTEGER := 0;
+            AVERAGE_MODE  : BOOLEAN := false);
+        port (
+            clk             : in  STD_LOGIC;
+            reset           : in  STD_LOGIC;
+            ce              : in  STD_LOGIC;
+            in_addr         : in  STD_LOGIC_VECTOR;
+            in_len          : in  STD_LOGIC_VECTOR;
+            in_req_valid    : in  STD_LOGIC;
+            out_req_ready   : out STD_LOGIC;
+            out_addr        : out STD_LOGIC_VECTOR;
+            out_len         : out STD_LOGIC_VECTOR;
+            out_req_valid   : out STD_LOGIC;
+            in_req_ready    : in  STD_LOGIC;
+            in_data         : in  STD_LOGIC_VECTOR;
+            in_strb         : in  STD_LOGIC_VECTOR;
+            in_last         : in  STD_LOGIC;
+            in_data_valid   : in  STD_LOGIC;
+            out_data_ready  : out STD_LOGIC;
+            out_data        : out STD_LOGIC_VECTOR;
+            out_strb        : out STD_LOGIC_VECTOR;
+            out_last        : out STD_LOGIC;
+            out_data_valid  : out STD_LOGIC;
+            in_data_ready   : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_throttl;
+
+    signal      AWADDR_Dummy    : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
+    signal      AWLEN_Dummy     : STD_LOGIC_VECTOR(7 downto 0);
+    signal      AWVALID_Dummy   : STD_LOGIC;
+    signal      AWREADY_Dummy   : STD_LOGIC;
+    signal      WDATA_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
+    signal      WSTRB_Dummy     : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+    signal      WLAST_Dummy     : STD_LOGIC;
+    signal      WVALID_Dummy    : STD_LOGIC;
+    signal      WREADY_Dummy    : STD_LOGIC;
+
+begin
+
+    wreq_throttl : mmult_out_mem_m_axi_throttl
+        generic map (
+            USED_FIX        => false,
+            ADDR_WIDTH      => C_M_AXI_ADDR_WIDTH,
+            DATA_WIDTH      => C_M_AXI_DATA_WIDTH,
+            DEPTH           => MAX_WRITE_BURST_LENGTH,
+            USER_MAXREQS    => NUM_WRITE_OUTSTANDING,
+            CONSERVATIVE    => CONSERVATIVE,
+            AVERAGE_MODE    => false)
+        port map (
+            clk             => ACLK,
+            reset           => ARESET,
+            ce              => ACLK_EN,
+            in_addr         => AWADDR_Dummy,
+            in_len          => AWLEN_Dummy,
+            in_req_valid    => AWVALID_Dummy,
+            out_req_ready   => AWREADY_Dummy,
+            out_addr        => AWADDR,
+            out_len         => AWLEN,
+            out_req_valid   => AWVALID,
+            in_req_ready    => AWREADY,
+            in_data         => WDATA_Dummy,
+            in_strb         => WSTRB_Dummy,
+            in_last         => WLAST_Dummy,
+            in_data_valid   => WVALID_Dummy,
+            out_data_ready  => WREADY_Dummy,
+            out_data        => WDATA,
+            out_strb        => WSTRB,
+            out_last        => WLAST,
+            out_data_valid  => WVALID,
+            in_data_ready   => WREADY);
+
+    I_BID   <= (others => '0');
+    I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
+    I_RID   <= (others => '0');
+    I_RLAST <= '0';
+    I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
+
+    -- Instantiation
+    bus_write : mmult_out_mem_m_axi_write
+        generic map (
+            NUM_WRITE_OUTSTANDING     => NUM_WRITE_OUTSTANDING,
+            MAX_WRITE_BURST_LENGTH    => MAX_WRITE_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_AWUSER_WIDTH      => C_M_AXI_AWUSER_WIDTH,
+            C_M_AXI_WUSER_WIDTH       => C_M_AXI_WUSER_WIDTH,
+            C_M_AXI_BUSER_WIDTH       => C_M_AXI_BUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(AWID)      => AWID,
+            STD_LOGIC_VECTOR(AWADDR)    => AWADDR_Dummy,
+            STD_LOGIC_VECTOR(AWLEN)     => AWLEN_Dummy,
+            STD_LOGIC_VECTOR(AWSIZE)    => AWSIZE,
+            STD_LOGIC_VECTOR(AWBURST)   => AWBURST,
+            STD_LOGIC_VECTOR(AWLOCK)    => AWLOCK,
+            STD_LOGIC_VECTOR(AWCACHE)   => AWCACHE,
+            STD_LOGIC_VECTOR(AWPROT)    => AWPROT,
+            STD_LOGIC_VECTOR(AWQOS)     => AWQOS,
+            STD_LOGIC_VECTOR(AWREGION)  => AWREGION,
+            STD_LOGIC_VECTOR(AWUSER)    => AWUSER,
+            AWVALID                     => AWVALID_Dummy,
+            AWREADY                     => AWREADY_Dummy,
+            STD_LOGIC_VECTOR(WID)       => WID,
+            STD_LOGIC_VECTOR(WDATA)     => WDATA_Dummy,
+            STD_LOGIC_VECTOR(WSTRB)     => WSTRB_Dummy,
+            WLAST                       => WLAST_Dummy,
+            STD_LOGIC_VECTOR(WUSER)     => WUSER,
+            WVALID                      => WVALID_Dummy,
+            WREADY                      => WREADY_Dummy,
+            BID                         => UNSIGNED(BID),
+            BRESP                       => UNSIGNED(BRESP),
+            BUSER                       => UNSIGNED(BUSER),
+            BVALID                      => BVALID,
+            BREADY                      => BREADY,
+            wreq_valid                  => I_AWVALID,
+            wreq_ack                    => I_AWREADY,
+            wreq_addr                   => UNSIGNED(I_AWADDR),
+            wreq_length                 => UNSIGNED(I_AWLEN),
+            wreq_cache                  => UNSIGNED(I_AWCACHE),
+            wreq_prot                   => UNSIGNED(I_AWPROT),
+            wreq_qos                    => UNSIGNED(I_AWQOS),
+            wreq_region                 => UNSIGNED(I_AWREGION),
+            wreq_user                   => UNSIGNED(I_AWUSER),
+            wdata_valid                 => I_WVALID,
+            wdata_ack                   => I_WREADY,
+            wdata_strb                  => UNSIGNED(I_WSTRB),
+            wdata_user                  => UNSIGNED(I_WUSER),
+            wdata_data                  => UNSIGNED(I_WDATA),
+            wrsp_valid                  => I_BVALID,
+            wrsp_ack                    => I_BREADY,
+            STD_LOGIC_VECTOR(wrsp)      => I_BRESP);
+
+    bus_read : mmult_out_mem_m_axi_read
+        generic map (
+            NUM_READ_OUTSTANDING      => NUM_READ_OUTSTANDING,
+            MAX_READ_BURST_LENGTH     => MAX_READ_BURST_LENGTH,
+            C_M_AXI_ID_WIDTH          => C_M_AXI_ID_WIDTH,
+            C_M_AXI_ADDR_WIDTH        => C_M_AXI_ADDR_WIDTH,
+            C_TARGET_ADDR             => C_TARGET_ADDR,
+            C_M_AXI_DATA_WIDTH        => C_M_AXI_DATA_WIDTH,
+            C_M_AXI_ARUSER_WIDTH      => C_M_AXI_ARUSER_WIDTH,
+            C_M_AXI_RUSER_WIDTH       => C_M_AXI_RUSER_WIDTH,
+            C_USER_VALUE              => C_USER_VALUE,
+            C_PROT_VALUE              => C_PROT_VALUE,
+            C_CACHE_VALUE             => C_CACHE_VALUE,
+            USER_DW                   => USER_DW,
+            USER_AW                   => USER_AW,
+            USER_MAXREQS              => USER_MAXREQS)
+        port map (
+            ACLK                        => ACLK,
+            ARESET                      => ARESET,
+            ACLK_EN                     => ACLK_EN,
+            STD_LOGIC_VECTOR(ARID)      => ARID,
+            STD_LOGIC_VECTOR(ARADDR)    => ARADDR,
+            STD_LOGIC_VECTOR(ARLEN)     => ARLEN,
+            STD_LOGIC_VECTOR(ARSIZE)    => ARSIZE,
+            STD_LOGIC_VECTOR(ARBURST)   => ARBURST,
+            STD_LOGIC_VECTOR(ARLOCK)    => ARLOCK,
+            STD_LOGIC_VECTOR(ARCACHE)   => ARCACHE,
+            STD_LOGIC_VECTOR(ARPROT)    => ARPROT,
+            STD_LOGIC_VECTOR(ARQOS)     => ARQOS,
+            STD_LOGIC_VECTOR(ARREGION)  => ARREGION,
+            STD_LOGIC_VECTOR(ARUSER)    => ARUSER,
+            ARVALID                     => ARVALID,
+            ARREADY                     => ARREADY,
+            RID                         => UNSIGNED(RID),
+            RDATA                       => UNSIGNED(RDATA),
+            RRESP                       => UNSIGNED(RRESP),
+            RLAST                       => RLAST,
+            RUSER                       => UNSIGNED(RUSER),
+            RVALID                      => RVALID,
+            RREADY                      => RREADY,
+            rreq_valid                  => I_ARVALID,
+            rreq_ack                    => I_ARREADY,
+            rreq_addr                   => UNSIGNED(I_ARADDR),
+            rreq_length                 => UNSIGNED(I_ARLEN),
+            rreq_cache                  => UNSIGNED(I_ARCACHE),
+            rreq_prot                   => UNSIGNED(I_ARPROT),
+            rreq_qos                    => UNSIGNED(I_ARQOS),
+            rreq_region                 => UNSIGNED(I_ARREGION),
+            rreq_user                   => UNSIGNED(I_ARUSER),
+            rdata_valid                 => I_RVALID,
+            rdata_ack                   => I_RREADY,
+            STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
+            STD_LOGIC_VECTOR(rrsp)      => I_RRESP);
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_reg_slice is
+    generic (
+        N           : INTEGER := 8);
+    port (
+        -- system signals
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        -- slave side
+        s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+        s_valid     : in  STD_LOGIC;
+        s_ready     : out STD_LOGIC;
+        -- master side
+        m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+        m_valid     : out STD_LOGIC;
+        m_ready     : in  STD_LOGIC);
+end entity mmult_out_mem_m_axi_reg_slice;
+
+architecture behave of mmult_out_mem_m_axi_reg_slice is
+    constant ZERO                     : STD_LOGIC_VECTOR(1 downto 0) := "10";
+    constant ONE                      : STD_LOGIC_VECTOR(1 downto 0) := "11";
+    constant TWO                      : STD_LOGIC_VECTOR(1 downto 0) := "01";
+    signal   data_p1                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   data_p2                  : STD_LOGIC_VECTOR(N-1 downto 0);
+    signal   load_p1                  : STD_LOGIC;
+    signal   load_p2                  : STD_LOGIC;
+    signal   load_p1_from_p2          : STD_LOGIC;
+    signal   s_ready_t                : STD_LOGIC;
+    signal   state                    : STD_LOGIC_VECTOR(1 downto 0);
+    signal   next_st                     : STD_LOGIC_VECTOR(1 downto 0);
+begin
+    s_ready <= s_ready_t;
+    m_data  <= data_p1;
+    m_valid <= state(0);
+
+    load_p1 <= '1' when (state = ZERO and s_valid = '1') or
+                        (state = ONE  and s_valid = '1' and m_ready = '1') or
+                        (state = TWO  and m_ready = '1')
+               else '0';
+
+    load_p2         <= s_valid and s_ready_t;
+    load_p1_from_p2 <= '1' when state = TWO else '0';
+
+    data_p1_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p1 = '1') then
+                if (load_p1_from_p2 = '1') then
+                    data_p1 <= data_p2;
+                else
+                    data_p1 <= s_data;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    data_p2_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (load_p2 = '1') then
+                data_p2 <= s_data;
+            end if;
+        end if;
+    end process;
+
+    s_ready_t_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                s_ready_t <= '0';
+            elsif (state = ZERO) then
+                s_ready_t <= '1';
+            elsif (state = ONE and next_st = TWO) then
+                s_ready_t <= '0';
+            elsif (state = TWO and next_st = ONE) then
+                s_ready_t <= '1';
+            end if;
+        end if;
+    end process;
+
+    state_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if (reset = '1') then
+                state <= ZERO;
+            else
+                state <= next_st;
+            end if;
+        end if;
+    end process;
+
+    next_st_proc : process (state, s_valid, s_ready_t, m_ready)
+    begin
+        case state is
+            when ZERO =>
+                if (s_valid = '1' and s_ready_t = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= ZERO;
+                end if;
+            when ONE =>
+                if (s_valid = '0' and m_ready = '1') then
+                    next_st <= ZERO;
+                elsif (s_valid = '1' and m_ready = '0') then
+                    next_st <= TWO;
+                else
+                    next_st <= ONE;
+                end if;
+            when TWO =>
+                if (m_ready = '1') then
+                    next_st <= ONE;
+                else
+                    next_st <= TWO;
+                end if;
+            when others =>
+                next_st <= ZERO;
+        end case;
+    end process;
+
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_fifo is
+    generic (
+        DATA_BITS   : INTEGER := 8;
+        DEPTH       : INTEGER := 16;
+        DEPTH_BITS  : INTEGER := 4);
+    port (
+        sclk        : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        empty_n     : out STD_LOGIC;
+        full_n      : out STD_LOGIC;
+        rdreq       : in  STD_LOGIC;
+        wrreq       : in  STD_LOGIC;
+        q           : out UNSIGNED(DATA_BITS-1 downto 0);
+        data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+end entity mmult_out_mem_m_axi_fifo;
+
+architecture behave of mmult_out_mem_m_axi_fifo is
+    signal push, pop, data_vld, full_cond     : STD_LOGIC;
+    signal empty_n_tmp, full_n_tmp            : STD_LOGIC;
+    signal pout                               : INTEGER range 0 to DEPTH -1;
+    subtype word is UNSIGNED(DATA_BITS-1 downto 0);
+    type regFileType is array(0 to DEPTH-1) of word;
+    signal mem                                : regFileType;
+begin
+    full_n <= full_n_tmp;
+    empty_n <= empty_n_tmp;
+
+    depth_nlt2 : if DEPTH >= 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
+    end generate;
+
+    depth_lt2 : if DEPTH < 2 generate
+        full_cond <= '1' when push = '1' and pop = '0' else '0';
+    end generate;
+
+    push <= full_n_tmp and wrreq;
+    pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
+
+    q_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                q <= (others => '0');
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    q <= mem(pout);
+                end if;
+            end if;
+        end if;
+    end process q_proc;
+
+    empty_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                empty_n_tmp <= '0';
+            elsif sclk_en = '1' then
+                if not (empty_n_tmp = '1' and rdreq = '0') then
+                    empty_n_tmp <= data_vld;
+                end if;
+            end if;
+        end if;
+    end process empty_n_proc;
+
+    data_vld_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                data_vld <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    data_vld <= '1';
+                elsif push = '0' and pop = '1' and pout = 0 then
+                    data_vld <= '0';
+                end if;
+            end if;
+        end if;
+    end process data_vld_proc;
+
+    full_n_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                full_n_tmp <= '1';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    full_n_tmp <= '1';
+                elsif full_cond = '1' then
+                    full_n_tmp <= '0';
+                end if;
+            end if;
+        end if;
+    end process full_n_proc;
+
+    pout_proc : process (sclk)
+    begin
+        if (sclk'event and sclk = '1') then
+            if reset = '1' then
+                pout <= 0;
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' and data_vld = '1' then
+                    pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
+                elsif push = '0' and pop = '1' and pout /= 0 then
+                    pout <= pout - 1;
+                end if;
+            end if;
+        end  if;
+    end process pout_proc;
+
+    process (sclk)
+    begin
+        if (sclk'event and sclk = '1') and sclk_en = '1' then
+            if push = '1' then
+                for i in 0 to DEPTH - 2 loop
+                    mem(i+1) <= mem(i);
+                end loop;
+                mem(0) <= data;
+            end if;
+        end  if;
+    end process;
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_buffer is
+    generic (
+        MEM_STYLE  : STRING  := "block";
+        DATA_WIDTH : NATURAL := 32;
+        ADDR_WIDTH : NATURAL := 5;
+        DEPTH      : NATURAL := 32
+    );
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        sclk_en     : in  STD_LOGIC;
+        if_full_n   : out STD_LOGIC;
+        if_write_ce : in  STD_LOGIC;
+        if_write    : in  STD_LOGIC;
+        if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_empty_n  : out STD_LOGIC;
+        if_read_ce  : in  STD_LOGIC;
+        if_read     : in  STD_LOGIC;
+        if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of mmult_out_mem_m_axi_buffer is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem        : memtype;
+    signal q_buf      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal waddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal raddr      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal wnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal rnext      : unsigned(ADDR_WIDTH - 1 downto 0);
+    signal push       : std_logic;
+    signal pop        : std_logic;
+    signal usedw      : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
+    signal full_n     : std_logic := '1';
+    signal empty_n    : std_logic := '0';
+    signal q_tmp      : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal show_ahead : std_logic := '0';
+    signal dout_buf   : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
+    signal dout_valid : std_logic := '0';
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+begin
+    if_full_n  <= full_n;
+    if_empty_n <= dout_valid;
+    if_dout    <= dout_buf;
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and (not dout_valid or if_read);
+    wnext      <= waddr when push = '0' else
+                  (others => '0') when waddr = DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr when pop = '0' else
+                  (others => '0') when raddr = DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            elsif sclk_en = '1' then
+                waddr <= wnext;
+            end if;
+        end if;
+    end process;
+
+    -- raddr
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            elsif sclk_en = '1' then
+                raddr <= rnext;
+            end if;
+        end if;
+    end process;
+
+    -- usedw
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                usedw <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    usedw <= usedw + 1;
+                elsif push = '0' and pop = '1' then
+                    usedw <= usedw - 1;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- full_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    if usedw = DEPTH - 1 then
+                        full_n <= '0';
+                    else
+                        full_n <= '1';
+                    end if;
+                elsif push = '0' and pop = '1' then
+                    full_n <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and pop = '0' then
+                    empty_n <= '1';
+                elsif push = '0' and pop = '1' then
+                    if usedw = 1 then
+                        empty_n <= '0';
+                    else
+                        empty_n <= '1';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- mem
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if push = '1' then
+                mem(to_integer(waddr)) <= if_din;
+            end if;
+        end if;
+    end process;
+
+    -- q_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            q_buf <= mem(to_integer(rnext));
+        end if;
+    end process;
+
+    -- q_tmp
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                q_tmp <= (others => '0');
+            elsif sclk_en = '1' then
+                if push = '1' then
+                    q_tmp <= if_din;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- show_ahead
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                show_ahead <= '0';
+            elsif sclk_en = '1' then
+                if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
+                    show_ahead <= '1';
+                else
+                    show_ahead <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_buf
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_buf <= (others => '0');
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    if show_ahead = '1' then
+                        dout_buf <= q_tmp;
+                    else
+                        dout_buf <= q_buf;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- dout_valid
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_valid <= '0';
+            elsif sclk_en = '1' then
+                if pop = '1' then
+                    dout_valid <= '1';
+                elsif if_read_ce = '1' and if_read = '1' then
+                    dout_valid <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_decoder is
+    generic (
+        DIN_WIDTH : integer := 3);
+    port (
+        din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+        dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+end entity mmult_out_mem_m_axi_decoder;
+
+architecture behav of mmult_out_mem_m_axi_decoder is
+begin
+    process (din)
+    begin
+        dout <= (others => '0');
+        if (not(din = 0)) then
+            dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
+        end if;
+    end process;
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_throttl is
+    generic (
+        USED_FIX      : BOOLEAN := false;
+        FIX_VALUE     : INTEGER := 4;
+        ADDR_WIDTH    : INTEGER := 32;
+        DATA_WIDTH    : INTEGER := 32;
+        DEPTH         : INTEGER := 16;
+        USER_MAXREQS  : INTEGER := 16;
+        CONSERVATIVE  : INTEGER := 0;
+        AVERAGE_MODE  : BOOLEAN := false);
+    port (
+        clk             : in  STD_LOGIC;
+        reset           : in  STD_LOGIC;
+        ce              : in  STD_LOGIC;
+        in_addr         : in  STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        in_len          : in  STD_LOGIC_VECTOR(7 downto 0);
+        in_req_valid    : in  STD_LOGIC;
+        out_req_ready   : out STD_LOGIC;
+        out_addr        : out STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
+        out_len         : out STD_LOGIC_VECTOR(7 downto 0);
+        out_req_valid   : out STD_LOGIC;
+        in_req_ready    : in  STD_LOGIC;
+        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        in_strb         : in  STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        in_last         : in  STD_LOGIC;
+        in_data_valid   : in  STD_LOGIC;
+        out_data_ready  : out STD_LOGIC;
+        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
+        out_strb        : out STD_LOGIC_VECTOR(DATA_WIDTH/8-1 downto 0);
+        out_last        : out STD_LOGIC;
+        out_data_valid  : out STD_LOGIC;
+        in_data_ready   : in  STD_LOGIC);
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+    function gt_4 (x : INTEGER) return INTEGER is
+        variable n : INTEGER;
+    begin
+        n := 4;
+        if x > 4 then
+            n := x;
+        end if;
+        return n;
+    end function gt_4;
+
+end entity mmult_out_mem_m_axi_throttl;
+
+architecture behav of mmult_out_mem_m_axi_throttl is
+begin
+
+    conservative_gen : if (CONSERVATIVE = 0) generate
+        type     switch_t   is array(boolean) of integer;
+        constant switch         : switch_t  := (true => FIX_VALUE-1, false => 0);
+        constant threshold      : INTEGER   := switch(USED_FIX);
+        signal   req_en         : STD_LOGIC;
+        signal   handshake      : STD_LOGIC;
+        signal   load_init      : UNSIGNED(7 downto 0);
+        signal   throttl_cnt    : UNSIGNED(7 downto 0);
+    begin
+        -- AW Channel
+        out_addr  <= in_addr;
+        out_len   <= in_len;
+
+        -- W Channel
+        out_data        <= in_data;
+        out_strb        <= in_strb;
+        out_last        <= in_last;
+        out_data_valid  <= in_data_valid;
+        out_data_ready  <= in_data_ready;
+
+        fix_gen : if USED_FIX generate
+            load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
+            handshake <= '1';
+        end generate;
+
+        average_gen : if not USED_FIX and AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len); 
+            handshake <= '1';
+        end generate;
+
+        no_fix_gen : if not USED_FIX and not AVERAGE_MODE generate
+            load_init <= UNSIGNED(in_len);
+            handshake <= in_data_valid and in_data_ready;
+        end generate;
+
+        out_req_valid <= in_req_valid and req_en;
+        out_req_ready <= in_req_ready and req_en;
+        req_en        <= '1' when throttl_cnt = 0 else
+                         '0';
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    throttl_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
+                        throttl_cnt <= load_init; --load
+                    elsif throttl_cnt > 0 and handshake = '1' then
+                        throttl_cnt <= throttl_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate;
+
+    aggressive_gen : if (CONSERVATIVE /= 0) generate
+        constant CNT_WIDTH      : INTEGER   := log2(gt_4(DEPTH));
+        signal   data_in        : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   data_out       : STD_LOGIC_VECTOR(DATA_WIDTH + DATA_WIDTH/8 downto 0);
+        signal   req_in         : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_out        : STD_LOGIC_VECTOR(ADDR_WIDTH + 7 downto 0);
+        signal   req_en         : STD_LOGIC;
+        signal   data_en        : STD_LOGIC;
+        signal   fifo_valid     : STD_LOGIC;
+        signal   read_fifo      : STD_LOGIC;
+        signal   req_fifo_valid : STD_LOGIC;
+        signal   read_req       : STD_LOGIC;
+        signal   data_push      : STD_LOGIC;
+        signal   data_pop       : STD_LOGIC;
+        signal   flying_req     : STD_LOGIC;
+        signal   last_cnt       : UNSIGNED(CNT_WIDTH-1 downto 0);
+
+        signal   out_data_ready_tmp : STD_LOGIC;
+
+        component mmult_out_mem_m_axi_fifo is
+            generic (
+                DATA_BITS   : INTEGER := 8;
+                DEPTH       : INTEGER := 16;
+                DEPTH_BITS  : INTEGER := 4);
+            port (
+                sclk        : in  STD_LOGIC;
+                reset       : in  STD_LOGIC;
+                sclk_en     : in  STD_LOGIC;
+                empty_n     : out STD_LOGIC;
+                full_n      : out STD_LOGIC;
+                rdreq       : in  STD_LOGIC;
+                wrreq       : in  STD_LOGIC;
+                q           : out UNSIGNED(DATA_BITS-1 downto 0);
+                data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+        end component mmult_out_mem_m_axi_fifo;
+    begin
+        --AW Channel
+        req_in          <= in_len & in_addr;
+        out_addr        <= req_out(ADDR_WIDTH-1 downto 0);
+        out_len         <= req_out(ADDR_WIDTH+7 downto ADDR_WIDTH);
+        out_req_valid   <= req_fifo_valid and req_en;
+
+        req_en          <= '1' when ((flying_req = '0' and data_en = '1') or (flying_req = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1') and (last_cnt(CNT_WIDTH-1 downto 1) /= "0"))) else
+                         '0';
+        read_req        <= in_req_ready and req_en;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    flying_req <= '0';
+                elsif ce = '1' then
+                    if (req_fifo_valid and req_en) = '1' and in_req_ready = '1' then
+                        flying_req <= '1';
+                    elsif data_out(DATA_WIDTH+DATA_WIDTH/8) = '1' and data_pop = '1' then
+                        flying_req <= '0';
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        req_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => ADDR_WIDTH + 8,
+            DEPTH               => USER_MAXREQS,
+            DEPTH_BITS          => log2(USER_MAXREQS))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => req_fifo_valid,
+            full_n              => out_req_ready,
+            rdreq               => read_req,
+            wrreq               => in_req_valid,
+            STD_LOGIC_VECTOR(q) => req_out,
+            data                => UNSIGNED(req_in));
+
+        --W Channel
+        data_in         <= in_last & in_strb & in_data;
+        out_data        <= data_out(DATA_WIDTH-1 downto 0);
+        out_strb        <= data_out(DATA_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH);
+        out_last        <= data_out(DATA_WIDTH+DATA_WIDTH/8);
+        out_data_valid  <= fifo_valid and data_en and flying_req;
+        out_data_ready   <= out_data_ready_tmp;
+
+        data_en         <= '1' when last_cnt /= "0" else '0';
+        data_push       <= in_data_valid and out_data_ready_tmp;
+        data_pop        <= fifo_valid and read_fifo;
+        read_fifo       <= in_data_ready and data_en and flying_req;
+
+        process (clk)
+        begin
+            if (clk'event and clk = '1') then
+                if reset = '1' then
+                    last_cnt <= (others => '0');
+                elsif ce = '1' then
+                    if (in_last and data_push) = '1' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '0' then
+                        last_cnt <= last_cnt + 1;
+                    elsif (in_last and data_push) = '0' and (data_out(DATA_WIDTH+DATA_WIDTH/8) and data_pop) = '1' then
+                        last_cnt <= last_cnt - 1;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+        data_fifo : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS           => DATA_WIDTH + DATA_WIDTH/8 + 1,
+            DEPTH               => DEPTH,
+            DEPTH_BITS          => log2(DEPTH))
+        port map (
+            sclk                => clk,
+            reset               => reset,
+            sclk_en             => ce,
+            empty_n             => fifo_valid,
+            full_n              => out_data_ready_tmp,
+            rdreq               => read_fifo,
+            wrreq               => in_data_valid,
+            STD_LOGIC_VECTOR(q) => data_out,
+            data                => UNSIGNED(data_in));
+
+    end generate;
+
+end architecture behav;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_read is
+    generic (
+        NUM_READ_OUTSTANDING      : INTEGER := 2;
+        MAX_READ_BURST_LENGTH     : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_ARUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_RUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        ARID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        ARADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        ARLEN           : out UNSIGNED(7 downto 0);
+        ARSIZE          : out UNSIGNED(2 downto 0);
+        ARBURST         : out UNSIGNED(1 downto 0);
+        ARLOCK          : out UNSIGNED(1 downto 0);
+        ARCACHE         : out UNSIGNED(3 downto 0);
+        ARPROT          : out UNSIGNED(2 downto 0);
+        ARQOS           : out UNSIGNED(3 downto 0);
+        ARREGION        : out UNSIGNED(3 downto 0);
+        ARUSER          : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        ARVALID         : out STD_LOGIC;
+        ARREADY         : in  STD_LOGIC;
+        RID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        RDATA           : in  UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        RRESP           : in  UNSIGNED(1 downto 0);
+        RLAST           : in  STD_LOGIC;
+        RUSER           : in  UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
+        RVALID          : in  STD_LOGIC;
+        RREADY          : out STD_LOGIC;
+        rreq_valid      : in  STD_LOGIC;
+        rreq_ack        : out STD_LOGIC;
+        rreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        rreq_length     : in  UNSIGNED(31 downto 0);
+        rreq_cache      : in  UNSIGNED(3 downto 0);
+        rreq_prot       : in  UNSIGNED(2 downto 0);
+        rreq_qos        : in  UNSIGNED(3 downto 0);
+        rreq_region     : in  UNSIGNED(3 downto 0);
+        rreq_user       : in  UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
+        rdata_valid     : out STD_LOGIC;
+        rdata_ack       : in  STD_LOGIC;
+        rdata_data      : out UNSIGNED(USER_DW-1 downto 0);
+        rrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_read;
+
+architecture behave of mmult_out_mem_m_axi_read is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant NUM_READ_WIDTH       : INTEGER := log2(MAX_READ_BURST_LENGTH);
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    --AR channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  rreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_rreq_valid       : STD_LOGIC;
+    signal  rs2f_rreq_ack         : STD_LOGIC;
+    signal  fifo_rreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  arlen_tmp             : UNSIGNED(7 downto 0);
+    signal  araddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  ar2r_ardata           : UNSIGNED(1 downto 0);
+    signal  fifo_rctl_r           : STD_LOGIC;
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_rreq_valid       : STD_LOGIC;
+    signal  fifo_rreq_valid_buf   : STD_LOGIC;
+    signal  fifo_rreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  ARVALID_Dummy         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  next_rreq             : BOOLEAN;
+    signal  ready_for_rreq        : BOOLEAN;
+    signal  rreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --R channel
+    signal  fifo_rresp_rdata      : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  data_pack             : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
+    signal  tmp_data              : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+    signal  rs_rrsp_rdata         : UNSIGNED(USER_DW + 1 downto 0);
+    signal  rdata_data_pack       : UNSIGNED(USER_DW + 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  ar2r_rdata            : UNSIGNED(1 downto 0);
+    signal  tmp_resp              : UNSIGNED(1 downto 0);
+    signal  resp_buf              : UNSIGNED(1 downto 0);
+    signal  tmp_last              : STD_LOGIC;
+    signal  tmp_last_2            : STD_LOGIC;
+    signal  need_rlast            : STD_LOGIC;
+    signal  fifo_rctl_ready       : STD_LOGIC;
+    signal  beat_valid            : STD_LOGIC;
+    signal  next_beat             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  rdata_ack_t           : STD_LOGIC;
+    signal  rdata_valid_t         : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AR channel begin -----------------------------------
+    -- Instantiation
+    rs_rreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N               =>  USER_AW+ 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(rreq_data),
+            s_valid         =>  rreq_valid,
+            s_ready         =>  rreq_ack,
+            UNSIGNED(m_data)=>  rs2f_rreq_data,
+            m_valid         =>  rs2f_rreq_valid,
+            m_ready         =>  rs2f_rreq_ack);
+
+    fifo_rreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_rreq_ack,
+            wrreq           =>  rs2f_rreq_valid,
+            data            =>  rs2f_rreq_data,
+            empty_n         =>  fifo_rreq_valid,
+            rdreq           =>  fifo_rreq_read,
+            q               =>  fifo_rreq_data);
+
+    rreq_data   <= (rreq_length & rreq_addr);
+    tmp_addr    <= fifo_rreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
+
+    next_rreq      <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
+    ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
+    fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_rreq_valid = '1' and ready_for_rreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_rreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_rreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    fifo_rreq_valid_buf <= fifo_rreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_rreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    rreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
+                    rreq_handling <= true;
+                elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
+                    rreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process rreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_rreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= rreq_handling and ready_for_sect = '1';
+
+    sect_addr  <= start_addr_buf when first_sect else
+                  sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    ARID      <= (others => '0');
+    ARSIZE    <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
+    ARBURST   <= "01";
+    ARLOCK    <= "00";
+    ARCACHE   <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
+    ARPROT    <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
+    ARUSER    <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
+    ARQOS     <= rreq_qos;
+    ARREGION  <= rreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
+    begin
+        ARADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        ARLEN   <= RESIZE(sect_len_buf, 8);
+        ARVALID <= ARVALID_Dummy;
+
+        ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_sect and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_sect else '0';
+        ar2r_ardata  <= "10" when last_sect else "00";
+
+        fifo_burst_w <= '1' when next_sect else '0';
+        araddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        arlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
+        signal  araddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  arlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        ARADDR  <= araddr_buf;
+        ARLEN   <= arlen_buf;
+        ARVALID <= ARVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if rreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not rreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        araddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    araddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process araddr_buf_proc;
+
+        arlen_tmp  <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
+        arlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    arlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        arlen_buf <= arlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process arlen_buf_proc;
+
+        arvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    ARVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        ARVALID_Dummy <= '1';
+                    elsif not next_loop and ARREADY = '1' then
+                        ARVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process arvalid_proc;
+
+        fifo_rctl_r  <= '1' when next_loop else '0';
+        ar2r_ardata  <= "10" when last_loop else "00";
+
+        fifo_burst_w <= '1' when next_loop else '0';
+        burst_end    <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AR channel end -------------------------------------
+
+    --------------------------- R channel begin ------------------------------------
+    -- Instantiation
+    fifo_rdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH        =>  BUS_DATA_WIDTH + 3,
+            DEPTH             =>  NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
+            ADDR_WIDTH        =>  log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => RREADY,
+            if_write_ce       => '1',
+            if_write          => RVALID,
+            if_din            => STD_LOGIC_VECTOR(fifo_rresp_rdata),
+            if_empty_n        => beat_valid,
+            if_read_ce        => '1',
+            if_read           => next_beat,
+            UNSIGNED(if_dout) => data_pack);
+
+    rs_rdata : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N                 => USER_DW + 2)
+        port map (
+            sclk              => ACLK,
+            reset             => ARESET,
+            s_data            => STD_LOGIC_VECTOR(rs_rrsp_rdata),
+            s_valid           => rdata_valid_t,
+            s_ready           => rdata_ack_t,
+            UNSIGNED(m_data)  => rdata_data_pack,
+            m_valid           => rdata_valid,
+            m_ready           => rdata_ack);
+
+    fifo_rctl : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       => 2,
+            DEPTH           => NUM_READ_OUTSTANDING-1,
+            DEPTH_BITS      => log2(NUM_READ_OUTSTANDING-1))
+        port map (
+            sclk            => ACLK,
+            reset           => ARESET,
+            sclk_en         => ACLK_EN,
+            empty_n         => need_rlast,
+            full_n          => fifo_rctl_ready,
+            rdreq           => tmp_last_2,
+            wrreq           => fifo_rctl_r,
+            q               => ar2r_rdata,
+            data            => ar2r_ardata);
+
+    fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
+    tmp_data         <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
+    tmp_resp         <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
+    tmp_last         <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
+    tmp_last_2       <= tmp_last and next_beat;
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf    : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  ready_for_data   : BOOLEAN;
+    begin
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when beat_valid = '1' and ready_for_data else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat = '1' then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_equal_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  tmp_burst_info  : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  burst_pack      : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  split_cnt_buf   : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  head_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tail_split      : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  burst_len       : UNSIGNED(7 downto 0);
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  2*SPLIT_ALIGN + 8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
+        rrsp          <= rdata_data_pack(USER_DW + 1 downto USER_DW);
+        rdata_data    <= rdata_data_pack(USER_DW - 1 downto 0);
+
+        tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
+        head_split     <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
+        tail_split     <= burst_pack(SPLIT_ALIGN + 7 downto 8);
+        burst_len      <= burst_pack(7 downto 0);
+
+        next_beat        <= '1' when last_split else '0';
+        next_burst       <= '1' when last_beat and last_split else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
+
+        first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
+                       (split_cnt = head_split and ready_for_data);
+        last_split  <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
+                       (split_cnt = tail_split and ready_for_data);
+        next_split  <= (split_cnt /= 0 and ready_for_data) when not first_beat else
+                       (split_cnt /= head_split and ready_for_data);
+
+        split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
+                     split_cnt_buf;
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt_buf <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt_buf <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_beat and last_split then
+                        len_cnt <= (others => '0');
+                    elsif last_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if first_split and first_beat then
+                        data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
+                    elsif first_split then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        resp_buf <= tmp_resp;
+                    end if;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if first_split then
+                        rdata_valid_t <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+
+    end generate bus_wide_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  next_data       : BOOLEAN;
+    begin
+        rrsp        <= resp_buf;
+        rdata_data  <= data_buf(USER_DW - 1 downto 0);
+        rdata_valid <= rdata_valid_t;
+
+        fifo_burst_ready <= '1';
+        next_beat        <= '1' when next_pad else '0';
+        ready_for_data   <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
+
+        next_pad  <= beat_valid = '1' and ready_for_data;
+        last_pad  <= pad_oh(TOTAL_PADS - 1) = '1';
+        next_data <= last_pad and ready_for_data;
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0') when beat_valid = '0' else
+                  TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+        end generate data_gen;
+
+        resp_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                if (ARESET = '1') then
+                    resp_buf <= "00";
+                elsif next_beat = '1' and resp_buf(0) = '0' then
+                    resp_buf <= tmp_resp;
+                end if;
+            end if;
+        end process resp_buf_proc;
+
+        rdata_valid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    rdata_valid_t <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data then
+                        rdata_valid_t <= '1';
+                    elsif ready_for_data then
+                        rdata_valid_t <= '0';
+                    end if;
+                end if;
+            end if;
+        end process rdata_valid_proc;
+    end generate bus_narrow_gen;
+--------------------------- R channel end --------------------------------------
+end architecture behave;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_out_mem_m_axi_write is
+    generic (
+        NUM_WRITE_OUTSTANDING     : INTEGER := 2;
+        MAX_WRITE_BURST_LENGTH    : INTEGER := 16;
+        C_M_AXI_ID_WIDTH          : INTEGER := 1;
+        C_M_AXI_ADDR_WIDTH        : INTEGER := 32;
+        C_TARGET_ADDR             : INTEGER := 16#00000000#;
+        C_M_AXI_DATA_WIDTH        : INTEGER := 32;
+        C_M_AXI_AWUSER_WIDTH      : INTEGER := 1;
+        C_M_AXI_WUSER_WIDTH       : INTEGER := 1;
+        C_M_AXI_BUSER_WIDTH       : INTEGER := 1;
+        C_USER_VALUE              : INTEGER := 0;
+        C_PROT_VALUE              : INTEGER := 0;
+        C_CACHE_VALUE             : INTEGER := 2#0011#;
+        USER_DW                   : INTEGER := 16;
+        USER_AW                   : INTEGER := 32;
+        USER_MAXREQS              : INTEGER := 16);
+    port (
+        ACLK            : in  STD_LOGIC;
+        ARESET          : in  STD_LOGIC;
+        ACLK_EN         : in  STD_LOGIC;
+        AWID            : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        AWADDR          : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
+        AWLEN           : out UNSIGNED(7 downto 0);
+        AWSIZE          : out UNSIGNED(2 downto 0);
+        AWBURST         : out UNSIGNED(1 downto 0);
+        AWLOCK          : out UNSIGNED(1 downto 0);
+        AWCACHE         : out UNSIGNED(3 downto 0);
+        AWPROT          : out UNSIGNED(2 downto 0);
+        AWQOS           : out UNSIGNED(3 downto 0);
+        AWREGION        : out UNSIGNED(3 downto 0);
+        AWUSER          : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        AWVALID         : out STD_LOGIC;
+        AWREADY         : in  STD_LOGIC;
+        WID             : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        WDATA           : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
+        WSTRB           : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+        WLAST           : out STD_LOGIC;
+        WUSER           : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        WVALID          : out STD_LOGIC;
+        WREADY          : in  STD_LOGIC;
+        BID             : in  UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
+        BRESP           : in  UNSIGNED(1 downto 0);
+        BUSER           : in  UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
+        BVALID          : in  STD_LOGIC;
+        BREADY          : out STD_LOGIC;
+        wreq_valid      : in  STD_LOGIC;
+        wreq_ack        : out STD_LOGIC;
+        wreq_addr       : in  UNSIGNED(USER_AW-1 downto 0);
+        wreq_length     : in  UNSIGNED(31 downto 0);
+        wreq_cache      : in  UNSIGNED(3 downto 0);
+        wreq_prot       : in  UNSIGNED(2 downto 0);
+        wreq_qos        : in  UNSIGNED(3 downto 0);
+        wreq_region     : in  UNSIGNED(3 downto 0);
+        wreq_user       : in  UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
+        wdata_valid     : in  STD_LOGIC;
+        wdata_ack       : out STD_LOGIC;
+        wdata_strb      : in  UNSIGNED(USER_DW/8-1 downto 0);
+        wdata_user      : in  UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
+        wdata_data      : in  UNSIGNED(USER_DW-1 downto 0);
+        wrsp_valid      : out STD_LOGIC;
+        wrsp_ack        : in  STD_LOGIC;
+        wrsp            : out UNSIGNED(1 downto 0));
+
+    function calc_data_width (x : INTEGER) return INTEGER is
+        variable y : INTEGER;
+    begin
+        y := 8;
+        while y < x loop
+            y := y * 2;
+        end loop;
+        return y;
+    end function calc_data_width;
+
+    function log2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 0;
+        m := 1;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function log2;
+
+end entity mmult_out_mem_m_axi_write;
+
+architecture behave of mmult_out_mem_m_axi_write is
+    --common
+    constant USER_DATA_WIDTH      : INTEGER := calc_data_width(USER_DW);
+    constant USER_DATA_BYTES      : INTEGER := USER_DATA_WIDTH / 8;
+    constant USER_ADDR_ALIGN      : INTEGER := log2(USER_DATA_BYTES);
+    constant BUS_DATA_WIDTH       : INTEGER := C_M_AXI_DATA_WIDTH;
+    constant BUS_DATA_BYTES       : INTEGER := BUS_DATA_WIDTH / 8;
+    constant BUS_ADDR_ALIGN       : INTEGER := log2(BUS_DATA_BYTES);
+    constant NUM_WRITE_WIDTH      : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
+    --AW channel
+    constant TARGET_ADDR          : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
+    constant BOUNDARY_BEATS       : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
+    signal  wreq_data             : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  rs2f_wreq_valid       : STD_LOGIC;
+    signal  rs2f_wreq_ack         : STD_LOGIC;
+    signal  fifo_wreq_data        : UNSIGNED(USER_AW + 31 downto 0);
+    signal  tmp_addr              : UNSIGNED(USER_AW - 1 downto 0);
+    signal  tmp_len               : UNSIGNED(31 downto 0);
+    signal  align_len             : UNSIGNED(31 downto 0);
+    signal  awlen_tmp             : UNSIGNED(7 downto 0);
+    signal  start_addr            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  start_addr_buf        : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  end_addr_buf          : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  awaddr_tmp            : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr             : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_addr_buf         : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+    signal  sect_end              : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  sect_end_buf          : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  burst_end             : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
+    signal  start_to_4k           : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len              : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  sect_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  beat_len_buf          : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
+    signal  aw2b_awdata           : UNSIGNED(1 downto 0);
+    signal  sect_cnt              : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
+    signal  zero_len_event        : STD_LOGIC;
+    signal  negative_len_event    : STD_LOGIC;
+    signal  invalid_len_event     : STD_LOGIC;
+    signal  invalid_len_event_1   : STD_LOGIC;
+    signal  invalid_len_event_2   : STD_LOGIC;
+    signal  fifo_wreq_valid       : STD_LOGIC;
+    signal  fifo_wreq_valid_buf   : STD_LOGIC;
+    signal  fifo_wreq_read        : STD_LOGIC;
+    signal  fifo_burst_w          : STD_LOGIC;
+    signal  fifo_resp_w           : STD_LOGIC;
+    signal  last_sect_buf         : STD_LOGIC;
+    signal  ready_for_sect        : STD_LOGIC;
+    signal  AWVALID_Dummy         : STD_LOGIC;
+    signal  next_wreq             : BOOLEAN;
+    signal  ready_for_wreq        : BOOLEAN;
+    signal  wreq_handling         : BOOLEAN;
+    signal  first_sect            : BOOLEAN;
+    signal  last_sect             : BOOLEAN;
+    signal  next_sect             : BOOLEAN;
+    --W channel
+    signal  fifo_wdata_wstrb      : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  data_pack             : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
+    signal  tmp_data              : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+    signal  tmp_strb              : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+    signal  len_cnt               : UNSIGNED(7 downto 0);
+    signal  burst_len             : UNSIGNED(7 downto 0);
+    signal  data_valid            : STD_LOGIC;
+    signal  next_data             : STD_LOGIC;
+    signal  burst_valid           : STD_LOGIC;
+    signal  fifo_burst_ready      : STD_LOGIC;
+    signal  next_burst            : STD_LOGIC;
+    signal  WVALID_Dummy              : STD_LOGIC;
+    signal  WLAST_Dummy               : STD_LOGIC;
+    --B channel
+    signal  aw2b_bdata            : UNSIGNED(1 downto 0);
+    signal  bresp_tmp             : UNSIGNED(1 downto 0);
+    signal  next_resp             : STD_LOGIC;
+    signal  last_resp             : STD_LOGIC;
+    signal  invalid_event         : STD_LOGIC;
+    signal  fifo_resp_ready       : STD_LOGIC;
+    signal  need_wrsp             : STD_LOGIC;
+    signal  resp_match            : STD_LOGIC;
+    signal  resp_ready            : STD_LOGIC;
+
+    component mmult_out_mem_m_axi_fifo is
+        generic (
+            DATA_BITS   : INTEGER := 8;
+            DEPTH       : INTEGER := 16;
+            DEPTH_BITS  : INTEGER := 4);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            sclk_en     : in  STD_LOGIC;
+            empty_n     : out STD_LOGIC;
+            full_n      : out STD_LOGIC;
+            rdreq       : in  STD_LOGIC;
+            wrreq       : in  STD_LOGIC;
+            q           : out UNSIGNED(DATA_BITS-1 downto 0);
+            data        : in  UNSIGNED(DATA_BITS-1 downto 0));
+    end component mmult_out_mem_m_axi_fifo;
+
+    component mmult_out_mem_m_axi_reg_slice is
+        generic (
+            N           : INTEGER := 8);
+        port (
+            sclk        : in  STD_LOGIC;
+            reset       : in  STD_LOGIC;
+            s_data      : in  STD_LOGIC_VECTOR(N-1 downto 0);
+            s_valid     : in  STD_LOGIC;
+            s_ready     : out STD_LOGIC;
+            m_data      : out STD_LOGIC_VECTOR(N-1 downto 0);
+            m_valid     : out STD_LOGIC;
+            m_ready     : in  STD_LOGIC);
+    end component mmult_out_mem_m_axi_reg_slice;
+
+    component mmult_out_mem_m_axi_buffer is
+        generic (
+                    MEM_STYLE  : STRING  := "block";
+            DATA_WIDTH : NATURAL := 32;
+            ADDR_WIDTH : NATURAL := 5;
+            DEPTH      : NATURAL := 32
+        );
+        port (
+             clk         : in  STD_LOGIC;
+             reset       : in  STD_LOGIC;
+             sclk_en     : in  STD_LOGIC;
+             if_full_n   : out STD_LOGIC;
+             if_write_ce : in  STD_LOGIC;
+             if_write    : in  STD_LOGIC;
+             if_din      : in  STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+             if_empty_n  : out STD_LOGIC;
+             if_read_ce  : in  STD_LOGIC;
+             if_read     : in  STD_LOGIC;
+             if_dout     : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+    end component mmult_out_mem_m_axi_buffer;
+
+begin
+    --------------------------- AW channel begin -----------------------------------
+    -- Instantiation
+    rs_wreq : mmult_out_mem_m_axi_reg_slice
+        generic map (
+            N => USER_AW + 32)
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            s_data          =>  STD_LOGIC_VECTOR(wreq_data),
+            s_valid         =>  wreq_valid,
+            s_ready         =>  wreq_ack,
+            UNSIGNED(m_data)=>  rs2f_wreq_data,
+            m_valid         =>  rs2f_wreq_valid,
+            m_ready         =>  rs2f_wreq_ack);
+
+    fifo_wreq : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  USER_AW + 32,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            full_n          =>  rs2f_wreq_ack,
+            wrreq           =>  rs2f_wreq_valid,
+            data            =>  rs2f_wreq_data,
+            empty_n         =>  fifo_wreq_valid,
+            rdreq           =>  fifo_wreq_read,
+            q               =>  fifo_wreq_data);
+
+    wreq_data   <= (wreq_length & wreq_addr);
+    tmp_addr    <= fifo_wreq_data(USER_AW - 1 downto 0);
+    tmp_len     <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
+    end_addr    <= start_addr + align_len;
+
+    zero_len_event        <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
+    negative_len_event    <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
+
+    next_wreq      <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
+    ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
+    fifo_wreq_read <= '1' when next_wreq else '0';
+
+    align_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                align_len <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    if (zero_len_event = '1' or negative_len_event = '1') then
+                        align_len <= (others => '0');
+                    else
+                        align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process align_len_proc;
+
+    start_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if (fifo_wreq_valid = '1' and ready_for_wreq) then
+                    start_addr  <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process start_addr_proc;
+
+    fifo_wreq_valid_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                fifo_wreq_valid_buf <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    fifo_wreq_valid_buf <= fifo_wreq_valid;
+                end if;
+            end if;
+        end if;
+    end process fifo_wreq_valid_buf_proc;
+
+    invalid_len_event_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event <= '0';
+            elsif ACLK_EN = '1' then
+                if (next_wreq) then
+                    invalid_len_event <= zero_len_event or negative_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_proc;
+
+    wreq_handling_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wreq_handling <= false;
+            elsif ACLK_EN = '1' then
+                if fifo_wreq_valid_buf = '1' and not wreq_handling then
+                    wreq_handling <= true;
+                elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
+                    wreq_handling <= false;
+                end if;
+            end if;
+        end if;
+    end process wreq_handling_proc;
+
+    start_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                start_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    start_addr_buf <= start_addr;
+                end if;
+            end if;
+        end if;
+    end process start_addr_buf_proc;
+
+    end_addr_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                end_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    end_addr_buf <= end_addr;
+                end if;
+            end if;
+        end if;
+    end process end_addr_buf_proc;
+
+    beat_len_buf_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                beat_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
+                end if;
+            end if;
+        end if;
+    end process beat_len_buf_proc;
+
+    sect_cnt_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_cnt <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
+                elsif next_sect then
+                    sect_cnt <= sect_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process sect_cnt_proc;
+
+    -- event registers
+    invalid_len_event_1_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_1 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_wreq then
+                    invalid_len_event_1 <= invalid_len_event;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_1_proc;
+    -- end event registers
+
+    first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
+    last_sect  <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
+    next_sect  <= wreq_handling and ready_for_sect = '1';
+
+    sect_addr <= start_addr_buf when first_sect else
+                 sect_cnt & (11 downto 0 => '0');
+    sect_addr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_addr_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_addr_buf <= sect_addr;
+                end if;
+            end if;
+        end if;
+    end process sect_addr_proc;
+
+    start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
+    sect_len    <= beat_len_buf                            when     first_sect and     last_sect else
+                   start_to_4k                             when     first_sect and not last_sect else
+                   end_addr_buf(11 downto BUS_ADDR_ALIGN)  when not first_sect and     last_sect else
+                   BOUNDARY_BEATS;
+
+    sect_len_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_len_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_len_buf <= sect_len;
+                end if;
+            end if;
+        end if;
+    end process sect_len_proc;
+
+    sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
+                (others => '1');
+    sect_end_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                sect_end_buf <= (others => '0');
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    sect_end_buf <= sect_end;
+                end if;
+            end if;
+        end if;
+    end process sect_end_proc;
+
+    -- event registers
+    invalid_len_event_2_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                invalid_len_event_2 <= '0';
+            elsif ACLK_EN = '1' then
+                if next_sect then
+                    invalid_len_event_2 <= invalid_len_event_1;
+                end if;
+            end if;
+        end if;
+    end process invalid_len_event_2_proc;
+    -- end event registers
+
+    AWID     <= (others => '0');
+    AWSIZE   <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
+    AWBURST  <= "01";
+    AWLOCK   <= "00";
+    AWCACHE  <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
+    AWPROT   <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
+    AWUSER   <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
+    AWQOS    <= wreq_qos;
+    AWREGION <= wreq_region;
+
+    must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
+    begin
+        AWADDR  <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+        AWLEN   <= RESIZE(sect_len_buf, 8);
+        AWVALID <= AWVALID_Dummy;
+
+        ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_1 = '1' and next_sect then
+                        AWVALID_Dummy <= '0';
+                    elsif next_sect then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_sect and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_sect else '0';
+        aw2b_awdata <= '1' & invalid_len_event_1 when last_sect else '0' & invalid_len_event_1;
+
+        fifo_burst_w <= '1' when invalid_len_event_1 = '0' and next_sect else '0';
+        awaddr_tmp   <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        awlen_tmp    <= RESIZE(sect_len, 8);
+        burst_end    <= sect_end;
+    end generate must_one_burst;
+
+    could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
+        signal  awaddr_buf      : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
+        signal  awlen_buf       : UNSIGNED(7 downto 0);
+        signal  loop_cnt        : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
+        signal  last_loop       : BOOLEAN;
+        signal  next_loop       : BOOLEAN;
+        signal  ready_for_loop  : BOOLEAN;
+        signal  sect_handling   : BOOLEAN;
+    begin
+        AWADDR  <= awaddr_buf;
+        AWLEN   <= awlen_buf;
+        AWVALID <= AWVALID_Dummy;
+
+        last_loop      <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
+        next_loop      <= sect_handling and ready_for_loop;
+        ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
+        ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
+
+        sect_handling_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    sect_handling <= false;
+                elsif ACLK_EN = '1' then
+                    if wreq_handling and not sect_handling then
+                        sect_handling <= true;
+                    elsif not wreq_handling and last_loop and next_loop then
+                        sect_handling <= false;
+                    end if;
+                end if;
+            end if;
+        end process sect_handling_proc;
+
+        loop_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    loop_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_sect then
+                        loop_cnt <= (others => '0');
+                    elsif next_loop then
+                        loop_cnt <= loop_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process loop_cnt_proc;
+
+        awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
+                      awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
+        awaddr_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awaddr_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
+                    end if;
+                end if;
+            end if;
+        end process awaddr_buf_proc;
+
+        awlen_tmp  <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
+                      TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
+        awlen_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    awlen_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_loop then
+                        awlen_buf <= awlen_tmp;
+                    end if;
+                end if;
+            end if;
+        end process awlen_buf_proc;
+
+        awvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    AWVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if invalid_len_event_2 = '1' and next_loop then
+                        AWVALID_Dummy <= '0';
+                    elsif next_loop then
+                        AWVALID_Dummy <= '1';
+                    elsif not next_loop and AWREADY = '1' then
+                        AWVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process awvalid_proc;
+
+        fifo_resp_w <= '1' when next_loop else '0';
+        aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
+        last_sect_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    last_sect_buf <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_sect and last_sect then
+                        last_sect_buf <= '1';
+                    elsif next_sect then
+                        last_sect_buf <= '0';
+                    end if;
+                end if;
+            end if;
+        end process last_sect_buf_proc;
+
+        fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
+        burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
+    end generate could_multi_bursts;
+    --------------------------- AW channel end -------------------------------------
+
+    --------------------------- W channel begin ------------------------------------
+    -- Instantiation
+    buff_wdata : mmult_out_mem_m_axi_buffer
+        generic map (
+            DATA_WIDTH      => USER_DW + USER_DW/8,
+            DEPTH           => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
+            ADDR_WIDTH      => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
+        port map (
+            clk               => ACLK,
+            reset             => ARESET,
+            sclk_en           => ACLK_EN,
+            if_full_n         => wdata_ack,
+            if_write_ce       => '1',
+            if_write          => wdata_valid,
+            if_din            => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
+            if_empty_n        => data_valid,
+            if_read_ce        => '1',
+            if_read           => next_data,
+            UNSIGNED(if_dout) => data_pack);
+
+    fifo_wdata_wstrb <= (wdata_strb & wdata_data);
+    tmp_data         <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
+    tmp_strb         <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
+
+    WID     <= (others => '0');
+    WUSER   <= TO_UNSIGNED(C_USER_VALUE, WUSER'length);
+
+    bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+        next_data      <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
+        next_burst     <= '1' when len_cnt = burst_len and next_data = '1' else '0';
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+    end generate bus_equal_gen;
+
+    bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
+        constant TOTAL_SPLIT    : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
+        constant SPLIT_ALIGN    : INTEGER := log2(TOTAL_SPLIT);
+        signal  data_buf        : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
+        signal  split_cnt       : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(7 downto 0);
+        signal  first_split     : BOOLEAN;
+        signal  next_split      : BOOLEAN;
+        signal  last_split      : BOOLEAN;
+        signal  ready_for_data  : BOOLEAN;
+    begin
+        -- instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8,
+                DEPTH           =>  USER_MAXREQS,
+                DEPTH_BITS      =>  log2(USER_MAXREQS))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_len,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
+        WSTRB   <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= RESIZE(awlen_tmp, 8);
+
+        next_data      <= '1' when first_split else '0';
+        next_burst     <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
+        next_split  <= split_cnt /= 0 and ready_for_data;
+        last_split  <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
+
+        split_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    split_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if last_split then
+                        split_cnt <= (others => '0');
+                    elsif first_split or next_split then
+                        split_cnt <= split_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process split_cnt_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_data = '1' or next_split then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+
+        data_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if ACLK_EN = '1' then
+                    if next_data = '1' then
+                        data_buf <= tmp_data;
+                    elsif next_split then
+                        data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
+                    end if;
+                end if;
+            end if;
+        end process data_buf_proc;
+
+        strb_buf_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    strb_buf <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        strb_buf <= tmp_strb;
+                    elsif next_split then
+                        strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
+                    end if;
+                end if;
+            end if;
+        end process strb_buf_proc;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_data = '1' then
+                        WVALID_Dummy <= '1';
+                    elsif not (first_split or next_split) and ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' and last_split then
+                        WLAST_Dummy <= '1';
+                    elsif ready_for_data then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+    end generate bus_narrow_gen;
+
+    bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
+        constant TOTAL_PADS     : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
+        constant PAD_ALIGN      : INTEGER := log2(TOTAL_PADS);
+        signal  data_buf        : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
+        signal  strb_buf        : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
+        signal  burst_pack      : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  tmp_burst_info  : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
+        signal  head_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  tail_pads       : UNSIGNED(PAD_ALIGN - 1 downto 0);
+        signal  add_head        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  add_tail        : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh          : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  pad_oh_reg      : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  head_pad_sel    : UNSIGNED(TOTAL_PADS - 1 downto 0);
+        signal  tail_pad_sel    : UNSIGNED(0 to TOTAL_PADS - 1);
+        signal  ready_for_data  : BOOLEAN;
+        signal  next_pad        : BOOLEAN;
+        signal  first_pad       : BOOLEAN;
+        signal  last_pad        : BOOLEAN;
+        signal  first_beat      : BOOLEAN;
+        signal  last_beat       : BOOLEAN;
+        signal  next_beat       : BOOLEAN;
+
+        component mmult_out_mem_m_axi_decoder is
+            generic (
+                DIN_WIDTH : integer := 3);
+            port (
+                din     : in  UNSIGNED(DIN_WIDTH - 1 downto 0);
+                dout    : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
+        end component mmult_out_mem_m_axi_decoder;
+
+    begin
+        -- Instantiation
+        fifo_burst : mmult_out_mem_m_axi_fifo
+            generic map (
+                DATA_BITS       =>  8 + 2*PAD_ALIGN,
+                DEPTH           =>  user_maxreqs,
+                DEPTH_BITS      =>  log2(user_maxreqs))
+            port map (
+                sclk            =>  ACLK,
+                reset           =>  ARESET,
+                sclk_en         =>  ACLK_EN,
+                empty_n         =>  burst_valid,
+                full_n          =>  fifo_burst_ready,
+                rdreq           =>  next_burst,
+                wrreq           =>  fifo_burst_w,
+                q               =>  burst_pack,
+                data            =>  tmp_burst_info);
+
+        WDATA   <= data_buf;
+        WSTRB   <= strb_buf;
+        WLAST   <= WLAST_Dummy;
+        WVALID  <= WVALID_Dummy;
+
+        tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
+
+        head_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  head_pads,
+                dout            =>  head_pad_sel);
+
+        tail_pad_decoder : mmult_out_mem_m_axi_decoder
+            generic map (
+                DIN_WIDTH       =>  PAD_ALIGN)
+            port map (
+                din             =>  tail_pads,
+                dout            =>  tail_pad_sel);
+
+        head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
+        tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
+        burst_len <= burst_pack(7 downto 0);
+
+        next_data      <= '1' when next_pad else '0';
+        next_burst     <= '1' when last_beat and next_beat else '0';
+        ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
+
+        first_beat <= len_cnt = 0 and burst_valid = '1';
+        last_beat  <= len_cnt = burst_len and burst_valid = '1';
+        next_beat  <= burst_valid = '1' and last_pad and ready_for_data;
+
+        next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
+        last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
+                    pad_oh(TOTAL_PADS - 1) = '1';
+
+        first_pad_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    first_pad <= true;
+                elsif ACLK_EN = '1' then
+                    if next_pad and not last_pad then
+                        first_pad <= false;
+                    elsif next_pad and last_pad then
+                        first_pad <= true;
+                    end if;
+                end if;
+            end if;
+        end process first_pad_proc;
+
+        pad_oh <= (others => '0')                                               when data_valid = '0' else
+                  SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
+                  TO_UNSIGNED(1, TOTAL_PADS)                                    when first_pad else
+                  pad_oh_reg;
+        pad_oh_reg_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    pad_oh_reg <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_pad then
+                        pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
+                    end if;
+                end if;
+            end if;
+        end process pad_oh_reg_proc;
+
+        data_strb_gen : for i in 1 to TOTAL_PADS generate
+        begin
+            add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
+                             '0';
+            add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
+                             '0';
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') then
+                    if ACLK_EN = '1' then
+                        if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
+                        elsif pad_oh(i-1) = '1' and ready_for_data then
+                            data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
+                        end if;
+                    end if;
+                end if;
+            end process;
+
+            process (ACLK)
+            begin
+                if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
+                    if (ARESET = '1') then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
+                    elsif pad_oh(i-1) = '1' and ready_for_data then
+                        strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
+                    end if;
+                end if;
+            end process;
+        end generate data_strb_gen;
+
+        wvalid_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WVALID_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_beat then
+                        WVALID_Dummy <= '1';
+                    elsif ready_for_data then
+                        WVALID_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wvalid_proc;
+
+        wlast_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    WLAST_Dummy <= '0';
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        WLAST_Dummy <= '1';
+                    elsif next_data = '1' then
+                        WLAST_Dummy <= '0';
+                    end if;
+                end if;
+            end if;
+        end process wlast_proc;
+
+        len_cnt_proc : process (ACLK)
+        begin
+            if (ACLK'event and ACLK = '1') then
+                if (ARESET = '1') then
+                    len_cnt <= (others => '0');
+                elsif ACLK_EN = '1' then
+                    if next_burst = '1' then
+                        len_cnt <= (others => '0');
+                    elsif next_beat then
+                        len_cnt <= len_cnt + 1;
+                    end if;
+                end if;
+            end if;
+        end process len_cnt_proc;
+    end generate bus_wide_gen;
+    --------------------------- W channel end --------------------------------------
+
+    --------------------------- B channel begin ------------------------------------
+    -- Instantiation
+    fifo_resp : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  NUM_WRITE_OUTSTANDING-1,
+            DEPTH_BITS      =>  log2(NUM_WRITE_OUTSTANDING-1))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  need_wrsp,
+            full_n          =>  fifo_resp_ready,
+            rdreq           =>  next_resp,
+            wrreq           =>  fifo_resp_w,
+            q               =>  aw2b_bdata,
+            data            =>  aw2b_awdata);
+
+    fifo_resp_to_user : mmult_out_mem_m_axi_fifo
+        generic map (
+            DATA_BITS       =>  2,
+            DEPTH           =>  USER_MAXREQS,
+            DEPTH_BITS      =>  log2(USER_MAXREQS))
+        port map (
+            sclk            =>  ACLK,
+            reset           =>  ARESET,
+            sclk_en         =>  ACLK_EN,
+            empty_n         =>  wrsp_valid,
+            full_n          =>  resp_ready,
+            rdreq           =>  wrsp_ack,
+            wrreq           =>  resp_match,
+            q               =>  wrsp,
+            data            =>  bresp_tmp);
+
+    BREADY        <= resp_ready;
+    last_resp     <= aw2b_bdata(1);
+    invalid_event <= aw2b_bdata(0);
+    resp_match    <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
+
+    next_resp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                next_resp <= '0';
+            elsif ACLK_EN = '1' then
+                next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
+            end if;
+        end if;
+    end process next_resp_proc;
+
+    bresp_tmp_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                bresp_tmp <= "00";
+            elsif ACLK_EN = '1' then
+                if (resp_match = '1' and next_resp = '0') then
+                    bresp_tmp <= "00";
+                elsif (resp_match = '1' and next_resp = '1') then
+                    bresp_tmp <= BRESP;
+                elsif (next_resp = '1' and bresp_tmp(1) = '0') then
+                    bresp_tmp <= BRESP;
+                end if;
+            end if;
+        end if;
+    end process bresp_tmp_proc;
+--------------------------- B channel end --------------------------------------
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_params_s_axi.vhd b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_params_s_axi.vhd
new file mode 100755
index 0000000..1f9adde
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/hdl/vhdl/mmult_params_s_axi.vhd
@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;
diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/misc/logo.png b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/misc/logo.png
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diff --git a/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/xgui/mmult_v9_0.tcl b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/xgui/mmult_v9_0.tcl
new file mode 100755
index 0000000..0276fbf
--- /dev/null
+++ b/hls/lab2/exported_ips/xilinx_com_hls_exercise_9/xgui/mmult_v9_0.tcl
@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+
diff --git a/hls/lab2/hw/exercise_1.xsa b/hls/lab2/hw/exercise_1.xsa
new file mode 100644
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diff --git a/hls/lab2/hw/exercise_2.xsa b/hls/lab2/hw/exercise_2.xsa
new file mode 100644
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literal 0
HcmV?d00001

diff --git a/hls/lab2/sw/lscript.ld b/hls/lab2/sw/lscript.ld
new file mode 100644
index 0000000..6b49b6b
--- /dev/null
+++ b/hls/lab2/sw/lscript.ld
@@ -0,0 +1,322 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version: 2020.1                                                 */
+/*                                                                 */
+/* Copyright (c) 2010-2019 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : ARM v8 Linker Script                           */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x8000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x8000;
+
+_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
+_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
+_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   psu_ddr_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x7FF00000
+   psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > psu_ddr_0_MEM_0
+
+.init (ALIGN(64)) : {
+   KEEP (*(.init))
+} > psu_ddr_0_MEM_0
+
+.fini (ALIGN(64)) : {
+   KEEP (*(.fini))
+} > psu_ddr_0_MEM_0
+
+.interp : {
+   KEEP (*(.interp))
+} > psu_ddr_0_MEM_0
+
+.note-ABI-tag : {
+   KEEP (*(.note-ABI-tag))
+} > psu_ddr_0_MEM_0
+
+.rodata : {
+   . = ALIGN(64);
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > psu_ddr_0_MEM_0
+
+.rodata1 : {
+   . = ALIGN(64);
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > psu_ddr_0_MEM_0
+
+.sdata2 : {
+   . = ALIGN(64);
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > psu_ddr_0_MEM_0
+
+.sbss2 : {
+   . = ALIGN(64);
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > psu_ddr_0_MEM_0
+
+.data : {
+   . = ALIGN(64);
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > psu_ddr_0_MEM_0
+
+.data1 : {
+   . = ALIGN(64);
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > psu_ddr_0_MEM_0
+
+.got : {
+   *(.got)
+} > psu_ddr_0_MEM_0
+
+.got1 : {
+   *(.got1)
+} > psu_ddr_0_MEM_0
+
+.got2 : {
+   *(.got2)
+} > psu_ddr_0_MEM_0
+
+.note.gnu.build-id : {
+   KEEP (*(.note.gnu.build-id))
+} > psu_ddr_0_MEM_0
+
+.ctors : {
+   . = ALIGN(64);
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > psu_ddr_0_MEM_0
+
+.dtors : {
+   . = ALIGN(64);
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > psu_ddr_0_MEM_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > psu_ddr_0_MEM_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > psu_ddr_0_MEM_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > psu_ddr_0_MEM_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > psu_ddr_0_MEM_0
+
+.mmu_tbl0 (ALIGN(4096)) : {
+   __mmu_tbl0_start = .;
+   *(.mmu_tbl0)
+   __mmu_tbl0_end = .;
+} > psu_ddr_0_MEM_0
+
+.mmu_tbl1 (ALIGN(4096)) : {
+   __mmu_tbl1_start = .;
+   *(.mmu_tbl1)
+   __mmu_tbl1_end = .;
+} > psu_ddr_0_MEM_0
+
+.mmu_tbl2 (ALIGN(4096)) : {
+   __mmu_tbl2_start = .;
+   *(.mmu_tbl2)
+   __mmu_tbl2_end = .;
+} > psu_ddr_0_MEM_0
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > psu_ddr_0_MEM_0
+
+.preinit_array : {
+   . = ALIGN(64);
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > psu_ddr_0_MEM_0
+
+.init_array : {
+   . = ALIGN(64);
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > psu_ddr_0_MEM_0
+
+.fini_array : {
+   . = ALIGN(64);
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > psu_ddr_0_MEM_0
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > psu_ddr_0_MEM_0
+
+.sdata : {
+   . = ALIGN(64);
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > psu_ddr_0_MEM_0
+
+.sbss (NOLOAD) : {
+   . = ALIGN(64);
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   . = ALIGN(64);
+   __sbss_end = .;
+} > psu_ddr_0_MEM_0
+
+.tdata : {
+   . = ALIGN(64);
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > psu_ddr_0_MEM_0
+
+.tbss : {
+   . = ALIGN(64);
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > psu_ddr_0_MEM_0
+
+.bss (NOLOAD) : {
+   . = ALIGN(64);
+   __bss_start__ = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   . = ALIGN(64);
+   __bss_end__ = .;
+} > psu_ddr_0_MEM_0
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(64);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > psu_ddr_0_MEM_0
+
+.stack (NOLOAD) : {
+   . = ALIGN(64);
+   _el3_stack_end = .;
+   . += _STACK_SIZE;
+   __el3_stack = .;
+   _el2_stack_end = .;
+   . += _EL2_STACK_SIZE;
+   . = ALIGN(64);
+   __el2_stack = .;
+   _el1_stack_end = .;
+   . += _EL1_STACK_SIZE;
+   . = ALIGN(64);
+   __el1_stack = .;
+   _el0_stack_end = .;
+   . += _EL0_STACK_SIZE;
+   . = ALIGN(64);
+   __el0_stack = .;
+} > psu_ddr_0_MEM_0
+
+_end = .;
+}
+
diff --git a/hls/lab2/sw/main.c b/hls/lab2/sw/main.c
new file mode 100644
index 0000000..3489a87
--- /dev/null
+++ b/hls/lab2/sw/main.c
@@ -0,0 +1,102 @@
+#include <stdio.h>
+#include "platform.h"
+#include "xil_printf.h"
+#include "xtmrctr.h"
+#include "xmmult.h"
+#include "xparameters.h"
+#include "xil_cache.h"
+#include "xil_io.h"
+
+#define MAX_SIZE 64
+
+void mmult_hardware(
+		XMmult* mmult_accel,
+        u32 in1,   // Input matrix 1
+        u32 in2,   // Input matrix 2
+        u32 out,   // Output matrix (out = A x B)
+        u32 dim     // Size of one dimension of matrix
+		) {
+
+	XMmult_Set_in1(mmult_accel, in1);
+	XMmult_Set_in2(mmult_accel, in2);
+	XMmult_Set_out_r(mmult_accel, out);
+	XMmult_Set_dim(mmult_accel, MAX_SIZE);
+
+	XMmult_Start(mmult_accel);
+
+	while(!XMmult_IsDone(mmult_accel)){
+		/* wait polling */
+	}
+}
+
+void mmult_software(
+		int* in1,   // Input matrix 1
+		int* in2,   // Input matrix 2
+		int* out,   // Output matrix (out = A x B)
+		int dim     // Size of one dimension of matrix
+              )
+{
+    //Performs matrix multiplication out = in1 x in2
+    for (int i = 0; i < dim; i++){
+        for (int j = 0; j < dim; j++){
+            for (int k = 0; k < dim; k++){
+                out[i * dim + j] += in1[i * dim + k] * in2[k * dim  + j];
+            }
+        }
+    }
+}
+
+
+
+int main()
+{
+    init_platform();
+
+    printf("MMULT benchmark size: %d\n", MAX_SIZE);
+
+    int in1[MAX_SIZE*MAX_SIZE];
+    int in2[MAX_SIZE*MAX_SIZE];
+    int out[MAX_SIZE*MAX_SIZE];
+
+    printf("in1: %p\n", in1);
+    printf("in2: %p\n", in2);
+    printf("out: %p\n", out);
+
+    for(int i = 0; i < MAX_SIZE*MAX_SIZE; i++) {
+    	in1[i] = i;
+    	in2[i] = i;
+    	out[i] = 0;
+    }
+    Xil_DCacheFlush();
+
+    XTmrCtr timer;
+    XTmrCtr_Initialize(&timer, XPAR_AXI_TIMER_0_DEVICE_ID);
+
+	XMmult mmult_accel;
+	XMmult_Initialize(&mmult_accel, 0);
+
+    XTmrCtr_Start(&timer, 0);
+    mmult_hardware(&mmult_accel, (u32)in1, (u32)in2, (u32)out, MAX_SIZE);
+    XTmrCtr_Stop(&timer, 0);
+
+    printf("hardware: %d\n", XTmrCtr_GetValue(&timer, 0));
+
+    Xil_DCacheDisable();
+
+    XTmrCtr_Start(&timer, 0);
+    mmult_software(in1, in2, out, MAX_SIZE);
+    XTmrCtr_Stop(&timer, 0);
+
+    printf("software: %d\n", XTmrCtr_GetValue(&timer, 0));
+
+    Xil_DCacheInvalidate();
+//    printf("out\n");
+//    for(int i = 0; i < MAX_SIZE*MAX_SIZE; i++) {
+//    	printf("%d \n", out[i]);
+//    }
+//    printf("\n");
+
+    cleanup_platform();
+
+    return 0;
+}
diff --git a/hls/lab2/sw/platform.c b/hls/lab2/sw/platform.c
new file mode 100644
index 0000000..0ee2dcb
--- /dev/null
+++ b/hls/lab2/sw/platform.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_cache.h"
+
+#include "platform_config.h"
+
+/*
+ * Uncomment one of the following two lines, depending on the target,
+ * if ps7/psu init source files are added in the source directory for
+ * compiling example outside of SDK.
+ */
+/*#include "ps7_init.h"*/
+/*#include "psu_init.h"*/
+
+#ifdef STDOUT_IS_16550
+ #include "xuartns550_l.h"
+
+ #define UART_BAUD 9600
+#endif
+
+void
+enable_caches()
+{
+#ifdef __PPC__
+    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
+    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
+#elif __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheEnable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheEnable();
+#endif
+#endif
+}
+
+void
+disable_caches()
+{
+#ifdef __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheDisable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheDisable();
+#endif
+#endif
+}
+
+void
+init_uart()
+{
+#ifdef STDOUT_IS_16550
+    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
+    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
+#endif
+    /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
+}
+
+void
+init_platform()
+{
+    /*
+     * If you want to run this example outside of SDK,
+     * uncomment one of the following two lines and also #include "ps7_init.h"
+     * or #include "ps7_init.h" at the top, depending on the target.
+     * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
+     * along with this example source files for compilation.
+     */
+    /* ps7_init();*/
+    /* psu_init();*/
+    enable_caches();
+    init_uart();
+}
+
+void
+cleanup_platform()
+{
+    disable_caches();
+}
diff --git a/hls/lab2/sw/platform.h b/hls/lab2/sw/platform.h
new file mode 100644
index 0000000..e273e37
--- /dev/null
+++ b/hls/lab2/sw/platform.h
@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef __PLATFORM_H_
+#define __PLATFORM_H_
+
+#include "platform_config.h"
+
+void init_platform();
+void cleanup_platform();
+
+#endif
diff --git a/hls/lab2/sw/platform_config.h b/hls/lab2/sw/platform_config.h
new file mode 100644
index 0000000..30d16a1
--- /dev/null
+++ b/hls/lab2/sw/platform_config.h
@@ -0,0 +1,6 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+#define STDOUT_IS_PSU_UART
+#define UART_DEVICE_ID 1
+#endif